52 lines
1.3 KiB
Text
52 lines
1.3 KiB
Text
#include <dt-bindings/clock/qcom,gcc-sdxpinn.h>
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&soc {
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usb: ssusb@a600000 {
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compatible = "qcom,dwc-usb3-msm";
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reg = <0x0a600000 0x100000>;
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reg-names = "core_base";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "pwr_event_irq";
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USB3_GDSC-supply = <&gcc_usb30_gdsc>;
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clocks = <&gcc GCC_USB30_MASTER_CLK>,
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<&gcc GCC_USB30_SLV_AHB_CLK>,
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<&gcc GCC_USB30_MSTR_AXI_CLK>,
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<&gcc GCC_USB30_MOCK_UTMI_CLK>,
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<&gcc GCC_USB30_SLEEP_CLK>;
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clock-names = "core_clk", "iface_clk",
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"bus_aggr_clk", "utmi_clk",
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"sleep_clk";
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resets = <&gcc GCC_USB30_BCR>;
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reset-names = "core_reset";
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qcom,core-clk-rate = <200000000>;
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qcom,core-clk-rate-hs = <66666667>;
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qcom,default-bus-vote = <2>; /* use svs bus voting */
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qcom,num-gsi-evt-buffs = <0x3>;
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qcom,gsi-reg-offset =
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<0x0fc /* GSI_GENERAL_CFG */
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0x208 /* GSI_DBL_ADDR_L */
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0x224 /* GSI_DBL_ADDR_H */
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0x240 /* GSI_RING_BASE_ADDR_L */
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0x25c /* GSI_RING_BASE_ADDR_H */
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0x1a4>; /* GSI_IF_STS */
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dwc3@a600000 {
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compatible = "snps,dwc3";
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reg = <0x0a600000 0xd93c>;
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interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
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snps,has-lpm-erratum;
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snps,hird-threshold = /bits/ 8 <0x10>;
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tx-fifo-resize;
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maximum-speed = "super-speed-plus";
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dr_mode = "otg";
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};
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};
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};
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