271 lines
9.6 KiB
C
271 lines
9.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#ifndef _DT_BINDINGS_CLK_QCOM_GCC_TRINKET_H
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#define _DT_BINDINGS_CLK_QCOM_GCC_TRINKET_H
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/* GCC clocks */
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#define GCC_AHB2PHY_CSI_CLK 0
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#define GCC_AHB2PHY_USB_CLK 1
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#define GCC_APC_VS_CLK 2
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#define GCC_BIMC_GPU_AXI_CLK 3
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#define GCC_BOOT_ROM_AHB_CLK 4
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#define GCC_CAMERA_AHB_CLK 5
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#define GCC_CAMERA_XO_CLK 6
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#define GCC_CAMSS_AHB_CLK_SRC 7
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#define GCC_CAMSS_CCI_AHB_CLK 8
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#define GCC_CAMSS_CCI_CLK 9
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#define GCC_CAMSS_CCI_CLK_SRC 10
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#define GCC_CAMSS_CPHY_CSID0_CLK 11
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#define GCC_CAMSS_CPHY_CSID1_CLK 12
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#define GCC_CAMSS_CPHY_CSID2_CLK 13
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#define GCC_CAMSS_CPHY_CSID3_CLK 14
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#define GCC_CAMSS_CPP_AHB_CLK 15
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#define GCC_CAMSS_CPP_AXI_CLK 16
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#define GCC_CAMSS_CPP_CLK 17
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#define GCC_CAMSS_CPP_CLK_SRC 18
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#define GCC_CAMSS_CPP_VBIF_AHB_CLK 19
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#define GCC_CAMSS_CSI0_AHB_CLK 20
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#define GCC_CAMSS_CSI0_CLK 21
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#define GCC_CAMSS_CSI0_CLK_SRC 22
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#define GCC_CAMSS_CSI0PHYTIMER_CLK 23
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#define GCC_CAMSS_CSI0PHYTIMER_CLK_SRC 24
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#define GCC_CAMSS_CSI0PIX_CLK 25
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#define GCC_CAMSS_CSI0RDI_CLK 26
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#define GCC_CAMSS_CSI1_AHB_CLK 27
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#define GCC_CAMSS_CSI1_CLK 28
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#define GCC_CAMSS_CSI1_CLK_SRC 29
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#define GCC_CAMSS_CSI1PHYTIMER_CLK 30
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#define GCC_CAMSS_CSI1PHYTIMER_CLK_SRC 31
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#define GCC_CAMSS_CSI1PIX_CLK 32
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#define GCC_CAMSS_CSI1RDI_CLK 33
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#define GCC_CAMSS_CSI2_AHB_CLK 34
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#define GCC_CAMSS_CSI2_CLK 35
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#define GCC_CAMSS_CSI2_CLK_SRC 36
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#define GCC_CAMSS_CSI2PHYTIMER_CLK 37
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#define GCC_CAMSS_CSI2PHYTIMER_CLK_SRC 38
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#define GCC_CAMSS_CSI2PIX_CLK 39
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#define GCC_CAMSS_CSI2RDI_CLK 40
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#define GCC_CAMSS_CSI3_AHB_CLK 41
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#define GCC_CAMSS_CSI3_CLK 42
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#define GCC_CAMSS_CSI3_CLK_SRC 43
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#define GCC_CAMSS_CSI3PIX_CLK 44
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#define GCC_CAMSS_CSI3RDI_CLK 45
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#define GCC_CAMSS_CSI_VFE0_CLK 46
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#define GCC_CAMSS_CSI_VFE1_CLK 47
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#define GCC_CAMSS_CSIPHY0_CLK 48
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#define GCC_CAMSS_CSIPHY1_CLK 49
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#define GCC_CAMSS_CSIPHY2_CLK 50
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#define GCC_CAMSS_CSIPHY3_CLK 51
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#define GCC_CAMSS_CSIPHY_CLK_SRC 52
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#define GCC_CAMSS_GP0_CLK 53
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#define GCC_CAMSS_GP0_CLK_SRC 54
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#define GCC_CAMSS_GP1_CLK 55
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#define GCC_CAMSS_GP1_CLK_SRC 56
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#define GCC_CAMSS_ISPIF_AHB_CLK 57
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#define GCC_CAMSS_JPEG_AHB_CLK 58
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#define GCC_CAMSS_JPEG_AXI_CLK 59
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#define GCC_CAMSS_JPEG_CLK 60
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#define GCC_CAMSS_JPEG_CLK_SRC 61
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#define GCC_CAMSS_MCLK0_CLK 62
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#define GCC_CAMSS_MCLK0_CLK_SRC 63
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#define GCC_CAMSS_MCLK1_CLK 64
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#define GCC_CAMSS_MCLK1_CLK_SRC 65
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#define GCC_CAMSS_MCLK2_CLK 66
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#define GCC_CAMSS_MCLK2_CLK_SRC 67
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#define GCC_CAMSS_MCLK3_CLK 68
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#define GCC_CAMSS_MCLK3_CLK_SRC 69
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#define GCC_CAMSS_MICRO_AHB_CLK 70
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#define GCC_CAMSS_THROTTLE_NRT_AXI_CLK 71
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#define GCC_CAMSS_THROTTLE_RT_AXI_CLK 72
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#define GCC_CAMSS_TOP_AHB_CLK 73
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#define GCC_CAMSS_VFE0_AHB_CLK 74
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#define GCC_CAMSS_VFE0_CLK 75
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#define GCC_CAMSS_VFE0_CLK_SRC 76
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#define GCC_CAMSS_VFE0_STREAM_CLK 77
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#define GCC_CAMSS_VFE1_AHB_CLK 78
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#define GCC_CAMSS_VFE1_CLK 79
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#define GCC_CAMSS_VFE1_CLK_SRC 80
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#define GCC_CAMSS_VFE1_STREAM_CLK 81
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#define GCC_CAMSS_VFE_VBIF_AHB_CLK 82
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#define GCC_CAMSS_VFE_VBIF_AXI_CLK 83
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#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 84
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#define GCC_CPUSS_AHB_CLK_SRC 85
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#define GCC_CPUSS_AHB_POSTDIV_CLK_SRC 86
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#define GCC_CPUSS_GNOC_CLK 87
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#define GCC_CPUSS_THROTTLE_CORE_CLK 88
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#define GCC_CPUSS_THROTTLE_XO_CLK 89
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#define GCC_DISP_AHB_CLK 90
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#define GCC_DISP_GPLL0_DIV_CLK_SRC 91
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#define GCC_DISP_HF_AXI_CLK 92
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#define GCC_DISP_THROTTLE_CORE_CLK 93
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#define GCC_DISP_XO_CLK 94
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#define GCC_GP1_CLK 95
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#define GCC_GP1_CLK_SRC 96
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#define GCC_GP2_CLK 97
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#define GCC_GP2_CLK_SRC 98
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#define GCC_GP3_CLK 99
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#define GCC_GP3_CLK_SRC 100
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#define GCC_GPU_CFG_AHB_CLK 101
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#define GCC_GPU_GPLL0_CLK_SRC 102
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#define GCC_GPU_GPLL0_DIV_CLK_SRC 103
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#define GCC_GPU_IREF_CLK 104
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#define GCC_GPU_MEMNOC_GFX_CLK 105
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#define GCC_GPU_SNOC_DVM_GFX_CLK 106
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#define GCC_GPU_THROTTLE_CORE_CLK 107
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#define GCC_GPU_THROTTLE_XO_CLK 108
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#define GCC_PCIE_0_CLKREF_CLK 109
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#define GCC_PDM2_CLK 110
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#define GCC_PDM2_CLK_SRC 111
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#define GCC_PDM_AHB_CLK 112
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#define GCC_PDM_XO4_CLK 113
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#define GCC_PRNG_AHB_CLK 114
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#define GCC_QMIP_CAMERA_NRT_AHB_CLK 115
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#define GCC_QMIP_CAMERA_RT_AHB_CLK 116
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#define GCC_QMIP_CPUSS_CFG_AHB_CLK 117
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#define GCC_QMIP_DISP_AHB_CLK 118
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#define GCC_QMIP_GPU_CFG_AHB_CLK 119
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#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 120
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#define GCC_QUPV3_WRAP0_CORE_2X_CLK 121
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#define GCC_QUPV3_WRAP0_CORE_CLK 122
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#define GCC_QUPV3_WRAP0_S0_CLK 123
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#define GCC_QUPV3_WRAP0_S0_CLK_SRC 124
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#define GCC_QUPV3_WRAP0_S1_CLK 125
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#define GCC_QUPV3_WRAP0_S1_CLK_SRC 126
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#define GCC_QUPV3_WRAP0_S2_CLK 127
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#define GCC_QUPV3_WRAP0_S2_CLK_SRC 128
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#define GCC_QUPV3_WRAP0_S3_CLK 129
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#define GCC_QUPV3_WRAP0_S3_CLK_SRC 130
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#define GCC_QUPV3_WRAP0_S4_CLK 131
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#define GCC_QUPV3_WRAP0_S4_CLK_SRC 132
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#define GCC_QUPV3_WRAP0_S5_CLK 133
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#define GCC_QUPV3_WRAP0_S5_CLK_SRC 134
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#define GCC_QUPV3_WRAP1_CORE_2X_CLK 135
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#define GCC_QUPV3_WRAP1_CORE_CLK 136
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#define GCC_QUPV3_WRAP1_S0_CLK 137
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#define GCC_QUPV3_WRAP1_S0_CLK_SRC 138
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#define GCC_QUPV3_WRAP1_S1_CLK 139
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#define GCC_QUPV3_WRAP1_S1_CLK_SRC 140
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#define GCC_QUPV3_WRAP1_S2_CLK 141
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#define GCC_QUPV3_WRAP1_S2_CLK_SRC 142
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#define GCC_QUPV3_WRAP1_S3_CLK 143
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#define GCC_QUPV3_WRAP1_S3_CLK_SRC 144
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#define GCC_QUPV3_WRAP1_S4_CLK 145
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#define GCC_QUPV3_WRAP1_S4_CLK_SRC 146
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#define GCC_QUPV3_WRAP1_S5_CLK 147
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#define GCC_QUPV3_WRAP1_S5_CLK_SRC 148
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#define GCC_QUPV3_WRAP_0_M_AHB_CLK 149
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#define GCC_QUPV3_WRAP_0_S_AHB_CLK 150
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#define GCC_QUPV3_WRAP_1_M_AHB_CLK 151
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#define GCC_QUPV3_WRAP_1_S_AHB_CLK 152
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#define GCC_RX1_USB2_CLKREF_CLK 153
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#define GCC_SDCC1_AHB_CLK 155
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#define GCC_SDCC1_APPS_CLK 156
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#define GCC_SDCC1_APPS_CLK_SRC 157
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#define GCC_SDCC1_ICE_CORE_CLK 158
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#define GCC_SDCC1_ICE_CORE_CLK_SRC 159
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#define GCC_SDCC2_AHB_CLK 160
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#define GCC_SDCC2_APPS_CLK 161
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#define GCC_SDCC2_APPS_CLK_SRC 162
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#define GCC_SYS_NOC_CPUSS_AHB_CLK 163
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#define GCC_SYS_NOC_UFS_PHY_AXI_CLK 164
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#define GCC_SYS_NOC_USB3_PRIM_AXI_CLK 165
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#define GCC_UFS_MEM_CLKREF_CLK 166
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#define GCC_UFS_PHY_AHB_CLK 167
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#define GCC_UFS_PHY_AXI_CLK 168
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#define GCC_UFS_PHY_AXI_CLK_SRC 169
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#define GCC_UFS_PHY_ICE_CORE_CLK 170
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#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 171
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#define GCC_UFS_PHY_PHY_AUX_CLK 172
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#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 173
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#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 174
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#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 175
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#define GCC_UFS_PHY_UNIPRO_CORE_CLK 176
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#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 177
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#define GCC_USB30_PRIM_MASTER_CLK 178
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#define GCC_USB30_PRIM_MASTER_CLK_SRC 179
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#define GCC_USB30_PRIM_MOCK_UTMI_CLK 180
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#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 181
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#define GCC_USB30_PRIM_SLEEP_CLK 183
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#define GCC_USB3_PRIM_CLKREF_CLK 184
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#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 185
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#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 186
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#define GCC_USB3_PRIM_PHY_PIPE_CLK 187
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#define GCC_VDDA_VS_CLK 188
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#define GCC_VDDCX_VS_CLK 189
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#define GCC_VDDMX_VS_CLK 190
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#define GCC_VIDEO_AHB_CLK 191
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#define GCC_VIDEO_AXI0_CLK 192
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#define GCC_VIDEO_THROTTLE_CORE_CLK 193
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#define GCC_VIDEO_XO_CLK 194
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#define GCC_VS_CTRL_AHB_CLK 195
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#define GCC_VS_CTRL_CLK 196
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#define GCC_VS_CTRL_CLK_SRC 197
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#define GCC_VSENSOR_CLK_SRC 198
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#define GCC_WCSS_VS_CLK 199
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#define GPLL0 200
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#define GPLL0_OUT_AUX2 201
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#define GPLL3 202
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#define GPLL4 203
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#define GPLL5 204
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#define GPLL6 205
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#define GPLL6_OUT_MAIN 206
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#define GPLL7 207
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#define GPLL7_OUT_MAIN 208
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#define GPLL8 209
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#define GPLL8_OUT_MAIN 210
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#define GPLL9 211
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#define GPLL9_OUT_MAIN 212
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#define GCC_MSS_VS_CLK 213
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#define MEASURE_ONLY_MMCC_CLK 214
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#define MEASURE_ONLY_IPA_2X_CLK 215
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/* GCC resets */
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#define GCC_CAMSS_CCI_BCR 0
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#define GCC_CAMSS_CPP_BCR 1
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#define GCC_CAMSS_CPP_TOP_BCR 2
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#define GCC_CAMSS_CSI0_BCR 3
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#define GCC_CAMSS_CSI0PIX_BCR 4
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#define GCC_CAMSS_CSI0RDI_BCR 5
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#define GCC_CAMSS_CSI1_BCR 6
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#define GCC_CAMSS_CSI1PIX_BCR 7
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#define GCC_CAMSS_CSI1RDI_BCR 8
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#define GCC_CAMSS_CSI2_BCR 9
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#define GCC_CAMSS_CSI2PIX_BCR 10
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#define GCC_CAMSS_CSI2RDI_BCR 11
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#define GCC_CAMSS_CSI3_BCR 12
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#define GCC_CAMSS_CSI3PIX_BCR 13
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#define GCC_CAMSS_CSI3RDI_BCR 14
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#define GCC_CAMSS_CSI_VFE0_BCR 15
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#define GCC_CAMSS_CSI_VFE1_BCR 16
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#define GCC_CAMSS_ISPIF_BCR 17
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#define GCC_CAMSS_JPEG_BCR 18
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#define GCC_CAMSS_MICRO_BCR 19
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#define GCC_CAMSS_PHY0_BCR 20
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#define GCC_CAMSS_PHY1_BCR 21
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#define GCC_CAMSS_PHY2_BCR 22
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#define GCC_CAMSS_TOP_BCR 23
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#define GCC_CAMSS_VFE0_BCR 24
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#define GCC_CAMSS_VFE1_BCR 25
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#define GCC_CAMSS_VFE_VBIF_BCR 26
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#define GCC_GPU_BCR 27
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#define GCC_MMSS_BCR 28
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#define GCC_PDM_BCR 29
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#define GCC_PRNG_BCR 30
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#define GCC_QUPV3_WRAPPER_0_BCR 31
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#define GCC_QUPV3_WRAPPER_1_BCR 32
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#define GCC_QUSB2PHY_PRIM_BCR 33
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#define GCC_QUSB2PHY_SEC_BCR 34
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#define GCC_SDCC1_BCR 35
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#define GCC_SDCC2_BCR 36
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#define GCC_UFS_PHY_BCR 37
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#define GCC_USB30_PRIM_BCR 38
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#define GCC_USB_PHY_CFG_AHB2PHY_BCR 39
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#define GCC_VS_BCR 40
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#define GCC_USB3PHY_PHY_PRIM_SP0_BCR 41
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#define GCC_USB3_PHY_PRIM_SP0_BCR 42
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#endif
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