40 lines
1.1 KiB
C
40 lines
1.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2020, The Linux Foundation. All rights reserved.
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* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#ifndef _DT_BINDINGS_CLK_QCOM_NPU_CC_SM8150_H
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#define _DT_BINDINGS_CLK_QCOM_NPU_CC_SM8150_H
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/* NPU_CC clocks */
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#define NPU_CC_PLL0 0
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#define NPU_CC_PLL1 1
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#define NPU_CC_ARMWIC_CORE_CLK 2
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#define NPU_CC_BTO_CORE_CLK 3
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#define NPU_CC_BWMON_CLK 4
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#define NPU_CC_CAL_DP_CDC_CLK 5
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#define NPU_CC_CAL_DP_CLK 6
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#define NPU_CC_CAL_DP_CLK_SRC 7
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#define NPU_CC_COMP_NOC_AXI_CLK 8
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#define NPU_CC_CONF_NOC_AHB_CLK 9
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#define NPU_CC_NPU_CORE_APB_CLK 10
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#define NPU_CC_NPU_CORE_ATB_CLK 11
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#define NPU_CC_NPU_CORE_CLK 12
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#define NPU_CC_NPU_CORE_CLK_SRC 13
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#define NPU_CC_NPU_CORE_CTI_CLK 14
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#define NPU_CC_NPU_CPC_CLK 15
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#define NPU_CC_NPU_CPC_TIMER_CLK 16
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#define NPU_CC_PERF_CNT_CLK 17
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#define NPU_CC_QTIMER_CORE_CLK 18
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#define NPU_CC_SLEEP_CLK 19
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#define NPU_CC_XO_CLK 20
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/* NPU_CC power domains */
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#define NPU_CORE_GDSC 0
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/* NPU_CC resets */
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#define NPU_CC_CAL_DP_BCR 0
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#define NPU_CC_NPU_CORE_BCR 1
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#endif
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