62 lines
1.9 KiB
C
62 lines
1.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2022, 2024 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#ifndef _DT_BINDINGS_CLK_QCOM_NPU_CC_SM8250_H
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#define _DT_BINDINGS_CLK_QCOM_NPU_CC_SM8250_H
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/* NPU_CC clocks */
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#define NPU_CC_PLL0 0
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#define NPU_CC_PLL1 1
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#define NPU_Q6SS_PLL 2
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#define NPU_CC_ATB_CLK 3
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#define NPU_CC_BTO_CORE_CLK 4
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#define NPU_CC_BWMON_CLK 5
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#define NPU_CC_CAL_HM0_CDC_CLK 6
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#define NPU_CC_CAL_HM0_CLK 7
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#define NPU_CC_CAL_HM0_CLK_SRC 8
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#define NPU_CC_CAL_HM0_DPM_IP_CLK 9
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#define NPU_CC_CAL_HM0_PERF_CNT_CLK 10
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#define NPU_CC_CAL_HM1_CDC_CLK 11
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#define NPU_CC_CAL_HM1_CLK 12
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#define NPU_CC_CAL_HM1_CLK_SRC 13
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#define NPU_CC_CAL_HM1_DPM_IP_CLK 14
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#define NPU_CC_CAL_HM1_PERF_CNT_CLK 15
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#define NPU_CC_CORE_CLK 16
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#define NPU_CC_CORE_CLK_SRC 17
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#define NPU_CC_DL_DPM_CLK 18
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#define NPU_CC_DL_LLM_CLK 19
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#define NPU_CC_DPM_CLK 20
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#define NPU_CC_DPM_TEMP_CLK 21
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#define NPU_CC_DPM_XO_CLK 22
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#define NPU_CC_DSP_AHBM_CLK 23
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#define NPU_CC_DSP_AHBS_CLK 24
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#define NPU_CC_DSP_AXI_CLK 25
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#define NPU_CC_DSP_BWMON_AHB_CLK 26
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#define NPU_CC_DSP_BWMON_CLK 27
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#define NPU_CC_ISENSE_CLK 28
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#define NPU_CC_LLM_CLK 29
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#define NPU_CC_LLM_CURR_CLK 30
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#define NPU_CC_LLM_TEMP_CLK 31
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#define NPU_CC_LLM_XO_CLK 32
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#define NPU_CC_LMH_CLK_SRC 33
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#define NPU_CC_NOC_AHB_CLK 34
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#define NPU_CC_NOC_AXI_CLK 35
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#define NPU_CC_NOC_DMA_CLK 36
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#define NPU_CC_RSC_XO_CLK 37
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#define NPU_CC_S2P_CLK 38
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#define NPU_CC_XO_CLK 39
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#define NPU_CC_XO_CLK_SRC 40
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#define NPU_DSP_CORE_CLK_SRC 41
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/* NPU_CC resets */
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#define NPU_CC_CAL_HM0_BCR 0
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#define NPU_CC_CAL_HM1_BCR 1
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#define NPU_CC_CORE_BCR 2
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#define NPU_CC_DSP_BCR 3
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#define NPU_CC_DPM_TEMP_CLK_ARES 4
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#define NPU_CC_LLM_CURR_CLK_ARES 5
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#define NPU_CC_LLM_TEMP_CLK_ARES 6
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#endif
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