57 lines
2.1 KiB
C
57 lines
2.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
|
|
/*
|
|
* Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
|
|
*/
|
|
|
|
#ifndef _DT_BINDINGS_CLK_QCOM_LPASS_AON_CC_SCUBA_H
|
|
#define _DT_BINDINGS_CLK_QCOM_LPASS_AON_CC_SCUBA_H
|
|
|
|
/* LPASS_AON_CC clocks */
|
|
#define LPASS_AON_CC_AHB_TIMEOUT_CLK 0
|
|
#define LPASS_AON_CC_AON_H_CLK 1
|
|
#define LPASS_AON_CC_AUDIO_HM_H_CLK 2
|
|
#define LPASS_AON_CC_AUDIO_HM_SLEEP_CLK 3
|
|
#define LPASS_AON_CC_BUS_ALT_CLK 4
|
|
#define LPASS_AON_CC_CDIV_TX_MCLK_DIV_CLK_SRC 5
|
|
#define LPASS_AON_CC_CDIV_VA_DIV_CLK_SRC 6
|
|
#define LPASS_AON_CC_CPR_CLK 7
|
|
#define LPASS_AON_CC_CPR_CLK_SRC 8
|
|
#define LPASS_AON_CC_CSR_H_CLK 9
|
|
#define LPASS_AON_CC_MAIN_RCG_CLK_SRC 10
|
|
#define LPASS_AON_CC_MCC_ACCESS_CLK 11
|
|
#define LPASS_AON_CC_PDC_GDS_CLK 12
|
|
#define LPASS_AON_CC_PDC_H_CLK 13
|
|
#define LPASS_AON_CC_PLL 14
|
|
#define LPASS_AON_CC_PLL_OUT_AUX 15
|
|
#define LPASS_AON_CC_PLL_OUT_AUX2 16
|
|
#define LPASS_AON_CC_Q6_AHBM_CLK 17
|
|
#define LPASS_AON_CC_Q6_AHBS_CLK 18
|
|
#define LPASS_AON_CC_Q6_ATBM_CLK 19
|
|
#define LPASS_AON_CC_Q6_XO_CLK 20
|
|
#define LPASS_AON_CC_Q6_XO_CLK_SRC 21
|
|
#define LPASS_AON_CC_Q6_XPU2_CLIENT_CLK 22
|
|
#define LPASS_AON_CC_Q6_XPU2_CONFIG_CLK 23
|
|
#define LPASS_AON_CC_QSM_XO_CLK 24
|
|
#define LPASS_AON_CC_RO_CLK 25
|
|
#define LPASS_AON_CC_RO_PLL 26
|
|
#define LPASS_AON_CC_RO_PLL_OUT_EVEN 27
|
|
#define LPASS_AON_CC_RO_PLL_OUT_MAIN 28
|
|
#define LPASS_AON_CC_RSC_HCLK_CLK 29
|
|
#define LPASS_AON_CC_SLEEP_CLK 30
|
|
#define LPASS_AON_CC_SSC_H_CLK 31
|
|
#define LPASS_AON_CC_TX_MCLK_2X_CLK 32
|
|
#define LPASS_AON_CC_TX_MCLK_CLK 33
|
|
#define LPASS_AON_CC_TX_MCLK_RCG_CLK_SRC 34
|
|
#define LPASS_AON_CC_VA_2X_CLK 35
|
|
#define LPASS_AON_CC_VA_CLK 36
|
|
#define LPASS_AON_CC_VA_MEM0_CLK 37
|
|
#define LPASS_AON_CC_VA_RCG_CLK_SRC 38
|
|
#define LPASS_AON_CC_VA_XPU2_CLIENT_CLK 39
|
|
#define LPASS_AON_CC_VS_VDDCX_CLK 40
|
|
#define LPASS_AON_CC_VS_VDDCX_CLK_SRC 41
|
|
#define LPASS_AON_CC_VS_VDDMX_CLK 42
|
|
#define LPASS_AON_CC_VS_VDDMX_CLK_SRC 43
|
|
#define LPASS_QDSP6SS_SLEEP_CLK 44
|
|
#define LPASS_QDSP6SS_XO_CLK 45
|
|
|
|
#endif
|