55 lines
1.9 KiB
C
55 lines
1.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PM8550VX_H
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#define _DT_BINDINGS_QCOM_SPMI_VADC_PM8550VX_H
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#ifndef PM8550VS_C_SID
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#define PM8550VS_C_SID 2
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#endif
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#ifndef PM8550VS_D_SID
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#define PM8550VS_D_SID 3
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#endif
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#ifndef PM8550VS_E_SID
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#define PM8550VS_E_SID 4
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#endif
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#ifndef PM8550VS_G_SID
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#define PM8550VS_G_SID 6
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#endif
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#ifndef PM8550VE_SID
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#define PM8550VE_SID 5
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#endif
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/* ADC channels for PM8550VX_ADC for PMIC5 Gen3 */
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#define PM8550VS_C_ADC5_GEN3_OFFSET_REF (PM8550VS_C_SID << 8 | 0x00)
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#define PM8550VS_C_ADC5_GEN3_1P25VREF (PM8550VS_C_SID << 8 | 0x01)
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#define PM8550VS_C_ADC5_GEN3_VREF_VADC (PM8550VS_C_SID << 8 | 0X02)
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#define PM8550VS_C_ADC5_GEN3_DIE_TEMP (PM8550VS_C_SID << 8 | 0x03)
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#define PM8550VS_D_ADC5_GEN3_OFFSET_REF (PM8550VS_D_SID << 8 | 0x00)
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#define PM8550VS_D_ADC5_GEN3_1P25VREF (PM8550VS_D_SID << 8 | 0x01)
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#define PM8550VS_D_ADC5_GEN3_VREF_VADC (PM8550VS_D_SID << 8 | 0X02)
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#define PM8550VS_D_ADC5_GEN3_DIE_TEMP (PM8550VS_D_SID << 8 | 0x03)
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#define PM8550VS_E_ADC5_GEN3_OFFSET_REF (PM8550VS_E_SID << 8 | 0x00)
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#define PM8550VS_E_ADC5_GEN3_1P25VREF (PM8550VS_E_SID << 8 | 0x01)
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#define PM8550VS_E_ADC5_GEN3_VREF_VADC (PM8550VS_E_SID << 8 | 0X02)
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#define PM8550VS_E_ADC5_GEN3_DIE_TEMP (PM8550VS_E_SID << 8 | 0x03)
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#define PM8550VS_G_ADC5_GEN3_OFFSET_REF (PM8550VS_G_SID << 8 | 0x00)
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#define PM8550VS_G_ADC5_GEN3_1P25VREF (PM8550VS_G_SID << 8 | 0x01)
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#define PM8550VS_G_ADC5_GEN3_VREF_VADC (PM8550VS_G_SID << 8 | 0X02)
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#define PM8550VS_G_ADC5_GEN3_DIE_TEMP (PM8550VS_G_SID << 8 | 0x03)
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#define PM8550VE_ADC5_GEN3_OFFSET_REF (PM8550VE_SID << 8 | 0x00)
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#define PM8550VE_ADC5_GEN3_1P25VREF (PM8550VE_SID << 8 | 0x01)
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#define PM8550VE_ADC5_GEN3_VREF_VADC (PM8550VE_SID << 8 | 0X02)
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#define PM8550VE_ADC5_GEN3_DIE_TEMP (PM8550VE_SID << 8 | 0x03)
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#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PM8550VX_H */
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