146 lines
7.5 KiB
C
146 lines
7.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PM8775_H
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#define _DT_BINDINGS_QCOM_SPMI_VADC_PM8775_H
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#ifndef PM8775_1_SID
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#define PM8775_1_SID 0
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#endif
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#ifndef PM8775_2_SID
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#define PM8775_2_SID 2
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#endif
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#ifndef PM8775_3_SID
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#define PM8775_3_SID 4
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#endif
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#ifndef PM8775_4_SID
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#define PM8775_4_SID 6
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#endif
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/* ADC channels for PM8775_1_ADC for PMIC5 Gen3 */
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#define PM8775_1_ADC5_GEN3_OFFSET_REF (PM8775_1_SID << 8 | 0x0)
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#define PM8775_1_ADC5_GEN3_1P25VREF (PM8775_1_SID << 8 | 0x01)
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#define PM8775_1_ADC5_GEN3_VREF_VADC (PM8775_1_SID << 8 | 0x02)
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#define PM8775_1_ADC5_GEN3_DIE_TEMP (PM8775_1_SID << 8 | 0x03)
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#define PM8775_1_ADC5_GEN3_AMUX1_THM (PM8775_1_SID << 8 | 0x04)
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#define PM8775_1_ADC5_GEN3_AMUX2_THM (PM8775_1_SID << 8 | 0x05)
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#define PM8775_1_ADC5_GEN3_AMUX3_THM (PM8775_1_SID << 8 | 0x06)
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#define PM8775_1_ADC5_GEN3_AMUX4_THM (PM8775_1_SID << 8 | 0x07)
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#define PM8775_1_ADC5_GEN3_AMUX5_THM (PM8775_1_SID << 8 | 0x08)
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#define PM8775_1_ADC5_GEN3_AMUX6_THM (PM8775_1_SID << 8 | 0x09)
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#define PM8775_1_ADC5_GEN3_AMUX1_GPIO9 (PM8775_1_SID << 8 | 0x0a)
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#define PM8775_1_ADC5_GEN3_AMUX2_GPIO10 (PM8775_1_SID << 8 | 0x0b)
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#define PM8775_1_ADC5_GEN3_AMUX3_GPIO11 (PM8775_1_SID << 8 | 0x0c)
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#define PM8775_1_ADC5_GEN3_AMUX4_GPIO12 (PM8775_1_SID << 8 | 0x0d)
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/* 100k pull-up2 */
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#define PM8775_1_ADC5_GEN3_AMUX1_THM_100K_PU (PM8775_1_SID << 8 | 0x44)
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#define PM8775_1_ADC5_GEN3_AMUX2_THM_100K_PU (PM8775_1_SID << 8 | 0x45)
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#define PM8775_1_ADC5_GEN3_AMUX3_THM_100K_PU (PM8775_1_SID << 8 | 0x46)
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#define PM8775_1_ADC5_GEN3_AMUX4_THM_100K_PU (PM8775_1_SID << 8 | 0x47)
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#define PM8775_1_ADC5_GEN3_AMUX5_THM_100K_PU (PM8775_1_SID << 8 | 0x48)
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#define PM8775_1_ADC5_GEN3_AMUX6_THM_100K_PU (PM8775_1_SID << 8 | 0x49)
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#define PM8775_1_ADC5_GEN3_AMUX1_GPIO9_100K_PU (PM8775_1_SID << 8 | 0x4a)
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#define PM8775_1_ADC5_GEN3_AMUX2_GPIO10_100K_PU (PM8775_1_SID << 8 | 0x4b)
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#define PM8775_1_ADC5_GEN3_AMUX3_GPIO11_100K_PU (PM8775_1_SID << 8 | 0x4c)
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#define PM8775_1_ADC5_GEN3_AMUX4_GPIO12_100K_PU (PM8775_1_SID << 8 | 0x4d)
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#define PM8775_1_ADC5_GEN3_VPH_PWR (PM8775_1_SID << 8 | 0x8e)
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/* ADC channels for PM8775_2_ADC for PMIC5 Gen3 */
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#define PM8775_2_ADC5_GEN3_OFFSET_REF (PM8775_2_SID << 8 | 0x0)
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#define PM8775_2_ADC5_GEN3_1P25VREF (PM8775_2_SID << 8 | 0x01)
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#define PM8775_2_ADC5_GEN3_VREF_VADC (PM8775_2_SID << 8 | 0x02)
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#define PM8775_2_ADC5_GEN3_DIE_TEMP (PM8775_2_SID << 8 | 0x03)
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#define PM8775_2_ADC5_GEN3_AMUX1_THM (PM8775_2_SID << 8 | 0x04)
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#define PM8775_2_ADC5_GEN3_AMUX2_THM (PM8775_2_SID << 8 | 0x05)
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#define PM8775_2_ADC5_GEN3_AMUX3_THM (PM8775_2_SID << 8 | 0x06)
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#define PM8775_2_ADC5_GEN3_AMUX4_THM (PM8775_2_SID << 8 | 0x07)
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#define PM8775_2_ADC5_GEN3_AMUX5_THM (PM8775_2_SID << 8 | 0x08)
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#define PM8775_2_ADC5_GEN3_AMUX6_THM (PM8775_2_SID << 8 | 0x09)
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#define PM8775_2_ADC5_GEN3_AMUX1_GPIO9 (PM8775_2_SID << 8 | 0x0a)
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#define PM8775_2_ADC5_GEN3_AMUX2_GPIO10 (PM8775_2_SID << 8 | 0x0b)
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#define PM8775_2_ADC5_GEN3_AMUX3_GPIO11 (PM8775_2_SID << 8 | 0x0c)
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#define PM8775_2_ADC5_GEN3_AMUX4_GPIO12 (PM8775_2_SID << 8 | 0x0d)
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/* 100k pull-up2 */
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#define PM8775_2_ADC5_GEN3_AMUX1_THM_100K_PU (PM8775_2_SID << 8 | 0x44)
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#define PM8775_2_ADC5_GEN3_AMUX2_THM_100K_PU (PM8775_2_SID << 8 | 0x45)
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#define PM8775_2_ADC5_GEN3_AMUX3_THM_100K_PU (PM8775_2_SID << 8 | 0x46)
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#define PM8775_2_ADC5_GEN3_AMUX4_THM_100K_PU (PM8775_2_SID << 8 | 0x47)
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#define PM8775_2_ADC5_GEN3_AMUX5_THM_100K_PU (PM8775_2_SID << 8 | 0x48)
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#define PM8775_2_ADC5_GEN3_AMUX6_THM_100K_PU (PM8775_2_SID << 8 | 0x49)
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#define PM8775_2_ADC5_GEN3_AMUX1_GPIO9_100K_PU (PM8775_2_SID << 8 | 0x4a)
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#define PM8775_2_ADC5_GEN3_AMUX2_GPIO10_100K_PU (PM8775_2_SID << 8 | 0x4b)
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#define PM8775_2_ADC5_GEN3_AMUX3_GPIO11_100K_PU (PM8775_2_SID << 8 | 0x4c)
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#define PM8775_2_ADC5_GEN3_AMUX4_GPIO12_100K_PU (PM8775_2_SID << 8 | 0x4d)
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#define PM8775_2_ADC5_GEN3_VPH_PWR (PM8775_2_SID << 8 | 0x8e)
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/* ADC channels for PM8775_3_ADC for PMIC5 Gen3 */
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#define PM8775_3_ADC5_GEN3_OFFSET_REF (PM8775_3_SID << 8 | 0x0)
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#define PM8775_3_ADC5_GEN3_1P25VREF (PM8775_3_SID << 8 | 0x01)
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#define PM8775_3_ADC5_GEN3_VREF_VADC (PM8775_3_SID << 8 | 0x02)
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#define PM8775_3_ADC5_GEN3_DIE_TEMP (PM8775_3_SID << 8 | 0x03)
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#define PM8775_3_ADC5_GEN3_AMUX1_THM (PM8775_3_SID << 8 | 0x04)
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#define PM8775_3_ADC5_GEN3_AMUX2_THM (PM8775_3_SID << 8 | 0x05)
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#define PM8775_3_ADC5_GEN3_AMUX3_THM (PM8775_3_SID << 8 | 0x06)
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#define PM8775_3_ADC5_GEN3_AMUX4_THM (PM8775_3_SID << 8 | 0x07)
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#define PM8775_3_ADC5_GEN3_AMUX5_THM (PM8775_3_SID << 8 | 0x08)
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#define PM8775_3_ADC5_GEN3_AMUX6_THM (PM8775_3_SID << 8 | 0x09)
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#define PM8775_3_ADC5_GEN3_AMUX1_GPIO9 (PM8775_3_SID << 8 | 0x0a)
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#define PM8775_3_ADC5_GEN3_AMUX2_GPIO10 (PM8775_3_SID << 8 | 0x0b)
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#define PM8775_3_ADC5_GEN3_AMUX3_GPIO11 (PM8775_3_SID << 8 | 0x0c)
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#define PM8775_3_ADC5_GEN3_AMUX4_GPIO12 (PM8775_3_SID << 8 | 0x0d)
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/* 100k pull-up2 */
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#define PM8775_3_ADC5_GEN3_AMUX1_THM_100K_PU (PM8775_3_SID << 8 | 0x44)
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#define PM8775_3_ADC5_GEN3_AMUX2_THM_100K_PU (PM8775_3_SID << 8 | 0x45)
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#define PM8775_3_ADC5_GEN3_AMUX3_THM_100K_PU (PM8775_3_SID << 8 | 0x46)
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#define PM8775_3_ADC5_GEN3_AMUX4_THM_100K_PU (PM8775_3_SID << 8 | 0x47)
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#define PM8775_3_ADC5_GEN3_AMUX5_THM_100K_PU (PM8775_3_SID << 8 | 0x48)
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#define PM8775_3_ADC5_GEN3_AMUX6_THM_100K_PU (PM8775_3_SID << 8 | 0x49)
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#define PM8775_3_ADC5_GEN3_AMUX1_GPIO9_100K_PU (PM8775_3_SID << 8 | 0x4a)
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#define PM8775_3_ADC5_GEN3_AMUX2_GPIO10_100K_PU (PM8775_3_SID << 8 | 0x4b)
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#define PM8775_3_ADC5_GEN3_AMUX3_GPIO11_100K_PU (PM8775_3_SID << 8 | 0x4c)
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#define PM8775_3_ADC5_GEN3_AMUX4_GPIO12_100K_PU (PM8775_3_SID << 8 | 0x4d)
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#define PM8775_3_ADC5_GEN3_VPH_PWR (PM8775_3_SID << 8 | 0x8e)
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/* ADC channels for PM8775_4_ADC for PMIC5 Gen3 */
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#define PM8775_4_ADC5_GEN3_OFFSET_REF (PM8775_4_SID << 8 | 0x0)
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#define PM8775_4_ADC5_GEN3_1P25VREF (PM8775_4_SID << 8 | 0x01)
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#define PM8775_4_ADC5_GEN3_VREF_VADC (PM8775_4_SID << 8 | 0x02)
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#define PM8775_4_ADC5_GEN3_DIE_TEMP (PM8775_4_SID << 8 | 0x03)
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#define PM8775_4_ADC5_GEN3_AMUX1_THM (PM8775_4_SID << 8 | 0x04)
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#define PM8775_4_ADC5_GEN3_AMUX2_THM (PM8775_4_SID << 8 | 0x05)
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#define PM8775_4_ADC5_GEN3_AMUX3_THM (PM8775_4_SID << 8 | 0x06)
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#define PM8775_4_ADC5_GEN3_AMUX4_THM (PM8775_4_SID << 8 | 0x07)
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#define PM8775_4_ADC5_GEN3_AMUX5_THM (PM8775_4_SID << 8 | 0x08)
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#define PM8775_4_ADC5_GEN3_AMUX6_THM (PM8775_4_SID << 8 | 0x09)
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#define PM8775_4_ADC5_GEN3_AMUX1_GPIO9 (PM8775_4_SID << 8 | 0x0a)
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#define PM8775_4_ADC5_GEN3_AMUX2_GPIO10 (PM8775_4_SID << 8 | 0x0b)
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#define PM8775_4_ADC5_GEN3_AMUX3_GPIO11 (PM8775_4_SID << 8 | 0x0c)
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#define PM8775_4_ADC5_GEN3_AMUX4_GPIO12 (PM8775_4_SID << 8 | 0x0d)
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/* 100k pull-up2 */
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#define PM8775_4_ADC5_GEN3_AMUX1_THM_100K_PU (PM8775_4_SID << 8 | 0x44)
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#define PM8775_4_ADC5_GEN3_AMUX2_THM_100K_PU (PM8775_4_SID << 8 | 0x45)
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#define PM8775_4_ADC5_GEN3_AMUX3_THM_100K_PU (PM8775_4_SID << 8 | 0x46)
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#define PM8775_4_ADC5_GEN3_AMUX4_THM_100K_PU (PM8775_4_SID << 8 | 0x47)
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#define PM8775_4_ADC5_GEN3_AMUX5_THM_100K_PU (PM8775_4_SID << 8 | 0x48)
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#define PM8775_4_ADC5_GEN3_AMUX6_THM_100K_PU (PM8775_4_SID << 8 | 0x49)
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#define PM8775_4_ADC5_GEN3_AMUX1_GPIO9_100K_PU (PM8775_4_SID << 8 | 0x4a)
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#define PM8775_4_ADC5_GEN3_AMUX2_GPIO10_100K_PU (PM8775_4_SID << 8 | 0x4b)
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#define PM8775_4_ADC5_GEN3_AMUX3_GPIO11_100K_PU (PM8775_4_SID << 8 | 0x4c)
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#define PM8775_4_ADC5_GEN3_AMUX4_GPIO12_100K_PU (PM8775_4_SID << 8 | 0x4d)
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#define PM8775_4_ADC5_GEN3_VPH_PWR (PM8775_4_SID << 8 | 0x8e)
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#endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PM8775_H */
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