64 lines
2.9 KiB
C
64 lines
2.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
|
|
/*
|
|
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
|
|
*/
|
|
|
|
#ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PMX35_H
|
|
#define _DT_BINDINGS_QCOM_SPMI_VADC_PMX35_H
|
|
|
|
#ifndef PMX35_SID
|
|
#define PMX35_SID 0
|
|
#endif
|
|
|
|
/* ADC channels for PMX35_ADC for PMIC5 Gen3 */
|
|
#define PMX35_ADC5_GEN3_OFFSET_REF (PMX35_SID << 0 | 0x00)
|
|
#define PMX35_ADC5_GEN3_1P25VREF (PMX35_SID << 0 | 0X01)
|
|
#define PMX35_ADC5_GEN3_VREF_VADC (PMX35_SID << 0 | 0x02)
|
|
#define PMX35_ADC5_GEN3_DIE_TEMP (PMX35_SID << 0 | 0x03)
|
|
|
|
#define PMX35_ADC5_GEN3_AMUX_THM1 (PMX35_SID << 0 | 0x04)
|
|
#define PMX35_ADC5_GEN3_AMUX_THM2 (PMX35_SID << 0 | 0x05)
|
|
#define PMX35_ADC5_GEN3_AMUX_THM3 (PMX35_SID << 0 | 0x06)
|
|
#define PMX35_ADC5_GEN3_AMUX_THM4 (PMX35_SID << 0 | 0x07)
|
|
#define PMX35_ADC5_GEN3_AMUX_THM5 (PMX35_SID << 0 | 0x08)
|
|
#define PMX35_ADC5_GEN3_AMUX1_GPIO4 (PMX35_SID << 0 | 0x0a)
|
|
#define PMX35_ADC5_GEN3_AMUX2_GPIO5 (PMX35_SID << 0 | 0x0b)
|
|
#define PMX35_ADC5_GEN3_AMUX3_GPIO6 (PMX35_SID << 0 | 0x0c)
|
|
|
|
/* 30K pull-up */
|
|
#define PMX35_ADC5_GEN3_AMUX_THM1_30K_PU (PMX75_SID << 8 | 0x24)
|
|
#define PMX35_ADC5_GEN3_AMUX_THM2_30K_PU (PMX75_SID << 8 | 0x25)
|
|
#define PMX35_ADC5_GEN3_AMUX_THM3_30K_PU (PMX75_SID << 8 | 0x26)
|
|
#define PMX35_ADC5_GEN3_AMUX_THM4_30K_PU (PMX75_SID << 8 | 0x27)
|
|
#define PMX35_ADC5_GEN3_AMUX_THM5_30K_PU (PMX75_SID << 8 | 0x28)
|
|
#define PMX35_ADC5_GEN3_AMUX1_GPIO4_30K_PU (PMX75_SID << 8 | 0x2a)
|
|
#define PMX35_ADC5_GEN3_AMUX2_GPIO5_30K_PU (PMX75_SID << 8 | 0x2b)
|
|
#define PMX35_ADC5_GEN3_AMUX3_GPIO6_30K_PU (PMX75_SID << 8 | 0x2c)
|
|
|
|
/* 100K pull-up */
|
|
#define PMX35_ADC5_GEN3_AMUX_THM1_100K_PU (PMX35_SID << 0 | 0x44)
|
|
#define PMX35_ADC5_GEN3_AMUX_THM2_100K_PU (PMX35_SID << 0 | 0x45)
|
|
#define PMX35_ADC5_GEN3_AMUX_THM3_100K_PU (PMX35_SID << 0 | 0x46)
|
|
#define PMX35_ADC5_GEN3_AMUX_THM4_100K_PU (PMX35_SID << 0 | 0x47)
|
|
#define PMX35_ADC5_GEN3_AMUX_THM5_100K_PU (PMX35_SID << 0 | 0x48)
|
|
#define PMX35_ADC5_GEN3_AMUX1_GPIO4_100K_PU (PMX35_SID << 0 | 0x4a)
|
|
#define PMX35_ADC5_GEN3_AMUX2_GPIO5_100K_PU (PMX35_SID << 0 | 0x4b)
|
|
#define PMX35_ADC5_GEN3_AMUX3_GPIO6_100K_PU (PMX35_SID << 0 | 0x4c)
|
|
|
|
/* 400K pull-up */
|
|
#define PMX35_ADC5_GEN3_AMUX_THM1_400K_PU (PMX75_SID << 8 | 0x64)
|
|
#define PMX35_ADC5_GEN3_AMUX_THM2_400K_PU (PMX75_SID << 8 | 0x65)
|
|
#define PMX35_ADC5_GEN3_AMUX_THM3_400K_PU (PMX75_SID << 8 | 0x66)
|
|
#define PMX35_ADC5_GEN3_AMUX_THM4_400K_PU (PMX75_SID << 8 | 0x67)
|
|
#define PMX35_ADC5_GEN3_AMUX_THM5_400K_PU (PMX75_SID << 8 | 0x68)
|
|
#define PMX35_ADC5_GEN3_AMUX1_GPIO4_400K_PU (PMX75_SID << 8 | 0x6a)
|
|
#define PMX35_ADC5_GEN3_AMUX2_GPIO5_400K_PU (PMX75_SID << 8 | 0x6b)
|
|
#define PMX35_ADC5_GEN3_AMUX3_GPIO6_400K_PU (PMX75_SID << 8 | 0x6c)
|
|
|
|
/* 1/3 Divider */
|
|
#define PMX35_ADC5_GEN3_AMUX2_GPIO5_DIV3 (PMX35_SID << 0 | 0x8b)
|
|
#define PMX35_ADC5_GEN3_AMUX3_GPIO6_DIV3 (PMX35_SID << 0 | 0x8c)
|
|
|
|
#define PMX35_ADC5_GEN3_VPH_PWR (PMX35_SID << 0 | 0x8e)
|
|
|
|
#endif /* __DT_BINDINGS_QCOM_SPMI_VADC_PMX35_H */
|