88 lines
3.3 KiB
Text
88 lines
3.3 KiB
Text
GENI based Qualcomm Technologies Inc Universal Peripheral version 3 (QUPv3)
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Serial Peripheral Interface (SPI)
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The QUP v3 core is a GENI based AHB slave that provides a common data path
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(an output FIFO and an input FIFO) for serial peripheral interface (SPI)
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mini-core.
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SPI in master mode supports up to 50MHz, up to four chip selects, programmable
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data path from 4 bits to 32 bits and numerous protocol variants.
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Required properties:
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- compatible: Should contain "qcom,spi-geni"
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- reg: Should contain base register location and length
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- interrupts: Interrupt number used by this controller
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- clocks: Should contain the core clock and the AHB clock.
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- clock-names: Should be "core" for the core clock and "iface" for the
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AHB clock.
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- pinctrl-names: Property should contain "default" and "sleep" for the
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pin configurations during the usecase and during idle.
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- pinctrl-x: phandle to the default/sleep pin configurations.
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- #address-cells: Number of cells required to define a chip select
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address on the SPI bus. Should be set to 1.
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- #size-cells: Should be zero.
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- spi-max-frequency: Specifies maximum SPI clock frequency,
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Units - Hz. Definition as per
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Documentation/devicetree/bindings/spi/spi-bus.txt
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- qcom,wrapper-core: Wrapper QUPv3 core containing this SPI controller.
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Optional properties:
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- qcom,rt: Specifies if the framework worker thread for this
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controller device should have "real-time" priority.
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- qcom,disable-autosuspend: Specifies to disable runtime PM auto suspend.
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- qcom,disable-dma: Set this flag to use FIFO mode only.
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- qcom,shared_ee: Specifies that this serial engine is shared between
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execution environments.
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- qcom,shared_se: Specifies that this serial engine is shared simultaneously
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between execution environments. A true multi-EE usecase.
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- qcom,le_vm: Specifies that this serial engine is operating in a trusted VM.
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- qcom,xfer-timeout-offset: Adds extra timeout offset on top driver calculated timeout.
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Depending on the use case and system latencies, the client can
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configure this.
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Unit - ms.
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SPI slave nodes must be children of the SPI master node and can contain
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the following properties.
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Required properties:
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- compatible: Should contain:
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"qcom,spi-msm-codec-slave" for external codec control
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- reg: Chip select address of device.
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- spi-max-frequency: Maximum SPI clocking speed of device in Hz.
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Optional properties:
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- spi-cpha: Empty property indicating device requires
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shifted clock phase (CPHA) mode.
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- qcom,slv-ctrl : Set this flag to configure QUPV3 as SPI slave controller.
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Other optional properties described in
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Documentation/devicetree/bindings/spi/spi-bus.txt
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Example:
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qupv3_spi10: spi@a84000 {
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compatible = "qcom,spi-geni";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0xa84000 0x4000>;
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reg-names = "se_phys";
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clock-names = "se-clk", "m-ahb", "s-ahb";
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clocks = <&clock_gcc GCC_QUPV3_WRAP0_S0_CLK>,
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<&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
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<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
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pinctrl-names = "default", "sleep";
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pinctrl-0 = <&qup_1_spi_2_active>;
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pinctrl-1 = <&qup_1_spi_2_sleep>;
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interrupts = <GIC_SPI 354 0>;
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spi-max-frequency = <19200000>;
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qcom,wrapper-core = <&qupv3_0>;
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dev@0 {
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compatible = "dummy,slave";
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reg = <0>;
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spi-max-frequency = <9600000>;
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};
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};
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