563 lines
20 KiB
Text
563 lines
20 KiB
Text
#include <dt-bindings/clock/qcom,gcc-sm8250.h>
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#include <dt-bindings/phy/qcom,kona-qmp-usb3.h>
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&soc {
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/* Primary USB port related controller */
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usb0: ssusb@a600000 {
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compatible = "qcom,dwc-usb3-msm";
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reg = <0x0a600000 0x100000>;
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reg-names = "core_base";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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interrupts-extended = <&pdc 14 IRQ_TYPE_EDGE_RISING>,
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<&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
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<&pdc 17 IRQ_TYPE_LEVEL_HIGH>,
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<&pdc 15 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "dp_hs_phy_irq", "pwr_event_irq",
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"ss_phy_irq", "dm_hs_phy_irq";
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qcom,use-pdc-interrupts;
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USB3_GDSC-supply = <&usb30_prim_gdsc>;
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dpdm-supply = <&usb2_phy0>;
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clocks = <&gcc GCC_USB30_PRIM_MASTER_CLK>,
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<&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
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<&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
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<&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
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<&gcc GCC_USB30_PRIM_SLEEP_CLK>,
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/*
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* GCC_USB3_SEC_CLKREF_EN provides ref_clk for both
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* USB instances.
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*/
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<&gcc GCC_USB3_SEC_CLKREF_EN>;
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clock-names = "core_clk", "iface_clk", "bus_aggr_clk",
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"utmi_clk", "sleep_clk", "xo";
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resets = <&gcc GCC_USB30_PRIM_BCR>;
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reset-names = "core_reset";
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qcom,core-clk-rate = <200000000>;
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qcom,core-clk-rate-hs = <66666667>;
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qcom,num-gsi-evt-buffs = <0x3>;
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qcom,gsi-reg-offset =
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<0x0fc /* GSI_GENERAL_CFG */
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0x110 /* GSI_DBL_ADDR_L */
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0x120 /* GSI_DBL_ADDR_H */
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0x130 /* GSI_RING_BASE_ADDR_L */
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0x144 /* GSI_RING_BASE_ADDR_H */
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0x1a4>; /* GSI_IF_STS */
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interconnect-names = "usb-ddr", "usb-ipa", "ddr-usb";
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interconnects = <&aggre1_noc MASTER_USB3_0 &mc_virt SLAVE_EBI1>,
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<&aggre1_noc MASTER_USB3_0 &config_noc SLAVE_IPA_CFG>,
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<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_USB3_0>;
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qcom,interconnect-values-nom = /* NOMINAL Votes */
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<1000000 6500000>,
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<0 2400>,
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<0 40000>;
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qcom,interconnect-values-svs = /* SVS Votes */
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<240000 1000000>,
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<0 2400>,
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<0 40000>;
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dwc0: dwc3@a600000 {
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compatible = "snps,dwc3";
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reg = <0x0a600000 0xd93c>;
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iommus = <&apps_smmu 0x0 0x0>;
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qcom,iommu-dma = "atomic";
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qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>;
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interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
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usb-phy = <&usb2_phy0>, <&usb_qmp_dp_phy>;
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snps,has-lpm-erratum;
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snps,hird-threshold = /bits/ 8 <0x10>;
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snps,usb3_lpm_capable;
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snps,dis-u1-entry-quirk;
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snps,dis-u2-entry-quirk;
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snps,dis_u2_susphy_quirk;
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tx-fifo-resize;
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maximum-speed = "super-speed-plus";
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dr_mode = "otg";
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usb-role-switch;
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};
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qcom,usbbam@a704000 {
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compatible = "qcom,usb-bam-msm";
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reg = <0xa704000 0x17000>;
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interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
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qcom,usb-bam-fifo-baseaddr = <0x146bb000>;
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qcom,usb-bam-num-pipes = <4>;
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qcom,disable-clk-gating;
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qcom,usb-bam-override-threshold = <0x4001>;
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qcom,usb-bam-max-mbps-highspeed = <400>;
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qcom,usb-bam-max-mbps-superspeed = <3600>;
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qcom,reset-bam-on-connect;
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qcom,pipe0 {
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label = "ssusb-qdss-in-0";
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qcom,usb-bam-mem-type = <2>;
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qcom,dir = <1>;
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qcom,pipe-num = <0>;
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qcom,peer-bam = <0>;
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qcom,peer-bam-physical-address = <0x6064000>;
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qcom,src-bam-pipe-index = <0>;
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qcom,dst-bam-pipe-index = <0>;
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qcom,data-fifo-offset = <0x0>;
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qcom,data-fifo-size = <0x1800>;
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qcom,descriptor-fifo-offset = <0x1800>;
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qcom,descriptor-fifo-size = <0x800>;
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};
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};
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};
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/* Primary USB port related High Speed PHY */
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usb2_phy0: hsphy@88e3000 {
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compatible = "qcom,usb-hsphy-snps-femto";
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reg = <0x88e3000 0x110>,
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<0x088e2000 0x4>;
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reg-names = "hsusb_phy_base",
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"eud_enable_reg";
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vdd-supply = <&pm8150_l5>;
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vdda18-supply = <&pm8150_l12>;
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vdda33-supply = <&pm8150_l2>;
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qcom,vdd-voltage-level = <0 880000 880000>;
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clocks = <&rpmhcc RPMH_CXO_CLK>;
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clock-names = "ref_clk_src";
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resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
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reset-names = "phy_reset";
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qcom,param-override-seq = <0x43 0x70>;
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};
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/* Primary USB port related QMP USB DP Combo PHY */
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usb_qmp_dp_phy: ssphy@88e8000 {
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compatible = "qcom,usb-ssphy-qmp-dp-combo";
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reg = <0x88e8000 0x3000>;
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reg-names = "qmp_phy_base";
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vdd-supply = <&pm8150_l18>;
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qcom,vdd-voltage-level = <0 912000 912000>;
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qcom,vdd-max-load-uA = <47000>;
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core-supply = <&pm8150_l9>;
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qcom,qmp-phy-init-seq =
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/* <reg_offset, value, delay> */
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<USB3_DP_QSERDES_COM_SSC_EN_CENTER 0x01
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USB3_DP_QSERDES_COM_SSC_PER1 0x31
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USB3_DP_QSERDES_COM_SSC_PER2 0x01
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USB3_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE0 0xDE
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USB3_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE0 0x07
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USB3_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE1 0xDE
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USB3_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE1 0x07
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USB3_DP_QSERDES_COM_SYSCLK_BUF_ENABLE 0x0A
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USB3_DP_QSERDES_COM_CMN_IPTRIM 0x20
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USB3_DP_QSERDES_COM_CP_CTRL_MODE0 0x06
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USB3_DP_QSERDES_COM_CP_CTRL_MODE1 0x06
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USB3_DP_QSERDES_COM_PLL_RCTRL_MODE0 0x16
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USB3_DP_QSERDES_COM_PLL_RCTRL_MODE1 0x16
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USB3_DP_QSERDES_COM_PLL_CCTRL_MODE0 0x36
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USB3_DP_QSERDES_COM_PLL_CCTRL_MODE1 0x36
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USB3_DP_QSERDES_COM_SYSCLK_EN_SEL 0x1A
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USB3_DP_QSERDES_COM_LOCK_CMP_EN 0x04
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USB3_DP_QSERDES_COM_LOCK_CMP1_MODE0 0x14
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USB3_DP_QSERDES_COM_LOCK_CMP2_MODE0 0x34
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USB3_DP_QSERDES_COM_LOCK_CMP1_MODE1 0x34
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USB3_DP_QSERDES_COM_LOCK_CMP2_MODE1 0x82
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USB3_DP_QSERDES_COM_DEC_START_MODE0 0x82
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USB3_DP_QSERDES_COM_DEC_START_MODE1 0x82
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USB3_DP_QSERDES_COM_DIV_FRAC_START1_MODE0 0xAB
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USB3_DP_QSERDES_COM_DIV_FRAC_START2_MODE0 0xEA
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USB3_DP_QSERDES_COM_DIV_FRAC_START3_MODE0 0x02
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USB3_DP_QSERDES_COM_DIV_FRAC_START1_MODE1 0xAB
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USB3_DP_QSERDES_COM_DIV_FRAC_START2_MODE1 0xEA
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USB3_DP_QSERDES_COM_DIV_FRAC_START3_MODE1 0x02
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USB3_DP_QSERDES_COM_VCO_TUNE_MAP 0x02
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USB3_DP_QSERDES_COM_VCO_TUNE1_MODE0 0x24
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USB3_DP_QSERDES_COM_VCO_TUNE1_MODE1 0x24
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USB3_DP_QSERDES_COM_VCO_TUNE2_MODE1 0x02
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USB3_DP_QSERDES_COM_HSCLK_SEL 0x01
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USB3_DP_QSERDES_COM_CORECLK_DIV_MODE1 0x08
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USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0xCA
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USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1E
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USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0xCA
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USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1E
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USB3_DP_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL 0x11
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USB3_DP_QSERDES_TXA_RES_CODE_LANE_TX 0x60
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USB3_DP_QSERDES_TXA_RES_CODE_LANE_RX 0x60
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USB3_DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_TX 0x11
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USB3_DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_RX 0x02
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USB3_DP_QSERDES_TXA_LANE_MODE_1 0xD5
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USB3_DP_QSERDES_TXA_LANE_MODE_2 0x00
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USB3_DP_QSERDES_TXA_RCV_DETECT_LVL_2 0x12
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USB3_DP_QSERDES_TXA_PI_QEC_CTRL 0x40
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USB3_DP_QSERDES_RXA_UCDR_FO_GAIN 0x09
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USB3_DP_QSERDES_RXA_UCDR_SO_GAIN 0x05
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USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_FO_GAIN 0x2F
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USB3_DP_QSERDES_RXA_UCDR_SO_SATURATION_AND_ENABLE 0x7F
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USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_COUNT_LOW 0xFF
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USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_COUNT_HIGH 0x0F
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USB3_DP_QSERDES_RXA_UCDR_PI_CONTROLS 0x99
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USB3_DP_QSERDES_RXA_UCDR_SB2_THRESH1 0x08
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USB3_DP_QSERDES_RXA_UCDR_SB2_THRESH2 0x08
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USB3_DP_QSERDES_RXA_UCDR_SB2_GAIN1 0x00
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USB3_DP_QSERDES_RXA_UCDR_SB2_GAIN2 0x04
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USB3_DP_QSERDES_RXA_VGA_CAL_CNTRL1 0x54
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USB3_DP_QSERDES_RXA_VGA_CAL_CNTRL2 0x0C
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USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL2 0x0F
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USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL3 0x4A
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USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL4 0x0A
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USB3_DP_QSERDES_RXA_RX_IDAC_TSETTLE_LOW 0xC0
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USB3_DP_QSERDES_RXA_RX_IDAC_TSETTLE_HIGH 0x00
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USB3_DP_QSERDES_RXA_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x77
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USB3_DP_QSERDES_RXA_SIGDET_CNTRL 0x04
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USB3_DP_QSERDES_RXA_SIGDET_DEGLITCH_CNTRL 0x0E
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USB3_DP_QSERDES_RXA_RX_MODE_00_LOW 0xFF
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USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH 0x7F
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USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH2 0x7F
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USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH3 0x7F
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USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH4 0x97
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USB3_DP_QSERDES_RXA_RX_MODE_01_LOW 0xDC
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USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH 0xDC
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USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH2 0x5C
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USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH3 0x7B
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USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH4 0xB4
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USB3_DP_QSERDES_RXA_DFE_EN_TIMER 0x04
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USB3_DP_QSERDES_RXA_DFE_CTLE_POST_CAL_OFFSET 0x38
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USB3_DP_QSERDES_RXA_AUX_DATA_TCOARSE_TFINE 0xA0
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USB3_DP_QSERDES_RXA_DCC_CTRL1 0x0C
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USB3_DP_QSERDES_RXA_GM_CAL 0x1F
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USB3_DP_QSERDES_RXA_VTH_CODE 0x10
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USB3_DP_QSERDES_TXB_RES_CODE_LANE_TX 0x60
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USB3_DP_QSERDES_TXB_RES_CODE_LANE_RX 0x60
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USB3_DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_TX 0x11
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USB3_DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_RX 0x02
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USB3_DP_QSERDES_TXB_LANE_MODE_1 0xD5
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USB3_DP_QSERDES_TXB_LANE_MODE_2 0x00
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USB3_DP_QSERDES_TXB_RCV_DETECT_LVL_2 0x12
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USB3_DP_QSERDES_TXB_PI_QEC_CTRL 0x54
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USB3_DP_QSERDES_RXB_UCDR_FO_GAIN 0x09
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USB3_DP_QSERDES_RXB_UCDR_SO_GAIN 0x05
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USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_FO_GAIN 0x2F
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USB3_DP_QSERDES_RXB_UCDR_SO_SATURATION_AND_ENABLE 0x7F
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USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_COUNT_LOW 0xFF
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USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_COUNT_HIGH 0x0F
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USB3_DP_QSERDES_RXB_UCDR_PI_CONTROLS 0x99
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USB3_DP_QSERDES_RXB_UCDR_SB2_THRESH1 0x08
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USB3_DP_QSERDES_RXB_UCDR_SB2_THRESH2 0x08
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USB3_DP_QSERDES_RXB_UCDR_SB2_GAIN1 0x00
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USB3_DP_QSERDES_RXB_UCDR_SB2_GAIN2 0x04
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USB3_DP_QSERDES_RXB_VGA_CAL_CNTRL1 0x54
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USB3_DP_QSERDES_RXB_VGA_CAL_CNTRL2 0x0C
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USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL2 0x0F
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USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL3 0x4A
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USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL4 0x0A
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USB3_DP_QSERDES_RXB_RX_IDAC_TSETTLE_LOW 0xC0
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USB3_DP_QSERDES_RXB_RX_IDAC_TSETTLE_HIGH 0x00
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USB3_DP_QSERDES_RXB_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x77
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USB3_DP_QSERDES_RXB_SIGDET_CNTRL 0x04
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USB3_DP_QSERDES_RXB_SIGDET_DEGLITCH_CNTRL 0x0E
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USB3_DP_QSERDES_RXB_RX_MODE_00_LOW 0x7F
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USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH 0xFF
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USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH2 0x3F
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USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH3 0x7F
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USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH4 0xA6
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USB3_DP_QSERDES_RXB_RX_MODE_01_LOW 0xDC
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USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH 0xDC
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USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH2 0x5C
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USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH3 0x7B
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USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH4 0xB4
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USB3_DP_QSERDES_RXB_DFE_EN_TIMER 0x04
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USB3_DP_QSERDES_RXB_DFE_CTLE_POST_CAL_OFFSET 0x38
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USB3_DP_QSERDES_RXB_AUX_DATA_TCOARSE_TFINE 0xA0
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USB3_DP_QSERDES_RXB_DCC_CTRL1 0x0C
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USB3_DP_QSERDES_RXB_GM_CAL 0x1F
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USB3_DP_QSERDES_RXB_VTH_CODE 0x10
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USB3_DP_PCS_LOCK_DETECT_CONFIG1 0xD0
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USB3_DP_PCS_LOCK_DETECT_CONFIG2 0x07
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USB3_DP_PCS_LOCK_DETECT_CONFIG3 0x20
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USB3_DP_PCS_LOCK_DETECT_CONFIG6 0x13
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USB3_DP_PCS_REFGEN_REQ_CONFIG1 0x21
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USB3_DP_PCS_RX_SIGDET_LVL 0xA9
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USB3_DP_PCS_CDR_RESET_TIME 0x0A
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USB3_DP_PCS_ALIGN_DETECT_CONFIG1 0x88
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USB3_DP_PCS_ALIGN_DETECT_CONFIG2 0x13
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USB3_DP_PCS_PCS_TX_RX_CONFIG 0x0C
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USB3_DP_PCS_EQ_CONFIG1 0x4B
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USB3_DP_PCS_EQ_CONFIG5 0x10
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USB3_DP_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0xF8
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USB3_DP_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x07>;
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qcom,qmp-phy-reg-offset =
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<USB3_DP_PCS_PCS_STATUS1
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USB3_DP_PCS_USB3_AUTONOMOUS_MODE_CTRL
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USB3_DP_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR
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USB3_DP_PCS_POWER_DOWN_CONTROL
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USB3_DP_PCS_SW_RESET
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USB3_DP_PCS_START_CONTROL
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0xffff /* USB3_PHY_PCS_MISC_TYPEC_CTRL */
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USB3_DP_COM_POWER_DOWN_CTRL
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USB3_DP_COM_SW_RESET
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USB3_DP_COM_RESET_OVRD_CTRL
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USB3_DP_COM_PHY_MODE_CTRL
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USB3_DP_COM_TYPEC_CTRL
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USB3_DP_PCS_CLAMP_ENABLE>;
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clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
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<&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>,
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<&gcc GCC_USB3_PRIM_PHY_PIPE_CLK_SRC>,
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<&usb3_phy_wrapper_gcc_usb30_pipe_clk>,
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<&rpmhcc RPMH_CXO_CLK>,
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<&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
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clock-names = "aux_clk", "pipe_clk", "pipe_clk_mux",
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"pipe_clk_ext_src", "ref_clk_src",
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"com_aux_clk";
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resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
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<&gcc GCC_USB3_PHY_PRIM_BCR>;
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reset-names = "global_phy_reset", "phy_reset";
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};
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usb_audio_qmi_dev {
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compatible = "qcom,usb-audio-qmi-dev";
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iommus = <&apps_smmu 0x180f 0x0>;
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qcom,iommu-dma = "disabled";
|
|
qcom,usb-audio-stream-id = <0xf>;
|
|
qcom,usb-audio-intr-num = <2>;
|
|
};
|
|
|
|
usb_nop_phy: usb_nop_phy {
|
|
compatible = "usb-nop-xceiv";
|
|
};
|
|
|
|
/* Secondary USB port related controller */
|
|
usb1: ssusb@a800000 {
|
|
compatible = "qcom,dwc-usb3-msm";
|
|
reg = <0xa800000 0x100000>;
|
|
reg-names = "core_base";
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
|
|
interrupts-extended = <&pdc 12 IRQ_TYPE_EDGE_BOTH>,
|
|
<&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
|
|
<&pdc 16 IRQ_TYPE_LEVEL_HIGH>,
|
|
<&pdc 13 IRQ_TYPE_EDGE_BOTH>;
|
|
interrupt-names = "dp_hs_phy_irq", "pwr_event_irq",
|
|
"ss_phy_irq", "dm_hs_phy_irq";
|
|
qcom,use-pdc-interrupts;
|
|
|
|
USB3_GDSC-supply = <&usb30_sec_gdsc>;
|
|
clocks = <&gcc GCC_USB30_SEC_MASTER_CLK>,
|
|
<&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
|
|
<&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
|
|
<&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
|
|
<&gcc GCC_USB30_SEC_SLEEP_CLK>,
|
|
<&gcc GCC_USB3_SEC_CLKREF_EN>;
|
|
|
|
clock-names = "core_clk", "iface_clk", "bus_aggr_clk",
|
|
"utmi_clk", "sleep_clk", "xo";
|
|
|
|
resets = <&gcc GCC_USB30_SEC_BCR>;
|
|
reset-names = "core_reset";
|
|
|
|
qcom,core-clk-rate = <200000000>;
|
|
qcom,core-clk-rate-hs = <66666667>;
|
|
qcom,num-gsi-evt-buffs = <0x3>;
|
|
qcom,gsi-reg-offset =
|
|
<0x0fc /* GSI_GENERAL_CFG */
|
|
0x110 /* GSI_DBL_ADDR_L */
|
|
0x120 /* GSI_DBL_ADDR_H */
|
|
0x130 /* GSI_RING_BASE_ADDR_L */
|
|
0x144 /* GSI_RING_BASE_ADDR_H */
|
|
0x1a4>; /* GSI_IF_STS */
|
|
qcom,charging-disabled;
|
|
|
|
interconnect-names = "usb-ddr", "usb-ipa", "ddr-usb";
|
|
interconnects = <&aggre1_noc MASTER_USB3_1 &mc_virt SLAVE_EBI1>,
|
|
<&aggre1_noc MASTER_USB3_1 &config_noc SLAVE_IPA_CFG>,
|
|
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_USB3_1>;
|
|
|
|
dwc1: dwc3@a800000 {
|
|
compatible = "snps,dwc3";
|
|
reg = <0xa800000 0xd93c>;
|
|
iommus = <&apps_smmu 0x20 0x0>;
|
|
qcom,iommu-dma = "atomic";
|
|
qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>;
|
|
|
|
interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
|
|
usb-phy = <&usb2_phy1>, <&usb_qmp_phy>;
|
|
snps,has-lpm-erratum;
|
|
snps,hird-threshold = /bits/ 8 <0x10>;
|
|
snps,usb3_lpm_capable;
|
|
snps,dis-u1-entry-quirk;
|
|
snps,dis-u2-entry-quirk;
|
|
snps,dis_u2_susphy_quirk;
|
|
tx-fifo-resize;
|
|
maximum-speed = "super-speed";
|
|
dr_mode = "otg";
|
|
usb-role-switch;
|
|
};
|
|
};
|
|
|
|
/* Primary USB port related High Speed PHY */
|
|
usb2_phy1: hsphy@88e4000 {
|
|
compatible = "qcom,usb-hsphy-snps-femto";
|
|
reg = <0x88e4000 0x110>;
|
|
reg-names = "hsusb_phy_base";
|
|
|
|
vdd-supply = <&pm8150_l5>;
|
|
vdda18-supply = <&pm8150_l12>;
|
|
vdda33-supply = <&pm8150_l2>;
|
|
qcom,vdd-voltage-level = <0 880000 880000>;
|
|
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>;
|
|
clock-names = "ref_clk_src";
|
|
|
|
resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
|
|
reset-names = "phy_reset";
|
|
qcom,param-override-seq = <0x43 0x70>;
|
|
};
|
|
|
|
/* Secondary USB port related QMP PHY */
|
|
usb_qmp_phy: ssphy@88eb000 {
|
|
compatible = "qcom,usb-ssphy-qmp-v2";
|
|
reg = <0x88eb000 0x1000>,
|
|
<0x088eb88c 0x4>;
|
|
reg-names = "qmp_phy_base",
|
|
"pcs_clamp_enable_reg";
|
|
|
|
vdd-supply = <&pm8150_l18>;
|
|
qcom,vdd-voltage-level = <0 912000 912000>;
|
|
qcom,vdd-max-load-uA = <47000>;
|
|
core-supply = <&pm8150_l9>;
|
|
qcom,vbus-valid-override;
|
|
qcom,qmp-phy-init-seq =
|
|
/* <reg_offset, value, delay> */
|
|
<USB3_UNI_QSERDES_COM_SYSCLK_EN_SEL 0x1a
|
|
USB3_UNI_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL 0x11
|
|
USB3_UNI_QSERDES_COM_HSCLK_SEL 0x01
|
|
USB3_UNI_QSERDES_COM_DEC_START_MODE0 0x82
|
|
USB3_UNI_QSERDES_COM_DIV_FRAC_START1_MODE0 0xab
|
|
USB3_UNI_QSERDES_COM_DIV_FRAC_START2_MODE0 0xea
|
|
USB3_UNI_QSERDES_COM_DIV_FRAC_START3_MODE0 0x02
|
|
USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0xca
|
|
USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1e
|
|
USB3_UNI_QSERDES_COM_CP_CTRL_MODE0 0x06
|
|
USB3_UNI_QSERDES_COM_PLL_RCTRL_MODE0 0x16
|
|
USB3_UNI_QSERDES_COM_PLL_CCTRL_MODE0 0x36
|
|
USB3_UNI_QSERDES_COM_VCO_TUNE1_MODE0 0x24
|
|
USB3_UNI_QSERDES_COM_LOCK_CMP2_MODE0 0x34
|
|
USB3_UNI_QSERDES_COM_LOCK_CMP1_MODE0 0x14
|
|
USB3_UNI_QSERDES_COM_LOCK_CMP_EN 0x04
|
|
USB3_UNI_QSERDES_COM_SYSCLK_BUF_ENABLE 0x0a
|
|
USB3_UNI_QSERDES_COM_VCO_TUNE2_MODE1 0x02
|
|
USB3_UNI_QSERDES_COM_VCO_TUNE1_MODE1 0x24
|
|
USB3_UNI_QSERDES_COM_CORECLK_DIV_MODE1 0x08
|
|
USB3_UNI_QSERDES_COM_DEC_START_MODE1 0x82
|
|
USB3_UNI_QSERDES_COM_DIV_FRAC_START1_MODE1 0xab
|
|
USB3_UNI_QSERDES_COM_DIV_FRAC_START2_MODE1 0xea
|
|
USB3_UNI_QSERDES_COM_DIV_FRAC_START3_MODE1 0x02
|
|
USB3_UNI_QSERDES_COM_LOCK_CMP2_MODE1 0x82
|
|
USB3_UNI_QSERDES_COM_LOCK_CMP1_MODE1 0x34
|
|
USB3_UNI_QSERDES_COM_CP_CTRL_MODE1 0x06
|
|
USB3_UNI_QSERDES_COM_PLL_RCTRL_MODE1 0x16
|
|
USB3_UNI_QSERDES_COM_PLL_CCTRL_MODE1 0x36
|
|
USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0xca
|
|
USB3_UNI_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1e
|
|
USB3_UNI_QSERDES_COM_CMN_IPTRIM 0x20
|
|
USB3_UNI_QSERDES_COM_SSC_EN_CENTER 0x01
|
|
USB3_UNI_QSERDES_COM_SSC_PER1 0x31
|
|
USB3_UNI_QSERDES_COM_SSC_PER2 0x01
|
|
USB3_UNI_QSERDES_COM_SSC_STEP_SIZE1_MODE1 0xde
|
|
USB3_UNI_QSERDES_COM_SSC_STEP_SIZE2_MODE1 0x07
|
|
USB3_UNI_QSERDES_COM_SSC_STEP_SIZE1_MODE0 0xde
|
|
USB3_UNI_QSERDES_COM_SSC_STEP_SIZE2_MODE0 0x07
|
|
USB3_UNI_QSERDES_COM_VCO_TUNE_MAP 0x02
|
|
USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH4 0xb8
|
|
USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH3 0xff
|
|
USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH2 0xbf
|
|
USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH 0x7f
|
|
USB3_UNI_QSERDES_RX_RX_MODE_00_LOW 0x7f
|
|
USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH4 0xb4
|
|
USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH3 0x7b
|
|
USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH2 0x5c
|
|
USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH 0xdc
|
|
USB3_UNI_QSERDES_RX_RX_MODE_01_LOW 0xdc
|
|
USB3_UNI_QSERDES_RX_UCDR_PI_CONTROLS 0x99
|
|
USB3_UNI_QSERDES_RX_UCDR_SB2_THRESH1 0x04
|
|
USB3_UNI_QSERDES_RX_UCDR_SB2_THRESH2 0x08
|
|
USB3_UNI_QSERDES_RX_UCDR_SB2_GAIN1 0x05
|
|
USB3_UNI_QSERDES_RX_UCDR_SB2_GAIN2 0x05
|
|
USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_FO_GAIN 0x2f
|
|
USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_COUNT_LOW 0xff
|
|
USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_COUNT_HIGH 0x0f
|
|
USB3_UNI_QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE 0x7f
|
|
USB3_UNI_QSERDES_RX_UCDR_FO_GAIN 0x0A
|
|
USB3_UNI_QSERDES_RX_VGA_CAL_CNTRL1 0x54
|
|
USB3_UNI_QSERDES_RX_VGA_CAL_CNTRL2 0x0c
|
|
USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2 0x0f
|
|
USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3 0x4a
|
|
USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4 0x0a
|
|
USB3_UNI_QSERDES_RX_DFE_EN_TIMER 0x04
|
|
USB3_UNI_QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x47
|
|
USB3_UNI_QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x80
|
|
USB3_UNI_QSERDES_RX_SIGDET_CNTRL 0x04
|
|
USB3_UNI_QSERDES_RX_SIGDET_DEGLITCH_CNTRL 0x0e
|
|
USB3_UNI_QSERDES_RX_RX_IDAC_TSETTLE_HIGH 0x00
|
|
USB3_UNI_QSERDES_RX_RX_IDAC_TSETTLE_LOW 0xc0
|
|
USB3_UNI_QSERDES_RX_DFE_CTLE_POST_CAL_OFFSET 0x38
|
|
USB3_UNI_QSERDES_RX_UCDR_SO_GAIN 0x06
|
|
USB3_UNI_QSERDES_RX_DCC_CTRL1 0x0c
|
|
USB3_UNI_QSERDES_RX_GM_CAL 0x1f
|
|
USB3_UNI_QSERDES_TX_RCV_DETECT_LVL_2 0x12
|
|
USB3_UNI_QSERDES_TX_LANE_MODE_1 0xd5
|
|
USB3_UNI_QSERDES_TX_LANE_MODE_2 0x82
|
|
USB3_UNI_QSERDES_TX_PI_QEC_CTRL 0x40
|
|
USB3_UNI_QSERDES_TX_RES_CODE_LANE_OFFSET_TX 0x11
|
|
USB3_UNI_QSERDES_TX_RES_CODE_LANE_OFFSET_RX 0x02
|
|
USB3_UNI_PCS_LOCK_DETECT_CONFIG1 0xd0
|
|
USB3_UNI_PCS_LOCK_DETECT_CONFIG2 0x07
|
|
USB3_UNI_PCS_LOCK_DETECT_CONFIG3 0x20
|
|
USB3_UNI_PCS_LOCK_DETECT_CONFIG6 0x13
|
|
USB3_UNI_PCS_RCVR_DTCT_DLY_P1U2_L 0xe7
|
|
USB3_UNI_PCS_RCVR_DTCT_DLY_P1U2_H 0x03
|
|
USB3_UNI_PCS_RX_SIGDET_LVL 0xa9
|
|
USB3_UNI_PCS_PCS_TX_RX_CONFIG 0x0c
|
|
USB3_UNI_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x07
|
|
USB3_UNI_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0xf8
|
|
USB3_UNI_PCS_CDR_RESET_TIME 0x0a
|
|
USB3_UNI_PCS_ALIGN_DETECT_CONFIG1 0x88
|
|
USB3_UNI_PCS_ALIGN_DETECT_CONFIG2 0x13
|
|
USB3_UNI_PCS_EQ_CONFIG1 0x4b
|
|
USB3_UNI_PCS_EQ_CONFIG5 0x10
|
|
USB3_UNI_PCS_REFGEN_REQ_CONFIG1 0x21>;
|
|
|
|
qcom,qmp-phy-reg-offset =
|
|
<USB3_UNI_PCS_PCS_STATUS1
|
|
USB3_UNI_PCS_USB3_AUTONOMOUS_MODE_CTRL
|
|
USB3_UNI_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR
|
|
USB3_UNI_PCS_POWER_DOWN_CONTROL
|
|
USB3_UNI_PCS_SW_RESET
|
|
USB3_UNI_PCS_START_CONTROL>;
|
|
|
|
clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
|
|
<&gcc GCC_USB3_SEC_PHY_PIPE_CLK>,
|
|
<&gcc GCC_USB3_SEC_PHY_PIPE_CLK_SRC>,
|
|
<&usb3_uni_phy_sec_gcc_usb30_pipe_clk>,
|
|
<&rpmhcc RPMH_CXO_CLK>,
|
|
<&gcc GCC_USB3_SEC_CLKREF_EN>,
|
|
<&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
|
|
clock-names = "aux_clk", "pipe_clk", "pipe_clk_mux",
|
|
"pipe_clk_ext_src", "ref_clk_src",
|
|
"ref_clk", "com_aux_clk";
|
|
|
|
resets = <&gcc GCC_USB3_PHY_SEC_BCR>,
|
|
<&gcc GCC_USB3PHY_PHY_SEC_BCR>;
|
|
reset-names = "phy_reset", "phy_phy_reset";
|
|
};
|
|
};
|