154 lines
3.2 KiB
Text
154 lines
3.2 KiB
Text
#include <dt-bindings/input/linux-event-codes.h>
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#include <dt-bindings/input/qcom,qpnp-power-on.h>
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#include <dt-bindings/iio/qcom,spmi-vadc.h>
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#include <dt-bindings/spmi/spmi.h>
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&spmi_bus {
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qcom,pms405@0 {
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compatible ="qcom,spmi-pmic";
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reg = <0 SPMI_USID>;
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#address-cells = <1>;
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#size-cells = <0>;
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pms405_vadc: vadc@3100 {
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compatible = "qcom,spmi-adc-rev2";
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reg = <0x3100>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
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#io-channel-cells = <1>;
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io-channel-ranges;
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ref_gnd {
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label = "ref_gnd";
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reg = <ADC5_REF_GND>;
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qcom,pre-scaling = <1 1>;
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};
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vref_1p25 {
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label = "vref_1p25";
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reg = <ADC5_1P25VREF>;
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qcom,pre-scaling = <1 1>;
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};
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die_temp {
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label = "die_temp";
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reg = <ADC5_DIE_TEMP>;
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qcom,pre-scaling = <1 1>;
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};
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vph_pwr {
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label = "vph_pwr";
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reg = <ADC5_VPH_PWR>;
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qcom,pre-scaling = <1 3>;
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};
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xo_therm {
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label = "xo_therm";
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reg = <ADC5_XO_THERM_100K_PU>;
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qcom,ratiometric;
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qcom,hw-settle-time = <200>;
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qcom,pre-scaling = <1 1>;
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};
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pa_therm1 {
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label = "pa_therm1";
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reg = <ADC5_AMUX_THM1_100K_PU>;
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qcom,ratiometric;
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qcom,hw-settle-time = <200>;
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qcom,pre-scaling = <1 1>;
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};
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pa_therm3 {
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label = "pa_therm3";
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reg = <ADC5_AMUX_THM3_100K_PU>;
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qcom,ratiometric;
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qcom,hw-settle-time = <200>;
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qcom,pre-scaling = <1 1>;
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};
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};
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pms405_adc_tm_iio: adc_tm@3500 {
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compatible = "qcom,spmi-adc-tm5-iio";
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reg = <0x3500>;
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#thermal-sensor-cells = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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xo_therm {
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reg = <0>;
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io-channels = <&pms405_vadc ADC5_XO_THERM_100K_PU>;
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};
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pa_therm1 {
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reg = <1>;
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io-channels = <&pms405_vadc ADC5_AMUX_THM1_100K_PU>;
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};
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pa_therm3 {
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reg = <2>;
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io-channels = <&pms405_vadc ADC5_AMUX_THM3_100K_PU>;
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};
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};
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pms405_pon: qcom,power-on@800 {
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compatible = "qcom,qpnp-power-on";
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reg = <0x800>;
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interrupts = <0x0 0x8 0x0 IRQ_TYPE_NONE>;
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interrupt-names = "kpdpwr";
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qcom,pon-dbc-delay = <15625>;
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qcom,system-reset;
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qcom,store-hard-reset-reason;
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qcom,pon_1 {
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qcom,pon-type = <PON_POWER_ON_TYPE_KPDPWR>;
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qcom,pull-up;
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linux,code = <KEY_POWER>;
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};
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};
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pms405_clkdiv: clock-controller@5b00 {
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compatible = "qcom,spmi-clkdiv";
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reg = <0x5b00>;
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#clock-cells = <1>;
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qcom,num-clkdivs = <1>;
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clock-output-names = "pms405_div_clk1";
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clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
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clock-names = "xo";
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assigned-clocks = <&pms405_clkdiv 1>;
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assigned-clock-rates = <9600000>;
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};
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/* QCS405 + PMS405 GPIO configuration */
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pms405_gpios: pinctrl@c000 {
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compatible = "qcom,pms405-gpio";
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reg = <0xc000>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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qcom,pms405_rtc {
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compatible = "qcom,pm8941-rtc";
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reg = <0x6000>, <0x6100>;
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reg-names = "rtc", "alarm";
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interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>;
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};
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};
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qcom,pms405@1 {
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compatible = "qcom,spmi-pmic";
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reg = <1 SPMI_USID>;
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#address-cells = <1>;
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#size-cells = <0>;
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pms405_pwm: qcom,pwms@bc00 {
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compatible = "qcom,pwm-lpg";
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reg = <0xbc00>;
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reg-names = "lpg-base";
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qcom,num-lpg-channels = <2>;
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#pwm-cells = <2>;
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};
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};
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};
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