2927 lines
65 KiB
Text
2927 lines
65 KiB
Text
#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/qcom,gcc-sdm845.h>
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#include <dt-bindings/clock/qcom,camcc-sdm845.h>
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#include <dt-bindings/clock/qcom,dispcc-sdm845.h>
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#include <dt-bindings/clock/qcom,gpucc-sdm845.h>
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#include <dt-bindings/clock/qcom,videocc-sdm845.h>
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#include <dt-bindings/interconnect/qcom,icc.h>
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/soc/qcom,rpmh-rsc.h>
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#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
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#include <dt-bindings/clock/qcom,aop-qmp.h>
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#define MHZ_TO_MBPS(mhz, w) ((mhz * 1000000 * w) / (1024 * 1024))
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/ {
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model = "Qualcomm Technologies, Inc. SDM670";
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compatible = "qcom,sdm670";
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qcom,msm-id = <336 0x0>;
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interrupt-parent = <&intc>;
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#address-cells = <2>;
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#size-cells = <2>;
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memory { device_type = "memory"; reg = <0 0 0 0>; };
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ddr-regions { };
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reserved_memory: reserved-memory { };
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aliases {
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ufshc1 = &ufshc_mem; /* Embedded UFS slot */
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sdhc1 = &sdhc_1; /* SDC1 eMMC slot */
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sdhc2 = &sdhc_2; /* SDC2 SD Card slot */
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serial0 = &qupv3_se12_2uart;
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spi0 = &qupv3_se8_spi;
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i2c0 = &qupv3_se10_i2c;
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i2c1 = &qupv3_se3_i2c;
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hsuart0 = &qupv3_se6_4uart;
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};
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soc: soc { };
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firmware: firmware {};
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chosen {
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bootargs = "lpm_levels.sleep_disabled=1 console=ttyMSM0,115200n8 msm_rtb.filter=0x237 service_locator.enable=1 swiotlb=2048 loop.max_part=7 cpufreq.default_governor=performance rcupdate.rcu_expedited=1 rcu_nocbs=0-7 kpti=off export_pmu_events movable_node ftrace_dump_on_oops ssbd=force-off disable_dma32=on cgroup.memory=nokmem,nosocket";
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};
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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CPU0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x0>;
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enable-method = "psci";
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efficiency = <1024>;
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cache-size = <0x10000>;
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cpu-release-addr = <0x0 0x90000000>;
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next-level-cache = <&L2_0>;
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sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;
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qcom,lmh-dcvs = <&lmh_dcvs0>;
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#cooling-cells = <2>;
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L2_0: l2-cache {
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compatible = "arm,arch-cache";
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cache-size = <0x20000>;
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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L3_0: l3-cache {
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compatible = "arm,arch-cache";
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cache-size = <0x100000>;
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cache-level = <3>;
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};
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};
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L1_I_0: l1-icache {
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compatible = "arm,arch-cache";
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qcom,dump-size = <0x12000>;
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};
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L1_D_0: l1-dcache {
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compatible = "arm,arch-cache";
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qcom,dump-size = <0xa000>;
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};
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L1_TLB_0: l1-tlb {
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qcom,dump-size = <0x3000>;
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};
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};
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CPU1: cpu@100 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x100>;
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enable-method = "psci";
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efficiency = <1024>;
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cache-size = <0x10000>;
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cpu-release-addr = <0x0 0x90000000>;
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next-level-cache = <&L2_100>;
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sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;
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qcom,lmh-dcvs = <&lmh_dcvs0>;
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#cooling-cells = <2>;
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L2_100: l2-cache {
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compatible = "arm,arch-cache";
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cache-size = <0x20000>;
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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L1_I_100: l1-icache {
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compatible = "arm,arch-cache";
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qcom,dump-size = <0x12000>;
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};
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L1_D_100: l1-dcache {
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compatible = "arm,arch-cache";
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qcom,dump-size = <0xa000>;
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};
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L1_TLB_100: l1-tlb {
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qcom,dump-size = <0x3000>;
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};
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};
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CPU2: cpu@200 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x200>;
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enable-method = "psci";
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efficiency = <1024>;
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cache-size = <0x10000>;
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cpu-release-addr = <0x0 0x90000000>;
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next-level-cache = <&L2_200>;
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sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;
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qcom,lmh-dcvs = <&lmh_dcvs0>;
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#cooling-cells = <2>;
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L2_200: l2-cache {
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compatible = "arm,arch-cache";
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cache-size = <0x20000>;
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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L1_I_200: l1-icache {
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compatible = "arm,arch-cache";
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qcom,dump-size = <0x12000>;
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};
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L1_D_200: l1-dcache {
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compatible = "arm,arch-cache";
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qcom,dump-size = <0xa000>;
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};
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L1_TLB_200: l1-tlb {
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qcom,dump-size = <0x3000>;
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};
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};
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CPU3: cpu@300 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x300>;
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enable-method = "psci";
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efficiency = <1024>;
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cache-size = <0x10000>;
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cpu-release-addr = <0x0 0x90000000>;
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next-level-cache = <&L2_300>;
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sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;
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qcom,lmh-dcvs = <&lmh_dcvs0>;
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#cooling-cells = <2>;
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L2_300: l2-cache {
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compatible = "arm,arch-cache";
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cache-size = <0x20000>;
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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L1_I_300: l1-icache {
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compatible = "arm,arch-cache";
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qcom,dump-size = <0x12000>;
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};
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L1_D_300: l1-dcache {
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compatible = "arm,arch-cache";
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qcom,dump-size = <0xa000>;
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};
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L1_TLB_300: l1-tlb {
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qcom,dump-size = <0x3000>;
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};
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};
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CPU4: cpu@400 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x400>;
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enable-method = "psci";
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efficiency = <1024>;
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cache-size = <0x10000>;
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cpu-release-addr = <0x0 0x90000000>;
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next-level-cache = <&L2_400>;
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sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;
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qcom,lmh-dcvs = <&lmh_dcvs0>;
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#cooling-cells = <2>;
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L2_400: l2-cache {
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compatible = "arm,arch-cache";
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cache-size = <0x20000>;
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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L1_I_400: l1-icache {
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compatible = "arm,arch-cache";
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qcom,dump-size = <0x12000>;
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};
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L1_D_400: l1-dcache {
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compatible = "arm,arch-cache";
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qcom,dump-size = <0xa000>;
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};
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L1_TLB_400: l1-tlb {
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qcom,dump-size = <0x3000>;
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};
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};
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CPU5: cpu@500 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x500>;
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enable-method = "psci";
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efficiency = <1024>;
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cache-size = <0x10000>;
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cpu-release-addr = <0x0 0x90000000>;
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next-level-cache = <&L2_500>;
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sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;
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qcom,lmh-dcvs = <&lmh_dcvs0>;
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#cooling-cells = <2>;
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L2_500: l2-cache {
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compatible = "arm,arch-cache";
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cache-size = <0x20000>;
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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L1_I_500: l1-icache {
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compatible = "arm,arch-cache";
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qcom,dump-size = <0x12000>;
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};
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L1_D_500: l1-dcache {
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compatible = "arm,arch-cache";
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qcom,dump-size = <0xa000>;
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};
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L1_TLB_500: l1-tlb {
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qcom,dump-size = <0x3000>;
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};
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};
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CPU6: cpu@600 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x600>;
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enable-method = "psci";
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efficiency = <1740>;
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cache-size = <0x20000>;
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cpu-release-addr = <0x0 0x90000000>;
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next-level-cache = <&L2_600>;
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sched-energy-costs = <&CPU_COST_1 &CLUSTER_COST_1>;
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qcom,lmh-dcvs = <&lmh_dcvs1>;
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#cooling-cells = <2>;
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L2_600: l2-cache {
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compatible = "arm,arch-cache";
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cache-size = <0x40000>;
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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L1_I_600: l1-icache {
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compatible = "arm,arch-cache";
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qcom,dump-size = <0x24000>;
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};
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L1_D_600: l1-dcache {
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compatible = "arm,arch-cache";
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qcom,dump-size = <0x14000>;
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};
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L1_TLB_600: l1-tlb {
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qcom,dump-size = <0x3c000>;
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};
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};
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CPU7: cpu@700 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x700>;
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enable-method = "psci";
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efficiency = <1740>;
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cache-size = <0x20000>;
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cpu-release-addr = <0x0 0x90000000>;
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next-level-cache = <&L2_700>;
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sched-energy-costs = <&CPU_COST_1 &CLUSTER_COST_1>;
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qcom,lmh-dcvs = <&lmh_dcvs1>;
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#cooling-cells = <2>;
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L2_700: l2-cache {
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compatible = "arm,arch-cache";
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cache-size = <0x40000>;
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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L1_I_700: l1-icache {
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compatible = "arm,arch-cache";
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qcom,dump-size = <0x24000>;
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};
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L1_D_700: l1-dcache {
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compatible = "arm,arch-cache";
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qcom,dump-size = <0x14000>;
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};
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L1_TLB_700: l1-tlb {
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qcom,dump-size = <0x3c000>;
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};
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};
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&CPU0>;
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};
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core1 {
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cpu = <&CPU1>;
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};
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core2 {
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cpu = <&CPU2>;
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};
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core3 {
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cpu = <&CPU3>;
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};
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core4 {
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cpu = <&CPU4>;
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};
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core5 {
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cpu = <&CPU5>;
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};
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};
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cluster1 {
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core0 {
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cpu = <&CPU6>;
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};
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core1 {
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cpu = <&CPU7>;
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};
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};
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};
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};
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energy_costs: energy-costs {
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CPU_COST_0: core-cost0 {
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busy-cost-data = <
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300000 14
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576000 25
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748800 31
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998400 46
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1209600 57
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1324800 84
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1516800 96
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1612800 114
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1708800 139
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>;
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idle-cost-data = <
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12 10 8 6 4
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>;
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};
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CPU_COST_1: core-cost1 {
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busy-cost-data = <
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300000 256
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652800 307
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825600 332
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979200 382
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1132800 408
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1363200 448
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1536000 586
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1747200 641
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1843200 659
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1996800 696
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2016000 865
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|
2054400 876
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2169600 900
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2208000 924
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2304000 940
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2361600 948
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2400000 1170
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2457600 1200
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2515200 1300
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2611200 1400
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>;
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idle-cost-data = <
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100 80 60 40 20
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>;
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};
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CLUSTER_COST_0: cluster-cost0 {
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busy-cost-data = <
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300000 6
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576000 7
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748800 8
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998400 9
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1209600 10
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|
1324800 13
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|
1516800 15
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1612800 16
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1708800 19
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>;
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idle-cost-data = <
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5 4 3 2 1
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>;
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};
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CLUSTER_COST_1: cluster-cost1 {
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busy-cost-data = <
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300000 25
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652800 30
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825600 33
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979200 38
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|
1132800 40
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|
1363200 44
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|
1536000 58
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|
1747200 64
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|
1843200 65
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|
1996800 69
|
|
2016000 85
|
|
2054400 87
|
|
2169600 90
|
|
2208000 92
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|
2304000 93
|
|
2361600 94
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|
2400000 117
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|
2457600 120
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|
2515200 130
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|
2611200 140
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>;
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idle-cost-data = <
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5 4 3 2 1
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>;
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};
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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vendor: vendor {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0 0 0xffffffff>;
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compatible = "simple-bus";
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};
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clocks {
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xo_board: xo-board {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <38400000>;
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clock-output-names = "xo_board";
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};
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sleep_clk: sleep-clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <32764>;
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clock-output-names = "sleep_clk";
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};
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};
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};
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&firmware {
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scm {
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compatible = "qcom,scm";
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};
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android {
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compatible = "android,firmware";
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vbmeta {
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compatible = "android,vbmeta";
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parts = "vbmeta,boot,system,vendor,dtbo";
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};
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fstab {
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compatible = "android,fstab";
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vendor {
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compatible = "android,vendor";
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dev = "/dev/block/platform/soc/1d84000.ufshc/by-name/vendor";
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type = "ext4";
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mnt_flags = "ro,barrier=1,discard";
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fsmgr_flags = "wait,slotselect,avb";
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status = "ok";
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};
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};
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};
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};
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&reserved_memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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hyp_region: hyp_region@85700000 {
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no-map;
|
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reg = <0x0 0x85700000 0x0 0x600000>;
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};
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xbl_region: xbl_region@85e00000 {
|
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no-map;
|
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reg = <0x0 0x85e00000 0x0 0x100000>;
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};
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aop_mem: memory@85f00000 {
|
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reg = <0x0 0x85f00000 0x0 0x20000>;
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no-map;
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};
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aop_cmd_db: memory@85fe0000 {
|
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compatible = "qcom,cmd-db";
|
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reg = <0x0 0x85FE0000 0x0 0x20000>;
|
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no-map;
|
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};
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|
|
removed_region: removed_region@85fc0000 {
|
|
no-map;
|
|
reg = <0x0 0x85fc0000 0x0 0x20000>;
|
|
};
|
|
|
|
smem_mem: smem-mem@86000000 {
|
|
no-map;
|
|
reg = <0x0 0x86000000 0x0 0x200000>;
|
|
};
|
|
|
|
removed_region1: removed_region@86200000 {
|
|
no-map;
|
|
reg = <0x0 0x86200000 0x0 0x2f00000>;
|
|
};
|
|
|
|
pil_camera_mem: camera_region@8ab00000 {
|
|
no-map;
|
|
reg = <0x0 0x8ab00000 0x0 0x500000>;
|
|
};
|
|
|
|
pil_modem_mem: modem_region@8b000000 {
|
|
no-map;
|
|
reg = <0x0 0x8b000000 0x0 0x7e00000>;
|
|
};
|
|
|
|
pil_video_mem: pil_video_region@92e00000 {
|
|
no-map;
|
|
reg = <0x0 0x92e00000 0x0 0x500000>;
|
|
};
|
|
|
|
wlan_msa_mem: wlan_msa_region@93300000 {
|
|
no-map;
|
|
reg = <0x0 0x93300000 0x0 0x100000>;
|
|
};
|
|
|
|
pil_cdsp_mem: cdsp_regions@93400000 {
|
|
no-map;
|
|
reg = <0x0 0x93400000 0x0 0x800000>;
|
|
};
|
|
|
|
pil_mba_mem: pil_mba_region@0x93c00000 {
|
|
no-map;
|
|
reg = <0x0 0x93c00000 0x0 0x200000>;
|
|
};
|
|
|
|
pil_adsp_mem: pil_adsp_region@93e00000 {
|
|
no-map;
|
|
reg = <0x0 0x93e00000 0x0 0x1e00000>;
|
|
};
|
|
|
|
pil_ipa_fw_mem: ips_fw_region@0x95c00000 {
|
|
no-map;
|
|
reg = <0x0 0x95c00000 0x0 0x10000>;
|
|
};
|
|
|
|
pil_ipa_gsi_mem: ipa_gsi_region@0x95c10000 {
|
|
no-map;
|
|
reg = <0x0 0x95c10000 0x0 0x5000>;
|
|
};
|
|
|
|
pil_gpu_mem: gpu_region@0x95c15000 {
|
|
no-map;
|
|
reg = <0x0 0x95c15000 0x0 0x2000>;
|
|
};
|
|
|
|
qseecom_mem: qseecom_region@0x9e400000 {
|
|
compatible = "shared-dma-pool";
|
|
no-map;
|
|
reg = <0x0 0x9e400000 0x0 0x1400000>;
|
|
};
|
|
|
|
adsp_mem: adsp_region {
|
|
compatible = "shared-dma-pool";
|
|
alloc-ranges = <0 0x00000000 0 0xffffffff>;
|
|
reusable;
|
|
alignment = <0 0x400000>;
|
|
size = <0 0x800000>;
|
|
};
|
|
|
|
sdsp_mem: sdsp_region {
|
|
compatible = "shared-dma-pool";
|
|
alloc-ranges = <0 0x00000000 0 0xffffffff>;
|
|
reusable;
|
|
alignment = <0 0x400000>;
|
|
size = <0 0x800000>;
|
|
};
|
|
|
|
qseecom_ta_mem: qseecom_ta_region {
|
|
compatible = "shared-dma-pool";
|
|
alloc-ranges = <0 0x00000000 0 0xffffffff>;
|
|
reusable;
|
|
alignment = <0 0x400000>;
|
|
size = <0 0x1000000>;
|
|
};
|
|
|
|
sp_mem: sp_region { /* SPSS-HLOS ION shared mem */
|
|
compatible = "shared-dma-pool";
|
|
alloc-ranges = <0 0x00000000 0 0xffffffff>; /* 32-bit */
|
|
reusable;
|
|
alignment = <0 0x400000>;
|
|
size = <0 0x800000>;
|
|
};
|
|
|
|
secure_display_memory: secure_display_region {
|
|
compatible = "shared-dma-pool";
|
|
alloc-ranges = <0 0x00000000 0 0xffffffff>;
|
|
reusable;
|
|
alignment = <0 0x400000>;
|
|
size = <0 0xd000000>;
|
|
};
|
|
|
|
splash_memory: cont_splash_region@9c000000 {
|
|
reg = <0x0 0x9c000000 0x0 0x2300000>;
|
|
label = "cont_splash_region";
|
|
};
|
|
|
|
dfps_data_memory: dfps_data_region@9e300000 {
|
|
reg = <0x0 0x9e300000 0x0 0x0100000>;
|
|
label = "dfps_data_region";
|
|
};
|
|
|
|
dump_mem: mem_dump_region {
|
|
compatible = "shared-dma-pool";
|
|
reusable;
|
|
size = <0 0x2400000>;
|
|
};
|
|
|
|
/* global autoconfigured region for contiguous allocations */
|
|
system_cma: linux,cma {
|
|
compatible = "shared-dma-pool";
|
|
alloc-ranges = <0 0x00000000 0 0xffffffff>;
|
|
reusable;
|
|
alignment = <0 0x400000>;
|
|
size = <0 0x2000000>;
|
|
linux,cma-default;
|
|
};
|
|
};
|
|
|
|
#include "sdm670-dma-heaps.dtsi"
|
|
|
|
#include "msm-rdbg.dtsi"
|
|
|
|
#include "sdm670-qupv3.dtsi"
|
|
|
|
#include "sdm670-coresight.dtsi"
|
|
|
|
&soc {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0 0 0 0xffffffff>;
|
|
compatible = "simple-bus";
|
|
|
|
jtag_mm0: jtagmm@7040000 {
|
|
compatible = "qcom,jtagv8-mm";
|
|
reg = <0x7040000 0x1000>;
|
|
reg-names = "etm-base";
|
|
|
|
clocks = <&clock_aop QDSS_CLK>;
|
|
clock-names = "core_clk";
|
|
|
|
qcom,coresight-jtagmm-cpu = <&CPU0>;
|
|
};
|
|
|
|
jtag_mm1: jtagmm@7140000 {
|
|
compatible = "qcom,jtagv8-mm";
|
|
reg = <0x7140000 0x1000>;
|
|
reg-names = "etm-base";
|
|
|
|
clocks = <&clock_aop QDSS_CLK>;
|
|
clock-names = "core_clk";
|
|
|
|
qcom,coresight-jtagmm-cpu = <&CPU1>;
|
|
};
|
|
|
|
jtag_mm2: jtagmm@7240000 {
|
|
compatible = "qcom,jtagv8-mm";
|
|
reg = <0x7240000 0x1000>;
|
|
reg-names = "etm-base";
|
|
|
|
clocks = <&clock_aop QDSS_CLK>;
|
|
clock-names = "core_clk";
|
|
|
|
qcom,coresight-jtagmm-cpu = <&CPU2>;
|
|
};
|
|
|
|
jtag_mm3: jtagmm@7340000 {
|
|
compatible = "qcom,jtagv8-mm";
|
|
reg = <0x7340000 0x1000>;
|
|
reg-names = "etm-base";
|
|
|
|
clocks = <&clock_aop QDSS_CLK>;
|
|
clock-names = "core_clk";
|
|
|
|
qcom,coresight-jtagmm-cpu = <&CPU3>;
|
|
};
|
|
|
|
jtag_mm4: jtagmm@7440000 {
|
|
compatible = "qcom,jtagv8-mm";
|
|
reg = <0x7440000 0x1000>;
|
|
reg-names = "etm-base";
|
|
|
|
clocks = <&clock_aop QDSS_CLK>;
|
|
clock-names = "core_clk";
|
|
|
|
qcom,coresight-jtagmm-cpu = <&CPU4>;
|
|
};
|
|
|
|
jtag_mm5: jtagmm@7540000 {
|
|
compatible = "qcom,jtagv8-mm";
|
|
reg = <0x7540000 0x1000>;
|
|
reg-names = "etm-base";
|
|
|
|
clocks = <&clock_aop QDSS_CLK>;
|
|
clock-names = "core_clk";
|
|
|
|
qcom,coresight-jtagmm-cpu = <&CPU5>;
|
|
};
|
|
|
|
jtag_mm6: jtagmm@7640000 {
|
|
compatible = "qcom,jtagv8-mm";
|
|
reg = <0x7640000 0x1000>;
|
|
reg-names = "etm-base";
|
|
|
|
clocks = <&clock_aop QDSS_CLK>;
|
|
clock-names = "core_clk";
|
|
|
|
qcom,coresight-jtagmm-cpu = <&CPU6>;
|
|
};
|
|
|
|
jtag_mm7: jtagmm@7740000 {
|
|
compatible = "qcom,jtagv8-mm";
|
|
reg = <0x7740000 0x1000>;
|
|
reg-names = "etm-base";
|
|
|
|
clocks = <&clock_aop QDSS_CLK>;
|
|
clock-names = "core_clk";
|
|
|
|
qcom,coresight-jtagmm-cpu = <&CPU7>;
|
|
};
|
|
|
|
intc: interrupt-controller@17a00000 {
|
|
compatible = "arm,gic-v3";
|
|
#interrupt-cells = <3>;
|
|
interrupt-controller;
|
|
#redistributor-regions = <1>;
|
|
redistributor-stride = <0x0 0x20000>;
|
|
reg = <0x17a00000 0x10000>, /* GICD */
|
|
<0x17a60000 0x100000>; /* GICR * 8 */
|
|
interrupts = <1 9 4>;
|
|
interrupt-parent = <&intc>;
|
|
ignored-save-restore-irqs = <38>;
|
|
};
|
|
|
|
pdc: interrupt-controller@b220000 {
|
|
compatible = "qcom,sdm670-pdc","qcom,pdc";
|
|
reg = <0xb220000 0x400>, <0x179900F0 0x60>;
|
|
qcom,pdc-ranges = <0 480 94>,<94 609 28>;
|
|
qcom,scm-spi-cfg;
|
|
#interrupt-cells = <3>;
|
|
interrupt-parent = <&intc>;
|
|
interrupt-controller;
|
|
};
|
|
|
|
timer {
|
|
compatible = "arm,armv8-timer";
|
|
interrupts = <1 1 0xf08>,
|
|
<1 2 0xf08>,
|
|
<1 3 0xf08>,
|
|
<1 0 0xf08>;
|
|
clock-frequency = <19200000>;
|
|
};
|
|
|
|
qcom,memshare {
|
|
compatible = "qcom,memshare";
|
|
|
|
qcom,client_1 {
|
|
compatible = "qcom,memshare-peripheral";
|
|
qcom,peripheral-size = <0x0>;
|
|
qcom,client-id = <0>;
|
|
qcom,allocate-boot-time;
|
|
label = "modem";
|
|
};
|
|
|
|
qcom,client_2 {
|
|
compatible = "qcom,memshare-peripheral";
|
|
qcom,peripheral-size = <0x0>;
|
|
qcom,client-id = <2>;
|
|
label = "modem";
|
|
};
|
|
|
|
mem_client_3_size: qcom,client_3 {
|
|
compatible = "qcom,memshare-peripheral";
|
|
qcom,peripheral-size = <0x500000>;
|
|
qcom,client-id = <1>;
|
|
qcom,allocate-boot-time;
|
|
label = "modem";
|
|
};
|
|
};
|
|
|
|
qcom,sps {
|
|
compatible = "qcom,msm-sps-4k";
|
|
qcom,pipe-attr-ee;
|
|
};
|
|
|
|
qcom_cedev: qcedev@1de0000 {
|
|
compatible = "qcom,qcedev";
|
|
reg = <0x1de0000 0x20000>,
|
|
<0x1dc4000 0x24000>;
|
|
reg-names = "crypto-base","crypto-bam-base";
|
|
interrupts = <0 272 IRQ_TYPE_LEVEL_HIGH>;
|
|
qcom,bam-pipe-pair = <3>;
|
|
qcom,ce-hw-instance = <0>;
|
|
qcom,ce-device = <0>;
|
|
qcom,ce-hw-shared;
|
|
qcom,bam-ee = <0>;
|
|
qcom,msm-bus,name = "qcedev-noc";
|
|
qcom,msm-bus,num-cases = <2>;
|
|
qcom,msm-bus,num-paths = <1>;
|
|
qcom,msm-bus,vectors-KBps =
|
|
<125 512 0 0>,
|
|
<125 512 393600 393600>;
|
|
clock-names = "core_clk_src", "core_clk",
|
|
"iface_clk", "bus_clk";
|
|
clocks = <&gcc GCC_CE1_CLK>,
|
|
<&gcc GCC_CE1_CLK>,
|
|
<&gcc GCC_CE1_AHB_CLK>,
|
|
<&gcc GCC_CE1_AXI_CLK>;
|
|
qcom,ce-opp-freq = <171430000>;
|
|
qcom,request-bw-before-clk;
|
|
qcom,smmu-s1-enable;
|
|
iommus = <&apps_smmu 0x706 0x1>,
|
|
<&apps_smmu 0x716 0x1>;
|
|
};
|
|
|
|
qcom_crypto: qcrypto@1de0000 {
|
|
compatible = "qcom,qcrypto";
|
|
reg = <0x1de0000 0x20000>,
|
|
<0x1dc4000 0x24000>;
|
|
reg-names = "crypto-base","crypto-bam-base";
|
|
interrupts = <0 272 IRQ_TYPE_LEVEL_HIGH>;
|
|
qcom,bam-pipe-pair = <2>;
|
|
qcom,ce-hw-instance = <0>;
|
|
qcom,ce-device = <0>;
|
|
qcom,bam-ee = <0>;
|
|
qcom,ce-hw-shared;
|
|
qcom,clk-mgmt-sus-res;
|
|
qcom,msm-bus,name = "qcrypto-noc";
|
|
qcom,msm-bus,num-cases = <2>;
|
|
qcom,msm-bus,num-paths = <1>;
|
|
qcom,msm-bus,vectors-KBps =
|
|
<125 512 0 0>,
|
|
<125 512 393600 393600>;
|
|
clock-names = "core_clk_src", "core_clk",
|
|
"iface_clk", "bus_clk";
|
|
clocks = <&gcc GCC_CE1_CLK>,
|
|
<&gcc GCC_CE1_CLK>,
|
|
<&gcc GCC_CE1_AHB_CLK>,
|
|
<&gcc GCC_CE1_AXI_CLK>;
|
|
qcom,ce-opp-freq = <171430000>;
|
|
qcom,request-bw-before-clk;
|
|
qcom,use-sw-aes-cbc-ecb-ctr-algo;
|
|
qcom,use-sw-aes-xts-algo;
|
|
qcom,use-sw-aes-ccm-algo;
|
|
qcom,use-sw-aead-algo;
|
|
qcom,use-sw-ahash-algo;
|
|
qcom,use-sw-hmac-algo;
|
|
qcom,smmu-s1-enable;
|
|
iommus = <&apps_smmu 0x704 0x1>,
|
|
<&apps_smmu 0x714 0x1>;
|
|
};
|
|
|
|
qcom,qbt1000 {
|
|
clock-names = "core", "iface";
|
|
clock-frequency = <25000000>;
|
|
qcom,ipc-gpio = <&tlmm 121 0>;
|
|
qcom,finger-detect-gpio = <&tlmm 122 0>;
|
|
};
|
|
|
|
qcom_seecom: qseecom@86d00000 {
|
|
compatible = "qcom,qseecom";
|
|
reg = <0x86d00000 0x2200000>;
|
|
reg-names = "secapp-region";
|
|
qcom,hlos-num-ce-hw-instances = <1>;
|
|
qcom,hlos-ce-hw-instance = <0>;
|
|
qcom,qsee-ce-hw-instance = <0>;
|
|
qcom,disk-encrypt-pipe-pair = <2>;
|
|
qcom,support-fde;
|
|
qcom,no-clock-support;
|
|
qcom,fde-key-size;
|
|
qcom,appsbl-qseecom-support;
|
|
qcom,msm-bus,name = "qseecom-noc";
|
|
qcom,msm-bus,num-cases = <4>;
|
|
qcom,msm-bus,num-paths = <1>;
|
|
qcom,msm-bus,vectors-KBps =
|
|
<125 512 0 0>,
|
|
<125 512 200000 400000>,
|
|
<125 512 300000 800000>,
|
|
<125 512 400000 1000000>;
|
|
clock-names = "core_clk_src", "core_clk",
|
|
"iface_clk", "bus_clk";
|
|
clocks = <&gcc GCC_CE1_CLK>,
|
|
<&gcc GCC_CE1_CLK>,
|
|
<&gcc GCC_CE1_AHB_CLK>,
|
|
<&gcc GCC_CE1_AXI_CLK>;
|
|
qcom,ce-opp-freq = <171430000>;
|
|
qcom,qsee-reentrancy-support = <2>;
|
|
};
|
|
|
|
qcom_tzlog: tz-log@146bf720 {
|
|
compatible = "qcom,tz-log";
|
|
reg = <0x146bf720 0x3000>;
|
|
qcom,hyplog-enabled;
|
|
hyplog-address-offset = <0x410>;
|
|
hyplog-size-offset = <0x414>;
|
|
};
|
|
|
|
qcom_rng: qrng@793000 {
|
|
compatible = "qcom,msm-rng";
|
|
reg = <0x793000 0x1000>;
|
|
qcom,msm-rng-iface-clk;
|
|
qcom,no-qrng-config;
|
|
qcom,msm-bus,name = "msm-rng-noc";
|
|
qcom,msm-bus,num-cases = <2>;
|
|
qcom,msm-bus,num-paths = <1>;
|
|
qcom,msm-bus,vectors-KBps =
|
|
<1 618 0 0>, /* No vote */
|
|
<1 618 0 800>; /* 100 KHz */
|
|
clocks = <&gcc GCC_PRNG_AHB_CLK>;
|
|
clock-names = "iface_clk";
|
|
};
|
|
|
|
thermal_zones: thermal-zones {};
|
|
|
|
qcom,secure-buffer {
|
|
compatible = "qcom,secure-buffer";
|
|
};
|
|
|
|
logbuf: qcom,logbuf-vendor-hooks {
|
|
compatible = "qcom,logbuf-vendor-hooks";
|
|
};
|
|
|
|
tsens0: tsens@c222000 {
|
|
compatible = "qcom,tsens24xx";
|
|
reg = <0xc222000 0x4>,
|
|
<0xc263000 0x1ff>;
|
|
reg-names = "tsens_srot_physical",
|
|
"tsens_tm_physical";
|
|
interrupts = <0 506 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0 508 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "tsens-upper-lower", "tsens-critical";
|
|
#thermal-sensor-cells = <1>;
|
|
};
|
|
|
|
tsens1: tsens@c223000 {
|
|
compatible = "qcom,tsens24xx";
|
|
reg = <0xc223000 0x4>,
|
|
<0xc265000 0x1ff>;
|
|
reg-names = "tsens_srot_physical",
|
|
"tsens_tm_physical";
|
|
interrupts = <0 507 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0 509 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "tsens-upper-lower", "tsens-critical";
|
|
#thermal-sensor-cells = <1>;
|
|
};
|
|
|
|
timer@0x17c90000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
compatible = "arm,armv7-timer-mem";
|
|
reg = <0x17c90000 0x1000>;
|
|
clock-frequency = <19200000>;
|
|
|
|
frame@0x17ca0000 {
|
|
frame-number = <0>;
|
|
interrupts = <0 7 0x4>,
|
|
<0 6 0x4>;
|
|
reg = <0x17ca0000 0x1000>,
|
|
<0x17cb0000 0x1000>;
|
|
};
|
|
|
|
frame@17cc0000 {
|
|
frame-number = <1>;
|
|
interrupts = <0 8 0x4>;
|
|
reg = <0x17cc0000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@17cd0000 {
|
|
frame-number = <2>;
|
|
interrupts = <0 9 0x4>;
|
|
reg = <0x17cd0000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@17ce0000 {
|
|
frame-number = <3>;
|
|
interrupts = <0 10 0x4>;
|
|
reg = <0x17ce0000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@17cf0000 {
|
|
frame-number = <4>;
|
|
interrupts = <0 11 0x4>;
|
|
reg = <0x17cf0000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@17d00000 {
|
|
frame-number = <5>;
|
|
interrupts = <0 12 0x4>;
|
|
reg = <0x17d00000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@17d10000 {
|
|
frame-number = <6>;
|
|
interrupts = <0 13 0x4>;
|
|
reg = <0x17d10000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
restart@10ac000 {
|
|
compatible = "qcom,pshold";
|
|
reg = <0xC264000 0x4>,
|
|
<0x1fd3000 0x4>;
|
|
reg-names = "pshold-base", "tcsr-boot-misc-detect";
|
|
};
|
|
|
|
gcc: clock-controller@100000 {
|
|
compatible = "qcom,sdm670-gcc", "syscon";
|
|
reg = <0x100000 0x1f0000>;
|
|
reg-names = "cc_base";
|
|
vdd_cx-supply = <&pm660l_s3_level>;
|
|
vdd_cx_ao-supply = <&pm660l_s3_level_ao>;
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>,
|
|
<&sleep_clk>;
|
|
clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
videocc: clock-controller@ab00000 {
|
|
compatible = "qcom,sdm670-videocc", "syscon";
|
|
reg = <0xab00000 0x10000>;
|
|
reg-names = "cc_base";
|
|
vdd_cx-supply = <&pm660l_s3_level>;
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>;
|
|
clock-names = "bi_tcxo";
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
camcc: clock-controller@ad00000 {
|
|
compatible = "qcom,sdm670-camcc", "syscon";
|
|
reg = <0xad00000 0x10000>;
|
|
reg-names = "cc_base";
|
|
vdd_cx-supply = <&pm660l_s3_level>;
|
|
vdd_mx-supply = <&pm660l_s1_level>;
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>;
|
|
clock-names = "bi_tcxo";
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
/* TBD */
|
|
};
|
|
|
|
dispcc: clock-controller@af00000 {
|
|
compatible = "qcom,sdm670-dispcc", "syscon";
|
|
reg = <0xaf00000 0x10000>;
|
|
reg-names = "cc_base";
|
|
vdd_cx-supply = <&pm660l_s3_level>;
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>;
|
|
clock-names = "bi_tcxo";
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
gpucc: clock-controller@5090000 {
|
|
compatible = "qcom,sdm670-gpucc", "syscon";
|
|
reg = <0x5090000 0x9000>;
|
|
reg-names = "cc_base";
|
|
vdd_cx-supply = <&pm660l_s3_level>;
|
|
vdd_mx-supply = <&pm660l_s1_level>;
|
|
vdd_gfx-supply = <&pm660l_s2_level>;
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>;
|
|
clock-names = "bi_tcxo";
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
cpucc_debug: syscon@17970018 {
|
|
compatible = "syscon";
|
|
reg = <0x17970018 0x4>;
|
|
};
|
|
|
|
debugcc: clock-controller@0 {
|
|
compatible = "qcom,sdm845-debugcc";
|
|
qcom,cc-count = <6>;
|
|
qcom,gcc = <&gcc>;
|
|
qcom,videocc = <&videocc>;
|
|
qcom,camcc = <&camcc>;
|
|
qcom,dispcc = <&dispcc>;
|
|
qcom,gpucc = <&gpucc>;
|
|
qcom,cpucc = <&cpucc_debug>;
|
|
clock-names = "xo_clk_src";
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
clock_cpucc: qcom,cpucc@0x17d41000 {
|
|
reg = <0x17d41000 0x1400>,
|
|
<0x17d43000 0x1400>,
|
|
<0x17d45800 0x1400>;
|
|
reg-names = "osm_l3_base", "osm_pwrcl_base", "osm_perfcl_base";
|
|
vdd_l3_mx_ao-supply = <&pm660l_s1_level_ao>;
|
|
vdd_pwrcl_mx_ao-supply = <&pm660l_s1_level_ao>;
|
|
|
|
qcom,mx-turbo-freq = <1440000000 1708000000 3300000001>;
|
|
l3-devs = <&l3_cpu0 &l3_cpu6 &l3_cdsp>;
|
|
|
|
clock-names = "xo_ao";
|
|
clocks = <&rpmhcc RPMH_CXO_CLK_A>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
clock_aop: qcom,aopclk {
|
|
#clock-cells = <1>;
|
|
mboxes = <&qmp_aop 0>;
|
|
mbox-names = "qdss_clk";
|
|
};
|
|
|
|
slim_aud: slim@62dc0000 {
|
|
cell-index = <1>;
|
|
compatible = "qcom,slim-ngd";
|
|
reg = <0x62dc0000 0x2c000>,
|
|
<0x62d84000 0x2a000>;
|
|
reg-names = "slimbus_physical", "slimbus_bam_physical";
|
|
interrupts = <0 163 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0 164 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "slimbus_irq", "slimbus_bam_irq";
|
|
qcom,apps-ch-pipes = <0x780000>;
|
|
qcom,ea-pc = <0x290>;
|
|
status = "disabled";
|
|
qcom,iommu-s1-bypass;
|
|
|
|
iommu_slim_aud_ctrl_cb: qcom,iommu_slim_ctrl_cb {
|
|
iommus = <&apps_smmu 0x1826 0x0>,
|
|
<&apps_smmu 0x182d 0x0>,
|
|
<&apps_smmu 0x182e 0x1>,
|
|
<&apps_smmu 0x1830 0x1>;
|
|
};
|
|
|
|
};
|
|
|
|
slim_qca: slim@62e40000 {
|
|
cell-index = <3>;
|
|
compatible = "qcom,slim-ngd";
|
|
reg = <0x62e40000 0x2c000>,
|
|
<0x62e04000 0x20000>;
|
|
reg-names = "slimbus_physical", "slimbus_bam_physical";
|
|
interrupts = <0 291 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0 292 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "slimbus_irq", "slimbus_bam_irq";
|
|
status = "ok";
|
|
qcom,iommu-s1-bypass;
|
|
|
|
iommu_slim_qca_ctrl_cb: qcom,iommu_slim_ctrl_cb {
|
|
iommus = <&apps_smmu 0x1833 0x0>;
|
|
};
|
|
};
|
|
|
|
wdog: qcom,wdt@17980000 {
|
|
compatible = "qcom,msm-watchdog";
|
|
reg = <0x17980000 0x1000>;
|
|
reg-names = "wdt-base";
|
|
interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0 1 IRQ_TYPE_LEVEL_HIGH>;
|
|
qcom,bark-time = <11000>;
|
|
qcom,pet-time = <9360>;
|
|
qcom,ipi-ping;
|
|
qcom,wakeup-enable;
|
|
};
|
|
|
|
qcom,msm-rtb {
|
|
compatible = "qcom,msm-rtb";
|
|
qcom,rtb-size = <0x100000>;
|
|
};
|
|
|
|
qcom,mpm2-sleep-counter@c221000 {
|
|
compatible = "qcom,mpm2-sleep-counter";
|
|
reg = <0x0c221000 0x1000>;
|
|
clock-frequency = <32768>;
|
|
};
|
|
|
|
vendor_hooks: qcom,cpu-vendor-hooks {
|
|
compatible = "qcom,cpu-vendor-hooks";
|
|
};
|
|
|
|
qcom,msm-imem@146bf000 {
|
|
compatible = "qcom,msm-imem";
|
|
reg = <0x146bf000 0x1000>;
|
|
ranges = <0x0 0x146bf000 0x1000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
mem_dump_table@10 {
|
|
compatible = "qcom,msm-imem-mem_dump_table";
|
|
reg = <0x10 0x8>;
|
|
};
|
|
|
|
dload_type@1c {
|
|
compatible = "qcom,msm-imem-dload-type";
|
|
reg = <0x1c 0x4>;
|
|
};
|
|
|
|
restart_reason@65c {
|
|
compatible = "qcom,msm-imem-restart_reason";
|
|
reg = <0x65c 0x4>;
|
|
};
|
|
|
|
pil@94c {
|
|
compatible = "qcom,msm-imem-pil";
|
|
reg = <0x94c 0xc8>;
|
|
};
|
|
|
|
kaslr_offset@6d0 {
|
|
compatible = "qcom,msm-imem-kaslr_offset";
|
|
reg = <0x6d0 0xc>;
|
|
};
|
|
|
|
boot_stats@6b0 {
|
|
compatible = "qcom,msm-imem-boot_stats";
|
|
reg = <0x6b0 0x20>;
|
|
};
|
|
|
|
diag_dload@c8 {
|
|
compatible = "qcom,msm-imem-diag-dload";
|
|
reg = <0xc8 0xc8>;
|
|
};
|
|
};
|
|
|
|
cpuss_dump {
|
|
qcom,l1_i_cache0 {
|
|
qcom,dump-node = <&L1_I_0>;
|
|
qcom,dump-id = <0x60>;
|
|
};
|
|
|
|
qcom,l1_i_cache100 {
|
|
qcom,dump-node = <&L1_I_100>;
|
|
qcom,dump-id = <0x61>;
|
|
};
|
|
|
|
qcom,l1_i_cache200 {
|
|
qcom,dump-node = <&L1_I_200>;
|
|
qcom,dump-id = <0x62>;
|
|
};
|
|
|
|
qcom,l1_i_cache300 {
|
|
qcom,dump-node = <&L1_I_300>;
|
|
qcom,dump-id = <0x63>;
|
|
};
|
|
|
|
qcom,l1_i_cache400 {
|
|
qcom,dump-node = <&L1_I_400>;
|
|
qcom,dump-id = <0x64>;
|
|
};
|
|
|
|
qcom,l1_i_cache500 {
|
|
qcom,dump-node = <&L1_I_500>;
|
|
qcom,dump-id = <0x65>;
|
|
};
|
|
|
|
qcom,l1_i_cache600 {
|
|
qcom,dump-node = <&L1_I_600>;
|
|
qcom,dump-id = <0x66>;
|
|
};
|
|
|
|
qcom,l1_i_cache700 {
|
|
qcom,dump-node = <&L1_I_700>;
|
|
qcom,dump-id = <0x67>;
|
|
};
|
|
|
|
qcom,l1_d_cache0 {
|
|
qcom,dump-node = <&L1_D_0>;
|
|
qcom,dump-id = <0x80>;
|
|
};
|
|
|
|
qcom,l1_d_cache100 {
|
|
qcom,dump-node = <&L1_D_100>;
|
|
qcom,dump-id = <0x81>;
|
|
};
|
|
|
|
qcom,l1_d_cache200 {
|
|
qcom,dump-node = <&L1_D_200>;
|
|
qcom,dump-id = <0x82>;
|
|
};
|
|
|
|
qcom,l1_d_cache300 {
|
|
qcom,dump-node = <&L1_D_300>;
|
|
qcom,dump-id = <0x83>;
|
|
};
|
|
|
|
qcom,l1_d_cache400 {
|
|
qcom,dump-node = <&L1_D_400>;
|
|
qcom,dump-id = <0x84>;
|
|
};
|
|
|
|
qcom,l1_d_cache500 {
|
|
qcom,dump-node = <&L1_D_500>;
|
|
qcom,dump-id = <0x85>;
|
|
};
|
|
|
|
qcom,l1_d_cache600 {
|
|
qcom,dump-node = <&L1_D_600>;
|
|
qcom,dump-id = <0x86>;
|
|
};
|
|
|
|
qcom,l1_d_cache700 {
|
|
qcom,dump-node = <&L1_D_700>;
|
|
qcom,dump-id = <0x87>;
|
|
};
|
|
|
|
qcom,llcc1_d_cache {
|
|
qcom,dump-node = <&LLCC_1>;
|
|
qcom,dump-id = <0x140>;
|
|
};
|
|
|
|
qcom,llcc2_d_cache {
|
|
qcom,dump-node = <&LLCC_2>;
|
|
qcom,dump-id = <0x141>;
|
|
};
|
|
|
|
qcom,l1_tlb_dump0 {
|
|
qcom,dump-node = <&L1_TLB_0>;
|
|
qcom,dump-id = <0x20>;
|
|
};
|
|
|
|
qcom,l1_tlb_dump100 {
|
|
qcom,dump-node = <&L1_TLB_100>;
|
|
qcom,dump-id = <0x21>;
|
|
};
|
|
|
|
qcom,l1_tlb_dump200 {
|
|
qcom,dump-node = <&L1_TLB_200>;
|
|
qcom,dump-id = <0x22>;
|
|
};
|
|
|
|
qcom,l1_tlb_dump300 {
|
|
qcom,dump-node = <&L1_TLB_300>;
|
|
qcom,dump-id = <0x23>;
|
|
};
|
|
|
|
qcom,l1_tlb_dump400 {
|
|
qcom,dump-node = <&L1_TLB_400>;
|
|
qcom,dump-id = <0x24>;
|
|
};
|
|
|
|
qcom,l1_tlb_dump500 {
|
|
qcom,dump-node = <&L1_TLB_500>;
|
|
qcom,dump-id = <0x25>;
|
|
};
|
|
|
|
qcom,l1_tlb_dump600 {
|
|
qcom,dump-node = <&L1_TLB_600>;
|
|
qcom,dump-id = <0x26>;
|
|
};
|
|
|
|
qcom,l1_tlb_dump700 {
|
|
qcom,dump-node = <&L1_TLB_700>;
|
|
qcom,dump-id = <0x27>;
|
|
};
|
|
};
|
|
|
|
mem_dump: mem_dump {
|
|
compatible = "qcom,mem-dump";
|
|
memory-region = <&dump_mem>;
|
|
|
|
rpmh {
|
|
qcom,dump-size = <0x2000000>;
|
|
qcom,dump-id = <0xec>;
|
|
};
|
|
|
|
fcm {
|
|
qcom,dump-size = <0x8400>;
|
|
qcom,dump-id = <0xee>;
|
|
};
|
|
|
|
rpm_sw {
|
|
qcom,dump-size = <0x28000>;
|
|
qcom,dump-id = <0xea>;
|
|
};
|
|
|
|
pmic {
|
|
qcom,dump-size = <0x10000>;
|
|
qcom,dump-id = <0xe4>;
|
|
};
|
|
|
|
tmc_etf {
|
|
qcom,dump-size = <0x10000>;
|
|
qcom,dump-id = <0xf0>;
|
|
};
|
|
|
|
tmc_etfswao {
|
|
qcom,dump-size = <0x8400>;
|
|
qcom,dump-id = <0xf1>;
|
|
};
|
|
|
|
tmc_etr_reg {
|
|
qcom,dump-size = <0x1000>;
|
|
qcom,dump-id = <0x100>;
|
|
};
|
|
|
|
tmc_etf_reg {
|
|
qcom,dump-size = <0x1000>;
|
|
qcom,dump-id = <0x101>;
|
|
};
|
|
|
|
etfswao_reg {
|
|
qcom,dump-size = <0x1000>;
|
|
qcom,dump-id = <0x102>;
|
|
};
|
|
|
|
misc_data {
|
|
qcom,dump-size = <0x1000>;
|
|
qcom,dump-id = <0xe8>;
|
|
};
|
|
|
|
power_regs {
|
|
qcom,dump-size = <0x100000>;
|
|
qcom,dump-id = <0xed>;
|
|
};
|
|
};
|
|
|
|
kryo3xx-erp {
|
|
interrupts = <1 6 4>,
|
|
<1 7 4>,
|
|
<0 34 4>,
|
|
<0 35 4>;
|
|
|
|
interrupt-names = "l1-l2-faultirq",
|
|
"l1-l2-errirq",
|
|
"l3-scu-errirq",
|
|
"l3-scu-faultirq";
|
|
};
|
|
|
|
tcsr_mutex_block: syscon@1f40000 {
|
|
compatible = "syscon";
|
|
reg = <0x1f40000 0x20000>;
|
|
};
|
|
|
|
tcsr_mutex: hwlock {
|
|
compatible = "qcom,tcsr-mutex";
|
|
syscon = <&tcsr_mutex_block 0 0x1000>;
|
|
#hwlock-cells = <1>;
|
|
};
|
|
|
|
smem {
|
|
compatible = "qcom,smem";
|
|
memory-region = <&smem_mem>;
|
|
hwlocks = <&tcsr_mutex 3>;
|
|
};
|
|
|
|
apcs: syscon@1799000c {
|
|
compatible = "syscon";
|
|
reg = <0x1799000c 0x4>;
|
|
};
|
|
|
|
|
|
apss_shared: mailbox@17990000 {
|
|
compatible = "qcom,sm8150-apss-shared";
|
|
reg = <0x17990000 0x1000>;
|
|
#mbox-cells = <1>;
|
|
};
|
|
|
|
aoss_qmp: power-controller@c300000 {
|
|
compatible = "qcom,qcs605-aoss-qmp";
|
|
reg = <0xc300000 0x100000>;
|
|
interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
|
|
mboxes = <&apss_shared 0>;
|
|
|
|
#clock-cells = <0>;
|
|
#power-domain-cells = <1>;
|
|
};
|
|
|
|
qmp_aop: qcom,qmp-aop@c300000 {
|
|
compatible = "qcom,qmp-mbox";
|
|
qcom,qmp = <&aoss_qmp>;
|
|
label = "aop";
|
|
#mbox-cells = <1>;
|
|
};
|
|
|
|
qcom,smp2p-modem {
|
|
compatible = "qcom,smp2p";
|
|
qcom,smem = <435>, <428>;
|
|
interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
|
|
mboxes = <&apss_shared 14>;
|
|
qcom,local-pid = <0>;
|
|
qcom,remote-pid = <1>;
|
|
|
|
modem_smp2p_out: master-kernel {
|
|
qcom,entry-name = "master-kernel";
|
|
#qcom,smem-state-cells = <1>;
|
|
};
|
|
|
|
modem_smp2p_in: slave-kernel {
|
|
qcom,entry-name = "slave-kernel";
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
};
|
|
|
|
qcom,smp2p-adsp {
|
|
compatible = "qcom,smp2p";
|
|
qcom,smem = <443>, <429>;
|
|
mboxes = <&apss_shared 10>;
|
|
qcom,local-pid = <0>;
|
|
qcom,remote-pid = <2>;
|
|
interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>;
|
|
adsp_smp2p_out: master-kernel {
|
|
qcom,entry-name = "master-kernel";
|
|
#qcom,smem-state-cells = <1>;
|
|
};
|
|
|
|
adsp_smp2p_in: slave-kernel {
|
|
qcom,entry-name = "slave-kernel";
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
smp2p_rdbg2_out: qcom,smp2p-rdbg2-out {
|
|
qcom,entry-name = "rdbg";
|
|
#qcom,smem-state-cells = <1>;
|
|
};
|
|
|
|
smp2p_rdbg2_in: qcom,smp2p-rdbg2-in {
|
|
qcom,entry-name = "rdbg";
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
|
|
};
|
|
|
|
qcom,smp2p-cdsp@1799000c {
|
|
compatible = "qcom,smp2p";
|
|
qcom,smem = <94>, <432>;
|
|
mboxes = <&apss_shared 30>;
|
|
qcom,local-pid = <0>;
|
|
qcom,remote-pid = <5>;
|
|
interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;
|
|
cdsp_smp2p_out: master-kernel {
|
|
qcom,entry-name = "master-kernel";
|
|
#qcom,smem-state-cells = <1>;
|
|
};
|
|
|
|
cdsp_smp2p_in: slave-kernel {
|
|
qcom,entry-name = "slave-kernel";
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
smp2p_rdbg5_out: qcom,smp2p-rdbg5-out {
|
|
qcom,entry-name = "rdbg";
|
|
#qcom,smem-state-cells = <1>;
|
|
};
|
|
|
|
smp2p_rdbg5_in: qcom,smp2p-rdbg5-in {
|
|
qcom,entry-name = "rdbg";
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
|
|
};
|
|
|
|
qcom,glinkpkt {
|
|
compatible = "qcom,glinkpkt";
|
|
|
|
qcom,glinkpkt-at-mdm0 {
|
|
qcom,glinkpkt-edge = "mpss";
|
|
qcom,glinkpkt-ch-name = "DS";
|
|
qcom,glinkpkt-dev-name = "at_mdm0";
|
|
};
|
|
|
|
qcom,glinkpkt-apr-apps2 {
|
|
qcom,glinkpkt-edge = "adsp";
|
|
qcom,glinkpkt-ch-name = "apr_apps2";
|
|
qcom,glinkpkt-dev-name = "apr_apps2";
|
|
};
|
|
|
|
qcom,glinkpkt-data40-cntl {
|
|
qcom,glinkpkt-edge = "mpss";
|
|
qcom,glinkpkt-ch-name = "DATA40_CNTL";
|
|
qcom,glinkpkt-dev-name = "smdcntl8";
|
|
};
|
|
|
|
qcom,glinkpkt-data1 {
|
|
qcom,glinkpkt-edge = "mpss";
|
|
qcom,glinkpkt-ch-name = "DATA1";
|
|
qcom,glinkpkt-dev-name = "smd7";
|
|
};
|
|
|
|
qcom,glinkpkt-data4 {
|
|
qcom,glinkpkt-edge = "mpss";
|
|
qcom,glinkpkt-ch-name = "DATA4";
|
|
qcom,glinkpkt-dev-name = "smd8";
|
|
};
|
|
|
|
qcom,glinkpkt-data11 {
|
|
qcom,glinkpkt-edge = "mpss";
|
|
qcom,glinkpkt-ch-name = "DATA11";
|
|
qcom,glinkpkt-dev-name = "smd11";
|
|
};
|
|
|
|
};
|
|
|
|
qcom,chd_silver {
|
|
compatible = "qcom,core-hang-detect";
|
|
label = "silver";
|
|
qcom,threshold-arr = <0x17e00058 0x17e10058 0x17e20058
|
|
0x17e30058 0x17e40058 0x17e50058>;
|
|
qcom,config-arr = <0x17e00060 0x17e10060 0x17e20060
|
|
0x17e30060 0x17e40060 0x17e50060>;
|
|
};
|
|
|
|
qcom,chd_gold {
|
|
compatible = "qcom,core-hang-detect";
|
|
label = "gold";
|
|
qcom,threshold-arr = <0x17e60058 0x17e70058>;
|
|
qcom,config-arr = <0x17e60060 0x17e70060>;
|
|
};
|
|
|
|
qcom,ghd {
|
|
compatible = "qcom,gladiator-hang-detect-v2";
|
|
qcom,threshold-arr = <0x1799041c 0x17990420>;
|
|
qcom,config-reg = <0x17990434>;
|
|
};
|
|
|
|
qcom,msm-gladiator-v3@17900000 {
|
|
compatible = "qcom,msm-gladiator-v3";
|
|
reg = <0x17900000 0xd080>;
|
|
reg-names = "gladiator_base";
|
|
interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
eud: qcom,msm-eud@88e0000 {
|
|
compatible = "qcom,msm-eud";
|
|
interrupt-names = "eud_irq";
|
|
interrupts = <GIC_SPI 492 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x88e0000 0x2000>;
|
|
reg-names = "eud_base";
|
|
clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>;
|
|
clock-names = "cfg_ahb_clk";
|
|
};
|
|
|
|
qcom,llcc@1100000 {
|
|
reg = <0x1100000 0x250000>;
|
|
reg-names = "llcc_base";
|
|
qcom,llcc-banks-off = <0x0 0x80000 >;
|
|
qcom,llcc-broadcast-off = <0x200000>;
|
|
|
|
llcc: qcom,sdm670-llcc {
|
|
#cache-cells = <1>;
|
|
max-slices = <32>;
|
|
qcom,dump-size = <0x80000>;
|
|
};
|
|
|
|
qcom,llcc-erp {
|
|
interrupt-names = "ecc_irq";
|
|
interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
LLCC_1: llcc_1_dcache {
|
|
qcom,dump-size = <0xd8000>;
|
|
};
|
|
|
|
LLCC_2: llcc_2_dcache {
|
|
qcom,dump-size = <0xd8000>;
|
|
};
|
|
};
|
|
|
|
apps_rsc: rsc@179c0000 {
|
|
label = "apps_rsc";
|
|
compatible = "qcom,rpmh-rsc";
|
|
reg = <0x179c0000 0x10000>,
|
|
<0x179d0000 0x10000>,
|
|
<0x179e0000 0x10000>;
|
|
reg-names = "drv-0", "drv-1", "drv-2";
|
|
qcom,drv-count = <3>;
|
|
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
apps_rsc_drv2: drv@2 {
|
|
qcom,drv-id = <2>;
|
|
qcom,tcs-offset = <0xd00>;
|
|
channel@0 {
|
|
qcom,tcs-config = <ACTIVE_TCS 2>,
|
|
<SLEEP_TCS 3>,
|
|
<WAKE_TCS 3>,
|
|
<CONTROL_TCS 1>,
|
|
<FAST_PATH_TCS 0>;
|
|
};
|
|
|
|
rpmhcc: clock-controller {
|
|
compatible = "qcom,sdm670-rpmh-clk";
|
|
#clock-cells = <1>;
|
|
clock-names = "xo";
|
|
clocks = <&xo_board>;
|
|
status = "okay";
|
|
};
|
|
|
|
apps_bcm_voter: bcm_voter {
|
|
compatible = "qcom,bcm-voter";
|
|
};
|
|
|
|
};
|
|
};
|
|
|
|
disp_rsc: disp_rsc@af20000 {
|
|
label = "disp_rsc";
|
|
compatible = "qcom,rpmh-rsc";
|
|
reg = <0xaf20000 0x10000>;
|
|
reg-names = "drv-0";
|
|
qcom,drv-count = <1>;
|
|
interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&dispcc DISP_CC_MDSS_RSCC_AHB_CLK>;
|
|
|
|
disp_rsc_drv0: drv@0 {
|
|
qcom,drv-id = <0>;
|
|
qcom,tcs-offset = <0x1c00>;
|
|
channel@0 {
|
|
qcom,tcs-config = <ACTIVE_TCS 0>,
|
|
<SLEEP_TCS 1>,
|
|
<WAKE_TCS 1>,
|
|
<CONTROL_TCS 1>,
|
|
<FAST_PATH_TCS 0>;
|
|
};
|
|
|
|
disp_bcm_voter: bcm_voter {
|
|
compatible = "qcom,bcm-voter";
|
|
qcom,tcs-wait = <QCOM_ICC_TAG_AMC>;
|
|
};
|
|
};
|
|
};
|
|
|
|
dcc: dcc_v2@10a2000 {
|
|
compatible = "qcom,dcc-v2";
|
|
reg = <0x10a2000 0x1000>,
|
|
<0x10ae000 0x2000>;
|
|
reg-names = "dcc-base", "dcc-ram-base";
|
|
|
|
dcc-ram-offset = <0x6000>;
|
|
/*Need to check for */
|
|
};
|
|
|
|
spmi_bus: qcom,spmi@c440000 {
|
|
compatible = "qcom,spmi-pmic-arb";
|
|
reg = <0xc440000 0x1100>,
|
|
<0xc600000 0x2000000>,
|
|
<0xe600000 0x100000>,
|
|
<0xe700000 0xa0000>,
|
|
<0xc40a000 0x26000>;
|
|
reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
|
|
interrupt-names = "periph_irq";
|
|
interrupts = <GIC_SPI 481 IRQ_TYPE_EDGE_RISING>;
|
|
qcom,ee = <0>;
|
|
qcom,channel = <0>;
|
|
#address-cells = <2>;
|
|
#size-cells = <0>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <4>;
|
|
cell-index = <0>;
|
|
};
|
|
|
|
ufs_ice: ufsice@1d90000 {
|
|
compatible = "qcom,ice";
|
|
reg = <0x1d90000 0x8000>;
|
|
qcom,enable-ice-clk;
|
|
clock-names = "ufs_core_clk", "bus_clk",
|
|
"iface_clk", "ice_core_clk";
|
|
clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
|
|
<&gcc GCC_UFS_MEM_CLKREF_CLK>,
|
|
<&gcc GCC_UFS_PHY_AHB_CLK>,
|
|
<&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
|
|
qcom,op-freq-hz = <0>, <0>, <0>, <300000000>;
|
|
vdd-hba-supply = <&ufs_phy_gdsc>;
|
|
qcom,msm-bus,name = "ufs_ice_noc";
|
|
qcom,msm-bus,num-cases = <2>;
|
|
qcom,msm-bus,num-paths = <1>;
|
|
qcom,msm-bus,vectors-KBps =
|
|
<1 650 0 0>, /* No vote */
|
|
<1 650 1000 0>; /* Max. bandwidth */
|
|
qcom,bus-vector-names = "MIN",
|
|
"MAX";
|
|
qcom,instance-type = "ufs";
|
|
};
|
|
|
|
ufsphy_mem: ufsphy_mem@1d87000 {
|
|
reg = <0x1d87000 0xe00>; /* PHY regs */
|
|
reg-names = "phy_mem";
|
|
#phy-cells = <0>;
|
|
|
|
lanes-per-direction = <1>;
|
|
|
|
clock-names = "ref_clk_src",
|
|
"ref_clk",
|
|
"ref_aux_clk";
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
|
<&gcc GCC_UFS_MEM_CLKREF_CLK>,
|
|
<&gcc GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
ufshc_mem: ufshc@1d84000 {
|
|
compatible = "qcom,ufshc";
|
|
reg = <0x1d84000 0x3000>;
|
|
interrupts = <0 265 IRQ_TYPE_LEVEL_HIGH>;
|
|
phys = <&ufsphy_mem>;
|
|
phy-names = "ufsphy";
|
|
ufs-qcom-crypto = <&ufs_ice>;
|
|
|
|
lanes-per-direction = <1>;
|
|
spm-level = <5>;
|
|
dev-ref-clk-freq = <0>; /* 19.2 MHz */
|
|
|
|
clock-names =
|
|
"core_clk",
|
|
"bus_aggr_clk",
|
|
"iface_clk",
|
|
"core_clk_unipro",
|
|
"core_clk_ice",
|
|
"ref_clk",
|
|
"tx_lane0_sync_clk",
|
|
"rx_lane0_sync_clk";
|
|
clocks =
|
|
<&gcc GCC_UFS_PHY_AXI_HW_CTL_CLK>,
|
|
<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
|
|
<&gcc GCC_UFS_PHY_AHB_CLK>,
|
|
<&gcc GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK>,
|
|
<&gcc GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK>,
|
|
<&rpmhcc RPMH_CXO_CLK>,
|
|
<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
|
|
<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>;
|
|
freq-table-hz =
|
|
<50000000 200000000>,
|
|
<0 0>,
|
|
<0 0>,
|
|
<37500000 150000000>,
|
|
<75000000 300000000>,
|
|
<0 0>,
|
|
<0 0>,
|
|
<0 0>;
|
|
|
|
non-removable;
|
|
qcom,msm-bus,name = "ufshc_mem";
|
|
qcom,msm-bus,num-cases = <12>;
|
|
qcom,msm-bus,num-paths = <2>;
|
|
qcom,msm-bus,vectors-KBps =
|
|
/*
|
|
* During HS G3 UFS runs at nominal voltage corner, vote
|
|
* higher bandwidth to push other buses in the data path
|
|
* to run at nominal to achieve max throughput.
|
|
* 4GBps pushes BIMC to run at nominal.
|
|
* 200MBps pushes CNOC to run at nominal.
|
|
* Vote for half of this bandwidth for HS G3 1-lane.
|
|
* For max bandwidth, vote high enough to push the buses
|
|
* to run in turbo voltage corner.
|
|
*/
|
|
<123 512 0 0>, <1 757 0 0>, /* No vote */
|
|
<123 512 922 0>, <1 757 1000 0>, /* PWM G1 */
|
|
<123 512 1844 0>, <1 757 1000 0>, /* PWM G2 */
|
|
<123 512 3688 0>, <1 757 1000 0>, /* PWM G3 */
|
|
<123 512 7376 0>, <1 757 1000 0>, /* PWM G4 */
|
|
<123 512 127796 0>, <1 757 1000 0>, /* HS G1 RA */
|
|
<123 512 255591 0>, <1 757 1000 0>, /* HS G2 RA */
|
|
<123 512 2097152 0>, <1 757 102400 0>, /* HS G3 RA */
|
|
<123 512 149422 0>, <1 757 1000 0>, /* HS G1 RB */
|
|
<123 512 298189 0>, <1 757 1000 0>, /* HS G2 RB */
|
|
<123 512 2097152 0>, <1 757 102400 0>, /* HS G3 RB */
|
|
<123 512 7643136 0>, <1 757 307200 0>; /* Max. bandwidth */
|
|
|
|
qcom,bus-vector-names = "MIN",
|
|
"PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1",
|
|
"HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1",
|
|
"HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1",
|
|
"MAX";
|
|
|
|
/* PM QoS */
|
|
qcom,pm-qos-cpu-groups = <0x3f 0xC0>;
|
|
qcom,pm-qos-cpu-group-latency-us = <67 67>;
|
|
qcom,pm-qos-default-cpu = <0>;
|
|
|
|
pinctrl-names = "dev-reset-assert", "dev-reset-deassert";
|
|
pinctrl-0 = <&ufs_dev_reset_assert>;
|
|
pinctrl-1 = <&ufs_dev_reset_deassert>;
|
|
|
|
resets = <&gcc GCC_UFS_PHY_BCR>;
|
|
reset-names = "core_reset";
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
adsp_pas:remoteproc-adsp@62400000 {
|
|
compatible = "qcom,qcs605-adsp-pas";
|
|
reg = <0x62400000 0x00100>;
|
|
|
|
cx-supply = <&pm660l_l9_level>;
|
|
cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
|
|
reg-names = "cx";
|
|
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>;
|
|
clock-names = "xo";
|
|
|
|
memory-region = <&pil_adsp_mem>;
|
|
|
|
/* Inputs from lpass */
|
|
interrupts-extended = <&intc 0 162 1>,
|
|
<&adsp_smp2p_in 0 0>,
|
|
<&adsp_smp2p_in 2 0>,
|
|
<&adsp_smp2p_in 1 0>,
|
|
<&adsp_smp2p_in 3 0>,
|
|
<&adsp_smp2p_in 7 0>;
|
|
|
|
interrupt-names = "wdog",
|
|
"fatal",
|
|
"handover",
|
|
"ready",
|
|
"stop-ack",
|
|
"shutdown-ack";
|
|
|
|
/* Outputs to lpass */
|
|
qcom,smem-states = <&adsp_smp2p_out 0>;
|
|
qcom,smem-state-names = "stop";
|
|
|
|
status = "ok";
|
|
|
|
glink_edge: glink-edge {
|
|
qcom,remote-pid = <2>;
|
|
transport = "smem";
|
|
mboxes = <&qmp_aop 0>;
|
|
mbox-names = "adsp_smem";
|
|
interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>;
|
|
|
|
label = "adsp";
|
|
qcom,glink-label = "lpass";
|
|
|
|
qcom,adsp_qrtr {
|
|
qcom,glink-channels = "IPCRTR";
|
|
qcom,intents = <0x800 5
|
|
0x2000 3
|
|
0x4400 2>;
|
|
qcom,no-wake-svc = <0x190>;
|
|
};
|
|
|
|
qcom,msm_fastrpc_rpmsg {
|
|
compatible = "qcom,msm-fastrpc-rpmsg";
|
|
qcom,glink-channels = "fastrpcglink-apps-dsp";
|
|
qcom,intents = <0x64 64>;
|
|
};
|
|
|
|
qcom,apr_tal_rpmsg {
|
|
qcom,glink-channels = "apr_audio_svc";
|
|
qcom,intents = <0x200 20>;
|
|
};
|
|
};
|
|
};
|
|
|
|
|
|
qcom,rmtfs_sharedmem@0 {
|
|
compatible = "qcom,sharedmem-uio";
|
|
reg = <0x0 0x200000>;
|
|
reg-names = "rmtfs";
|
|
qcom,client-id = <0x00000001>;
|
|
qcom,guard-memory;
|
|
};
|
|
|
|
qcom,msm_gsi {
|
|
compatible = "qcom,msm_gsi";
|
|
};
|
|
|
|
qcom,rmnet-ipa {
|
|
compatible = "qcom,rmnet-ipa3";
|
|
qcom,rmnet-ipa-ssr;
|
|
qcom,ipa-loaduC;
|
|
qcom,ipa-advertise-sg-support;
|
|
qcom,ipa-napi-enable;
|
|
};
|
|
|
|
ipa_hw: qcom,ipa@01e00000 {
|
|
compatible = "qcom,ipa";
|
|
reg = <0x1e00000 0x34000>,
|
|
<0x1e04000 0x2c000>;
|
|
reg-names = "ipa-base", "gsi-base";
|
|
interrupts =
|
|
<0 311 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0 432 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "ipa-irq", "gsi-irq";
|
|
qcom,ipa-hw-ver = <13>; /* IPA core version = IPAv3.5.1 */
|
|
qcom,ipa-hw-mode = <0>;
|
|
qcom,ee = <0>;
|
|
qcom,use-ipa-tethering-bridge;
|
|
qcom,modem-cfg-emb-pipe-flt;
|
|
qcom,ipa-wdi2;
|
|
qcom,use-64-bit-dma-mask;
|
|
qcom,arm-smmu;
|
|
qcom,bandwidth-vote-for-ipa;
|
|
qcom,msm-bus,name = "ipa";
|
|
qcom,msm-bus,num-cases = <5>;
|
|
qcom,msm-bus,num-paths = <4>;
|
|
qcom,msm-bus,vectors-KBps =
|
|
/* No vote */
|
|
<90 512 0 0>,
|
|
<90 585 0 0>,
|
|
<1 676 0 0>,
|
|
<143 777 0 0>,
|
|
/* SVS2 */
|
|
<90 512 80000 600000>,
|
|
<90 585 80000 350000>,
|
|
<1 676 40000 40000>, /*gcc_config_noc_clk_src */
|
|
<143 777 0 75>, /* IB defined for IPA2X_clk in MHz*/
|
|
/* SVS */
|
|
<90 512 80000 640000>,
|
|
<90 585 80000 640000>,
|
|
<1 676 80000 80000>,
|
|
<143 777 0 150>, /* IB defined for IPA2X_clk in MHz*/
|
|
/* NOMINAL */
|
|
<90 512 206000 960000>,
|
|
<90 585 206000 960000>,
|
|
<1 676 206000 160000>,
|
|
<143 777 0 300>, /* IB defined for IPA2X_clk in MHz*/
|
|
/* TURBO */
|
|
<90 512 206000 3600000>,
|
|
<90 585 206000 3600000>,
|
|
<1 676 206000 300000>,
|
|
<143 777 0 355>; /* IB defined for IPA clk in MHz*/
|
|
qcom,bus-vector-names =
|
|
"MIN", "SVS2", "SVS", "NOMINAL", "TURBO";
|
|
|
|
/* IPA RAM mmap */
|
|
qcom,ipa-ram-mmap = <
|
|
0x280 /* ofst_start; */
|
|
0x0 /* nat_ofst; */
|
|
0x0 /* nat_size; */
|
|
0x288 /* v4_flt_hash_ofst; */
|
|
0x78 /* v4_flt_hash_size; */
|
|
0x4000 /* v4_flt_hash_size_ddr; */
|
|
0x308 /* v4_flt_nhash_ofst; */
|
|
0x78 /* v4_flt_nhash_size; */
|
|
0x4000 /* v4_flt_nhash_size_ddr; */
|
|
0x388 /* v6_flt_hash_ofst; */
|
|
0x78 /* v6_flt_hash_size; */
|
|
0x4000 /* v6_flt_hash_size_ddr; */
|
|
0x408 /* v6_flt_nhash_ofst; */
|
|
0x78 /* v6_flt_nhash_size; */
|
|
0x4000 /* v6_flt_nhash_size_ddr; */
|
|
0xf /* v4_rt_num_index; */
|
|
0x0 /* v4_modem_rt_index_lo; */
|
|
0x7 /* v4_modem_rt_index_hi; */
|
|
0x8 /* v4_apps_rt_index_lo; */
|
|
0xe /* v4_apps_rt_index_hi; */
|
|
0x488 /* v4_rt_hash_ofst; */
|
|
0x78 /* v4_rt_hash_size; */
|
|
0x4000 /* v4_rt_hash_size_ddr; */
|
|
0x508 /* v4_rt_nhash_ofst; */
|
|
0x78 /* v4_rt_nhash_size; */
|
|
0x4000 /* v4_rt_nhash_size_ddr; */
|
|
0xf /* v6_rt_num_index; */
|
|
0x0 /* v6_modem_rt_index_lo; */
|
|
0x7 /* v6_modem_rt_index_hi; */
|
|
0x8 /* v6_apps_rt_index_lo; */
|
|
0xe /* v6_apps_rt_index_hi; */
|
|
0x588 /* v6_rt_hash_ofst; */
|
|
0x78 /* v6_rt_hash_size; */
|
|
0x4000 /* v6_rt_hash_size_ddr; */
|
|
0x608 /* v6_rt_nhash_ofst; */
|
|
0x78 /* v6_rt_nhash_size; */
|
|
0x4000 /* v6_rt_nhash_size_ddr; */
|
|
0x688 /* modem_hdr_ofst; */
|
|
0x140 /* modem_hdr_size; */
|
|
0x7c8 /* apps_hdr_ofst; */
|
|
0x0 /* apps_hdr_size; */
|
|
0x800 /* apps_hdr_size_ddr; */
|
|
0x7d0 /* modem_hdr_proc_ctx_ofst; */
|
|
0x200 /* modem_hdr_proc_ctx_size; */
|
|
0x9d0 /* apps_hdr_proc_ctx_ofst; */
|
|
0x200 /* apps_hdr_proc_ctx_size; */
|
|
0x0 /* apps_hdr_proc_ctx_size_ddr; */
|
|
0x0 /* modem_comp_decomp_ofst; diff */
|
|
0x0 /* modem_comp_decomp_size; diff */
|
|
0xbd8 /* modem_ofst; */
|
|
0x1024 /* modem_size; */
|
|
0x2000 /* apps_v4_flt_hash_ofst; */
|
|
0x0 /* apps_v4_flt_hash_size; */
|
|
0x2000 /* apps_v4_flt_nhash_ofst; */
|
|
0x0 /* apps_v4_flt_nhash_size; */
|
|
0x2000 /* apps_v6_flt_hash_ofst; */
|
|
0x0 /* apps_v6_flt_hash_size; */
|
|
0x2000 /* apps_v6_flt_nhash_ofst; */
|
|
0x0 /* apps_v6_flt_nhash_size; */
|
|
0x80 /* uc_info_ofst; */
|
|
0x200 /* uc_info_size; */
|
|
0x2000 /* end_ofst; */
|
|
0x2000 /* apps_v4_rt_hash_ofst; */
|
|
0x0 /* apps_v4_rt_hash_size; */
|
|
0x2000 /* apps_v4_rt_nhash_ofst; */
|
|
0x0 /* apps_v4_rt_nhash_size; */
|
|
0x2000 /* apps_v6_rt_hash_ofst; */
|
|
0x0 /* apps_v6_rt_hash_size; */
|
|
0x2000 /* apps_v6_rt_nhash_ofst; */
|
|
0x0 /* apps_v6_rt_nhash_size; */
|
|
0x1c00 /* uc_event_ring_ofst; */
|
|
0x400 /* uc_event_ring_size; */
|
|
>;
|
|
|
|
ipa_smmu_ap: ipa_smmu_ap {
|
|
compatible = "qcom,ipa-smmu-ap-cb";
|
|
qcom,smmu-s1-bypass;
|
|
iommus = <&apps_smmu 0x720 0x0>;
|
|
qcom,iova-mapping = <0x20000000 0x40000000>;
|
|
};
|
|
|
|
ipa_smmu_wlan: ipa_smmu_wlan {
|
|
compatible = "qcom,ipa-smmu-wlan-cb";
|
|
qcom,smmu-s1-bypass;
|
|
iommus = <&apps_smmu 0x721 0x0>;
|
|
};
|
|
|
|
ipa_smmu_uc: ipa_smmu_uc {
|
|
compatible = "qcom,ipa-smmu-uc-cb";
|
|
qcom,smmu-s1-bypass;
|
|
iommus = <&apps_smmu 0x722 0x0>;
|
|
qcom,iova-mapping = <0x40000000 0x20000000>;
|
|
};
|
|
};
|
|
|
|
qcom,ipa_fws {
|
|
compatible = "qcom,pil-tz-generic";
|
|
qcom,pas-id = <0xf>;
|
|
qcom,firmware-name = "ipa_fws";
|
|
qcom,pil-force-shutdown;
|
|
memory-region = <&pil_ipa_fw_mem>;
|
|
};
|
|
|
|
modem_pas: remoteproc-mss@4080000 {
|
|
compatible = "qcom,qcs605-modem-pas";
|
|
reg = <0x4080000 0x100>;
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>,
|
|
<&gcc GCC_MSS_CFG_AHB_CLK>,
|
|
<&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>,
|
|
<&gcc GCC_BOOT_ROM_AHB_CLK>,
|
|
<&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>,
|
|
<&gcc GCC_MSS_SNOC_AXI_CLK>,
|
|
<&gcc GCC_MSS_MFAB_AXIS_CLK>,
|
|
<&gcc GCC_PRNG_AHB_CLK>;
|
|
clock-names = "xo", "iface_clk", "bus_clk",
|
|
"mem_clk", "gpll0_mss_clk", "snoc_axi_clk",
|
|
"mnoc_axi_clk", "prng_clk";
|
|
qcom,active-clock-names = "iface_clk", "bus_clk", "mem_clk",
|
|
"gpll0_mss_clk", "snoc_axi_clk",
|
|
"mnoc_axi_clk";
|
|
|
|
cx-supply = <&pm660l_s3_level>;
|
|
cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 0>;
|
|
mx-supply = <&pm660l_s1_level>;
|
|
mx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 0>;
|
|
mss-supply = <&pm660_s5_level>;
|
|
mss-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 0>;
|
|
reg-names = "cx", "mx", "mss";
|
|
status = "ok";
|
|
memory-region = <&pil_modem_mem>;
|
|
|
|
/* Inputs from mss */
|
|
interrupts-extended = <&intc 0 266 1>,
|
|
<&modem_smp2p_in 0 0>,
|
|
<&modem_smp2p_in 2 0>,
|
|
<&modem_smp2p_in 1 0>,
|
|
<&modem_smp2p_in 3 0>,
|
|
<&modem_smp2p_in 7 0>;
|
|
|
|
interrupt-names = "wdog",
|
|
"fatal",
|
|
"handover",
|
|
"ready",
|
|
"stop-ack",
|
|
"shutdown-ack";
|
|
|
|
/* Outputs to mss */
|
|
qcom,smem-states = <&modem_smp2p_out 0>;
|
|
qcom,smem-state-names = "stop";
|
|
|
|
/* TBD mboxes = <&qmp_aop 0>;*/
|
|
|
|
qcom,mba-mem@0 {
|
|
memory-region = <&pil_mba_mem>;
|
|
};
|
|
|
|
glink-edge {
|
|
qcom,remote-pid = <1>;
|
|
transport = "smem";
|
|
mboxes = <&qmp_aop 0>;
|
|
mbox-names = "mpss_smem";
|
|
interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
|
|
|
|
label = "modem";
|
|
qcom,glink-label = "mpss";
|
|
|
|
qcom,modem_qrtr {
|
|
qcom,glink-channels = "IPCRTR";
|
|
qcom,intents = <0x800 5
|
|
0x2000 3
|
|
0x4400 2>;
|
|
};
|
|
|
|
qcom,msm_fastrpc_rpmsg {
|
|
compatible = "qcom,msm-fastrpc-rpmsg";
|
|
qcom,glink-channels = "fastrpcglink-apps-dsp";
|
|
qcom,intents = <0x64 64>;
|
|
};
|
|
|
|
qcom,modem_ds {
|
|
qcom,glink-channels = "DS";
|
|
qcom,intents = <0x4000 2>;
|
|
};
|
|
};
|
|
};
|
|
|
|
cdsp_pas: remoteproc-cdsp@8300000 {
|
|
compatible = "qcom,qcs605-cdsp-pas";
|
|
reg = <0x8300000 0x100000>;
|
|
|
|
cx-supply = <&pm660l_s3_level>;
|
|
cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
|
|
reg-names = "cx";
|
|
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>;
|
|
clock-names = "xo";
|
|
|
|
memory-region = <&pil_cdsp_mem>;
|
|
|
|
/* Inputs from turing */
|
|
interrupts-extended = <&intc 0 578 1>,
|
|
<&cdsp_smp2p_in 0 0>,
|
|
<&cdsp_smp2p_in 2 0>,
|
|
<&cdsp_smp2p_in 1 0>,
|
|
<&cdsp_smp2p_in 3 0>,
|
|
<&cdsp_smp2p_in 7 0>;
|
|
|
|
interrupt-names = "wdog",
|
|
"fatal",
|
|
"handover",
|
|
"ready",
|
|
"stop-ack",
|
|
"shutdown-ack";
|
|
|
|
/* Outputs to turing */
|
|
qcom,smem-states = <&cdsp_smp2p_out 0>;
|
|
qcom,smem-state-names = "stop";
|
|
|
|
status = "ok";
|
|
|
|
glink-edge {
|
|
qcom,remote-pid = <5>;
|
|
transport = "smem";
|
|
mboxes = <&qmp_aop 0>;
|
|
mbox-names = "cdsp_smem";
|
|
interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>;
|
|
|
|
label = "cdsp";
|
|
qcom,glink-label = "cdsp";
|
|
|
|
qcom,cdsp_qrtr {
|
|
qcom,glink-channels = "IPCRTR";
|
|
qcom,intents = <0x800 5
|
|
0x2000 3
|
|
0x4400 2>;
|
|
};
|
|
|
|
qcom,msm_fastrpc_rpmsg {
|
|
compatible = "qcom,msm-fastrpc-rpmsg";
|
|
qcom,glink-channels = "fastrpcglink-apps-dsp";
|
|
qcom,intents = <0x64 64>;
|
|
};
|
|
|
|
qcom,msm_cdsprm_rpmsg {
|
|
compatible = "qcom,msm-cdsprm-rpmsg";
|
|
qcom,glink-channels = "cdsprmglink-apps-dsp";
|
|
qcom,intents = <0x20 12>;
|
|
|
|
msm_cdsp_rm: qcom,msm_cdsp_rm {
|
|
compatible = "qcom,msm-cdsp-rm";
|
|
qcom,qos-latency-us = <100>;
|
|
qcom,qos-maxhold-ms = <20>;
|
|
};
|
|
};
|
|
};
|
|
|
|
};
|
|
|
|
sdcc1_ice: sdcc1ice@7c8000 {
|
|
compatible = "qcom,ice";
|
|
reg = <0x7c8000 0x8000>;
|
|
qcom,enable-ice-clk;
|
|
clock-names = "ice_core_clk_src", "ice_core_clk",
|
|
"bus_clk", "iface_clk";
|
|
clocks = <&gcc GCC_SDCC1_ICE_CORE_CLK_SRC>,
|
|
<&gcc GCC_SDCC1_ICE_CORE_CLK>,
|
|
<&gcc GCC_SDCC1_APPS_CLK>,
|
|
<&gcc GCC_SDCC1_AHB_CLK>;
|
|
qcom,op-freq-hz = <300000000>, <0>, <0>, <0>;
|
|
qcom,msm-bus,name = "sdcc_ice_noc";
|
|
qcom,msm-bus,num-cases = <2>;
|
|
qcom,msm-bus,num-paths = <1>;
|
|
qcom,msm-bus,vectors-KBps =
|
|
<150 512 0 0>, /* No vote */
|
|
<150 512 1000 0>; /* Max. bandwidth */
|
|
qcom,bus-vector-names = "MIN",
|
|
"MAX";
|
|
qcom,instance-type = "sdcc";
|
|
};
|
|
|
|
sdhc_1: sdhci@7c4000 {
|
|
compatible = "qcom,sdhci-msm-v5";
|
|
reg = <0x7C4000 0x1000>, <0x7C5000 0x1000>;
|
|
reg-names = "hc_mem", "cmdq_mem";
|
|
|
|
interrupts = <0 641 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0 644 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "hc_irq", "pwr_irq";
|
|
|
|
qcom,bus-width = <8>;
|
|
qcom,large-address-bus;
|
|
sdhc-msm-crypto = <&sdcc1_ice>;
|
|
|
|
qcom,clk-rates = <400000 20000000 25000000 50000000 100000000
|
|
192000000 384000000>;
|
|
qcom,bus-aggr-clk-rates = <50000000 50000000 50000000 50000000
|
|
100000000 200000000 200000000>;
|
|
qcom,bus-speed-mode = "HS400_1p8v", "HS200_1p8v", "DDR_1p8v";
|
|
|
|
qcom,devfreq,freq-table = <50000000 200000000>;
|
|
|
|
qcom,msm-bus,name = "sdhc1";
|
|
qcom,msm-bus,num-cases = <9>;
|
|
qcom,msm-bus,num-paths = <2>;
|
|
qcom,msm-bus,vectors-KBps =
|
|
/* No vote */
|
|
<150 512 0 0>, <1 782 0 0>,
|
|
/* 400 KB/s*/
|
|
<150 512 1046 1600>,
|
|
<1 782 1600 1600>,
|
|
/* 20 MB/s */
|
|
<150 512 52286 80000>,
|
|
<1 782 80000 80000>,
|
|
/* 25 MB/s */
|
|
<150 512 65360 100000>,
|
|
<1 782 100000 100000>,
|
|
/* 50 MB/s */
|
|
<150 512 130718 200000>,
|
|
<1 782 100000 100000>,
|
|
/* 100 MB/s */
|
|
<150 512 130718 200000>,
|
|
<1 782 130000 130000>,
|
|
/* 200 MB/s */
|
|
<150 512 261438 400000>,
|
|
<1 782 300000 300000>,
|
|
/* 400 MB/s */
|
|
<150 512 261438 400000>,
|
|
<1 782 300000 300000>,
|
|
/* Max. bandwidth */
|
|
<150 512 1338562 4096000>,
|
|
<1 782 1338562 4096000>;
|
|
qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000
|
|
100000000 200000000 400000000 4294967295>;
|
|
|
|
/* PM QoS */
|
|
qcom,pm-qos-irq-type = "affine_irq";
|
|
qcom,pm-qos-irq-latency = <67 67>;
|
|
qcom,pm-qos-cpu-groups = <0x3f 0xc0>;
|
|
qcom,pm-qos-cmdq-latency-us = <67 67>, <67 67>;
|
|
qcom,pm-qos-legacy-latency-us = <67 67>, <67 67>;
|
|
|
|
clocks = <&gcc GCC_SDCC1_AHB_CLK>,
|
|
<&gcc GCC_SDCC1_APPS_CLK>,
|
|
<&gcc GCC_SDCC1_ICE_CORE_CLK>;
|
|
clock-names = "iface_clk", "core_clk", "ice_core_clk";
|
|
|
|
qcom,ice-clk-rates = <300000000 75000000>;
|
|
|
|
qcom,ddr-config = <0xC3040873>;
|
|
|
|
qcom,nonremovable;
|
|
nvmem-cells = <&minor_rev>;
|
|
nvmem-cell-names = "minor_rev";
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
sdhc_2: sdhci@8804000 {
|
|
compatible = "qcom,sdhci-msm-v5";
|
|
reg = <0x8804000 0x1000>;
|
|
reg-names = "hc_mem";
|
|
|
|
interrupts = <0 204 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0 222 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "hc_irq", "pwr_irq";
|
|
|
|
qcom,bus-width = <4>;
|
|
qcom,large-address-bus;
|
|
|
|
qcom,clk-rates = <400000 20000000 25000000
|
|
50000000 100000000 201500000>;
|
|
qcom,bus-speed-mode = "SDR12", "SDR25", "SDR50", "DDR50",
|
|
"SDR104";
|
|
|
|
qcom,devfreq,freq-table = <50000000 201500000>;
|
|
|
|
qcom,msm-bus,name = "sdhc2";
|
|
qcom,msm-bus,num-cases = <8>;
|
|
qcom,msm-bus,num-paths = <2>;
|
|
qcom,msm-bus,vectors-KBps =
|
|
/* No vote */
|
|
<81 512 0 0>, <1 608 0 0>,
|
|
/* 400 KB/s*/
|
|
<81 512 1046 1600>,
|
|
<1 608 1600 1600>,
|
|
/* 20 MB/s */
|
|
<81 512 52286 80000>,
|
|
<1 608 80000 80000>,
|
|
/* 25 MB/s */
|
|
<81 512 65360 100000>,
|
|
<1 608 100000 100000>,
|
|
/* 50 MB/s */
|
|
<81 512 130718 200000>,
|
|
<1 608 100000 100000>,
|
|
/* 100 MB/s */
|
|
<81 512 261438 200000>,
|
|
<1 608 130000 130000>,
|
|
/* 200 MB/s */
|
|
<81 512 261438 400000>,
|
|
<1 608 300000 300000>,
|
|
/* Max. bandwidth */
|
|
<81 512 1338562 4096000>,
|
|
<1 608 1338562 4096000>;
|
|
qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000
|
|
100000000 200000000 4294967295>;
|
|
|
|
/* PM QoS */
|
|
qcom,pm-qos-irq-type = "affine_irq";
|
|
qcom,pm-qos-irq-latency = <67 67>;
|
|
qcom,pm-qos-cpu-groups = <0x3f 0xc0>;
|
|
qcom,pm-qos-legacy-latency-us = <67 67>, <67 67>;
|
|
|
|
clocks = <&gcc GCC_SDCC2_AHB_CLK>,
|
|
<&gcc GCC_SDCC2_APPS_CLK>;
|
|
clock-names = "iface_clk", "core_clk";
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
qcom,msm-cdsp-loader {
|
|
compatible = "qcom,cdsp-loader";
|
|
qcom,proc-img-to-load = "cdsp";
|
|
};
|
|
|
|
qcom,msm-adsprpc-mem {
|
|
compatible = "qcom,msm-adsprpc-mem-region";
|
|
memory-region = <&adsp_mem>;
|
|
restrict-access;
|
|
};
|
|
|
|
qcom,msm_fastrpc {
|
|
compatible = "qcom,msm-fastrpc-compute";
|
|
qcom,adsp-remoteheap-vmid = <22 37>;
|
|
qcom,fastrpc-adsp-audio-pdr;
|
|
qcom,fastrpc-adsp-sensors-pdr;
|
|
|
|
msm_fastrpc_compute_cb1: qcom,msm_fastrpc_compute_cb1 {
|
|
compatible = "qcom,msm-fastrpc-compute-cb";
|
|
label = "cdsprpc-smd";
|
|
iommus = <&apps_smmu 0x1421 0x30>;
|
|
dma-coherent;
|
|
};
|
|
|
|
msm_fastrpc_compute_cb2: qcom,msm_fastrpc_compute_cb2 {
|
|
compatible = "qcom,msm-fastrpc-compute-cb";
|
|
label = "cdsprpc-smd";
|
|
iommus = <&apps_smmu 0x1422 0x30>;
|
|
dma-coherent;
|
|
};
|
|
|
|
msm_fastrpc_compute_cb3: qcom,msm_fastrpc_compute_cb3 {
|
|
compatible = "qcom,msm-fastrpc-compute-cb";
|
|
label = "cdsprpc-smd";
|
|
iommus = <&apps_smmu 0x1423 0x30>;
|
|
dma-coherent;
|
|
};
|
|
|
|
msm_fastrpc_compute_cb4: qcom,msm_fastrpc_compute_cb4 {
|
|
compatible = "qcom,msm-fastrpc-compute-cb";
|
|
label = "cdsprpc-smd";
|
|
iommus = <&apps_smmu 0x1424 0x30>;
|
|
dma-coherent;
|
|
};
|
|
|
|
msm_fastrpc_compute_cb5: qcom,msm_fastrpc_compute_cb5 {
|
|
compatible = "qcom,msm-fastrpc-compute-cb";
|
|
label = "cdsprpc-smd";
|
|
iommus = <&apps_smmu 0x1425 0x30>;
|
|
dma-coherent;
|
|
};
|
|
|
|
msm_fastrpc_compute_cb6: qcom,msm_fastrpc_compute_cb6 {
|
|
compatible = "qcom,msm-fastrpc-compute-cb";
|
|
label = "cdsprpc-smd";
|
|
iommus = <&apps_smmu 0x1426 0x30>;
|
|
dma-coherent;
|
|
};
|
|
|
|
msm_fastrpc_compute_cb7: qcom,msm_fastrpc_compute_cb7 {
|
|
compatible = "qcom,msm-fastrpc-compute-cb";
|
|
label = "cdsprpc-smd";
|
|
qcom,secure-context-bank;
|
|
iommus = <&apps_smmu 0x1429 0x30>;
|
|
dma-coherent;
|
|
};
|
|
|
|
msm_fastrpc_compute_cb8: qcom,msm_fastrpc_compute_cb8 {
|
|
compatible = "qcom,msm-fastrpc-compute-cb";
|
|
label = "cdsprpc-smd";
|
|
qcom,secure-context-bank;
|
|
iommus = <&apps_smmu 0x142A 0x30>;
|
|
dma-coherent;
|
|
};
|
|
|
|
msm_fastrpc_compute_cb9: qcom,msm_fastrpc_compute_cb9 {
|
|
compatible = "qcom,msm-fastrpc-compute-cb";
|
|
label = "adsprpc-smd";
|
|
iommus = <&apps_smmu 0x1803 0x0>;
|
|
dma-coherent;
|
|
};
|
|
|
|
msm_fastrpc_compute_cb10: qcom,msm_fastrpc_compute_cb10 {
|
|
compatible = "qcom,msm-fastrpc-compute-cb";
|
|
label = "adsprpc-smd";
|
|
iommus = <&apps_smmu 0x1804 0x0>;
|
|
dma-coherent;
|
|
};
|
|
|
|
msm_fastrpc_compute_cb11: qcom,msm_fastrpc_compute_cb11 {
|
|
compatible = "qcom,msm-fastrpc-compute-cb";
|
|
label = "adsprpc-smd";
|
|
iommus = <&apps_smmu 0x1805 0x0>;
|
|
dma-coherent;
|
|
};
|
|
|
|
msm_fastrpc_compute_cb12: qcom,msm_fastrpc_compute_cb12 {
|
|
compatible = "qcom,msm-fastrpc-compute-cb";
|
|
label = "adsprpc-smd";
|
|
iommus = <&apps_smmu 0x1806 0x0>;
|
|
dma-coherent;
|
|
shared-cb;
|
|
};
|
|
};
|
|
|
|
bluetooth: bt_wcn3990 {
|
|
compatible = "qca,wcn3990";
|
|
qca,bt-vdd-core-supply = <&pm660_l9>;
|
|
qca,bt-vdd-pa-supply = <&pm660_l6>;
|
|
qca,bt-vdd-ldo-supply = <&pm660_l19>;
|
|
|
|
qca,bt-vdd-core-voltage-level = <1800000 1900000>;
|
|
qca,bt-vdd-pa-voltage-level = <1304000 1370000>;
|
|
qca,bt-vdd-ldo-voltage-level = <3312000 3400000>;
|
|
|
|
qca,bt-vdd-core-current-level = <1>; /* LPM/PFM */
|
|
qca,bt-vdd-pa-current-level = <1>; /* LPM/PFM */
|
|
qca,bt-vdd-ldo-current-level = <1>; /* LPM/PFM */
|
|
};
|
|
|
|
ddr_freq_table: ddr-freq-table {
|
|
qcom,freq-tbl =
|
|
< 100000 >,
|
|
< 200000 >,
|
|
< 300000 >,
|
|
< 451000 >,
|
|
< 547000 >,
|
|
< 681000 >,
|
|
< 768000 >,
|
|
< 1017000 >,
|
|
< 1353000 >,
|
|
< 1555000 >,
|
|
< 1804000 >;
|
|
};
|
|
|
|
qcom_dcvs: qcom,dcvs {
|
|
compatible = "qcom,dcvs";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
|
|
qcom_l3_dcvs_hw: l3 {
|
|
compatible = "qcom,dcvs-hw";
|
|
qcom,dcvs-hw-type = <2>;
|
|
/* TBD */
|
|
};
|
|
|
|
qcom_ddr_dcvs_hw: ddr {
|
|
compatible = "qcom,dcvs-hw";
|
|
qcom,dcvs-hw-type = <0>;
|
|
qcom,bus-width = <4>;
|
|
qcom,freq-tbl = <&ddr_freq_table>;
|
|
|
|
ddr_dcvs_sp: sp {
|
|
compatible = "qcom,dcvs-path";
|
|
qcom,dcvs-path-type = <0>;
|
|
/* TBD */
|
|
/* interconnects = <&bimc MASTER_AMPSS_M0 &bimc SLAVE_EBI_CH0>;*/
|
|
};
|
|
};
|
|
};
|
|
|
|
bwmon_ddr: qcom,bwmon-ddr@1436300 {
|
|
compatible = "qcom,bwmon4";
|
|
reg = <0x1436400 0x100>, <0x1436300 0x100>;
|
|
reg-names = "base", "global_base";
|
|
interrupts = <0 581 4>;
|
|
qcom,mport = <0>;
|
|
qcom,count-unit = <0x10000>;
|
|
qcom,hw-timer-hz = <19200000>;
|
|
qcom,target-dev = <&qcom_ddr_dcvs_hw>;
|
|
};
|
|
|
|
qcom_memlat: qcom,memlat {
|
|
compatible = "qcom,memlat";
|
|
ddr {
|
|
compatible = "qcom,memlat-grp";
|
|
qcom,target-dev = <&qcom_ddr_dcvs_hw>;
|
|
qcom,sampling-path = <&ddr_dcvs_sp>;
|
|
qcom,miss-ev = <0x2a>;
|
|
|
|
silver {
|
|
compatible = "qcom,memlat-mon";
|
|
qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>;
|
|
qcom,cpufreq-memfreq-tbl =
|
|
< 748800 300000 >,
|
|
< 998400 451000 >,
|
|
< 1209600 547000 >,
|
|
< 1516800 768000 >,
|
|
< 1708000 1017000 >;
|
|
qcom,sampling-enabled;
|
|
};
|
|
|
|
gold {
|
|
compatible = "qcom,memlat-mon";
|
|
qcom,cpulist = <&CPU6 &CPU7>;
|
|
qcom,cpufreq-memfreq-tbl =
|
|
< 825600 300000 >,
|
|
< 1132800 547000 >,
|
|
< 1363200 1017000 >,
|
|
< 1996800 1555000 >,
|
|
< 2457600 1804000 >;
|
|
qcom,sampling-enabled;
|
|
};
|
|
|
|
silver-compute {
|
|
compatible = "qcom,memlat-mon";
|
|
qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>;
|
|
qcom,sampling-enabled;
|
|
qcom,compute-mon;
|
|
qcom,cpufreq-memfreq-tbl =
|
|
< 748800 300000 >,
|
|
< 1209660 451000 >,
|
|
< 1612800 547000 >,
|
|
< 1708000 768000 >;
|
|
};
|
|
|
|
gold-compute {
|
|
compatible = "qcom,memlat-mon";
|
|
qcom,cpulist = <&CPU6 &CPU7>;
|
|
qcom,cpufreq-memfreq-tbl =
|
|
< 1132800 300000>,
|
|
< 1363200 547000>,
|
|
< 1747200 768000>,
|
|
< 1996800 1017000>,
|
|
< 2457600 1804000>;
|
|
qcom,sampling-enabled;
|
|
qcom,compute-mon;
|
|
};
|
|
};
|
|
|
|
l3 {
|
|
compatible = "qcom,memlat-grp";
|
|
qcom,target-dev = <&qcom_l3_dcvs_hw>;
|
|
qcom,miss-ev = <0x17>;
|
|
|
|
silver {
|
|
compatible = "qcom,memlat-mon";
|
|
qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3 &CPU4 &CPU5>;
|
|
qcom,cpufreq-memfreq-tbl =
|
|
< 576000 3000000 >,
|
|
< 998400 5568000 >,
|
|
< 1209660 8448000 >,
|
|
< 1516800 9408000 >,
|
|
< 1612800 13824000 >,
|
|
< 1708000 14400000 >;
|
|
qcom,sampling-enabled;
|
|
};
|
|
|
|
gold {
|
|
compatible = "qcom,memlat-mon";
|
|
qcom,cpulist = <&CPU6 &CPU7>;
|
|
qcom,cpufreq-memfreq-tbl =
|
|
< 1132800 5568000 >,
|
|
< 1363200 8064000 >,
|
|
< 1747200 9408000 >,
|
|
< 1996800 11904000 >,
|
|
< 2457600 14400000 >;
|
|
qcom,sampling-enabled;
|
|
};
|
|
};
|
|
};
|
|
|
|
l3_cpu0: qcom,l3-cpu0 {
|
|
compatible = "devfreq-simple-dev";
|
|
clock-names = "devfreq_clk";
|
|
governor = "performance";
|
|
};
|
|
|
|
l3_cpu6: qcom,l3-cpu6 {
|
|
compatible = "devfreq-simple-dev";
|
|
clock-names = "devfreq_clk";
|
|
governor = "performance";
|
|
};
|
|
|
|
l3_cdsp: qcom,l3-cdsp {
|
|
compatible = "devfreq-simple-dev";
|
|
clock-names = "devfreq_clk";
|
|
governor = "powersave";
|
|
};
|
|
|
|
cpu_pmu: cpu-pmu {
|
|
compatible = "arm,armv8-pmuv3";
|
|
qcom,irq-is-percpu;
|
|
interrupts = <1 5 4>;
|
|
};
|
|
|
|
gpu_gx_domain_addr: syscon@0x5091508 {
|
|
compatible = "syscon";
|
|
reg = <0x5091508 0x4>;
|
|
};
|
|
|
|
gpu_gx_sw_reset: syscon@0x5091008 {
|
|
compatible = "syscon";
|
|
reg = <0x5091008 0x4>;
|
|
};
|
|
|
|
qfprom: qfprom@0x780000 {
|
|
compatible = "qcom,qfprom";
|
|
reg = <0x00784000 0x1000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
|
|
minor_rev: minor_rev@0x78414c {
|
|
reg = <0x14c 0x4>;
|
|
bits = <0 30>; /* Access 30 bits from bit offset 0 */
|
|
};
|
|
};
|
|
|
|
};
|
|
|
|
#include "pm660.dtsi"
|
|
#include "pm660l.dtsi"
|
|
#include "sdm670-regulator.dtsi"
|
|
#include "sdm670-pinctrl.dtsi"
|
|
#include "msm-arm-smmu-sdm670.dtsi"
|
|
#include "msm-gdsc-sdm845.dtsi"
|
|
|
|
&usb30_prim_gdsc {
|
|
status = "ok";
|
|
};
|
|
|
|
&ufs_phy_gdsc {
|
|
status = "ok";
|
|
};
|
|
|
|
&hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc {
|
|
status = "ok";
|
|
};
|
|
|
|
&hlos1_vote_aggre_noc_mmu_tbu1_gdsc {
|
|
status = "ok";
|
|
};
|
|
|
|
&hlos1_vote_aggre_noc_mmu_tbu2_gdsc {
|
|
status = "ok";
|
|
};
|
|
|
|
&hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc {
|
|
status = "ok";
|
|
};
|
|
|
|
&hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc {
|
|
status = "ok";
|
|
};
|
|
|
|
&hlos1_vote_mmnoc_mmu_tbu_sf_gdsc {
|
|
status = "ok";
|
|
};
|
|
|
|
&bps_gdsc {
|
|
qcom,support-hw-trigger;
|
|
status = "ok";
|
|
};
|
|
|
|
&ife_0_gdsc {
|
|
status = "ok";
|
|
};
|
|
|
|
&ife_1_gdsc {
|
|
status = "ok";
|
|
};
|
|
|
|
&ipe_0_gdsc {
|
|
qcom,support-hw-trigger;
|
|
status = "ok";
|
|
};
|
|
|
|
&ipe_1_gdsc {
|
|
qcom,support-hw-trigger;
|
|
status = "ok";
|
|
};
|
|
|
|
&titan_top_gdsc {
|
|
status = "ok";
|
|
};
|
|
|
|
&mdss_core_gdsc {
|
|
status = "ok";
|
|
proxy-supply = <&mdss_core_gdsc>;
|
|
qcom,proxy-consumer-enable;
|
|
};
|
|
|
|
&gpu_cx_gdsc {
|
|
parent-supply = <&pm660l_s3_level>;
|
|
vdd_parent-supply = <&pm660l_s3_level>;
|
|
status = "ok";
|
|
};
|
|
|
|
&gpu_gx_gdsc {
|
|
clock-names = "core_root_clk";
|
|
clocks = <&gpucc GPU_CC_GX_GFX3D_CLK_SRC>;
|
|
qcom,force-enable-root-clk;
|
|
parent-supply = <&pm660l_s2_level>;
|
|
domain-addr = <&gpu_gx_domain_addr>;
|
|
sw-reset = <&gpu_gx_sw_reset>;
|
|
qcom,skip-disable-before-sw-enable;
|
|
qcom,reset-aon-logic;
|
|
status = "ok";
|
|
};
|
|
|
|
#include "sdm670-usb.dtsi"
|
|
#include "sdm670-thermal.dtsi"
|
|
|
|
&pm660_div_clk {
|
|
status = "ok";
|
|
};
|
|
|
|
&qupv3_se10_i2c {
|
|
nx30p6093: nx30p6093@36 {
|
|
status = "disabled";
|
|
reg = <0x36>;
|
|
interrupt-parent = <&tlmm>;
|
|
interrupts = <5 IRQ_TYPE_EDGE_RISING>;
|
|
nxp,long-wakeup-sec = <28800>; /* 8 hours */
|
|
nxp,short-wakeup-ms = <180000>; /* 3 mins */
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&nx30p6093_intr_default>;
|
|
};
|
|
};
|