1127 lines
18 KiB
Text
1127 lines
18 KiB
Text
&tlmm {
|
|
qupv3_se1_2uart_pins: qupv3_se1_2uart_pins {
|
|
qupv3_se1_2uart_tx_active: qupv3_se1_2uart_tx_active {
|
|
mux {
|
|
pins = "gpio12";
|
|
function = "qup_se1_l2_mira";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio12";
|
|
drive-strength= <2>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se1_2uart_rx_active: qupv3_se1_2uart_rx_active {
|
|
mux {
|
|
pins = "gpio13";
|
|
function = "qup_se1_l3_mira";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio13";
|
|
drive-strength= <2>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se1_2uart_sleep: qupv3_se1_2uart_sleep {
|
|
mux {
|
|
pins = "gpio12", "gpio13";
|
|
function = "gpio";
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|
};
|
|
|
|
config {
|
|
pins = "gpio12", "gpio13";
|
|
drive-strength = <2>;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se3_4uart_pins: qupv3_se3_4uart_pins {
|
|
qupv3_se3_default_cts: qupv3_se3_default_cts {
|
|
mux {
|
|
pins = "gpio52";
|
|
function = "gpio";
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|
};
|
|
|
|
config {
|
|
pins = "gpio52";
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|
drive-strength = <2>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se3_default_rts: qupv3_se3_default_rts {
|
|
mux {
|
|
pins = "gpio53";
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|
function = "gpio";
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|
};
|
|
|
|
config {
|
|
pins = "gpio53";
|
|
drive-strength = <2>;
|
|
bias-pull-down;
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|
};
|
|
};
|
|
|
|
qupv3_se3_default_tx: qupv3_se3_default_tx {
|
|
mux {
|
|
pins = "gpio54";
|
|
function = "gpio";
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|
};
|
|
|
|
config {
|
|
pins = "gpio54";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
qupv3_se3_default_rx: qupv3_se3_default_rx {
|
|
mux {
|
|
pins = "gpio55";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio55";
|
|
drive-strength = <2>;
|
|
bias-pull-down;
|
|
};
|
|
};
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|
|
|
qupv3_se3_cts: qupv3_se3_cts {
|
|
mux {
|
|
pins = "gpio52";
|
|
function = "qup_se3_l0";
|
|
};
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|
|
|
config {
|
|
pins = "gpio52";
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|
drive-strength = <2>;
|
|
bias-disable;
|
|
};
|
|
};
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|
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|
qupv3_se3_rts: qupv3_se3_rts {
|
|
mux {
|
|
pins = "gpio53";
|
|
function = "qup_se3_l1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio53";
|
|
drive-strength = <2>;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
|
|
qupv3_se3_tx: qupv3_se3_tx {
|
|
mux {
|
|
pins = "gpio54";
|
|
function = "qup_se3_l2";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio54";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
qupv3_se3_rx: qupv3_se3_rx {
|
|
mux {
|
|
pins = "gpio55";
|
|
function = "qup_se3_l3";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio55";
|
|
drive-strength = <2>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se0_i2c_pins: qupv3_se0_i2c_pins {
|
|
qupv3_se0_i2c_sda_active: qupv3_se0_i2c_sda_active {
|
|
mux {
|
|
pins = "gpio8";
|
|
function = "qup_se0_l0";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio8";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
qupv3_se0_i2c_scl_active: qupv3_se0_i2c_scl_active {
|
|
mux {
|
|
pins = "gpio9";
|
|
function = "qup_se0_l1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio9";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
qupv3_se0_i2c_sleep: qupv3_se0_i2c_sleep {
|
|
mux {
|
|
pins = "gpio8", "gpio9";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio8", "gpio9";
|
|
drive-strength = <2>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se0_spi_pins: qupv3_se0_spi_pins {
|
|
qupv3_se0_spi_miso_active: qupv3_se0_spi_miso_active {
|
|
mux {
|
|
pins = "gpio8";
|
|
function = "qup_se0_l0";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio8";
|
|
drive-strength = <6>;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
|
|
qupv3_se0_spi_mosi_active: qupv3_se0_spi_mosi_active {
|
|
mux {
|
|
pins = "gpio9";
|
|
function = "qup_se0_l1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio9";
|
|
drive-strength = <6>;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
|
|
qupv3_se0_spi_clk_active: qupv3_se0_spi_clk_active {
|
|
mux {
|
|
pins = "gpio10";
|
|
function = "qup_se0_l2";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio10";
|
|
drive-strength = <6>;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
|
|
qupv3_se0_spi_cs_active: qupv3_se0_spi_cs_active {
|
|
mux {
|
|
pins = "gpio11";
|
|
function = "qup_se0_l3";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio11";
|
|
drive-strength = <6>;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
|
|
qupv3_se0_spi_sleep: qupv3_se0_spi_sleep {
|
|
mux {
|
|
pins = "gpio8", "gpio9",
|
|
"gpio10", "gpio11";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio8", "gpio9",
|
|
"gpio10", "gpio11";
|
|
drive-strength = <2>;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se2_i2c_pins: qupv3_se2_i2c_pins {
|
|
qupv3_se2_i2c_sda_active: qupv3_se2_i2c_sda_active {
|
|
mux {
|
|
pins = "gpio14";
|
|
function = "qup_se2_l0";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio14";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
qupv3_se2_i2c_scl_active: qupv3_se2_i2c_scl_active {
|
|
mux {
|
|
pins = "gpio15";
|
|
function = "qup_se2_l1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio15";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
qupv3_se2_i2c_sleep: qupv3_se2_i2c_sleep {
|
|
mux {
|
|
pins = "gpio14", "gpio15";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio14", "gpio15";
|
|
drive-strength = <2>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se2_spi_pins: qupv3_se2_spi_pins {
|
|
qupv3_se2_spi_miso_active: qupv3_se2_spi_miso_active {
|
|
mux {
|
|
pins = "gpio14";
|
|
function = "qup_se2_l0";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio14";
|
|
drive-strength = <6>;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
|
|
qupv3_se2_spi_mosi_active: qupv3_se2_spi_mosi_active {
|
|
mux {
|
|
pins = "gpio15";
|
|
function = "qup_se2_l1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio15";
|
|
drive-strength = <6>;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
|
|
qupv3_se2_spi_clk_active: qupv3_se2_spi_clk_active {
|
|
mux {
|
|
pins = "gpio16";
|
|
function = "qup_se2_l2";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio16";
|
|
drive-strength = <6>;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
|
|
qupv3_se2_spi_cs_active: qupv3_se2_spi_cs_active {
|
|
mux {
|
|
pins = "gpio17";
|
|
function = "qup_se2_l3";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio17";
|
|
drive-strength = <6>;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
|
|
qupv3_se2_spi_sleep: qupv3_se2_spi_sleep {
|
|
mux {
|
|
pins = "gpio14", "gpio15",
|
|
"gpio16", "gpio17";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio14", "gpio15",
|
|
"gpio16", "gpio17";
|
|
drive-strength = <2>;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se3_i2c_pins: qupv3_se3_i2c_pins {
|
|
qupv3_se3_i2c_sda_active: qupv3_se3_i2c_sda_active {
|
|
mux {
|
|
pins = "gpio52";
|
|
function = "qup_se3_l0";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio52";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
qupv3_se3_i2c_scl_active: qupv3_se3_i2c_scl_active {
|
|
mux {
|
|
pins = "gpio53";
|
|
function = "qup_se3_l1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio53";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
qupv3_se3_i2c_sleep: qupv3_se3_i2c_sleep {
|
|
mux {
|
|
pins = "gpio52", "gpio53";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio52", "gpio53";
|
|
drive-strength = <2>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se3_spi_pins: qupv3_se3_spi_pins {
|
|
qupv3_se3_spi_miso_active: qupv3_se3_spi_miso_active {
|
|
mux {
|
|
pins = "gpio52";
|
|
function = "qup_se3_l0";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio52";
|
|
drive-strength = <6>;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
|
|
qupv3_se3_spi_mosi_active: qupv3_se3_spi_mosi_active {
|
|
mux {
|
|
pins = "gpio53";
|
|
function = "qup_se3_l1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio53";
|
|
drive-strength = <6>;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
|
|
qupv3_se3_spi_clk_active: qupv3_se3_spi_clk_active {
|
|
mux {
|
|
pins = "gpio54";
|
|
function = "qup_se3_l2";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio54";
|
|
drive-strength = <6>;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
|
|
qupv3_se3_spi_cs_active: qupv3_se3_spi_cs_active {
|
|
mux {
|
|
pins = "gpio55";
|
|
function = "qup_se3_l3";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio55";
|
|
drive-strength = <6>;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
|
|
qupv3_se3_spi_sleep: qupv3_se3_spi_sleep {
|
|
mux {
|
|
pins = "gpio52", "gpio53",
|
|
"gpio54", "gpio55";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio52", "gpio53",
|
|
"gpio54", "gpio55";
|
|
drive-strength = <2>;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se4_2uart_pins: qupv3_se4_2uart_pins {
|
|
qupv3_se4_2uart_tx_active: qupv3_se4_2uart_tx_active {
|
|
mux {
|
|
pins = "gpio64";
|
|
function = "qup_se4_l2";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio64";
|
|
drive-strength = <2>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se4_2uart_rx_active: qupv3_se4_2uart_rx_active {
|
|
mux {
|
|
pins = "gpio65";
|
|
function = "qup_se4_l3";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio65";
|
|
drive-strength = <2>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se4_2uart_sleep: qupv3_se4_2uart_sleep {
|
|
mux {
|
|
pins = "gpio64", "gpio65";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio64", "gpio65";
|
|
drive-strength = <2>;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se5_i2c_pins: qupv3_se5_i2c_pins {
|
|
qupv3_se5_i2c_sda_active: qupv3_se5_i2c_sda_active {
|
|
mux {
|
|
pins = "gpio110";
|
|
function = "qup_se5_l0";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio110";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
qupv3_se5_i2c_scl_active: qupv3_se5_i2c_scl_active {
|
|
mux {
|
|
pins = "gpio111";
|
|
function = "qup_se5_l1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio111";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
qupv3_se5_i2c_sleep: qupv3_se5_i2c_sleep {
|
|
mux {
|
|
pins = "gpio110", "gpio111";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio110", "gpio111";
|
|
drive-strength = <2>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se6_i2c_pins: qupv3_se6_i2c_pins {
|
|
qupv3_se6_i2c_sda_active: qupv3_se6_i2c_sda_active {
|
|
mux {
|
|
pins = "gpio112";
|
|
function = "qup_se6_l0";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio112";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
qupv3_se6_i2c_scl_active: qupv3_se6_i2c_scl_active {
|
|
mux {
|
|
pins = "gpio113";
|
|
function = "qup_se6_l1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio113";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
qupv3_se6_i2c_sleep: qupv3_se6_i2c_sleep {
|
|
mux {
|
|
pins = "gpio112", "gpio113";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio112", "gpio113";
|
|
drive-strength = <2>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se6_spi_pins: qupv3_se6_spi_pins {
|
|
qupv3_se6_spi_miso_active: qupv3_se6_spi_miso_active {
|
|
mux {
|
|
pins = "gpio112";
|
|
function = "qup_se6_l0";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio112";
|
|
drive-strength = <6>;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
|
|
qupv3_se6_spi_mosi_active: qupv3_se6_spi_mosi_active {
|
|
mux {
|
|
pins = "gpio113";
|
|
function = "qup_se6_l1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio113";
|
|
drive-strength = <6>;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
|
|
qupv3_se6_spi_clk_active: qupv3_se6_spi_clk_active {
|
|
mux {
|
|
pins = "gpio114";
|
|
function = "qup_se6_l2";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio114";
|
|
drive-strength = <6>;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
|
|
qupv3_se6_spi_cs_active: qupv3_se6_spi_cs_active {
|
|
mux {
|
|
pins = "gpio115";
|
|
function = "qup_se6_l3";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio115";
|
|
drive-strength = <6>;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
|
|
qupv3_se6_spi_sleep: qupv3_se6_spi_sleep {
|
|
mux {
|
|
pins = "gpio112", "gpio113",
|
|
"gpio114", "gpio115";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio112", "gpio113",
|
|
"gpio114", "gpio115";
|
|
drive-strength = <2>;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se7_i2c_pins: qupv3_se7_i2c_pins {
|
|
qupv3_se7_i2c_sda_active: qupv3_se7_i2c_sda_active {
|
|
mux {
|
|
pins = "gpio116";
|
|
function = "qup_se7_l0";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio116";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
qupv3_se7_i2c_scl_active: qupv3_se7_i2c_scl_active {
|
|
mux {
|
|
pins = "gpio117";
|
|
function = "qup_se7_l1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio117";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
qupv3_se7_i2c_sleep: qupv3_se7_i2c_sleep {
|
|
mux {
|
|
pins = "gpio116", "gpio117";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio116", "gpio117";
|
|
drive-strength = <2>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se7_spi_pins: qupv3_se7_spi_pins {
|
|
qupv3_se7_spi_miso_active: qupv3_se7_spi_miso_active {
|
|
mux {
|
|
pins = "gpio116";
|
|
function = "qup_se7_l0";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio116";
|
|
drive-strength = <6>;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
|
|
qupv3_se7_spi_mosi_active: qupv3_se7_spi_mosi_active {
|
|
mux {
|
|
pins = "gpio117";
|
|
function = "qup_se7_l1";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio117";
|
|
drive-strength = <6>;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
|
|
qupv3_se7_spi_clk_active: qupv3_se7_spi_clk_active {
|
|
mux {
|
|
pins = "gpio118";
|
|
function = "qup_se7_l2";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio118";
|
|
drive-strength = <6>;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
|
|
qupv3_se7_spi_cs_active: qupv3_se7_spi_cs_active {
|
|
mux {
|
|
pins = "gpio119";
|
|
function = "qup_se7_l3";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio119";
|
|
drive-strength = <6>;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
|
|
qupv3_se7_spi_sleep: qupv3_se7_spi_sleep {
|
|
mux {
|
|
pins = "gpio116", "gpio117",
|
|
"gpio118", "gpio119";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio116", "gpio117",
|
|
"gpio118", "gpio119";
|
|
drive-strength = <2>;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
};
|
|
|
|
qupv3_se8_2uart_pins: qupv3_se8_2uart_pins {
|
|
qupv3_se8_2uart_tx_active: qupv3_se8_2uart_tx_active {
|
|
mux {
|
|
pins = "gpio124";
|
|
function = "qup_se8_l2";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio124";
|
|
drive-strength = <2>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se8_2uart_rx_active: qupv3_se8_2uart_rx_active {
|
|
mux {
|
|
pins = "gpio125";
|
|
function = "qup_se8_l3";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio125";
|
|
drive-strength = <2>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
|
|
qupv3_se8_2uart_sleep: qupv3_se8_2uart_sleep {
|
|
mux {
|
|
pins = "gpio124", "gpio125";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio124", "gpio125";
|
|
drive-strength = <2>;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
};
|
|
|
|
sdc1_on: sdc1_on {
|
|
clk {
|
|
pins = "sdc1_clk";
|
|
bias-disable;
|
|
drive-strength = <16>;
|
|
};
|
|
|
|
cmd {
|
|
pins = "sdc1_cmd";
|
|
bias-pull-up;
|
|
drive-strength = <10>;
|
|
};
|
|
|
|
data {
|
|
pins = "sdc1_data";
|
|
bias-pull-up;
|
|
drive-strength = <10>;
|
|
};
|
|
|
|
rclk {
|
|
pins = "sdc1_rclk";
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
|
|
sdc1_off: sdc1_off {
|
|
clk {
|
|
pins = "sdc1_clk";
|
|
bias-disable;
|
|
drive-strength = <2>;
|
|
};
|
|
|
|
cmd {
|
|
pins = "sdc1_cmd";
|
|
bias-pull-up;
|
|
drive-strength = <2>;
|
|
};
|
|
|
|
data {
|
|
pins = "sdc1_data";
|
|
bias-pull-up;
|
|
drive-strength = <2>;
|
|
};
|
|
|
|
rclk {
|
|
pins = "sdc1_rclk";
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
|
|
sdc2_on: sdc2_on {
|
|
clk {
|
|
pins = "sdc2_clk";
|
|
bias-disable;
|
|
drive-strength = <16>;
|
|
};
|
|
|
|
cmd {
|
|
pins = "sdc2_cmd";
|
|
bias-pull-up;
|
|
drive-strength = <10>;
|
|
};
|
|
|
|
data {
|
|
pins = "sdc2_data";
|
|
bias-pull-up;
|
|
drive-strength = <10>;
|
|
};
|
|
|
|
sd-cd {
|
|
pins = "gpio103";
|
|
bias-pull-up;
|
|
drive-strength = <2>;
|
|
};
|
|
};
|
|
|
|
sdc2_off: sdc2_off {
|
|
clk {
|
|
pins = "sdc2_clk";
|
|
bias-disable;
|
|
drive-strength = <2>;
|
|
};
|
|
|
|
cmd {
|
|
pins = "sdc2_cmd";
|
|
bias-pull-up;
|
|
drive-strength = <2>;
|
|
};
|
|
|
|
data {
|
|
pins = "sdc2_data";
|
|
bias-pull-up;
|
|
drive-strength = <2>;
|
|
};
|
|
|
|
sd-cd {
|
|
pins = "gpio103";
|
|
bias-pull-up;
|
|
drive-strength = <2>;
|
|
};
|
|
};
|
|
|
|
pcie0 {
|
|
pcie0_perst_default: pcie0_perst_default {
|
|
mux {
|
|
pins = "gpio44";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio44";
|
|
drive-strength = <2>;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
|
|
pcie0_clkreq_default: pcie0_clkreq_default {
|
|
mux {
|
|
pins = "gpio43";
|
|
function = "pcie0_clkreq_n";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio43";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
pcie0_wake_default: pcie0_wake_default {
|
|
mux {
|
|
pins = "gpio42";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio42";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
pcie0_clkreq_sleep: pcie0_clkreq_sleep {
|
|
mux {
|
|
pins = "gpio43";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio43";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
};
|
|
|
|
pcie1 {
|
|
pcie1_perst_default: pcie1_perst_default {
|
|
mux {
|
|
pins = "gpio125";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio125";
|
|
drive-strength = <2>;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
|
|
pcie1_clkreq_default: pcie1_clkreq_default {
|
|
mux {
|
|
pins = "gpio124";
|
|
function = "pcie1_clkreq_n";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio124";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
pcie1_wake_default: pcie1_wake_default {
|
|
mux {
|
|
pins = "gpio123";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio123";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
pcie1_clkreq_sleep: pcie1_clkreq_sleep {
|
|
mux {
|
|
pins = "gpio124";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio124";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
};
|
|
|
|
pcie2 {
|
|
pcie2_perst_default: pcie2_perst_default {
|
|
mux {
|
|
pins = "gpio122";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio122";
|
|
drive-strength = <2>;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
|
|
pcie2_clkreq_default: pcie2_clkreq_default {
|
|
mux {
|
|
pins = "gpio121";
|
|
function = "pcie2_clkreq_n";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio121";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
pcie2_wake_default: pcie2_wake_default {
|
|
mux {
|
|
pins = "gpio120";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio120";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
|
|
pcie2_clkreq_sleep: pcie2_clkreq_sleep {
|
|
mux {
|
|
pins = "gpio121";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio121";
|
|
drive-strength = <2>;
|
|
bias-pull-up;
|
|
};
|
|
};
|
|
};
|
|
|
|
pcie_ep {
|
|
pcie_ep_clkreq_default: pcie_ep_clkreq_default {
|
|
mux {
|
|
pins = "gpio43";
|
|
function = "pcie0_clkreq_n";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio43";
|
|
drive-strength = <2>;
|
|
bias-disable;
|
|
input-enable;
|
|
};
|
|
};
|
|
|
|
pcie_ep_perst_default: pcie_ep_perst_default {
|
|
mux {
|
|
pins = "gpio44";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio44";
|
|
drive-strength = <2>;
|
|
bias-pull-down;
|
|
};
|
|
};
|
|
|
|
pcie_ep_wake_default: pcie_ep_wake_default {
|
|
mux {
|
|
pins = "gpio42";
|
|
function = "gpio";
|
|
};
|
|
|
|
config {
|
|
pins = "gpio42";
|
|
drive-strength = <2>;
|
|
bias-disable;
|
|
};
|
|
};
|
|
};
|
|
};
|