1633 lines
47 KiB
C
1633 lines
47 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/err.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/of.h>
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#include <linux/regmap.h>
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#include <linux/pm_runtime.h>
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#include <dt-bindings/clock/qcom,dispcc-lemans.h>
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#include "clk-alpha-pll.h"
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#include "clk-branch.h"
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#include "clk-pm.h"
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#include "clk-rcg.h"
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#include "clk-regmap.h"
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#include "clk-regmap-divider.h"
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#include "clk-regmap-mux.h"
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#include "common.h"
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#include "reset.h"
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#include "vdd-level-sm8150.h"
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static DEFINE_VDD_REGULATORS(vdd_mm, VDD_HIGH_L1 + 1, 1, vdd_corner);
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static struct clk_vdd_class *disp_cc_1_lemans_regulators[] = {
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&vdd_mm,
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};
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enum {
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P_BI_TCXO,
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P_DP0_PHY_PLL_LINK_CLK,
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P_DP0_PHY_PLL_VCO_DIV_CLK,
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P_DP1_PHY_PLL_LINK_CLK,
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P_DP1_PHY_PLL_VCO_DIV_CLK,
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P_DSI0_PHY_PLL_OUT_BYTECLK,
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P_DSI0_PHY_PLL_OUT_DSICLK,
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P_DSI1_PHY_PLL_OUT_BYTECLK,
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P_DSI1_PHY_PLL_OUT_DSICLK,
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P_MDSS_1_DISP_CC_PLL0_OUT_MAIN,
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P_MDSS_1_DISP_CC_PLL1_OUT_EVEN,
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P_MDSS_1_DISP_CC_PLL1_OUT_MAIN,
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P_SLEEP_CLK,
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};
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static const struct pll_vco lucid_evo_vco[] = {
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{ 249600000, 2000000000, 0 },
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};
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/* 1125MHz configuration */
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static struct alpha_pll_config mdss_1_disp_cc_pll0_config = {
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.l = 0x3A,
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.cal_l = 0x44,
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.alpha = 0x9800,
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.config_ctl_val = 0x20485699,
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.config_ctl_hi_val = 0x00182261,
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.config_ctl_hi1_val = 0x32AA299C,
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.user_ctl_val = 0x00000000,
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.user_ctl_hi_val = 0x00400805,
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};
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static struct clk_alpha_pll mdss_1_disp_cc_pll0 = {
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.offset = 0x0,
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.vco_table = lucid_evo_vco,
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.num_vco = ARRAY_SIZE(lucid_evo_vco),
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
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.config = &mdss_1_disp_cc_pll0_config,
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.clkr = {
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.hw.init = &(const struct clk_init_data){
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.name = "mdss_1_disp_cc_pll0",
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.parent_data = &(const struct clk_parent_data){
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.fw_name = "bi_tcxo",
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},
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.num_parents = 1,
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.ops = &clk_alpha_pll_lucid_evo_ops,
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},
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.vdd_data = {
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.vdd_class = &vdd_mm,
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.num_rate_max = VDD_NUM,
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.rate_max = (unsigned long[VDD_NUM]) {
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[VDD_LOWER_D1] = 500000000,
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[VDD_LOWER] = 615000000,
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[VDD_LOW] = 1066000000,
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[VDD_LOW_L1] = 1500000000,
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[VDD_NOMINAL] = 1800000000,
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[VDD_HIGH] = 2000000000},
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},
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},
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};
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/* 600MHz configuration */
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static struct alpha_pll_config mdss_1_disp_cc_pll1_config = {
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.l = 0x1F,
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.cal_l = 0x44,
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.alpha = 0x4000,
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.config_ctl_val = 0x20485699,
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.config_ctl_hi_val = 0x00182261,
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.config_ctl_hi1_val = 0x32AA299C,
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.user_ctl_val = 0x00000000,
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.user_ctl_hi_val = 0x00400805,
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};
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static struct clk_alpha_pll mdss_1_disp_cc_pll1 = {
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.offset = 0x1000,
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.vco_table = lucid_evo_vco,
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.num_vco = ARRAY_SIZE(lucid_evo_vco),
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
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.config = &mdss_1_disp_cc_pll1_config,
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.clkr = {
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.hw.init = &(const struct clk_init_data){
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.name = "mdss_1_disp_cc_pll1",
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.parent_data = &(const struct clk_parent_data){
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.fw_name = "bi_tcxo",
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},
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.num_parents = 1,
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.ops = &clk_alpha_pll_lucid_evo_ops,
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},
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.vdd_data = {
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.vdd_class = &vdd_mm,
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.num_rate_max = VDD_NUM,
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.rate_max = (unsigned long[VDD_NUM]) {
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[VDD_LOWER_D1] = 500000000,
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[VDD_LOWER] = 615000000,
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[VDD_LOW] = 1066000000,
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[VDD_LOW_L1] = 1500000000,
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[VDD_NOMINAL] = 1800000000,
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[VDD_HIGH] = 2000000000},
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},
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},
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};
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static const struct parent_map disp_cc_1_parent_map_0[] = {
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{ P_BI_TCXO, 0 },
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{ P_DP0_PHY_PLL_LINK_CLK, 1 },
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{ P_DP0_PHY_PLL_VCO_DIV_CLK, 2 },
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{ P_DP1_PHY_PLL_VCO_DIV_CLK, 4 },
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};
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static const struct clk_parent_data disp_cc_1_parent_data_0[] = {
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{ .fw_name = "bi_tcxo" },
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{ .fw_name = "dp0_phy_pll_link_clk", .name = "dp0_phy_pll_link_clk" },
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{ .fw_name = "dp0_phy_pll_vco_div_clk", .name = "dp0_phy_pll_vco_div_clk" },
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{ .fw_name = "dp1_phy_pll_vco_div_clk", .name = "dp1_phy_pll_vco_div_clk" },
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};
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static const struct parent_map disp_cc_1_parent_map_1[] = {
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{ P_BI_TCXO, 0 },
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{ P_DSI0_PHY_PLL_OUT_DSICLK, 1 },
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{ P_DSI0_PHY_PLL_OUT_BYTECLK, 2 },
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{ P_DSI1_PHY_PLL_OUT_DSICLK, 3 },
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{ P_DSI1_PHY_PLL_OUT_BYTECLK, 4 },
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};
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static const struct clk_parent_data disp_cc_1_parent_data_1[] = {
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{ .fw_name = "bi_tcxo" },
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{ .fw_name = "dsi0_phy_pll_out_dsiclk", .name = "dsi0_phy_pll_out_dsiclk" },
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{ .fw_name = "dsi0_phy_pll_out_byteclk", .name = "dsi0_phy_pll_out_byteclk" },
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{ .fw_name = "dsi1_phy_pll_out_dsiclk", .name = "dsi1_phy_pll_out_dsiclk" },
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{ .fw_name = "dsi1_phy_pll_out_byteclk", .name = "dsi1_phy_pll_out_byteclk" },
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};
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static const struct parent_map disp_cc_1_parent_map_2[] = {
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{ P_BI_TCXO, 0 },
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};
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static const struct clk_parent_data disp_cc_1_parent_data_2[] = {
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{ .fw_name = "bi_tcxo" },
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};
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static const struct clk_parent_data disp_cc_1_parent_data_2_ao[] = {
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{ .fw_name = "bi_tcxo_ao" },
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};
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static const struct parent_map disp_cc_1_parent_map_3[] = {
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{ P_BI_TCXO, 0 },
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{ P_DP0_PHY_PLL_LINK_CLK, 1 },
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{ P_DP1_PHY_PLL_LINK_CLK, 2 },
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};
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static const struct clk_parent_data disp_cc_1_parent_data_3[] = {
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{ .fw_name = "bi_tcxo" },
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{ .fw_name = "dp0_phy_pll_link_clk", .name = "dp0_phy_pll_link_clk" },
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{ .fw_name = "dp1_phy_pll_link_clk", .name = "dp1_phy_pll_link_clk" },
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};
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static const struct parent_map disp_cc_1_parent_map_4[] = {
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{ P_BI_TCXO, 0 },
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{ P_DSI0_PHY_PLL_OUT_BYTECLK, 2 },
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{ P_DSI1_PHY_PLL_OUT_BYTECLK, 4 },
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};
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static const struct clk_parent_data disp_cc_1_parent_data_4[] = {
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{ .fw_name = "bi_tcxo" },
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{ .fw_name = "dsi0_phy_pll_out_byteclk", .name = "dsi0_phy_pll_out_byteclk" },
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{ .fw_name = "dsi1_phy_pll_out_byteclk", .name = "dsi1_phy_pll_out_byteclk" },
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};
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static const struct parent_map disp_cc_1_parent_map_5[] = {
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{ P_BI_TCXO, 0 },
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{ P_MDSS_1_DISP_CC_PLL1_OUT_MAIN, 4 },
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{ P_MDSS_1_DISP_CC_PLL1_OUT_EVEN, 6 },
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};
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static const struct clk_parent_data disp_cc_1_parent_data_5[] = {
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{ .fw_name = "bi_tcxo" },
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{ .hw = &mdss_1_disp_cc_pll1.clkr.hw },
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{ .hw = &mdss_1_disp_cc_pll1.clkr.hw },
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};
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static const struct parent_map disp_cc_1_parent_map_6[] = {
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{ P_BI_TCXO, 0 },
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{ P_MDSS_1_DISP_CC_PLL0_OUT_MAIN, 1 },
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{ P_MDSS_1_DISP_CC_PLL1_OUT_MAIN, 4 },
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{ P_MDSS_1_DISP_CC_PLL1_OUT_EVEN, 6 },
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};
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static const struct clk_parent_data disp_cc_1_parent_data_6[] = {
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{ .fw_name = "bi_tcxo" },
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{ .hw = &mdss_1_disp_cc_pll0.clkr.hw },
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{ .hw = &mdss_1_disp_cc_pll1.clkr.hw },
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{ .hw = &mdss_1_disp_cc_pll1.clkr.hw },
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};
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static const struct parent_map disp_cc_1_parent_map_7[] = {
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{ P_SLEEP_CLK, 0 },
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};
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static const struct clk_parent_data disp_cc_1_parent_data_7[] = {
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{ .fw_name = "sleep_clk" },
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};
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static const struct freq_tbl ftbl_mdss_1_disp_cc_mdss_ahb_clk_src[] = {
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F(37500000, P_MDSS_1_DISP_CC_PLL1_OUT_MAIN, 16, 0, 0),
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F(75000000, P_MDSS_1_DISP_CC_PLL1_OUT_MAIN, 8, 0, 0),
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{ }
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};
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static struct clk_rcg2 mdss_1_disp_cc_mdss_ahb_clk_src = {
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.cmd_rcgr = 0x824c,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = disp_cc_1_parent_map_5,
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.freq_tbl = ftbl_mdss_1_disp_cc_mdss_ahb_clk_src,
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.enable_safe_config = true,
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.flags = HW_CLK_CTRL_MODE,
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.clkr.hw.init = &(const struct clk_init_data){
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.name = "mdss_1_disp_cc_mdss_ahb_clk_src",
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.parent_data = disp_cc_1_parent_data_5,
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.num_parents = ARRAY_SIZE(disp_cc_1_parent_data_5),
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_rcg2_ops,
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},
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.clkr.vdd_data = {
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.vdd_class = &vdd_mm,
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.num_rate_max = VDD_NUM,
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.rate_max = (unsigned long[VDD_NUM]) {
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[VDD_LOW_L1] = 37500000,
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[VDD_NOMINAL] = 75000000},
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},
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};
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static const struct freq_tbl ftbl_mdss_1_disp_cc_mdss_byte0_clk_src[] = {
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F(19200000, P_BI_TCXO, 1, 0, 0),
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{ }
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};
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static struct clk_rcg2 mdss_1_disp_cc_mdss_byte0_clk_src = {
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.cmd_rcgr = 0x80ec,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = disp_cc_1_parent_map_1,
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.freq_tbl = ftbl_mdss_1_disp_cc_mdss_byte0_clk_src,
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.clkr.hw.init = &(const struct clk_init_data){
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.name = "mdss_1_disp_cc_mdss_byte0_clk_src",
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.parent_data = disp_cc_1_parent_data_1,
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.num_parents = ARRAY_SIZE(disp_cc_1_parent_data_1),
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_byte2_ops,
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},
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.clkr.vdd_data = {
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.vdd_class = &vdd_mm,
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.num_rate_max = VDD_NUM,
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.rate_max = (unsigned long[VDD_NUM]) {
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[VDD_LOW_L1] = 358000000},
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},
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};
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static struct clk_rcg2 mdss_1_disp_cc_mdss_byte1_clk_src = {
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.cmd_rcgr = 0x8108,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = disp_cc_1_parent_map_1,
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.freq_tbl = ftbl_mdss_1_disp_cc_mdss_byte0_clk_src,
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.clkr.hw.init = &(const struct clk_init_data){
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.name = "mdss_1_disp_cc_mdss_byte1_clk_src",
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.parent_data = disp_cc_1_parent_data_1,
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.num_parents = ARRAY_SIZE(disp_cc_1_parent_data_1),
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_byte2_ops,
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},
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.clkr.vdd_data = {
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.vdd_class = &vdd_mm,
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.num_rate_max = VDD_NUM,
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.rate_max = (unsigned long[VDD_NUM]) {
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[VDD_LOW_L1] = 358000000},
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},
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};
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static struct clk_rcg2 mdss_1_disp_cc_mdss_dptx0_aux_clk_src = {
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.cmd_rcgr = 0x81b8,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = disp_cc_1_parent_map_2,
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.freq_tbl = ftbl_mdss_1_disp_cc_mdss_byte0_clk_src,
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.clkr.hw.init = &(const struct clk_init_data){
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.name = "mdss_1_disp_cc_mdss_dptx0_aux_clk_src",
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.parent_data = disp_cc_1_parent_data_2,
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.num_parents = ARRAY_SIZE(disp_cc_1_parent_data_2),
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_rcg2_ops,
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},
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.clkr.vdd_data = {
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.vdd_class = &vdd_mm,
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.num_rate_max = VDD_NUM,
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.rate_max = (unsigned long[VDD_NUM]) {
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[VDD_LOW_L1] = 19200000},
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},
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};
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static struct clk_rcg2 mdss_1_disp_cc_mdss_dptx0_crypto_clk_src = {
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.cmd_rcgr = 0x8170,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = disp_cc_1_parent_map_3,
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.freq_tbl = ftbl_mdss_1_disp_cc_mdss_byte0_clk_src,
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.clkr.hw.init = &(const struct clk_init_data){
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.name = "mdss_1_disp_cc_mdss_dptx0_crypto_clk_src",
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.parent_data = disp_cc_1_parent_data_3,
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.num_parents = ARRAY_SIZE(disp_cc_1_parent_data_3),
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_byte2_ops,
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},
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.clkr.vdd_data = {
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.vdd_class = &vdd_mm,
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.num_rate_max = VDD_NUM,
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.rate_max = (unsigned long[VDD_NUM]) {
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[VDD_LOW_L1] = 396000000,
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[VDD_NOMINAL] = 540000000},
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},
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};
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static struct clk_rcg2 mdss_1_disp_cc_mdss_dptx0_link_clk_src = {
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.cmd_rcgr = 0x8154,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = disp_cc_1_parent_map_3,
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.freq_tbl = ftbl_mdss_1_disp_cc_mdss_byte0_clk_src,
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.clkr.hw.init = &(const struct clk_init_data){
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.name = "mdss_1_disp_cc_mdss_dptx0_link_clk_src",
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.parent_data = disp_cc_1_parent_data_3,
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.num_parents = ARRAY_SIZE(disp_cc_1_parent_data_3),
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_byte2_ops,
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},
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.clkr.vdd_data = {
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.vdd_class = &vdd_mm,
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.num_rate_max = VDD_NUM,
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.rate_max = (unsigned long[VDD_NUM]) {
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[VDD_LOW_L1] = 594000000,
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[VDD_NOMINAL] = 810000000},
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},
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};
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static struct clk_rcg2 mdss_1_disp_cc_mdss_dptx0_pixel0_clk_src = {
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.cmd_rcgr = 0x8188,
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.mnd_width = 16,
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.hid_width = 5,
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.parent_map = disp_cc_1_parent_map_0,
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.freq_tbl = ftbl_mdss_1_disp_cc_mdss_byte0_clk_src,
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.clkr.hw.init = &(const struct clk_init_data){
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.name = "mdss_1_disp_cc_mdss_dptx0_pixel0_clk_src",
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.parent_data = disp_cc_1_parent_data_0,
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.num_parents = ARRAY_SIZE(disp_cc_1_parent_data_0),
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_dp_ops,
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},
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.clkr.vdd_data = {
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.vdd_class = &vdd_mm,
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.num_rate_max = VDD_NUM,
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.rate_max = (unsigned long[VDD_NUM]) {
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[VDD_LOW_L1] = 405000000,
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[VDD_NOMINAL] = 675000000},
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},
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};
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static struct clk_rcg2 mdss_1_disp_cc_mdss_dptx0_pixel1_clk_src = {
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.cmd_rcgr = 0x81a0,
|
|
.mnd_width = 16,
|
|
.hid_width = 5,
|
|
.parent_map = disp_cc_1_parent_map_0,
|
|
.freq_tbl = ftbl_mdss_1_disp_cc_mdss_byte0_clk_src,
|
|
.clkr.hw.init = &(const struct clk_init_data){
|
|
.name = "mdss_1_disp_cc_mdss_dptx0_pixel1_clk_src",
|
|
.parent_data = disp_cc_1_parent_data_0,
|
|
.num_parents = ARRAY_SIZE(disp_cc_1_parent_data_0),
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_dp_ops,
|
|
},
|
|
.clkr.vdd_data = {
|
|
.vdd_class = &vdd_mm,
|
|
.num_rate_max = VDD_NUM,
|
|
.rate_max = (unsigned long[VDD_NUM]) {
|
|
[VDD_LOW_L1] = 405000000,
|
|
[VDD_NOMINAL] = 675000000},
|
|
},
|
|
};
|
|
|
|
static struct clk_rcg2 mdss_1_disp_cc_mdss_dptx0_pixel2_clk_src = {
|
|
.cmd_rcgr = 0x826c,
|
|
.mnd_width = 16,
|
|
.hid_width = 5,
|
|
.parent_map = disp_cc_1_parent_map_0,
|
|
.freq_tbl = ftbl_mdss_1_disp_cc_mdss_byte0_clk_src,
|
|
.clkr.hw.init = &(const struct clk_init_data){
|
|
.name = "mdss_1_disp_cc_mdss_dptx0_pixel2_clk_src",
|
|
.parent_data = disp_cc_1_parent_data_0,
|
|
.num_parents = ARRAY_SIZE(disp_cc_1_parent_data_0),
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_dp_ops,
|
|
},
|
|
.clkr.vdd_data = {
|
|
.vdd_class = &vdd_mm,
|
|
.num_rate_max = VDD_NUM,
|
|
.rate_max = (unsigned long[VDD_NUM]) {
|
|
[VDD_LOW_L1] = 405000000,
|
|
[VDD_NOMINAL] = 675000000},
|
|
},
|
|
};
|
|
|
|
static struct clk_rcg2 mdss_1_disp_cc_mdss_dptx0_pixel3_clk_src = {
|
|
.cmd_rcgr = 0x8284,
|
|
.mnd_width = 16,
|
|
.hid_width = 5,
|
|
.parent_map = disp_cc_1_parent_map_0,
|
|
.freq_tbl = ftbl_mdss_1_disp_cc_mdss_byte0_clk_src,
|
|
.clkr.hw.init = &(const struct clk_init_data){
|
|
.name = "mdss_1_disp_cc_mdss_dptx0_pixel3_clk_src",
|
|
.parent_data = disp_cc_1_parent_data_0,
|
|
.num_parents = ARRAY_SIZE(disp_cc_1_parent_data_0),
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_dp_ops,
|
|
},
|
|
.clkr.vdd_data = {
|
|
.vdd_class = &vdd_mm,
|
|
.num_rate_max = VDD_NUM,
|
|
.rate_max = (unsigned long[VDD_NUM]) {
|
|
[VDD_LOW_L1] = 405000000,
|
|
[VDD_NOMINAL] = 675000000},
|
|
},
|
|
};
|
|
|
|
static struct clk_rcg2 mdss_1_disp_cc_mdss_dptx1_aux_clk_src = {
|
|
.cmd_rcgr = 0x8234,
|
|
.mnd_width = 0,
|
|
.hid_width = 5,
|
|
.parent_map = disp_cc_1_parent_map_2,
|
|
.freq_tbl = ftbl_mdss_1_disp_cc_mdss_byte0_clk_src,
|
|
.clkr.hw.init = &(const struct clk_init_data){
|
|
.name = "mdss_1_disp_cc_mdss_dptx1_aux_clk_src",
|
|
.parent_data = disp_cc_1_parent_data_2,
|
|
.num_parents = ARRAY_SIZE(disp_cc_1_parent_data_2),
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_rcg2_ops,
|
|
},
|
|
.clkr.vdd_data = {
|
|
.vdd_class = &vdd_mm,
|
|
.num_rate_max = VDD_NUM,
|
|
.rate_max = (unsigned long[VDD_NUM]) {
|
|
[VDD_LOW_L1] = 19200000},
|
|
},
|
|
};
|
|
|
|
static struct clk_rcg2 mdss_1_disp_cc_mdss_dptx1_crypto_clk_src = {
|
|
.cmd_rcgr = 0x821c,
|
|
.mnd_width = 0,
|
|
.hid_width = 5,
|
|
.parent_map = disp_cc_1_parent_map_3,
|
|
.freq_tbl = ftbl_mdss_1_disp_cc_mdss_byte0_clk_src,
|
|
.clkr.hw.init = &(const struct clk_init_data){
|
|
.name = "mdss_1_disp_cc_mdss_dptx1_crypto_clk_src",
|
|
.parent_data = disp_cc_1_parent_data_3,
|
|
.num_parents = ARRAY_SIZE(disp_cc_1_parent_data_3),
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_byte2_ops,
|
|
},
|
|
.clkr.vdd_data = {
|
|
.vdd_class = &vdd_mm,
|
|
.num_rate_max = VDD_NUM,
|
|
.rate_max = (unsigned long[VDD_NUM]) {
|
|
[VDD_LOW_L1] = 396000000,
|
|
[VDD_NOMINAL] = 540000000},
|
|
},
|
|
};
|
|
|
|
static struct clk_rcg2 mdss_1_disp_cc_mdss_dptx1_link_clk_src = {
|
|
.cmd_rcgr = 0x8200,
|
|
.mnd_width = 0,
|
|
.hid_width = 5,
|
|
.parent_map = disp_cc_1_parent_map_3,
|
|
.freq_tbl = ftbl_mdss_1_disp_cc_mdss_byte0_clk_src,
|
|
.clkr.hw.init = &(const struct clk_init_data){
|
|
.name = "mdss_1_disp_cc_mdss_dptx1_link_clk_src",
|
|
.parent_data = disp_cc_1_parent_data_3,
|
|
.num_parents = ARRAY_SIZE(disp_cc_1_parent_data_3),
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_byte2_ops,
|
|
},
|
|
.clkr.vdd_data = {
|
|
.vdd_class = &vdd_mm,
|
|
.num_rate_max = VDD_NUM,
|
|
.rate_max = (unsigned long[VDD_NUM]) {
|
|
[VDD_LOW_L1] = 594000000,
|
|
[VDD_NOMINAL] = 810000000},
|
|
},
|
|
};
|
|
|
|
static struct clk_rcg2 mdss_1_disp_cc_mdss_dptx1_pixel0_clk_src = {
|
|
.cmd_rcgr = 0x81d0,
|
|
.mnd_width = 16,
|
|
.hid_width = 5,
|
|
.parent_map = disp_cc_1_parent_map_0,
|
|
.freq_tbl = ftbl_mdss_1_disp_cc_mdss_byte0_clk_src,
|
|
.clkr.hw.init = &(const struct clk_init_data){
|
|
.name = "mdss_1_disp_cc_mdss_dptx1_pixel0_clk_src",
|
|
.parent_data = disp_cc_1_parent_data_0,
|
|
.num_parents = ARRAY_SIZE(disp_cc_1_parent_data_0),
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_dp_ops,
|
|
},
|
|
.clkr.vdd_data = {
|
|
.vdd_class = &vdd_mm,
|
|
.num_rate_max = VDD_NUM,
|
|
.rate_max = (unsigned long[VDD_NUM]) {
|
|
[VDD_LOW_L1] = 405000000,
|
|
[VDD_NOMINAL] = 675000000},
|
|
},
|
|
};
|
|
|
|
static struct clk_rcg2 mdss_1_disp_cc_mdss_dptx1_pixel1_clk_src = {
|
|
.cmd_rcgr = 0x81e8,
|
|
.mnd_width = 16,
|
|
.hid_width = 5,
|
|
.parent_map = disp_cc_1_parent_map_0,
|
|
.freq_tbl = ftbl_mdss_1_disp_cc_mdss_byte0_clk_src,
|
|
.clkr.hw.init = &(const struct clk_init_data){
|
|
.name = "mdss_1_disp_cc_mdss_dptx1_pixel1_clk_src",
|
|
.parent_data = disp_cc_1_parent_data_0,
|
|
.num_parents = ARRAY_SIZE(disp_cc_1_parent_data_0),
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_dp_ops,
|
|
},
|
|
.clkr.vdd_data = {
|
|
.vdd_class = &vdd_mm,
|
|
.num_rate_max = VDD_NUM,
|
|
.rate_max = (unsigned long[VDD_NUM]) {
|
|
[VDD_LOW_L1] = 405000000,
|
|
[VDD_NOMINAL] = 675000000},
|
|
},
|
|
};
|
|
|
|
static struct clk_rcg2 mdss_1_disp_cc_mdss_esc0_clk_src = {
|
|
.cmd_rcgr = 0x8124,
|
|
.mnd_width = 0,
|
|
.hid_width = 5,
|
|
.parent_map = disp_cc_1_parent_map_4,
|
|
.freq_tbl = ftbl_mdss_1_disp_cc_mdss_byte0_clk_src,
|
|
.clkr.hw.init = &(const struct clk_init_data){
|
|
.name = "mdss_1_disp_cc_mdss_esc0_clk_src",
|
|
.parent_data = disp_cc_1_parent_data_4,
|
|
.num_parents = ARRAY_SIZE(disp_cc_1_parent_data_4),
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_rcg2_ops,
|
|
},
|
|
.clkr.vdd_data = {
|
|
.vdd_class = &vdd_mm,
|
|
.num_rate_max = VDD_NUM,
|
|
.rate_max = (unsigned long[VDD_NUM]) {
|
|
[VDD_LOW_L1] = 19200000},
|
|
},
|
|
};
|
|
|
|
static struct clk_rcg2 mdss_1_disp_cc_mdss_esc1_clk_src = {
|
|
.cmd_rcgr = 0x813c,
|
|
.mnd_width = 0,
|
|
.hid_width = 5,
|
|
.parent_map = disp_cc_1_parent_map_4,
|
|
.freq_tbl = ftbl_mdss_1_disp_cc_mdss_byte0_clk_src,
|
|
.clkr.hw.init = &(const struct clk_init_data){
|
|
.name = "mdss_1_disp_cc_mdss_esc1_clk_src",
|
|
.parent_data = disp_cc_1_parent_data_4,
|
|
.num_parents = ARRAY_SIZE(disp_cc_1_parent_data_4),
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_rcg2_ops,
|
|
},
|
|
.clkr.vdd_data = {
|
|
.vdd_class = &vdd_mm,
|
|
.num_rate_max = VDD_NUM,
|
|
.rate_max = (unsigned long[VDD_NUM]) {
|
|
[VDD_LOW_L1] = 19200000},
|
|
},
|
|
};
|
|
|
|
static const struct freq_tbl ftbl_mdss_1_disp_cc_mdss_mdp_clk_src[] = {
|
|
F(375000000, P_MDSS_1_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
|
|
F(500000000, P_MDSS_1_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
|
|
F(575000000, P_MDSS_1_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
|
|
F(650000000, P_MDSS_1_DISP_CC_PLL0_OUT_MAIN, 3, 0, 0),
|
|
{ }
|
|
};
|
|
|
|
static struct clk_rcg2 mdss_1_disp_cc_mdss_mdp_clk_src = {
|
|
.cmd_rcgr = 0x80bc,
|
|
.mnd_width = 0,
|
|
.hid_width = 5,
|
|
.parent_map = disp_cc_1_parent_map_6,
|
|
.freq_tbl = ftbl_mdss_1_disp_cc_mdss_mdp_clk_src,
|
|
.enable_safe_config = true,
|
|
.flags = HW_CLK_CTRL_MODE,
|
|
.clkr.hw.init = &(const struct clk_init_data){
|
|
.name = "mdss_1_disp_cc_mdss_mdp_clk_src",
|
|
.parent_data = disp_cc_1_parent_data_6,
|
|
.num_parents = ARRAY_SIZE(disp_cc_1_parent_data_6),
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_rcg2_ops,
|
|
},
|
|
.clkr.vdd_data = {
|
|
.vdd_class = &vdd_mm,
|
|
.num_rate_max = VDD_NUM,
|
|
.rate_max = (unsigned long[VDD_NUM]) {
|
|
[VDD_LOW_L1] = 375000000,
|
|
[VDD_NOMINAL] = 500000000,
|
|
[VDD_HIGH] = 575000000,
|
|
[VDD_HIGH_L1] = 650000000},
|
|
},
|
|
};
|
|
|
|
static struct clk_rcg2 mdss_1_disp_cc_mdss_pclk0_clk_src = {
|
|
.cmd_rcgr = 0x808c,
|
|
.mnd_width = 8,
|
|
.hid_width = 5,
|
|
.parent_map = disp_cc_1_parent_map_1,
|
|
.freq_tbl = ftbl_mdss_1_disp_cc_mdss_byte0_clk_src,
|
|
.clkr.hw.init = &(const struct clk_init_data){
|
|
.name = "mdss_1_disp_cc_mdss_pclk0_clk_src",
|
|
.parent_data = disp_cc_1_parent_data_1,
|
|
.num_parents = ARRAY_SIZE(disp_cc_1_parent_data_1),
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_pixel_ops,
|
|
},
|
|
.clkr.vdd_data = {
|
|
.vdd_class = &vdd_mm,
|
|
.num_rate_max = VDD_NUM,
|
|
.rate_max = (unsigned long[VDD_NUM]) {
|
|
[VDD_LOW_L1] = 625000000},
|
|
},
|
|
};
|
|
|
|
static struct clk_rcg2 mdss_1_disp_cc_mdss_pclk1_clk_src = {
|
|
.cmd_rcgr = 0x80a4,
|
|
.mnd_width = 8,
|
|
.hid_width = 5,
|
|
.parent_map = disp_cc_1_parent_map_1,
|
|
.freq_tbl = ftbl_mdss_1_disp_cc_mdss_byte0_clk_src,
|
|
.clkr.hw.init = &(const struct clk_init_data){
|
|
.name = "mdss_1_disp_cc_mdss_pclk1_clk_src",
|
|
.parent_data = disp_cc_1_parent_data_1,
|
|
.num_parents = ARRAY_SIZE(disp_cc_1_parent_data_1),
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_pixel_ops,
|
|
},
|
|
.clkr.vdd_data = {
|
|
.vdd_class = &vdd_mm,
|
|
.num_rate_max = VDD_NUM,
|
|
.rate_max = (unsigned long[VDD_NUM]) {
|
|
[VDD_LOW_L1] = 625000000},
|
|
},
|
|
};
|
|
|
|
static struct clk_rcg2 mdss_1_disp_cc_mdss_vsync_clk_src = {
|
|
.cmd_rcgr = 0x80d4,
|
|
.mnd_width = 0,
|
|
.hid_width = 5,
|
|
.parent_map = disp_cc_1_parent_map_2,
|
|
.freq_tbl = ftbl_mdss_1_disp_cc_mdss_byte0_clk_src,
|
|
.clkr.hw.init = &(const struct clk_init_data){
|
|
.name = "mdss_1_disp_cc_mdss_vsync_clk_src",
|
|
.parent_data = disp_cc_1_parent_data_2,
|
|
.num_parents = ARRAY_SIZE(disp_cc_1_parent_data_2),
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_rcg2_ops,
|
|
},
|
|
.clkr.vdd_data = {
|
|
.vdd_class = &vdd_mm,
|
|
.num_rate_max = VDD_NUM,
|
|
.rate_max = (unsigned long[VDD_NUM]) {
|
|
[VDD_LOW_L1] = 19200000},
|
|
},
|
|
};
|
|
|
|
static const struct freq_tbl ftbl_mdss_1_disp_cc_sleep_clk_src[] = {
|
|
F(32000, P_SLEEP_CLK, 1, 0, 0),
|
|
{ }
|
|
};
|
|
|
|
static struct clk_rcg2 mdss_1_disp_cc_sleep_clk_src = {
|
|
.cmd_rcgr = 0xc058,
|
|
.mnd_width = 0,
|
|
.hid_width = 5,
|
|
.parent_map = disp_cc_1_parent_map_7,
|
|
.freq_tbl = ftbl_mdss_1_disp_cc_sleep_clk_src,
|
|
.clkr.hw.init = &(const struct clk_init_data){
|
|
.name = "mdss_1_disp_cc_sleep_clk_src",
|
|
.parent_data = disp_cc_1_parent_data_7,
|
|
.num_parents = ARRAY_SIZE(disp_cc_1_parent_data_7),
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_rcg2_ops,
|
|
},
|
|
.clkr.vdd_data = {
|
|
.vdd_class = &vdd_mm,
|
|
.num_rate_max = VDD_NUM,
|
|
.rate_max = (unsigned long[VDD_NUM]) {
|
|
[VDD_LOW_L1] = 32000},
|
|
},
|
|
};
|
|
|
|
static struct clk_rcg2 mdss_1_disp_cc_xo_clk_src = {
|
|
.cmd_rcgr = 0xc03c,
|
|
.mnd_width = 0,
|
|
.hid_width = 5,
|
|
.parent_map = disp_cc_1_parent_map_2,
|
|
.freq_tbl = ftbl_mdss_1_disp_cc_mdss_byte0_clk_src,
|
|
.clkr.hw.init = &(const struct clk_init_data){
|
|
.name = "mdss_1_disp_cc_xo_clk_src",
|
|
.parent_data = disp_cc_1_parent_data_2_ao,
|
|
.num_parents = ARRAY_SIZE(disp_cc_1_parent_data_2_ao),
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_rcg2_ops,
|
|
},
|
|
};
|
|
|
|
static struct clk_regmap_div mdss_1_disp_cc_mdss_byte0_div_clk_src = {
|
|
.reg = 0x8104,
|
|
.shift = 0,
|
|
.width = 4,
|
|
.clkr.hw.init = &(const struct clk_init_data) {
|
|
.name = "mdss_1_disp_cc_mdss_byte0_div_clk_src",
|
|
.parent_hws = (const struct clk_hw*[]){
|
|
&mdss_1_disp_cc_mdss_byte0_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_regmap_div_ops,
|
|
},
|
|
};
|
|
|
|
static struct clk_regmap_div mdss_1_disp_cc_mdss_byte1_div_clk_src = {
|
|
.reg = 0x8120,
|
|
.shift = 0,
|
|
.width = 4,
|
|
.clkr.hw.init = &(const struct clk_init_data) {
|
|
.name = "mdss_1_disp_cc_mdss_byte1_div_clk_src",
|
|
.parent_hws = (const struct clk_hw*[]){
|
|
&mdss_1_disp_cc_mdss_byte1_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_regmap_div_ops,
|
|
},
|
|
};
|
|
|
|
static struct clk_regmap_div mdss_1_disp_cc_mdss_dptx0_link_div_clk_src = {
|
|
.reg = 0x816c,
|
|
.shift = 0,
|
|
.width = 4,
|
|
.clkr.hw.init = &(const struct clk_init_data) {
|
|
.name = "mdss_1_disp_cc_mdss_dptx0_link_div_clk_src",
|
|
.parent_hws = (const struct clk_hw*[]){
|
|
&mdss_1_disp_cc_mdss_dptx0_link_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_regmap_div_ro_ops,
|
|
},
|
|
};
|
|
|
|
static struct clk_regmap_div mdss_1_disp_cc_mdss_dptx1_link_div_clk_src = {
|
|
.reg = 0x8218,
|
|
.shift = 0,
|
|
.width = 4,
|
|
.clkr.hw.init = &(const struct clk_init_data) {
|
|
.name = "mdss_1_disp_cc_mdss_dptx1_link_div_clk_src",
|
|
.parent_hws = (const struct clk_hw*[]){
|
|
&mdss_1_disp_cc_mdss_dptx1_link_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_regmap_div_ro_ops,
|
|
},
|
|
};
|
|
|
|
static struct clk_branch mdss_1_disp_cc_mdss_ahb1_clk = {
|
|
.halt_reg = 0x8088,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x8088,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data){
|
|
.name = "mdss_1_disp_cc_mdss_ahb1_clk",
|
|
.parent_hws = (const struct clk_hw*[]){
|
|
&mdss_1_disp_cc_mdss_ahb_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_DONT_HOLD_STATE | CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch mdss_1_disp_cc_mdss_ahb_clk = {
|
|
.halt_reg = 0x8084,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x8084,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data){
|
|
.name = "mdss_1_disp_cc_mdss_ahb_clk",
|
|
.parent_hws = (const struct clk_hw*[]){
|
|
&mdss_1_disp_cc_mdss_ahb_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_DONT_HOLD_STATE | CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch mdss_1_disp_cc_mdss_byte0_clk = {
|
|
.halt_reg = 0x8034,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x8034,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data){
|
|
.name = "mdss_1_disp_cc_mdss_byte0_clk",
|
|
.parent_hws = (const struct clk_hw*[]){
|
|
&mdss_1_disp_cc_mdss_byte0_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch mdss_1_disp_cc_mdss_byte0_intf_clk = {
|
|
.halt_reg = 0x8038,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x8038,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data){
|
|
.name = "mdss_1_disp_cc_mdss_byte0_intf_clk",
|
|
.parent_hws = (const struct clk_hw*[]){
|
|
&mdss_1_disp_cc_mdss_byte0_div_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch mdss_1_disp_cc_mdss_byte1_clk = {
|
|
.halt_reg = 0x803c,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x803c,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data){
|
|
.name = "mdss_1_disp_cc_mdss_byte1_clk",
|
|
.parent_hws = (const struct clk_hw*[]){
|
|
&mdss_1_disp_cc_mdss_byte1_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch mdss_1_disp_cc_mdss_byte1_intf_clk = {
|
|
.halt_reg = 0x8040,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x8040,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data){
|
|
.name = "mdss_1_disp_cc_mdss_byte1_intf_clk",
|
|
.parent_hws = (const struct clk_hw*[]){
|
|
&mdss_1_disp_cc_mdss_byte1_div_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch mdss_1_disp_cc_mdss_dptx0_aux_clk = {
|
|
.halt_reg = 0x805c,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x805c,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data){
|
|
.name = "mdss_1_disp_cc_mdss_dptx0_aux_clk",
|
|
.parent_hws = (const struct clk_hw*[]){
|
|
&mdss_1_disp_cc_mdss_dptx0_aux_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch mdss_1_disp_cc_mdss_dptx0_crypto_clk = {
|
|
.halt_reg = 0x8058,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x8058,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data){
|
|
.name = "mdss_1_disp_cc_mdss_dptx0_crypto_clk",
|
|
.parent_hws = (const struct clk_hw*[]){
|
|
&mdss_1_disp_cc_mdss_dptx0_crypto_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch mdss_1_disp_cc_mdss_dptx0_link_clk = {
|
|
.halt_reg = 0x804c,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x804c,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data){
|
|
.name = "mdss_1_disp_cc_mdss_dptx0_link_clk",
|
|
.parent_hws = (const struct clk_hw*[]){
|
|
&mdss_1_disp_cc_mdss_dptx0_link_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch mdss_1_disp_cc_mdss_dptx0_link_intf_clk = {
|
|
.halt_reg = 0x8050,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x8050,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data){
|
|
.name = "mdss_1_disp_cc_mdss_dptx0_link_intf_clk",
|
|
.parent_hws = (const struct clk_hw*[]){
|
|
&mdss_1_disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch mdss_1_disp_cc_mdss_dptx0_pixel0_clk = {
|
|
.halt_reg = 0x8060,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x8060,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data){
|
|
.name = "mdss_1_disp_cc_mdss_dptx0_pixel0_clk",
|
|
.parent_hws = (const struct clk_hw*[]){
|
|
&mdss_1_disp_cc_mdss_dptx0_pixel0_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch mdss_1_disp_cc_mdss_dptx0_pixel1_clk = {
|
|
.halt_reg = 0x8064,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x8064,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data){
|
|
.name = "mdss_1_disp_cc_mdss_dptx0_pixel1_clk",
|
|
.parent_hws = (const struct clk_hw*[]){
|
|
&mdss_1_disp_cc_mdss_dptx0_pixel1_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch mdss_1_disp_cc_mdss_dptx0_pixel2_clk = {
|
|
.halt_reg = 0x8264,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x8264,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data){
|
|
.name = "mdss_1_disp_cc_mdss_dptx0_pixel2_clk",
|
|
.parent_hws = (const struct clk_hw*[]){
|
|
&mdss_1_disp_cc_mdss_dptx0_pixel2_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch mdss_1_disp_cc_mdss_dptx0_pixel3_clk = {
|
|
.halt_reg = 0x8268,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x8268,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data){
|
|
.name = "mdss_1_disp_cc_mdss_dptx0_pixel3_clk",
|
|
.parent_hws = (const struct clk_hw*[]){
|
|
&mdss_1_disp_cc_mdss_dptx0_pixel3_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch mdss_1_disp_cc_mdss_dptx0_usb_router_link_intf_clk = {
|
|
.halt_reg = 0x8054,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x8054,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data){
|
|
.name = "mdss_1_disp_cc_mdss_dptx0_usb_router_link_intf_clk",
|
|
.parent_hws = (const struct clk_hw*[]){
|
|
&mdss_1_disp_cc_mdss_dptx0_link_div_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch mdss_1_disp_cc_mdss_dptx1_aux_clk = {
|
|
.halt_reg = 0x8080,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x8080,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data){
|
|
.name = "mdss_1_disp_cc_mdss_dptx1_aux_clk",
|
|
.parent_hws = (const struct clk_hw*[]){
|
|
&mdss_1_disp_cc_mdss_dptx1_aux_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch mdss_1_disp_cc_mdss_dptx1_crypto_clk = {
|
|
.halt_reg = 0x807c,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x807c,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data){
|
|
.name = "mdss_1_disp_cc_mdss_dptx1_crypto_clk",
|
|
.parent_hws = (const struct clk_hw*[]){
|
|
&mdss_1_disp_cc_mdss_dptx1_crypto_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch mdss_1_disp_cc_mdss_dptx1_link_clk = {
|
|
.halt_reg = 0x8070,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x8070,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data){
|
|
.name = "mdss_1_disp_cc_mdss_dptx1_link_clk",
|
|
.parent_hws = (const struct clk_hw*[]){
|
|
&mdss_1_disp_cc_mdss_dptx1_link_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch mdss_1_disp_cc_mdss_dptx1_link_intf_clk = {
|
|
.halt_reg = 0x8074,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x8074,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data){
|
|
.name = "mdss_1_disp_cc_mdss_dptx1_link_intf_clk",
|
|
.parent_hws = (const struct clk_hw*[]){
|
|
&mdss_1_disp_cc_mdss_dptx1_link_div_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch mdss_1_disp_cc_mdss_dptx1_pixel0_clk = {
|
|
.halt_reg = 0x8068,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x8068,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data){
|
|
.name = "mdss_1_disp_cc_mdss_dptx1_pixel0_clk",
|
|
.parent_hws = (const struct clk_hw*[]){
|
|
&mdss_1_disp_cc_mdss_dptx1_pixel0_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch mdss_1_disp_cc_mdss_dptx1_pixel1_clk = {
|
|
.halt_reg = 0x806c,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x806c,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data){
|
|
.name = "mdss_1_disp_cc_mdss_dptx1_pixel1_clk",
|
|
.parent_hws = (const struct clk_hw*[]){
|
|
&mdss_1_disp_cc_mdss_dptx1_pixel1_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch mdss_1_disp_cc_mdss_dptx1_usb_router_link_intf_clk = {
|
|
.halt_reg = 0x8078,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x8078,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data){
|
|
.name = "mdss_1_disp_cc_mdss_dptx1_usb_router_link_intf_clk",
|
|
.parent_hws = (const struct clk_hw*[]){
|
|
&mdss_1_disp_cc_mdss_dptx1_link_div_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch mdss_1_disp_cc_mdss_esc0_clk = {
|
|
.halt_reg = 0x8044,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x8044,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data){
|
|
.name = "mdss_1_disp_cc_mdss_esc0_clk",
|
|
.parent_hws = (const struct clk_hw*[]){
|
|
&mdss_1_disp_cc_mdss_esc0_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch mdss_1_disp_cc_mdss_esc1_clk = {
|
|
.halt_reg = 0x8048,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x8048,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data){
|
|
.name = "mdss_1_disp_cc_mdss_esc1_clk",
|
|
.parent_hws = (const struct clk_hw*[]){
|
|
&mdss_1_disp_cc_mdss_esc1_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch mdss_1_disp_cc_mdss_mdp1_clk = {
|
|
.halt_reg = 0x8014,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x8014,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data){
|
|
.name = "mdss_1_disp_cc_mdss_mdp1_clk",
|
|
.parent_hws = (const struct clk_hw*[]){
|
|
&mdss_1_disp_cc_mdss_mdp_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch mdss_1_disp_cc_mdss_mdp_clk = {
|
|
.halt_reg = 0x800c,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x800c,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data){
|
|
.name = "mdss_1_disp_cc_mdss_mdp_clk",
|
|
.parent_hws = (const struct clk_hw*[]){
|
|
&mdss_1_disp_cc_mdss_mdp_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch mdss_1_disp_cc_mdss_mdp_lut1_clk = {
|
|
.halt_reg = 0x8024,
|
|
.halt_check = BRANCH_HALT_VOTED,
|
|
.clkr = {
|
|
.enable_reg = 0x8024,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data){
|
|
.name = "mdss_1_disp_cc_mdss_mdp_lut1_clk",
|
|
.parent_hws = (const struct clk_hw*[]){
|
|
&mdss_1_disp_cc_mdss_mdp_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch mdss_1_disp_cc_mdss_mdp_lut_clk = {
|
|
.halt_reg = 0x801c,
|
|
.halt_check = BRANCH_HALT_VOTED,
|
|
.clkr = {
|
|
.enable_reg = 0x801c,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data){
|
|
.name = "mdss_1_disp_cc_mdss_mdp_lut_clk",
|
|
.parent_hws = (const struct clk_hw*[]){
|
|
&mdss_1_disp_cc_mdss_mdp_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch mdss_1_disp_cc_mdss_non_gdsc_ahb_clk = {
|
|
.halt_reg = 0xa004,
|
|
.halt_check = BRANCH_HALT_VOTED,
|
|
.clkr = {
|
|
.enable_reg = 0xa004,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data){
|
|
.name = "mdss_1_disp_cc_mdss_non_gdsc_ahb_clk",
|
|
.parent_hws = (const struct clk_hw*[]){
|
|
&mdss_1_disp_cc_mdss_ahb_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch mdss_1_disp_cc_mdss_pclk0_clk = {
|
|
.halt_reg = 0x8004,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x8004,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data){
|
|
.name = "mdss_1_disp_cc_mdss_pclk0_clk",
|
|
.parent_hws = (const struct clk_hw*[]){
|
|
&mdss_1_disp_cc_mdss_pclk0_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch mdss_1_disp_cc_mdss_pclk1_clk = {
|
|
.halt_reg = 0x8008,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x8008,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data){
|
|
.name = "mdss_1_disp_cc_mdss_pclk1_clk",
|
|
.parent_hws = (const struct clk_hw*[]){
|
|
&mdss_1_disp_cc_mdss_pclk1_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch mdss_1_disp_cc_mdss_rscc_ahb_clk = {
|
|
.halt_reg = 0xa00c,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0xa00c,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data){
|
|
.name = "mdss_1_disp_cc_mdss_rscc_ahb_clk",
|
|
.parent_hws = (const struct clk_hw*[]){
|
|
&mdss_1_disp_cc_mdss_ahb_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch mdss_1_disp_cc_mdss_rscc_vsync_clk = {
|
|
.halt_reg = 0xa008,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0xa008,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data){
|
|
.name = "mdss_1_disp_cc_mdss_rscc_vsync_clk",
|
|
.parent_hws = (const struct clk_hw*[]){
|
|
&mdss_1_disp_cc_mdss_vsync_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch mdss_1_disp_cc_mdss_vsync1_clk = {
|
|
.halt_reg = 0x8030,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x8030,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data){
|
|
.name = "mdss_1_disp_cc_mdss_vsync1_clk",
|
|
.parent_hws = (const struct clk_hw*[]){
|
|
&mdss_1_disp_cc_mdss_vsync_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch mdss_1_disp_cc_mdss_vsync_clk = {
|
|
.halt_reg = 0x802c,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0x802c,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data){
|
|
.name = "mdss_1_disp_cc_mdss_vsync_clk",
|
|
.parent_hws = (const struct clk_hw*[]){
|
|
&mdss_1_disp_cc_mdss_vsync_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
static struct clk_branch mdss_1_disp_cc_sleep_clk = {
|
|
.halt_reg = 0xc070,
|
|
.halt_check = BRANCH_HALT,
|
|
.clkr = {
|
|
.enable_reg = 0xc070,
|
|
.enable_mask = BIT(0),
|
|
.hw.init = &(const struct clk_init_data){
|
|
.name = "mdss_1_disp_cc_sleep_clk",
|
|
.parent_hws = (const struct clk_hw*[]){
|
|
&mdss_1_disp_cc_sleep_clk_src.clkr.hw,
|
|
},
|
|
.num_parents = 1,
|
|
.flags = CLK_SET_RATE_PARENT,
|
|
.ops = &clk_branch2_ops,
|
|
},
|
|
},
|
|
};
|
|
|
|
/*
|
|
* Keep the clocks always-ON
|
|
* MDSS_1_DISP_CC_XO_CLK.
|
|
*/
|
|
static struct critical_clk_offset critical_clk_list[] = {
|
|
{ .offset = 0xc054, .mask = BIT(0) },
|
|
};
|
|
|
|
static struct clk_regmap *disp_cc_1_lemans_clocks[] = {
|
|
[DISP_CC_MDSS_AHB1_CLK] = &mdss_1_disp_cc_mdss_ahb1_clk.clkr,
|
|
[DISP_CC_MDSS_AHB_CLK] = &mdss_1_disp_cc_mdss_ahb_clk.clkr,
|
|
[DISP_CC_MDSS_AHB_CLK_SRC] = &mdss_1_disp_cc_mdss_ahb_clk_src.clkr,
|
|
[DISP_CC_MDSS_BYTE0_CLK] = &mdss_1_disp_cc_mdss_byte0_clk.clkr,
|
|
[DISP_CC_MDSS_BYTE0_CLK_SRC] = &mdss_1_disp_cc_mdss_byte0_clk_src.clkr,
|
|
[DISP_CC_MDSS_BYTE0_DIV_CLK_SRC] = &mdss_1_disp_cc_mdss_byte0_div_clk_src.clkr,
|
|
[DISP_CC_MDSS_BYTE0_INTF_CLK] = &mdss_1_disp_cc_mdss_byte0_intf_clk.clkr,
|
|
[DISP_CC_MDSS_BYTE1_CLK] = &mdss_1_disp_cc_mdss_byte1_clk.clkr,
|
|
[DISP_CC_MDSS_BYTE1_CLK_SRC] = &mdss_1_disp_cc_mdss_byte1_clk_src.clkr,
|
|
[DISP_CC_MDSS_BYTE1_DIV_CLK_SRC] = &mdss_1_disp_cc_mdss_byte1_div_clk_src.clkr,
|
|
[DISP_CC_MDSS_BYTE1_INTF_CLK] = &mdss_1_disp_cc_mdss_byte1_intf_clk.clkr,
|
|
[DISP_CC_MDSS_DPTX0_AUX_CLK] = &mdss_1_disp_cc_mdss_dptx0_aux_clk.clkr,
|
|
[DISP_CC_MDSS_DPTX0_AUX_CLK_SRC] = &mdss_1_disp_cc_mdss_dptx0_aux_clk_src.clkr,
|
|
[DISP_CC_MDSS_DPTX0_CRYPTO_CLK] = &mdss_1_disp_cc_mdss_dptx0_crypto_clk.clkr,
|
|
[DISP_CC_MDSS_DPTX0_CRYPTO_CLK_SRC] = &mdss_1_disp_cc_mdss_dptx0_crypto_clk_src.clkr,
|
|
[DISP_CC_MDSS_DPTX0_LINK_CLK] = &mdss_1_disp_cc_mdss_dptx0_link_clk.clkr,
|
|
[DISP_CC_MDSS_DPTX0_LINK_CLK_SRC] = &mdss_1_disp_cc_mdss_dptx0_link_clk_src.clkr,
|
|
[DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC] =
|
|
&mdss_1_disp_cc_mdss_dptx0_link_div_clk_src.clkr,
|
|
[DISP_CC_MDSS_DPTX0_LINK_INTF_CLK] = &mdss_1_disp_cc_mdss_dptx0_link_intf_clk.clkr,
|
|
[DISP_CC_MDSS_DPTX0_PIXEL0_CLK] = &mdss_1_disp_cc_mdss_dptx0_pixel0_clk.clkr,
|
|
[DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC] = &mdss_1_disp_cc_mdss_dptx0_pixel0_clk_src.clkr,
|
|
[DISP_CC_MDSS_DPTX0_PIXEL1_CLK] = &mdss_1_disp_cc_mdss_dptx0_pixel1_clk.clkr,
|
|
[DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC] = &mdss_1_disp_cc_mdss_dptx0_pixel1_clk_src.clkr,
|
|
[DISP_CC_MDSS_DPTX0_PIXEL2_CLK] = &mdss_1_disp_cc_mdss_dptx0_pixel2_clk.clkr,
|
|
[DISP_CC_MDSS_DPTX0_PIXEL2_CLK_SRC] = &mdss_1_disp_cc_mdss_dptx0_pixel2_clk_src.clkr,
|
|
[DISP_CC_MDSS_DPTX0_PIXEL3_CLK] = &mdss_1_disp_cc_mdss_dptx0_pixel3_clk.clkr,
|
|
[DISP_CC_MDSS_DPTX0_PIXEL3_CLK_SRC] = &mdss_1_disp_cc_mdss_dptx0_pixel3_clk_src.clkr,
|
|
[DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK] =
|
|
&mdss_1_disp_cc_mdss_dptx0_usb_router_link_intf_clk.clkr,
|
|
[DISP_CC_MDSS_DPTX1_AUX_CLK] = &mdss_1_disp_cc_mdss_dptx1_aux_clk.clkr,
|
|
[DISP_CC_MDSS_DPTX1_AUX_CLK_SRC] = &mdss_1_disp_cc_mdss_dptx1_aux_clk_src.clkr,
|
|
[DISP_CC_MDSS_DPTX1_CRYPTO_CLK] = &mdss_1_disp_cc_mdss_dptx1_crypto_clk.clkr,
|
|
[DISP_CC_MDSS_DPTX1_CRYPTO_CLK_SRC] = &mdss_1_disp_cc_mdss_dptx1_crypto_clk_src.clkr,
|
|
[DISP_CC_MDSS_DPTX1_LINK_CLK] = &mdss_1_disp_cc_mdss_dptx1_link_clk.clkr,
|
|
[DISP_CC_MDSS_DPTX1_LINK_CLK_SRC] = &mdss_1_disp_cc_mdss_dptx1_link_clk_src.clkr,
|
|
[DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC] =
|
|
&mdss_1_disp_cc_mdss_dptx1_link_div_clk_src.clkr,
|
|
[DISP_CC_MDSS_DPTX1_LINK_INTF_CLK] = &mdss_1_disp_cc_mdss_dptx1_link_intf_clk.clkr,
|
|
[DISP_CC_MDSS_DPTX1_PIXEL0_CLK] = &mdss_1_disp_cc_mdss_dptx1_pixel0_clk.clkr,
|
|
[DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC] = &mdss_1_disp_cc_mdss_dptx1_pixel0_clk_src.clkr,
|
|
[DISP_CC_MDSS_DPTX1_PIXEL1_CLK] = &mdss_1_disp_cc_mdss_dptx1_pixel1_clk.clkr,
|
|
[DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC] = &mdss_1_disp_cc_mdss_dptx1_pixel1_clk_src.clkr,
|
|
[DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK] =
|
|
&mdss_1_disp_cc_mdss_dptx1_usb_router_link_intf_clk.clkr,
|
|
[DISP_CC_MDSS_ESC0_CLK] = &mdss_1_disp_cc_mdss_esc0_clk.clkr,
|
|
[DISP_CC_MDSS_ESC0_CLK_SRC] = &mdss_1_disp_cc_mdss_esc0_clk_src.clkr,
|
|
[DISP_CC_MDSS_ESC1_CLK] = &mdss_1_disp_cc_mdss_esc1_clk.clkr,
|
|
[DISP_CC_MDSS_ESC1_CLK_SRC] = &mdss_1_disp_cc_mdss_esc1_clk_src.clkr,
|
|
[DISP_CC_MDSS_MDP1_CLK] = &mdss_1_disp_cc_mdss_mdp1_clk.clkr,
|
|
[DISP_CC_MDSS_MDP_CLK] = &mdss_1_disp_cc_mdss_mdp_clk.clkr,
|
|
[DISP_CC_MDSS_MDP_CLK_SRC] = &mdss_1_disp_cc_mdss_mdp_clk_src.clkr,
|
|
[DISP_CC_MDSS_MDP_LUT1_CLK] = &mdss_1_disp_cc_mdss_mdp_lut1_clk.clkr,
|
|
[DISP_CC_MDSS_MDP_LUT_CLK] = &mdss_1_disp_cc_mdss_mdp_lut_clk.clkr,
|
|
[DISP_CC_MDSS_NON_GDSC_AHB_CLK] = &mdss_1_disp_cc_mdss_non_gdsc_ahb_clk.clkr,
|
|
[DISP_CC_MDSS_PCLK0_CLK] = &mdss_1_disp_cc_mdss_pclk0_clk.clkr,
|
|
[DISP_CC_MDSS_PCLK0_CLK_SRC] = &mdss_1_disp_cc_mdss_pclk0_clk_src.clkr,
|
|
[DISP_CC_MDSS_PCLK1_CLK] = &mdss_1_disp_cc_mdss_pclk1_clk.clkr,
|
|
[DISP_CC_MDSS_PCLK1_CLK_SRC] = &mdss_1_disp_cc_mdss_pclk1_clk_src.clkr,
|
|
[DISP_CC_MDSS_RSCC_AHB_CLK] = &mdss_1_disp_cc_mdss_rscc_ahb_clk.clkr,
|
|
[DISP_CC_MDSS_RSCC_VSYNC_CLK] = &mdss_1_disp_cc_mdss_rscc_vsync_clk.clkr,
|
|
[DISP_CC_MDSS_VSYNC1_CLK] = &mdss_1_disp_cc_mdss_vsync1_clk.clkr,
|
|
[DISP_CC_MDSS_VSYNC_CLK] = &mdss_1_disp_cc_mdss_vsync_clk.clkr,
|
|
[DISP_CC_MDSS_VSYNC_CLK_SRC] = &mdss_1_disp_cc_mdss_vsync_clk_src.clkr,
|
|
[DISP_CC_PLL0] = &mdss_1_disp_cc_pll0.clkr,
|
|
[DISP_CC_PLL1] = &mdss_1_disp_cc_pll1.clkr,
|
|
[DISP_CC_SLEEP_CLK] = &mdss_1_disp_cc_sleep_clk.clkr,
|
|
[DISP_CC_SLEEP_CLK_SRC] = &mdss_1_disp_cc_sleep_clk_src.clkr,
|
|
[DISP_CC_XO_CLK_SRC] = &mdss_1_disp_cc_xo_clk_src.clkr,
|
|
};
|
|
|
|
static const struct qcom_reset_map disp_cc_1_lemans_resets[] = {
|
|
[DISP_CC_MDSS_CORE_BCR] = { 0x8000 },
|
|
[DISP_CC_MDSS_RSCC_BCR] = { 0xa000 },
|
|
};
|
|
|
|
static const struct regmap_config disp_cc_1_lemans_regmap_config = {
|
|
.reg_bits = 32,
|
|
.reg_stride = 4,
|
|
.val_bits = 32,
|
|
.max_register = 0x12414,
|
|
.fast_io = true,
|
|
};
|
|
|
|
static struct qcom_cc_desc disp_cc_1_lemans_desc = {
|
|
.config = &disp_cc_1_lemans_regmap_config,
|
|
.clks = disp_cc_1_lemans_clocks,
|
|
.num_clks = ARRAY_SIZE(disp_cc_1_lemans_clocks),
|
|
.resets = disp_cc_1_lemans_resets,
|
|
.num_resets = ARRAY_SIZE(disp_cc_1_lemans_resets),
|
|
.clk_regulators = disp_cc_1_lemans_regulators,
|
|
.num_clk_regulators = ARRAY_SIZE(disp_cc_1_lemans_regulators),
|
|
.critical_clk_en = critical_clk_list,
|
|
.num_critical_clk = ARRAY_SIZE(critical_clk_list),
|
|
};
|
|
|
|
static const struct of_device_id disp_cc_1_lemans_match_table[] = {
|
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{ .compatible = "qcom,lemans-dispcc1" },
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{ }
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};
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MODULE_DEVICE_TABLE(of, disp_cc_1_lemans_match_table);
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static int disp_cc_1_lemans_probe(struct platform_device *pdev)
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{
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struct regmap *regmap;
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int ret;
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regmap = qcom_cc_map(pdev, &disp_cc_1_lemans_desc);
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if (IS_ERR(regmap))
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return PTR_ERR(regmap);
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ret = register_qcom_clks_pm(pdev, true, &disp_cc_1_lemans_desc);
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if (ret)
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dev_err(&pdev->dev, "Failed register disp_cc_1_pm_rt_ops clocks\n");
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clk_lucid_evo_pll_configure(&mdss_1_disp_cc_pll0, regmap, mdss_1_disp_cc_pll0.config);
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clk_lucid_evo_pll_configure(&mdss_1_disp_cc_pll1, regmap, mdss_1_disp_cc_pll1.config);
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/* Enabling always ON clocks */
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clk_restore_critical_clocks(&pdev->dev);
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ret = qcom_cc_really_probe(pdev, &disp_cc_1_lemans_desc, regmap);
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if (ret) {
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dev_err(&pdev->dev, "Failed to register DISP CC 1 clocks\n");
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return ret;
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}
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pm_runtime_put_sync(&pdev->dev);
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dev_info(&pdev->dev, "Registered DISP CC 1 clocks\n");
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return ret;
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}
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static void disp_cc_1_lemans_sync_state(struct device *dev)
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{
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qcom_cc_sync_state(dev, &disp_cc_1_lemans_desc);
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}
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static struct platform_driver disp_cc_1_lemans_driver = {
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.probe = disp_cc_1_lemans_probe,
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.driver = {
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.name = "disp_cc_1-lemans",
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.of_match_table = disp_cc_1_lemans_match_table,
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.sync_state = disp_cc_1_lemans_sync_state,
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},
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};
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static int __init disp_cc_1_lemans_init(void)
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{
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return platform_driver_register(&disp_cc_1_lemans_driver);
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}
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subsys_initcall(disp_cc_1_lemans_init);
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static void __exit disp_cc_1_lemans_exit(void)
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{
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platform_driver_unregister(&disp_cc_1_lemans_driver);
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}
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module_exit(disp_cc_1_lemans_exit);
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MODULE_DESCRIPTION("QTI DISP_CC_1 LEMANS Driver");
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MODULE_LICENSE("GPL v2");
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