419 lines
10 KiB
C
419 lines
10 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
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* Copyright (c) 2022, 2024, Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/err.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/of.h>
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#include <linux/regmap.h>
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#include <dt-bindings/clock/qcom,gpucc-scuba.h>
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#include "clk-alpha-pll.h"
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#include "clk-branch.h"
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#include "clk-rcg.h"
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#include "clk-regmap.h"
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#include "common.h"
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#include "reset.h"
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#include "vdd-level-scuba.h"
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static DEFINE_VDD_REGULATORS(vdd_cx, VDD_HIGH_L1 + 1, 1, vdd_corner);
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static struct clk_vdd_class *gpu_cc_scuba_regulators[] = {
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&vdd_cx,
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};
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enum {
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P_BI_TCXO,
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P_GPLL0_OUT_MAIN,
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P_GPLL0_OUT_MAIN_DIV,
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P_GPU_CC_PLL0_2X_DIV_CLK_SRC,
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P_GPU_CC_PLL0_OUT_AUX,
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P_GPU_CC_PLL0_OUT_AUX2,
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P_GPU_CC_PLL0_OUT_MAIN,
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};
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static const struct pll_vco huayra_vco[] = {
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{ 600000000, 3300000000, 0 },
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{ 600000000, 2200000000, 1 },
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};
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static const u8 clk_alpha_pll_regs_offset[][PLL_OFF_MAX_REGS] = {
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[CLK_ALPHA_PLL_TYPE_HUAYRA] = {
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[PLL_OFF_L_VAL] = 0x04,
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[PLL_OFF_ALPHA_VAL] = 0x08,
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[PLL_OFF_USER_CTL] = 0x0c,
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[PLL_OFF_CONFIG_CTL] = 0x10,
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[PLL_OFF_CONFIG_CTL_U] = 0x14,
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[PLL_OFF_CONFIG_CTL_U1] = 0x18,
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[PLL_OFF_TEST_CTL] = 0x1c,
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[PLL_OFF_TEST_CTL_U] = 0x20,
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[PLL_OFF_TEST_CTL_U1] = 0x24,
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[PLL_OFF_OPMODE] = 0x28,
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[PLL_OFF_STATUS] = 0x38,
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},
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};
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/* 710.4 MHz Configuration */
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static const struct alpha_pll_config gpu_cc_pll0_config = {
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.l = 0x25,
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.config_ctl_val = 0x200D4828,
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.config_ctl_hi_val = 0x6,
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.test_ctl_val = 0x1C000000,
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.test_ctl_hi_val = 0x00004000,
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.user_ctl_val = 0xF,
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};
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static struct clk_alpha_pll gpu_cc_pll0 = {
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.offset = 0x0,
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.vco_table = huayra_vco,
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.num_vco = ARRAY_SIZE(huayra_vco),
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.regs = clk_alpha_pll_regs_offset[CLK_ALPHA_PLL_TYPE_HUAYRA],
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.clkr = {
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.hw.init = &(const struct clk_init_data){
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.name = "gpu_cc_pll0",
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.parent_data = &(const struct clk_parent_data){
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.fw_name = "bi_tcxo",
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},
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.num_parents = 1,
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.ops = &clk_alpha_pll_huayra_ops,
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},
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.vdd_data = {
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.vdd_class = &vdd_cx,
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.num_rate_max = VDD_NUM,
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.rate_max = (unsigned long[VDD_NUM]) {
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[VDD_MIN] = 1200000000,
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[VDD_LOWER] = 2400000000,
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[VDD_LOW] = 3000000000,
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[VDD_NOMINAL] = 3300000000},
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},
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},
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};
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static const struct parent_map gpu_cc_parent_map_0[] = {
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{ P_BI_TCXO, 0 },
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{ P_GPU_CC_PLL0_OUT_MAIN, 1 },
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{ P_GPLL0_OUT_MAIN, 5 },
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{ P_GPLL0_OUT_MAIN_DIV, 6 },
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};
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static const struct clk_parent_data gpu_cc_parent_data_0[] = {
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{ .fw_name = "bi_tcxo" },
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{ .hw = &gpu_cc_pll0.clkr.hw },
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{ .fw_name = "gpll0_out_main" },
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{ .fw_name = "gpll0_out_main_div" },
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};
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static const struct parent_map gpu_cc_parent_map_1[] = {
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{ P_BI_TCXO, 0 },
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{ P_GPU_CC_PLL0_2X_DIV_CLK_SRC, 1 },
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{ P_GPU_CC_PLL0_OUT_AUX2, 2 },
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{ P_GPU_CC_PLL0_OUT_AUX, 3 },
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{ P_GPLL0_OUT_MAIN, 5 },
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};
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static const struct clk_parent_data gpu_cc_parent_data_1[] = {
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{ .fw_name = "bi_tcxo" },
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{ .hw = &gpu_cc_pll0.clkr.hw },
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{ .hw = &gpu_cc_pll0.clkr.hw },
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{ .hw = &gpu_cc_pll0.clkr.hw },
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{ .fw_name = "gpll0_out_main" },
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};
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static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = {
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F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
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{ }
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};
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static struct clk_rcg2 gpu_cc_gmu_clk_src = {
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.cmd_rcgr = 0x1120,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = gpu_cc_parent_map_0,
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.freq_tbl = ftbl_gpu_cc_gmu_clk_src,
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.clkr.hw.init = &(const struct clk_init_data){
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.name = "gpu_cc_gmu_clk_src",
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.parent_data = gpu_cc_parent_data_0,
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.num_parents = ARRAY_SIZE(gpu_cc_parent_data_0),
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.ops = &clk_rcg2_ops,
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},
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.clkr.vdd_data = {
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.vdd_class = &vdd_cx,
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.num_rate_max = VDD_NUM,
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.rate_max = (unsigned long[VDD_NUM]) {
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[VDD_LOWER] = 200000000},
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},
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};
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static const struct freq_tbl ftbl_gpu_cc_gx_gfx3d_clk_src[] = {
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F(355200000, P_GPU_CC_PLL0_OUT_AUX, 2, 0, 0),
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F(537600000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0),
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F(672000000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0),
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F(844800000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0),
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F(921600000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0),
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F(1017600000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0),
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F(1123200000, P_GPU_CC_PLL0_OUT_AUX2, 2, 0, 0),
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{ }
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};
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static struct clk_rcg2 gpu_cc_gx_gfx3d_clk_src = {
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.cmd_rcgr = 0x101c,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = gpu_cc_parent_map_1,
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.freq_tbl = ftbl_gpu_cc_gx_gfx3d_clk_src,
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.clkr.hw.init = &(const struct clk_init_data){
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.name = "gpu_cc_gx_gfx3d_clk_src",
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.parent_data = gpu_cc_parent_data_1,
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.num_parents = ARRAY_SIZE(gpu_cc_parent_data_1),
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.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
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.ops = &clk_rcg2_ops,
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},
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.clkr.vdd_data = {
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.vdd_class = &vdd_cx,
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.num_rate_max = VDD_NUM,
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.rate_max = (unsigned long[VDD_NUM]) {
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[VDD_LOWER] = 355200000,
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[VDD_LOW] = 537600000,
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[VDD_LOW_L1] = 672000000,
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[VDD_NOMINAL] = 844800000,
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[VDD_NOMINAL_L1] = 921600000,
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[VDD_HIGH] = 1017600000,
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[VDD_HIGH_L1] = 1123200000},
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},
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};
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static struct clk_branch gpu_cc_crc_ahb_clk = {
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.halt_reg = 0x107c,
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.halt_check = BRANCH_HALT_DELAY,
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.clkr = {
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.enable_reg = 0x107c,
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data){
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.name = "gpu_cc_crc_ahb_clk",
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch gpu_cc_cx_gfx3d_clk = {
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.halt_reg = 0x10a4,
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.halt_check = BRANCH_HALT_DELAY,
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.clkr = {
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.enable_reg = 0x10a4,
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data){
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.name = "gpu_cc_cx_gfx3d_clk",
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.parent_hws = (const struct clk_hw*[]){
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&gpu_cc_gx_gfx3d_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch gpu_cc_cx_gmu_clk = {
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.halt_reg = 0x1098,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x1098,
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data){
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.name = "gpu_cc_cx_gmu_clk",
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.parent_hws = (const struct clk_hw*[]){
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&gpu_cc_gmu_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch gpu_cc_cx_snoc_dvm_clk = {
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.halt_reg = 0x108c,
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.halt_check = BRANCH_HALT_DELAY,
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.clkr = {
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.enable_reg = 0x108c,
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data){
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.name = "gpu_cc_cx_snoc_dvm_clk",
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch gpu_cc_cxo_aon_clk = {
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.halt_reg = 0x1004,
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.halt_check = BRANCH_HALT_DELAY,
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.clkr = {
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.enable_reg = 0x1004,
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data){
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.name = "gpu_cc_cxo_aon_clk",
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch gpu_cc_cxo_clk = {
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.halt_reg = 0x109c,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x109c,
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data){
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.name = "gpu_cc_cxo_clk",
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.flags = CLK_DONT_HOLD_STATE,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch gpu_cc_gx_gfx3d_clk = {
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.halt_reg = 0x1054,
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.halt_check = BRANCH_HALT_DELAY,
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.clkr = {
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.enable_reg = 0x1054,
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data){
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.name = "gpu_cc_gx_gfx3d_clk",
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.parent_hws = (const struct clk_hw*[]){
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&gpu_cc_gx_gfx3d_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk = {
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.halt_reg = 0x5000,
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.halt_check = BRANCH_VOTED,
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.clkr = {
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.enable_reg = 0x5000,
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.enable_mask = BIT(0),
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.hw.init = &(struct clk_init_data){
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.name = "gpu_cc_hlos1_vote_gpu_smmu_clk",
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch gpu_cc_sleep_clk = {
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.halt_reg = 0x1090,
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.halt_check = BRANCH_VOTED,
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.clkr = {
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.enable_reg = 0x1090,
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data){
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.name = "gpu_cc_sleep_clk",
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_regmap *gpu_cc_scuba_clocks[] = {
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[GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr,
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[GPU_CC_CX_GFX3D_CLK] = &gpu_cc_cx_gfx3d_clk.clkr,
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[GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr,
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[GPU_CC_CX_SNOC_DVM_CLK] = &gpu_cc_cx_snoc_dvm_clk.clkr,
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[GPU_CC_CXO_AON_CLK] = &gpu_cc_cxo_aon_clk.clkr,
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[GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr,
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[GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr,
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[GPU_CC_GX_GFX3D_CLK] = &gpu_cc_gx_gfx3d_clk.clkr,
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[GPU_CC_GX_GFX3D_CLK_SRC] = &gpu_cc_gx_gfx3d_clk_src.clkr,
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[GPU_CC_PLL0] = &gpu_cc_pll0.clkr,
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[GPU_CC_SLEEP_CLK] = &gpu_cc_sleep_clk.clkr,
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[GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK] = &gpu_cc_hlos1_vote_gpu_smmu_clk.clkr,
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};
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static const struct regmap_config gpu_cc_scuba_regmap_config = {
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.reg_bits = 32,
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.reg_stride = 4,
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.val_bits = 32,
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.max_register = 0x7008,
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.fast_io = true,
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};
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static const struct qcom_cc_desc gpu_cc_scuba_desc = {
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.config = &gpu_cc_scuba_regmap_config,
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.clks = gpu_cc_scuba_clocks,
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.num_clks = ARRAY_SIZE(gpu_cc_scuba_clocks),
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.clk_regulators = gpu_cc_scuba_regulators,
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.num_clk_regulators = ARRAY_SIZE(gpu_cc_scuba_regulators),
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};
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static const struct of_device_id gpu_cc_scuba_match_table[] = {
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{ .compatible = "qcom,scuba-gpucc" },
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{ }
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};
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MODULE_DEVICE_TABLE(of, gpu_cc_scuba_match_table);
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static int gpu_cc_scuba_probe(struct platform_device *pdev)
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{
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struct regmap *regmap;
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int ret;
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regmap = qcom_cc_map(pdev, &gpu_cc_scuba_desc);
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if (IS_ERR(regmap))
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return PTR_ERR(regmap);
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/*
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* Keep the clocks always-ON
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* GPU_CC_GX_CXO_CLK, GPU_CC_AHB_CLK
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*/
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regmap_update_bits(regmap, 0x1060, BIT(0), BIT(0));
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regmap_update_bits(regmap, 0x1078, BIT(0), BIT(0));
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clk_huayra_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config);
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ret = qcom_cc_really_probe(pdev, &gpu_cc_scuba_desc, regmap);
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if (ret) {
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dev_err(&pdev->dev, "Failed to register GPU CC clocks\n");
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return ret;
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}
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dev_info(&pdev->dev, "Registered GPU CC clocks\n");
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return ret;
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}
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static void gpu_cc_scuba_sync_state(struct device *dev)
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{
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qcom_cc_sync_state(dev, &gpu_cc_scuba_desc);
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}
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static struct platform_driver gpu_cc_scuba_driver = {
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.probe = gpu_cc_scuba_probe,
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.driver = {
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.name = "gpu_cc-scuba",
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.of_match_table = gpu_cc_scuba_match_table,
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.sync_state = gpu_cc_scuba_sync_state,
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},
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};
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static int __init gpu_cc_scuba_init(void)
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{
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return platform_driver_register(&gpu_cc_scuba_driver);
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}
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subsys_initcall(gpu_cc_scuba_init);
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static void __exit gpu_cc_scuba_exit(void)
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{
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platform_driver_unregister(&gpu_cc_scuba_driver);
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}
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module_exit(gpu_cc_scuba_exit);
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MODULE_DESCRIPTION("QTI GPU_CC SCUBA Driver");
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MODULE_LICENSE("GPL v2");
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