570 lines
15 KiB
C
570 lines
15 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2021, 2023, Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/err.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/of.h>
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#include <linux/regmap.h>
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#include <linux/pm_runtime.h>
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#include <dt-bindings/clock/qcom,videocc-lemans.h>
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#include "clk-alpha-pll.h"
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#include "clk-branch.h"
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#include "clk-pm.h"
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#include "clk-rcg.h"
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#include "clk-regmap.h"
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#include "clk-regmap-divider.h"
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#include "common.h"
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#include "reset.h"
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#include "vdd-level-sm8150.h"
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static DEFINE_VDD_REGULATORS(vdd_mm, VDD_HIGH_L1 + 1, 1, vdd_corner);
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static DEFINE_VDD_REGULATORS(vdd_mx, VDD_HIGH_L1 + 1, 1, vdd_corner);
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static struct clk_vdd_class *video_cc_lemans_regulators[] = {
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&vdd_mm,
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&vdd_mx,
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};
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enum {
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P_BI_TCXO,
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P_SLEEP_CLK,
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P_VIDEO_PLL0_OUT_MAIN,
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P_VIDEO_PLL1_OUT_MAIN,
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};
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static const struct pll_vco lucid_evo_vco[] = {
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{ 249600000, 2020000000, 0 },
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};
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/* 1098MHz configuration */
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static struct alpha_pll_config video_pll0_config = {
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.l = 0x39,
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.cal_l = 0x44,
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.alpha = 0x3000,
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.config_ctl_val = 0x20485699,
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.config_ctl_hi_val = 0x00182261,
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.config_ctl_hi1_val = 0x32AA299C,
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.user_ctl_val = 0x00000001,
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.user_ctl_hi_val = 0x00400805,
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};
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static struct clk_alpha_pll video_pll0 = {
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.offset = 0x0,
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.vco_table = lucid_evo_vco,
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.num_vco = ARRAY_SIZE(lucid_evo_vco),
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
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.config = &video_pll0_config,
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.clkr = {
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.hw.init = &(const struct clk_init_data){
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.name = "video_pll0",
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.parent_data = &(const struct clk_parent_data){
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.fw_name = "bi_tcxo",
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},
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.num_parents = 1,
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.ops = &clk_alpha_pll_lucid_evo_ops,
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},
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.vdd_data = {
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.vdd_class = &vdd_mx,
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.num_rate_max = VDD_NUM,
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.rate_max = (unsigned long[VDD_NUM]) {
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[VDD_LOWER_D1] = 500000000,
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[VDD_LOWER] = 615000000,
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[VDD_LOW] = 1066000000,
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[VDD_LOW_L1] = 1500000000,
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[VDD_NOMINAL] = 1800000000,
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[VDD_HIGH] = 2020000000},
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},
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},
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};
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/* 1098MHz configuration */
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static struct alpha_pll_config video_pll1_config = {
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.l = 0x39,
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.cal_l = 0x44,
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.alpha = 0x3000,
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.config_ctl_val = 0x20485699,
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.config_ctl_hi_val = 0x00182261,
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.config_ctl_hi1_val = 0x32AA299C,
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.user_ctl_val = 0x00000001,
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.user_ctl_hi_val = 0x00400805,
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};
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static struct clk_alpha_pll video_pll1 = {
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.offset = 0x1000,
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.vco_table = lucid_evo_vco,
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.num_vco = ARRAY_SIZE(lucid_evo_vco),
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
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.config = &video_pll1_config,
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.clkr = {
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.hw.init = &(const struct clk_init_data){
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.name = "video_pll1",
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.parent_data = &(const struct clk_parent_data){
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.fw_name = "bi_tcxo",
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},
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.num_parents = 1,
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.ops = &clk_alpha_pll_lucid_evo_ops,
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},
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.vdd_data = {
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.vdd_class = &vdd_mx,
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.num_rate_max = VDD_NUM,
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.rate_max = (unsigned long[VDD_NUM]) {
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[VDD_LOWER_D1] = 500000000,
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[VDD_LOWER] = 615000000,
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[VDD_LOW] = 1066000000,
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[VDD_LOW_L1] = 1500000000,
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[VDD_NOMINAL] = 1800000000,
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[VDD_HIGH] = 2020000000},
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},
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},
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};
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static const struct parent_map video_cc_parent_map_0[] = {
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{ P_BI_TCXO, 0 },
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};
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static const struct clk_parent_data video_cc_parent_data_0_ao[] = {
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{ .fw_name = "bi_tcxo_ao" },
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};
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static const struct parent_map video_cc_parent_map_1[] = {
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{ P_BI_TCXO, 0 },
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{ P_VIDEO_PLL0_OUT_MAIN, 1 },
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};
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static const struct clk_parent_data video_cc_parent_data_1[] = {
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{ .fw_name = "bi_tcxo" },
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{ .hw = &video_pll0.clkr.hw },
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};
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static const struct parent_map video_cc_parent_map_2[] = {
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{ P_BI_TCXO, 0 },
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{ P_VIDEO_PLL1_OUT_MAIN, 1 },
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};
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static const struct clk_parent_data video_cc_parent_data_2[] = {
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{ .fw_name = "bi_tcxo" },
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{ .hw = &video_pll1.clkr.hw },
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};
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static const struct parent_map video_cc_parent_map_3[] = {
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{ P_SLEEP_CLK, 0 },
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};
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static const struct clk_parent_data video_cc_parent_data_3[] = {
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{ .fw_name = "sleep_clk" },
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};
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static const struct freq_tbl ftbl_video_cc_ahb_clk_src[] = {
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F(19200000, P_BI_TCXO, 1, 0, 0),
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{ }
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};
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static struct clk_rcg2 video_cc_ahb_clk_src = {
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.cmd_rcgr = 0x8030,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = video_cc_parent_map_0,
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.freq_tbl = ftbl_video_cc_ahb_clk_src,
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.enable_safe_config = true,
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.clkr.hw.init = &(const struct clk_init_data){
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.name = "video_cc_ahb_clk_src",
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.parent_data = video_cc_parent_data_0_ao,
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.num_parents = ARRAY_SIZE(video_cc_parent_data_0_ao),
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.ops = &clk_rcg2_ops,
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},
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};
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static const struct freq_tbl ftbl_video_cc_mvs0_clk_src[] = {
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F(1098000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
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F(1332000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
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F(1599000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
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F(1680000000, P_VIDEO_PLL0_OUT_MAIN, 1, 0, 0),
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{ }
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};
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static struct clk_rcg2 video_cc_mvs0_clk_src = {
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.cmd_rcgr = 0x8000,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = video_cc_parent_map_1,
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.freq_tbl = ftbl_video_cc_mvs0_clk_src,
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.enable_safe_config = true,
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.clkr.hw.init = &(const struct clk_init_data){
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.name = "video_cc_mvs0_clk_src",
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.parent_data = video_cc_parent_data_1,
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.num_parents = ARRAY_SIZE(video_cc_parent_data_1),
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_rcg2_ops,
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},
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.clkr.vdd_data = {
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.vdd_classes = video_cc_lemans_regulators,
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.num_vdd_classes = ARRAY_SIZE(video_cc_lemans_regulators),
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.num_rate_max = VDD_NUM,
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.rate_max = (unsigned long[VDD_NUM]) {
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[VDD_LOW_L1] = 1098000000,
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[VDD_NOMINAL] = 1332000000,
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[VDD_HIGH] = 1599000000,
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[VDD_HIGH_L1] = 1680000000},
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},
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};
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static const struct freq_tbl ftbl_video_cc_mvs1_clk_src[] = {
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F(1098000000, P_VIDEO_PLL1_OUT_MAIN, 1, 0, 0),
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F(1332000000, P_VIDEO_PLL1_OUT_MAIN, 1, 0, 0),
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F(1600000000, P_VIDEO_PLL1_OUT_MAIN, 1, 0, 0),
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F(1800000000, P_VIDEO_PLL1_OUT_MAIN, 1, 0, 0),
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{ }
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};
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static struct clk_rcg2 video_cc_mvs1_clk_src = {
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.cmd_rcgr = 0x8018,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = video_cc_parent_map_2,
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.freq_tbl = ftbl_video_cc_mvs1_clk_src,
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.enable_safe_config = true,
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.clkr.hw.init = &(const struct clk_init_data){
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.name = "video_cc_mvs1_clk_src",
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.parent_data = video_cc_parent_data_2,
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.num_parents = ARRAY_SIZE(video_cc_parent_data_2),
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_rcg2_ops,
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},
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.clkr.vdd_data = {
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.vdd_classes = video_cc_lemans_regulators,
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.num_vdd_classes = ARRAY_SIZE(video_cc_lemans_regulators),
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.num_rate_max = VDD_NUM,
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.rate_max = (unsigned long[VDD_NUM]) {
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[VDD_LOW_L1] = 1098000000,
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[VDD_NOMINAL] = 1332000000,
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[VDD_HIGH] = 1600000000,
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[VDD_HIGH_L1] = 1800000000},
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},
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};
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static const struct freq_tbl ftbl_video_cc_sleep_clk_src[] = {
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F(32000, P_SLEEP_CLK, 1, 0, 0),
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{ }
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};
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static struct clk_rcg2 video_cc_sleep_clk_src = {
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.cmd_rcgr = 0x812c,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = video_cc_parent_map_3,
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.freq_tbl = ftbl_video_cc_sleep_clk_src,
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.clkr.hw.init = &(const struct clk_init_data){
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.name = "video_cc_sleep_clk_src",
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.parent_data = video_cc_parent_data_3,
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.num_parents = ARRAY_SIZE(video_cc_parent_data_3),
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.ops = &clk_rcg2_ops,
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},
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.clkr.vdd_data = {
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.vdd_class = &vdd_mm,
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.num_rate_max = VDD_NUM,
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.rate_max = (unsigned long[VDD_NUM]) {
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[VDD_LOW_L1] = 32000},
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},
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};
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static struct clk_rcg2 video_cc_xo_clk_src = {
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.cmd_rcgr = 0x8110,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = video_cc_parent_map_0,
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.freq_tbl = ftbl_video_cc_ahb_clk_src,
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.enable_safe_config = true,
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.clkr.hw.init = &(const struct clk_init_data){
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.name = "video_cc_xo_clk_src",
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.parent_data = video_cc_parent_data_0_ao,
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.num_parents = ARRAY_SIZE(video_cc_parent_data_0_ao),
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.ops = &clk_rcg2_ops,
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},
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};
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static struct clk_regmap_div video_cc_mvs0_div_clk_src = {
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.reg = 0x80b8,
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.shift = 0,
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.width = 4,
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.clkr.hw.init = &(const struct clk_init_data) {
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.name = "video_cc_mvs0_div_clk_src",
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.parent_hws = (const struct clk_hw*[]){
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&video_cc_mvs0_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_regmap_div_ro_ops,
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},
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};
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static struct clk_regmap_div video_cc_mvs0c_div2_div_clk_src = {
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.reg = 0x806c,
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.shift = 0,
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.width = 4,
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.clkr.hw.init = &(const struct clk_init_data) {
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.name = "video_cc_mvs0c_div2_div_clk_src",
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.parent_hws = (const struct clk_hw*[]){
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&video_cc_mvs0_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_regmap_div_ro_ops,
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},
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};
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static struct clk_regmap_div video_cc_mvs1_div_clk_src = {
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.reg = 0x80dc,
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.shift = 0,
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.width = 4,
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.clkr.hw.init = &(const struct clk_init_data) {
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.name = "video_cc_mvs1_div_clk_src",
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.parent_hws = (const struct clk_hw*[]){
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&video_cc_mvs1_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_regmap_div_ro_ops,
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},
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};
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static struct clk_regmap_div video_cc_mvs1c_div2_div_clk_src = {
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.reg = 0x8094,
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.shift = 0,
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.width = 4,
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.clkr.hw.init = &(const struct clk_init_data) {
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.name = "video_cc_mvs1c_div2_div_clk_src",
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.parent_hws = (const struct clk_hw*[]){
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&video_cc_mvs1_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_regmap_div_ro_ops,
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},
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};
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static struct clk_branch video_cc_mvs0_clk = {
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.halt_reg = 0x80b0,
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.halt_check = BRANCH_HALT_VOTED,
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.hwcg_reg = 0x80b0,
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.hwcg_bit = 1,
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.clkr = {
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.enable_reg = 0x80b0,
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data){
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.name = "video_cc_mvs0_clk",
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.parent_hws = (const struct clk_hw*[]){
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&video_cc_mvs0_div_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch video_cc_mvs0c_clk = {
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.halt_reg = 0x8064,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x8064,
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data){
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.name = "video_cc_mvs0c_clk",
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.parent_hws = (const struct clk_hw*[]){
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&video_cc_mvs0c_div2_div_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch video_cc_mvs1_clk = {
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.halt_reg = 0x80d4,
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.halt_check = BRANCH_HALT_VOTED,
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.hwcg_reg = 0x80d4,
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.hwcg_bit = 1,
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.clkr = {
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.enable_reg = 0x80d4,
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data){
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.name = "video_cc_mvs1_clk",
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.parent_hws = (const struct clk_hw*[]){
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&video_cc_mvs1_div_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch video_cc_mvs1c_clk = {
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.halt_reg = 0x808c,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x808c,
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data){
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.name = "video_cc_mvs1c_clk",
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.parent_hws = (const struct clk_hw*[]){
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&video_cc_mvs1c_div2_div_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch video_cc_sleep_clk = {
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.halt_reg = 0x8144,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x8144,
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data){
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.name = "video_cc_sleep_clk",
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.parent_hws = (const struct clk_hw*[]){
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&video_cc_sleep_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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/*
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* Keep clocks always enabled:
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* video_cc_ahb_clk
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* video_cc_xo_clk
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*/
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static struct critical_clk_offset critical_clk_list[] = {
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{ .offset = 0x80ec, .mask = BIT(0) },
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{ .offset = 0x8128, .mask = BIT(0) },
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|
};
|
|
|
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static struct clk_regmap *video_cc_lemans_clocks[] = {
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[VIDEO_CC_AHB_CLK_SRC] = &video_cc_ahb_clk_src.clkr,
|
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[VIDEO_CC_MVS0_CLK] = &video_cc_mvs0_clk.clkr,
|
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[VIDEO_CC_MVS0_CLK_SRC] = &video_cc_mvs0_clk_src.clkr,
|
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[VIDEO_CC_MVS0_DIV_CLK_SRC] = &video_cc_mvs0_div_clk_src.clkr,
|
|
[VIDEO_CC_MVS0C_CLK] = &video_cc_mvs0c_clk.clkr,
|
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[VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC] = &video_cc_mvs0c_div2_div_clk_src.clkr,
|
|
[VIDEO_CC_MVS1_CLK] = &video_cc_mvs1_clk.clkr,
|
|
[VIDEO_CC_MVS1_CLK_SRC] = &video_cc_mvs1_clk_src.clkr,
|
|
[VIDEO_CC_MVS1_DIV_CLK_SRC] = &video_cc_mvs1_div_clk_src.clkr,
|
|
[VIDEO_CC_MVS1C_CLK] = &video_cc_mvs1c_clk.clkr,
|
|
[VIDEO_CC_MVS1C_DIV2_DIV_CLK_SRC] = &video_cc_mvs1c_div2_div_clk_src.clkr,
|
|
[VIDEO_CC_SLEEP_CLK] = &video_cc_sleep_clk.clkr,
|
|
[VIDEO_CC_SLEEP_CLK_SRC] = &video_cc_sleep_clk_src.clkr,
|
|
[VIDEO_CC_XO_CLK_SRC] = &video_cc_xo_clk_src.clkr,
|
|
[VIDEO_PLL0] = &video_pll0.clkr,
|
|
[VIDEO_PLL1] = &video_pll1.clkr,
|
|
};
|
|
|
|
static const struct qcom_reset_map video_cc_lemans_resets[] = {
|
|
[CVP_VIDEO_CC_INTERFACE_BCR] = { 0x80e8 },
|
|
[CVP_VIDEO_CC_MVS0_BCR] = { 0x8098 },
|
|
[VIDEO_CC_MVS0C_CLK_ARES] = { 0x8064, 2 },
|
|
[CVP_VIDEO_CC_MVS0C_BCR] = { 0x8048 },
|
|
[CVP_VIDEO_CC_MVS1_BCR] = { 0x80bc },
|
|
[VIDEO_CC_MVS1C_CLK_ARES] = { 0x808c, 2 },
|
|
[CVP_VIDEO_CC_MVS1C_BCR] = { 0x8070 },
|
|
};
|
|
|
|
static const struct regmap_config video_cc_lemans_regmap_config = {
|
|
.reg_bits = 32,
|
|
.reg_stride = 4,
|
|
.val_bits = 32,
|
|
.max_register = 0xb000,
|
|
.fast_io = true,
|
|
};
|
|
|
|
static struct qcom_cc_desc video_cc_lemans_desc = {
|
|
.config = &video_cc_lemans_regmap_config,
|
|
.clks = video_cc_lemans_clocks,
|
|
.num_clks = ARRAY_SIZE(video_cc_lemans_clocks),
|
|
.resets = video_cc_lemans_resets,
|
|
.num_resets = ARRAY_SIZE(video_cc_lemans_resets),
|
|
.clk_regulators = video_cc_lemans_regulators,
|
|
.num_clk_regulators = ARRAY_SIZE(video_cc_lemans_regulators),
|
|
.critical_clk_en = critical_clk_list,
|
|
.num_critical_clk = ARRAY_SIZE(critical_clk_list),
|
|
};
|
|
|
|
static const struct of_device_id video_cc_lemans_match_table[] = {
|
|
{ .compatible = "qcom,lemans-videocc" },
|
|
{ }
|
|
};
|
|
MODULE_DEVICE_TABLE(of, video_cc_lemans_match_table);
|
|
|
|
static int video_cc_lemans_probe(struct platform_device *pdev)
|
|
{
|
|
struct regmap *regmap;
|
|
int ret;
|
|
|
|
regmap = qcom_cc_map(pdev, &video_cc_lemans_desc);
|
|
if (IS_ERR(regmap))
|
|
return PTR_ERR(regmap);
|
|
|
|
ret = register_qcom_clks_pm(pdev, true, &video_cc_lemans_desc);
|
|
if (ret)
|
|
dev_err(&pdev->dev, "Failed register video_cc_pm_rt_ops clocks\n");
|
|
|
|
clk_lucid_evo_pll_configure(&video_pll0, regmap, video_pll0.config);
|
|
clk_lucid_evo_pll_configure(&video_pll1, regmap, video_pll1.config);
|
|
|
|
/* Enabling always ON clocks */
|
|
clk_restore_critical_clocks(&pdev->dev);
|
|
|
|
ret = qcom_cc_really_probe(pdev, &video_cc_lemans_desc, regmap);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "Failed to register VIDEO CC clocks\n");
|
|
return ret;
|
|
}
|
|
|
|
pm_runtime_put_sync(&pdev->dev);
|
|
dev_info(&pdev->dev, "Registered VIDEO CC clocks\n");
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void video_cc_lemans_sync_state(struct device *dev)
|
|
{
|
|
qcom_cc_sync_state(dev, &video_cc_lemans_desc);
|
|
}
|
|
|
|
static struct platform_driver video_cc_lemans_driver = {
|
|
.probe = video_cc_lemans_probe,
|
|
.driver = {
|
|
.name = "video_cc-lemans",
|
|
.of_match_table = video_cc_lemans_match_table,
|
|
.sync_state = video_cc_lemans_sync_state,
|
|
},
|
|
};
|
|
|
|
static int __init video_cc_lemans_init(void)
|
|
{
|
|
return platform_driver_register(&video_cc_lemans_driver);
|
|
}
|
|
subsys_initcall(video_cc_lemans_init);
|
|
|
|
static void __exit video_cc_lemans_exit(void)
|
|
{
|
|
platform_driver_unregister(&video_cc_lemans_driver);
|
|
}
|
|
module_exit(video_cc_lemans_exit);
|
|
|
|
MODULE_DESCRIPTION("QTI VIDEO_CC LEMANS Driver");
|
|
MODULE_LICENSE("GPL v2");
|