538 lines
18 KiB
C
538 lines
18 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2019-2021, The Linux Foundation. All rights reserved.
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* Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#include <linux/kernel.h>
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#include <linux/io.h>
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#include <linux/device.h>
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#include "arm-smmu.h"
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#include "arm-smmu-debug.h"
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#include <linux/qcom_scm.h>
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u32 arm_smmu_debug_qtb_debugchain_load(void __iomem *debugchain_base)
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{
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u32 shiftreglen = 0;
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/* Reading the debugchain_load register will start the debugchain sequence */
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readl_relaxed(debugchain_base + DebugChainQTB_debug_Load);
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shiftreglen = readl_relaxed(debugchain_base + DebugChainQTB_debug_ShiftRegLen);
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return (((shiftreglen * 2)/64 + ((shiftreglen * 2)%64 == 0 ? 0 : 1) + 1));
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}
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u64 arm_smmu_debug_qtb_debugchain_dump(void __iomem *debugchain_base)
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{
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u64 dump;
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dump = readl_relaxed(debugchain_base + DebugChainQTB_debug_Dump_Low);
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dump = (dump | (readl_relaxed(debugchain_base + DebugChainQTB_debug_Dump_High) << 31));
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return dump;
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}
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void arm_smmu_debug_qtb_transtracker_set_config(void __iomem *transactiontracker_base, u64 sel)
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{
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u64 val = 0;
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if (sel) {
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val |= TTQTB_GlbEn | TTQTB_IgnoreCtiTrigIn0 | TTQTB_LogAsstEn;
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writel_relaxed(val, transactiontracker_base + TransTrackerQTB_MainCtl);
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writel_relaxed(TTQTB_RESET_VAL, transactiontracker_base + TransTrackerQTB_LogClr);
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} else {
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/*By default All transactions through QTB are captured*/
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val |= TTQTB_GlbEn | TTQTB_IgnoreCtiTrigIn0 | TTQTB_LogAll;
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writel_relaxed(val, transactiontracker_base + TransTrackerQTB_MainCtl);
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writel_relaxed(TTQTB_RESET_VAL, transactiontracker_base + TransTrackerQTB_LogClr);
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}
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}
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u64 arm_smmu_debug_qtb_transtracker_get_config(void __iomem *transactiontracker_base)
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{
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return readl_relaxed(transactiontracker_base + TransTrackerQTB_MainCtl);
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}
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void arm_smmu_debug_qtb_transtracker_setfilter(void __iomem *transactiontracker_base,
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u64 sel, u64 filter, int qtb_type)
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{
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u64 val = 0;
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val = TTQTB_RESET_VAL | TTQTB_Filter_DevNeEn | TTQTB_Filter_DevEEn;
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if (sel == 1) {
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if (filter == 2)
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val |= TTQTB_Filter_NormalEn;
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else if (filter == 3)
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val |= TTQTB_Filter_CachedEn;
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else if (filter == 4)
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val |= TTQTB_Filter_SharedEn;
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else if (filter == 5)
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val |= TTQTB_Filter_PostedEn;
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writel_relaxed(val, transactiontracker_base + TransTrackerQTB_Filter_TrType);
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} else if (sel == 2) {
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if (qtb_type == 1)
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writeq_relaxed(filter, transactiontracker_base +
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TransTrackerQTB_gfx_Filter_Addr_Min);
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else if (qtb_type == 2)
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writeq_relaxed(filter, transactiontracker_base +
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TransTrackerQTB_Filter_Addr_Min_Low);
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} else if (sel == 3) {
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if (qtb_type == 1)
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writel_relaxed(filter, transactiontracker_base +
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TransTrackerQTB_gfx_Filter_Addr_Max);
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else if (qtb_type == 2)
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writeq_relaxed(filter, transactiontracker_base +
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TransTrackerQTB_Filter_Addr_Max_Low);
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}
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writel_relaxed(TTQTB_Filter_OpCode_Set_Val, transactiontracker_base +
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TransTrackerQTB_Filter_OpCode);
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writel_relaxed(TTQTB_Filter_Alloc_Set_Val, transactiontracker_base +
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TransTrackerQTB_Filter_Alloc);
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writel_relaxed(TTQTB_Filter_Length_Set_Val, transactiontracker_base +
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TransTrackerQTB_Filter_Length);
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}
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void arm_smmu_debug_qtb_transtracker_getfilter(void __iomem *transactiontracker_base,
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u64 filter[3], int qtb_type)
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{
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int i = 0;
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if (qtb_type == 1) {
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filter[i] = readl_relaxed(transactiontracker_base + TransTrackerQTB_Filter_TrType);
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filter[i+1] = readq_relaxed(transactiontracker_base +
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TransTrackerQTB_gfx_Filter_Addr_Min);
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filter[i+2] = readq_relaxed(transactiontracker_base +
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TransTrackerQTB_gfx_Filter_Addr_Max);
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} else if (qtb_type == 2) {
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filter[i] = readl_relaxed(transactiontracker_base + TransTrackerQTB_Filter_TrType);
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filter[i+1] = (readl_relaxed(transactiontracker_base +
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TransTrackerQTB_Filter_Addr_Min_Low) |
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readl_relaxed(transactiontracker_base +
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TransTrackerQTB_Filter_Addr_Min_High));
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filter[i+2] = (readl_relaxed(transactiontracker_base +
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TransTrackerQTB_Filter_Addr_Max_Low) |
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readl_relaxed(transactiontracker_base +
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TransTrackerQTB_Filter_Addr_Max_High));
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}
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}
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void arm_smmu_debug_qtb_transtrac_collect(void __iomem *transactiontracker_base,
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u64 gfxttlogs[TTQTB_Capture_Points][2*TTQTB_Regs_Per_Capture_Points],
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u64 ttlogs[TTQTB_Capture_Points][4*TTQTB_Regs_Per_Capture_Points],
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u64 ttlogs_time[2*TTQTB_Capture_Points], int qtb_type)
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{
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int i, j, x, y;
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for (i = 0, x = 0; i < TTQTB_Capture_Points && x < 2*TTQTB_Capture_Points; ++i, x += 2) {
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ttlogs_time[x] = readl_relaxed(transactiontracker_base +
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TransTrackerQTB_Latency(i));
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ttlogs_time[x+1] = readl_relaxed(transactiontracker_base +
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TransTrackerQTB_TimeStamp(i));
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if (qtb_type == 1) {
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for (j = 0, y = 0; j < TTQTB_Regs_Per_Capture_Points &&
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y < 2*TTQTB_Regs_Per_Capture_Points; ++j, y += 2) {
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gfxttlogs[i][y] = readl_relaxed(transactiontracker_base +
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TransTrackerQTB_LogIn_Low(i, j)) |
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readl_relaxed(transactiontracker_base +
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TransTrackerQTB_LogIn_High(i, j));
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gfxttlogs[i][y+1] = readl_relaxed(transactiontracker_base +
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TransTrackerQTB_LogOut_Low(i, j)) |
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readl_relaxed(transactiontracker_base +
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TransTrackerQTB_LogOut_High(i, j));
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}
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} else if (qtb_type == 2) {
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for (j = 0, y = 0; j < TTQTB_Regs_Per_Capture_Points &&
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y < 4*TTQTB_Regs_Per_Capture_Points; ++j, y += 4) {
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ttlogs[i][y] = readl_relaxed(transactiontracker_base +
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TransTrackerQTB_LogIn_Low(i, j));
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ttlogs[i][y+1] = readl_relaxed(transactiontracker_base +
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TransTrackerQTB_LogIn_High(i, j));
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ttlogs[i][y+2] = readl_relaxed(transactiontracker_base +
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TransTrackerQTB_LogOut_Low(i, j));
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ttlogs[i][y+3] = readl_relaxed(transactiontracker_base +
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TransTrackerQTB_LogOut_High(i, j));
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}
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}
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}
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}
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void arm_smmu_debug_qtb_transtrac_reset(void __iomem *transactiontracker_base)
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{
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/* reset the transaction tracker once called after each read */
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writel_relaxed(TTQTB_RESET_VAL, transactiontracker_base + TransTrackerQTB_MainCtl);
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writel_relaxed(TTQTB_SET, transactiontracker_base + TransTrackerQTB_LogClr);
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writel_relaxed(TTQTB_RESET_VAL, transactiontracker_base +
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TransTrackerQTB_Filter_TrType);
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writeq_relaxed(TTQTB_RESET_VAL, transactiontracker_base +
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TransTrackerQTB_gfx_Filter_Addr_Min);
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writeq_relaxed(TTQTB_RESET_VAL, transactiontracker_base +
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TransTrackerQTB_gfx_Filter_Addr_Max);
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writel_relaxed(TTQTB_RESET_VAL, transactiontracker_base +
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TransTrackerQTB_Filter_OpCode);
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writel_relaxed(TTQTB_RESET_VAL, transactiontracker_base +
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TransTrackerQTB_Filter_ReqUser_Base);
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writel_relaxed(TTQTB_RESET_VAL, transactiontracker_base +
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TransTrackerQTB_Filter_ReqUser_Mask);
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writel_relaxed(TTQTB_RESET_VAL, transactiontracker_base +
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TransTrackerQTB_Filter_LogUser_Base);
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writel_relaxed(TTQTB_RESET_VAL, transactiontracker_base +
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TransTrackerQTB_Filter_LogUser_Mask);
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writel_relaxed(TTQTB_RESET_VAL, transactiontracker_base +
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TransTrackerQTB_Filter_Alloc);
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writel_relaxed(TTQTB_RESET_VAL, transactiontracker_base +
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TransTrackerQTB_Filter_ExtId_Base);
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writel_relaxed(TTQTB_RESET_VAL, transactiontracker_base +
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TransTrackerQTB_Filter_ExtId_Mask);
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writel_relaxed(TTQTB_RESET_VAL, transactiontracker_base +
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TransTrackerQTB_Filter_Length);
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writel_relaxed(TTQTB_RESET_VAL, transactiontracker_base +
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TransTrackerQTB_Filter_Urgency);
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writel_relaxed(TTQTB_RESET_VAL, transactiontracker_base +
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TransTrackerQTB_Filter_CacheIndex_Base);
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writel_relaxed(TTQTB_RESET_VAL, transactiontracker_base +
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TransTrackerQTB_Filter_CacheIndex_Mask);
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}
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void arm_smmu_debug_dump_debugchain(struct device *dev, void __iomem *debugchain_base)
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{
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long chain_length = 0, index = 0;
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u64 val;
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if (debugchain_base == NULL) {
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dev_dbg(dev, "Debugchain base not implemented\n");
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return;
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}
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chain_length = arm_smmu_debug_qtb_debugchain_load(debugchain_base);
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dev_info(dev, "Dumping Debug chain: Length : %d\n", chain_length);
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/* First read is to dump away the 0xDEADBEEF value */
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arm_smmu_debug_qtb_debugchain_dump(debugchain_base);
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do {
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val = arm_smmu_debug_qtb_debugchain_dump(debugchain_base);
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dev_info(dev, "Debug chain: Index :%ld, val : 0x%lx\n", index++, val);
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} while (chain_length--);
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}
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void arm_smmu_debug_dump_qtb_regs(struct device *dev, void __iomem *tbu_base)
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{
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dev_info(dev, "QSMSTATUS: 0x%lx IDLESTATUS: 0x%lx\n",
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readl_relaxed(tbu_base + Qtb500_QtbNsDbgQsmStatus),
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readl_relaxed(tbu_base + Qtb500_QtbNsDbgIdleStatus));
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}
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u32 arm_smmu_debug_tbu_testbus_select(void __iomem *tbu_base,
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bool write, u32 val)
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{
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if (write) {
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writel_relaxed(val, tbu_base + DEBUG_TESTBUS_SEL_TBU);
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/* Make sure tbu select register is written to */
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wmb();
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} else {
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return readl_relaxed(tbu_base + DEBUG_TESTBUS_SEL_TBU);
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}
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return 0;
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}
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u32 arm_smmu_debug_tbu_testbus_output(void __iomem *tbu_base)
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{
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return readl_relaxed(tbu_base + DEBUG_TESTBUS_TBU);
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}
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u32 arm_smmu_debug_tcu_testbus_select(phys_addr_t phys_addr,
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void __iomem *tcu_base, enum tcu_testbus testbus,
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bool write, u32 val)
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{
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int offset;
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u32 testbus_sel;
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int ret = 0;
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if (testbus == CLK_TESTBUS) {
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if (write) {
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offset = ARM_SMMU_TESTBUS_SEL_HLOS1_NS;
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writel_relaxed(val, tcu_base + offset);
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/* Make sure tcu select register is written to */
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wmb();
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} else {
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offset = ARM_SMMU_TCU_TESTBUS_HLOS1_NS;
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return readl_relaxed(tcu_base + offset);
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}
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} else {
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offset = ARM_SMMU_TESTBUS_SEL;
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if (write) {
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ret = qcom_scm_io_writel((phys_addr + offset), val);
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if (ret)
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pr_err_ratelimited("SCM write of TESTBUS SEL fails: %d\n",
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ret);
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/* Make sure tcu select register is written to */
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wmb();
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} else {
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ret = qcom_scm_io_readl(phys_addr + offset,
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&testbus_sel);
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if (ret)
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pr_err_ratelimited("SCM write of TESTBUS SEL fails: %d\n",
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ret);
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else
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return testbus_sel;
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}
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}
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return 0;
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}
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u32 arm_smmu_debug_tcu_testbus_output(phys_addr_t phys_addr)
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{
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u32 testbus_output;
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int ret;
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ret = qcom_scm_io_readl(phys_addr + ARM_SMMU_TESTBUS, &testbus_output);
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if (!ret)
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return testbus_output;
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pr_err_ratelimited("SCM write of TESTBUS output fails: %d\n", ret);
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return 0;
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}
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static void arm_smmu_debug_dump_tbu_qns4_testbus(struct device *dev,
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void __iomem *tbu_base)
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{
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int i;
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u32 reg;
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for (i = 0 ; i < TBU_QNS4_BRIDGE_SIZE; ++i) {
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reg = arm_smmu_debug_tbu_testbus_select(tbu_base, READ, 0);
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reg = (reg & ~TBU_QNS4_BRIDGE_MASK) | i << 0;
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arm_smmu_debug_tbu_testbus_select(tbu_base, WRITE, reg);
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dev_info(dev, "testbus_sel: 0x%lx Index: %d val: 0x%llx\n",
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arm_smmu_debug_tbu_testbus_select(tbu_base,
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READ, 0), i,
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arm_smmu_debug_tbu_testbus_output(tbu_base));
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}
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}
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static void arm_smmu_debug_program_tbu_testbus(void __iomem *tbu_base,
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int tbu_testbus)
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{
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u32 reg;
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reg = arm_smmu_debug_tbu_testbus_select(tbu_base, READ, 0);
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reg = (reg & ~TBU_MASK) | tbu_testbus;
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arm_smmu_debug_tbu_testbus_select(tbu_base, WRITE, reg);
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}
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void arm_smmu_debug_dump_tbu_testbus(struct device *dev, void __iomem *tbu_base,
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int tbu_testbus_sel)
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{
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if (tbu_testbus_sel & TBU_CLK_GATE_CONTROLLER_TESTBUS_SEL) {
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dev_info(dev, "Dumping TBU clk gate controller:\n");
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arm_smmu_debug_program_tbu_testbus(tbu_base,
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TBU_CLK_GATE_CONTROLLER_TESTBUS);
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dev_info(dev, "testbus_sel: 0x%lx val: 0x%llx\n",
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arm_smmu_debug_tbu_testbus_select(tbu_base,
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READ, 0),
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arm_smmu_debug_tbu_testbus_output(tbu_base));
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}
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if (tbu_testbus_sel & TBU_QNS4_A2Q_TESTBUS_SEL) {
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dev_info(dev, "Dumping TBU qns4 a2q test bus:\n");
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arm_smmu_debug_program_tbu_testbus(tbu_base,
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TBU_QNS4_A2Q_TESTBUS);
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arm_smmu_debug_dump_tbu_qns4_testbus(dev, tbu_base);
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}
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if (tbu_testbus_sel & TBU_QNS4_Q2A_TESTBUS_SEL) {
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dev_info(dev, "Dumping qns4 q2a test bus:\n");
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arm_smmu_debug_program_tbu_testbus(tbu_base,
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TBU_QNS4_Q2A_TESTBUS);
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arm_smmu_debug_dump_tbu_qns4_testbus(dev, tbu_base);
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}
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if (tbu_testbus_sel & TBU_MULTIMASTER_QCHANNEL_TESTBUS_SEL) {
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dev_info(dev, "Dumping multi master qchannel:\n");
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arm_smmu_debug_program_tbu_testbus(tbu_base,
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TBU_MULTIMASTER_QCHANNEL_TESTBUS);
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dev_info(dev, "testbus_sel: 0x%lx val: 0x%llx\n",
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arm_smmu_debug_tbu_testbus_select(tbu_base,
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READ, 0),
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arm_smmu_debug_tbu_testbus_output(tbu_base));
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}
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if (tbu_testbus_sel & TBU_CLK_GATE_CONTROLLER_EXT_TESTBUS_SEL) {
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dev_info(dev, "Dumping tbu clk gate controller ext:\n");
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arm_smmu_debug_program_tbu_testbus(tbu_base,
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TBU_CLK_GATE_CONTROLLER_EXT_TESTBUS);
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dev_info(dev, "testbus_sel: 0x%lx val: 0x%llx\n",
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arm_smmu_debug_tbu_testbus_select(tbu_base,
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READ, 0),
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arm_smmu_debug_tbu_testbus_output(tbu_base));
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}
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if (tbu_testbus_sel & TBU_LOW_POWER_STATUS_TESTBUS_SEL) {
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dev_info(dev, "Dumping tbu low power status:\n");
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arm_smmu_debug_program_tbu_testbus(tbu_base,
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TBU_LOW_POWER_STATUS_TESTBUS);
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dev_info(dev, "testbus_sel: 0x%lx val: 0x%llx\n",
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arm_smmu_debug_tbu_testbus_select(tbu_base,
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READ, 0),
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arm_smmu_debug_tbu_testbus_output(tbu_base));
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}
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if (tbu_testbus_sel & TBU_QNS4_VLD_RDY_SEL) {
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dev_info(dev, "Dumping tbu qns4 vld rdy:\n");
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arm_smmu_debug_program_tbu_testbus(tbu_base,
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TBU_QNS4_VLD_RDY);
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dev_info(dev, "testbus_sel: 0x%lx val: 0x%llx\n",
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arm_smmu_debug_tbu_testbus_select(tbu_base,
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READ, 0),
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arm_smmu_debug_tbu_testbus_output(tbu_base));
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}
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}
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static void arm_smmu_debug_program_tcu_testbus(struct device *dev,
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phys_addr_t phys_addr, void __iomem *tcu_base,
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unsigned long mask, int start, int end, int shift,
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bool print)
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{
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u32 reg;
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int i;
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for (i = start; i < end; i++) {
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reg = arm_smmu_debug_tcu_testbus_select(phys_addr, tcu_base,
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PTW_AND_CACHE_TESTBUS, READ, 0);
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reg &= mask;
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reg |= i << shift;
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arm_smmu_debug_tcu_testbus_select(phys_addr, tcu_base,
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PTW_AND_CACHE_TESTBUS, WRITE, reg);
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|
if (print)
|
|
dev_info(dev, "testbus_sel: 0x%lx Index: %d val: 0x%lx\n",
|
|
arm_smmu_debug_tcu_testbus_select(phys_addr,
|
|
tcu_base, PTW_AND_CACHE_TESTBUS, READ, 0), i,
|
|
arm_smmu_debug_tcu_testbus_output(phys_addr));
|
|
}
|
|
}
|
|
|
|
void arm_smmu_debug_dump_tcu_testbus(struct device *dev, phys_addr_t phys_addr,
|
|
void __iomem *tcu_base, int tcu_testbus_sel)
|
|
{
|
|
int i;
|
|
|
|
if (tcu_testbus_sel & TCU_CACHE_TESTBUS_SEL) {
|
|
dev_info(dev, "Dumping TCU cache testbus:\n");
|
|
arm_smmu_debug_program_tcu_testbus(dev, phys_addr, tcu_base,
|
|
TCU_CACHE_TESTBUS, 0, 1, 0, false);
|
|
arm_smmu_debug_program_tcu_testbus(dev, phys_addr, tcu_base,
|
|
~TCU_PTW_QUEUE_MASK, 0,
|
|
TCU_CACHE_LOOKUP_QUEUE_SIZE,
|
|
2, true);
|
|
}
|
|
|
|
if (tcu_testbus_sel & TCU_PTW_TESTBUS_SEL) {
|
|
dev_info(dev, "Dumping TCU PTW test bus:\n");
|
|
arm_smmu_debug_program_tcu_testbus(dev, phys_addr, tcu_base, 1,
|
|
TCU_PTW_TESTBUS, TCU_PTW_TESTBUS + 1, 0, false);
|
|
|
|
arm_smmu_debug_program_tcu_testbus(dev, phys_addr, tcu_base,
|
|
~TCU_PTW_INTERNAL_STATES_MASK,
|
|
0, TCU_PTW_INTERNAL_STATES,
|
|
2, true);
|
|
|
|
for (i = TCU_PTW_QUEUE_START;
|
|
i < TCU_PTW_QUEUE_START + TCU_PTW_QUEUE_SIZE; ++i) {
|
|
arm_smmu_debug_program_tcu_testbus(dev, phys_addr,
|
|
tcu_base,
|
|
~TCU_PTW_QUEUE_MASK,
|
|
i, i + 1, 2, true);
|
|
arm_smmu_debug_program_tcu_testbus(dev, phys_addr,
|
|
tcu_base,
|
|
~TCU_PTW_TESTBUS_SEL2_MASK,
|
|
TCU_PTW_TESTBUS_SEL2,
|
|
TCU_PTW_TESTBUS_SEL2 + 1, 0,
|
|
false);
|
|
dev_info(dev, "testbus_sel: 0x%lx Index: %d val: 0x%lx\n",
|
|
arm_smmu_debug_tcu_testbus_select(phys_addr,
|
|
tcu_base, PTW_AND_CACHE_TESTBUS, READ, 0), i,
|
|
arm_smmu_debug_tcu_testbus_output(phys_addr));
|
|
}
|
|
}
|
|
|
|
if (tcu_testbus_sel & TCU_CD_TESTBUS_SEL) {
|
|
dev_info(dev, "Dumping TCU CD testbus:\n");
|
|
arm_smmu_debug_program_tcu_testbus(dev, phys_addr, tcu_base,
|
|
TCU_CD_TESTBUS, 0, 1, 0, false);
|
|
arm_smmu_debug_program_tcu_testbus(dev, phys_addr, tcu_base,
|
|
~TCU_PTW_QUEUE_MASK, 1,
|
|
2, TCU_CD_TESTBUS_SHIFT, true);
|
|
}
|
|
|
|
/* program ARM_SMMU_TESTBUS_SEL_HLOS1_NS to select TCU clk testbus*/
|
|
arm_smmu_debug_tcu_testbus_select(phys_addr, tcu_base,
|
|
CLK_TESTBUS, WRITE, TCU_CLK_TESTBUS_SEL);
|
|
dev_info(dev, "Programming Tcu clk gate controller: testbus_sel: 0x%lx\n",
|
|
arm_smmu_debug_tcu_testbus_select(phys_addr, tcu_base,
|
|
CLK_TESTBUS, READ, 0));
|
|
}
|
|
|
|
void arm_smmu_debug_set_tnx_tcr_cntl(void __iomem *tbu_base, u64 val)
|
|
{
|
|
u64 tcr_cntl_val = readq_relaxed(tbu_base + TNX_TCR_CNTL);
|
|
|
|
/* Don't override OT_CAPTURE configuration*/
|
|
if (!(tcr_cntl_val & TNX_TCR_CNTL_TBU_OT_CAPTURE_EN))
|
|
writeq_relaxed(val, tbu_base + TNX_TCR_CNTL);
|
|
else
|
|
pr_err_ratelimited("OT capture enbl, skip TCR CNTL write\n");
|
|
}
|
|
|
|
u64 arm_smmu_debug_get_tnx_tcr_cntl(void __iomem *tbu_base)
|
|
{
|
|
return readq_relaxed(tbu_base + TNX_TCR_CNTL);
|
|
}
|
|
|
|
void arm_smmu_debug_set_mask_and_match(void __iomem *tbu_base, u64 sel,
|
|
u64 mask, u64 match)
|
|
{
|
|
writeq_relaxed(mask, tbu_base + ARM_SMMU_CAPTURE1_MASK(sel));
|
|
writeq_relaxed(match, tbu_base + ARM_SMMU_CAPTURE1_MATCH(sel));
|
|
}
|
|
|
|
void arm_smmu_debug_get_mask_and_match(void __iomem *tbu_base, u64 *mask,
|
|
u64 *match)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < NO_OF_MASK_AND_MATCH; ++i) {
|
|
mask[i] = readq_relaxed(tbu_base +
|
|
ARM_SMMU_CAPTURE1_MASK(i+1));
|
|
match[i] = readq_relaxed(tbu_base +
|
|
ARM_SMMU_CAPTURE1_MATCH(i+1));
|
|
}
|
|
}
|
|
|
|
void arm_smmu_debug_get_capture_snapshot(void __iomem *tbu_base,
|
|
u64 snapshot[NO_OF_CAPTURE_POINTS][REGS_PER_CAPTURE_POINT])
|
|
{
|
|
int i, j;
|
|
u64 valid;
|
|
|
|
valid = readl_relaxed(tbu_base + TNX_TCR_CNTL_2);
|
|
|
|
for (i = 0; i < NO_OF_CAPTURE_POINTS ; ++i) {
|
|
if (valid & BIT(i))
|
|
for (j = 0; j < REGS_PER_CAPTURE_POINT; ++j)
|
|
snapshot[i][j] = readq_relaxed(tbu_base +
|
|
ARM_SMMU_CAPTURE_SNAPSHOT(i, j));
|
|
else
|
|
for (j = 0; j < REGS_PER_CAPTURE_POINT; ++j)
|
|
snapshot[i][j] = 0xdededede;
|
|
}
|
|
}
|
|
|
|
void arm_smmu_debug_clear_intr_and_validbits(void __iomem *tbu_base)
|
|
{
|
|
u64 val = 0;
|
|
|
|
val |= INTR_CLR | RESET_VALID;
|
|
writeq_relaxed(val, tbu_base + TNX_TCR_CNTL);
|
|
}
|