Rtwo/kernel/motorola/sm8550/include/dt-bindings/interconnect/qcom,crow.h
2025-09-30 19:22:48 -05:00

138 lines
4.2 KiB
C

/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_CROW_H
#define __DT_BINDINGS_INTERCONNECT_QCOM_CROW_H
#define MASTER_GPU_TCU 0
#define MASTER_SYS_TCU 1
#define MASTER_APPSS_PROC 2
#define MASTER_LLCC 3
#define MASTER_CNOC_LPASS_AG_NOC 4
#define MASTER_GIC_AHB 5
#define MASTER_CDSP_NOC_CFG 6
#define MASTER_QDSS_BAM 7
#define MASTER_QSPI_0 8
#define MASTER_QUP_0 9
#define MASTER_QUP_1 10
#define MASTER_A1NOC_SNOC 11
#define MASTER_A2NOC_SNOC 12
#define MASTER_CAMNOC_HF 13
#define MASTER_CAMNOC_ICP 14
#define MASTER_CAMNOC_SF 15
#define MASTER_CNOC_A2NOC 16
#define MASTER_GEM_NOC_CNOC 17
#define MASTER_GEM_NOC_PCIE_SNOC 18
#define MASTER_GFX3D 19
#define MASTER_LPASS_GEM_NOC 20
#define MASTER_MDP 21
#define MASTER_MSS_PROC 22
#define MASTER_MNOC_HF_MEM_NOC 23
#define MASTER_MNOC_SF_MEM_NOC 24
#define MASTER_COMPUTE_NOC 25
#define MASTER_ANOC_PCIE_GEM_NOC 26
#define MASTER_SNOC_GC_MEM_NOC 27
#define MASTER_SNOC_SF_MEM_NOC 28
#define MASTER_VIDEO 29
#define MASTER_VIDEO_PROC 30
#define MASTER_CNOC_CFG 31
#define MASTER_CNOC_MNOC_CFG 32
#define MASTER_PCIE_ANOC_CFG 33
#define MASTER_QUP_CORE_0 34
#define MASTER_QUP_CORE_1 35
#define MASTER_CRYPTO 36
#define MASTER_IPA 37
#define MASTER_LPASS_PROC 38
#define MASTER_CDSP_PROC 39
#define MASTER_WLAN_Q6 40
#define MASTER_GIC 41
#define MASTER_PCIE_0 42
#define MASTER_QDSS_ETR 43
#define MASTER_QDSS_ETR_1 44
#define MASTER_SDCC_1 45
#define MASTER_SDCC_2 46
#define MASTER_UFS_MEM 47
#define MASTER_USB3_0 48
#define SLAVE_EBI1 512
#define SLAVE_AHB2PHY_SOUTH 513
#define SLAVE_AHB2PHY_NORTH 514
#define SLAVE_AOSS 515
#define SLAVE_APPSS 516
#define SLAVE_CAMERA_CFG 517
#define SLAVE_CLK_CTL 518
#define SLAVE_CDSP_CFG 519
#define SLAVE_RBCPR_CX_CFG 520
#define SLAVE_RBCPR_MXA_CFG 521
#define SLAVE_RBCPR_MXC_CFG 522
#define SLAVE_CRYPTO_0_CFG 523
#define SLAVE_CX_RDPM 524
#define SLAVE_DISPLAY_CFG 525
#define SLAVE_GFX3D_CFG 526
#define SLAVE_IMEM_CFG 527
#define SLAVE_IPA_CFG 528
#define SLAVE_IPC_ROUTER_CFG 529
#define SLAVE_LPASS 530
#define SLAVE_LPASS_CORE_CFG 531
#define SLAVE_LPASS_LPI_CFG 532
#define SLAVE_LPASS_MPU_CFG 533
#define SLAVE_LPASS_TOP_CFG 534
#define SLAVE_CNOC_MSS 535
#define SLAVE_MX_RDPM 536
#define SLAVE_PCIE_0_CFG 537
#define SLAVE_PDM 538
#define SLAVE_PRNG 539
#define SLAVE_QDSS_CFG 540
#define SLAVE_QSPI_0 541
#define SLAVE_QUP_0 542
#define SLAVE_QUP_1 543
#define SLAVE_SDC1 544
#define SLAVE_SDCC_2 545
#define SLAVE_TCSR 546
#define SLAVE_TLMM 547
#define SLAVE_TME_CFG 548
#define SLAVE_UFS_MEM_CFG 549
#define SLAVE_USB3_0 550
#define SLAVE_VENUS_CFG 551
#define SLAVE_VSENSE_CTRL_CFG 552
#define SLAVE_A1NOC_SNOC 553
#define SLAVE_A2NOC_SNOC 554
#define SLAVE_GEM_NOC_CNOC 555
#define SLAVE_SNOC_GEM_NOC_GC 556
#define SLAVE_SNOC_GEM_NOC_SF 557
#define SLAVE_LLCC 558
#define SLAVE_MNOC_HF_MEM_NOC 559
#define SLAVE_MNOC_SF_MEM_NOC 560
#define SLAVE_CDSP_MEM_NOC 561
#define SLAVE_MEM_NOC_PCIE_SNOC 562
#define SLAVE_ANOC_PCIE_GEM_NOC 563
#define SLAVE_LPASS_ANOC 564
#define SLAVE_CNOC_CFG 565
#define SLAVE_DDRSS_CFG 566
#define SLAVE_LPASS_QTB_CFG 567
#define SLAVE_CNOC_MNOC_CFG 568
#define SLAVE_NSP_QTB_CFG 569
#define SLAVE_PCIE_ANOC_CFG 570
#define SLAVE_QUP_CORE_0 571
#define SLAVE_QUP_CORE_1 572
#define SLAVE_BOOT_IMEM 573
#define SLAVE_BOOT_IMEM_2 574
#define SLAVE_IMEM 575
#define SLAVE_SERVICE_NSP_NOC 576
#define SLAVE_SERVICE_MNOC 577
#define SLAVE_SERVICES_LPASS_AML_NOC 578
#define SLAVE_SERVICE_LPASS_AG_NOC 579
#define SLAVE_SERVICE_PCIE_ANOC 580
#define SLAVE_PCIE_0 581
#define SLAVE_QDSS_STM 582
#define SLAVE_TCU 583
#define MASTER_LLCC_DISP 1000
#define MASTER_MDP_DISP 1001
#define MASTER_MNOC_HF_MEM_NOC_DISP 1002
#define MASTER_ANOC_PCIE_GEM_NOC_DISP 1003
#define SLAVE_EBI1_DISP 1512
#define SLAVE_LLCC_DISP 1513
#define SLAVE_MNOC_HF_MEM_NOC_DISP 1514
#endif