138 lines
4.2 KiB
C
138 lines
4.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_CROW_H
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#define __DT_BINDINGS_INTERCONNECT_QCOM_CROW_H
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#define MASTER_GPU_TCU 0
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#define MASTER_SYS_TCU 1
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#define MASTER_APPSS_PROC 2
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#define MASTER_LLCC 3
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#define MASTER_CNOC_LPASS_AG_NOC 4
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#define MASTER_GIC_AHB 5
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#define MASTER_CDSP_NOC_CFG 6
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#define MASTER_QDSS_BAM 7
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#define MASTER_QSPI_0 8
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#define MASTER_QUP_0 9
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#define MASTER_QUP_1 10
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#define MASTER_A1NOC_SNOC 11
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#define MASTER_A2NOC_SNOC 12
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#define MASTER_CAMNOC_HF 13
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#define MASTER_CAMNOC_ICP 14
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#define MASTER_CAMNOC_SF 15
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#define MASTER_CNOC_A2NOC 16
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#define MASTER_GEM_NOC_CNOC 17
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#define MASTER_GEM_NOC_PCIE_SNOC 18
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#define MASTER_GFX3D 19
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#define MASTER_LPASS_GEM_NOC 20
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#define MASTER_MDP 21
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#define MASTER_MSS_PROC 22
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#define MASTER_MNOC_HF_MEM_NOC 23
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#define MASTER_MNOC_SF_MEM_NOC 24
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#define MASTER_COMPUTE_NOC 25
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#define MASTER_ANOC_PCIE_GEM_NOC 26
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#define MASTER_SNOC_GC_MEM_NOC 27
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#define MASTER_SNOC_SF_MEM_NOC 28
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#define MASTER_VIDEO 29
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#define MASTER_VIDEO_PROC 30
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#define MASTER_CNOC_CFG 31
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#define MASTER_CNOC_MNOC_CFG 32
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#define MASTER_PCIE_ANOC_CFG 33
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#define MASTER_QUP_CORE_0 34
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#define MASTER_QUP_CORE_1 35
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#define MASTER_CRYPTO 36
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#define MASTER_IPA 37
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#define MASTER_LPASS_PROC 38
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#define MASTER_CDSP_PROC 39
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#define MASTER_WLAN_Q6 40
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#define MASTER_GIC 41
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#define MASTER_PCIE_0 42
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#define MASTER_QDSS_ETR 43
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#define MASTER_QDSS_ETR_1 44
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#define MASTER_SDCC_1 45
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#define MASTER_SDCC_2 46
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#define MASTER_UFS_MEM 47
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#define MASTER_USB3_0 48
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#define SLAVE_EBI1 512
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#define SLAVE_AHB2PHY_SOUTH 513
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#define SLAVE_AHB2PHY_NORTH 514
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#define SLAVE_AOSS 515
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#define SLAVE_APPSS 516
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#define SLAVE_CAMERA_CFG 517
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#define SLAVE_CLK_CTL 518
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#define SLAVE_CDSP_CFG 519
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#define SLAVE_RBCPR_CX_CFG 520
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#define SLAVE_RBCPR_MXA_CFG 521
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#define SLAVE_RBCPR_MXC_CFG 522
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#define SLAVE_CRYPTO_0_CFG 523
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#define SLAVE_CX_RDPM 524
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#define SLAVE_DISPLAY_CFG 525
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#define SLAVE_GFX3D_CFG 526
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#define SLAVE_IMEM_CFG 527
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#define SLAVE_IPA_CFG 528
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#define SLAVE_IPC_ROUTER_CFG 529
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#define SLAVE_LPASS 530
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#define SLAVE_LPASS_CORE_CFG 531
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#define SLAVE_LPASS_LPI_CFG 532
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#define SLAVE_LPASS_MPU_CFG 533
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#define SLAVE_LPASS_TOP_CFG 534
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#define SLAVE_CNOC_MSS 535
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#define SLAVE_MX_RDPM 536
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#define SLAVE_PCIE_0_CFG 537
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#define SLAVE_PDM 538
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#define SLAVE_PRNG 539
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#define SLAVE_QDSS_CFG 540
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#define SLAVE_QSPI_0 541
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#define SLAVE_QUP_0 542
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#define SLAVE_QUP_1 543
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#define SLAVE_SDC1 544
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#define SLAVE_SDCC_2 545
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#define SLAVE_TCSR 546
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#define SLAVE_TLMM 547
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#define SLAVE_TME_CFG 548
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#define SLAVE_UFS_MEM_CFG 549
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#define SLAVE_USB3_0 550
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#define SLAVE_VENUS_CFG 551
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#define SLAVE_VSENSE_CTRL_CFG 552
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#define SLAVE_A1NOC_SNOC 553
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#define SLAVE_A2NOC_SNOC 554
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#define SLAVE_GEM_NOC_CNOC 555
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#define SLAVE_SNOC_GEM_NOC_GC 556
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#define SLAVE_SNOC_GEM_NOC_SF 557
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#define SLAVE_LLCC 558
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#define SLAVE_MNOC_HF_MEM_NOC 559
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#define SLAVE_MNOC_SF_MEM_NOC 560
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#define SLAVE_CDSP_MEM_NOC 561
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#define SLAVE_MEM_NOC_PCIE_SNOC 562
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#define SLAVE_ANOC_PCIE_GEM_NOC 563
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#define SLAVE_LPASS_ANOC 564
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#define SLAVE_CNOC_CFG 565
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#define SLAVE_DDRSS_CFG 566
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#define SLAVE_LPASS_QTB_CFG 567
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#define SLAVE_CNOC_MNOC_CFG 568
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#define SLAVE_NSP_QTB_CFG 569
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#define SLAVE_PCIE_ANOC_CFG 570
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#define SLAVE_QUP_CORE_0 571
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#define SLAVE_QUP_CORE_1 572
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#define SLAVE_BOOT_IMEM 573
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#define SLAVE_BOOT_IMEM_2 574
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#define SLAVE_IMEM 575
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#define SLAVE_SERVICE_NSP_NOC 576
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#define SLAVE_SERVICE_MNOC 577
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#define SLAVE_SERVICES_LPASS_AML_NOC 578
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#define SLAVE_SERVICE_LPASS_AG_NOC 579
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#define SLAVE_SERVICE_PCIE_ANOC 580
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#define SLAVE_PCIE_0 581
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#define SLAVE_QDSS_STM 582
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#define SLAVE_TCU 583
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#define MASTER_LLCC_DISP 1000
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#define MASTER_MDP_DISP 1001
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#define MASTER_MNOC_HF_MEM_NOC_DISP 1002
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#define MASTER_ANOC_PCIE_GEM_NOC_DISP 1003
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#define SLAVE_EBI1_DISP 1512
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#define SLAVE_LLCC_DISP 1513
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#define SLAVE_MNOC_HF_MEM_NOC_DISP 1514
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#endif
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