177 lines
5.3 KiB
C
177 lines
5.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_KONA_H
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#define __DT_BINDINGS_INTERCONNECT_QCOM_KONA_H
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#define MASTER_GPU_TCU 0
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#define MASTER_SYS_TCU 1
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#define MASTER_APPSS_PROC 2
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#define MASTER_LLCC 3
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#define MASTER_QDSS_BAM 4
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#define MASTER_QSPI_0 5
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#define MASTER_QUP_0 6
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#define MASTER_QUP_1 7
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#define MASTER_QUP_2 8
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#define MASTER_A1NOC_CFG 9
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#define MASTER_A2NOC_CFG 10
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#define MASTER_A1NOC_SNOC 11
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#define MASTER_A2NOC_SNOC 12
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#define MASTER_CAMNOC_HF 13
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#define MASTER_CAMNOC_ICP 14
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#define MASTER_CAMNOC_SF 15
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#define MASTER_COMPUTE_NOC 16
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#define MASTER_CNOC_DC_NOC 17
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#define MASTER_GEM_NOC_CFG 18
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#define MASTER_GEM_NOC_PCIE_SNOC 19
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#define MASTER_GFX3D 20
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#define MASTER_CNOC_MNOC_CFG 21
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#define MASTER_MNOC_HF_MEM_NOC 22
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#define MASTER_MNOC_SF_MEM_NOC 23
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#define MASTER_ANOC_PCIE_GEM_NOC 24
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#define MASTER_SNOC_CFG 25
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#define MASTER_SNOC_GC_MEM_NOC 26
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#define MASTER_SNOC_SF_MEM_NOC 27
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#define MASTER_VIDEO_P0 28
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#define MASTER_VIDEO_P1 29
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#define MASTER_VIDEO_PROC 30
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#define MASTER_CRYPTO 31
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#define MASTER_IPA 32
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#define MASTER_MDP0 33
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#define MASTER_MDP1 34
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#define MASTER_PIMEM 35
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#define MASTER_ROTATOR 36
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#define MASTER_GIC 37
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#define MASTER_PCIE_0 38
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#define MASTER_PCIE_1 39
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#define MASTER_QDSS_DAP 40
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#define MASTER_QDSS_ETR 41
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#define MASTER_SDCC_2 42
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#define MASTER_SDCC_4 43
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#define MASTER_UFS_CARD 44
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#define MASTER_UFS_MEM 45
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#define MASTER_USB3_0 46
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#define MASTER_USB3_1 47
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#define MASTER_TSIF 48
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#define MASTER_PCIE_2 49
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#define MASTER_CNOC_A2NOC 50
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#define MASTER_SNOC_CNOC 51
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#define MASTER_IPA_CORE 52
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#define MASTER_GEM_NOC_SNOC 53
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#define MASTER_ALC 54
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#define MASTER_NPU 55
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#define MASTER_NPU_SYS 56
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#define MASTER_NPU_CDP 57
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#define MASTER_NPU_NOC_CFG 58
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#define SLAVE_EBI1 512
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#define SLAVE_AHB2PHY_SOUTH 513
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#define SLAVE_AHB2PHY_NORTH 514
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#define SLAVE_AOSS 515
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#define SLAVE_APPSS 516
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#define SLAVE_CAMERA_CFG 517
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#define SLAVE_CLK_CTL 518
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#define SLAVE_CDSP_CFG 519
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#define SLAVE_RBCPR_CX_CFG 520
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#define SLAVE_RBCPR_MMCX_CFG 521
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#define SLAVE_RBCPR_MX_CFG 522
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#define SLAVE_CRYPTO_0_CFG 523
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#define SLAVE_CX_RDPM 524
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#define SLAVE_DCC_CFG 525
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#define SLAVE_DISPLAY_CFG 526
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#define SLAVE_GFX3D_CFG 527
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#define SLAVE_IMEM_CFG 528
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#define SLAVE_IPA_CFG 529
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#define SLAVE_IPC_ROUTER_CFG 530
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#define SLAVE_LLCC_CFG 531
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#define SLAVE_LPASS 532
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#define SLAVE_PCIE_0_CFG 533
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#define SLAVE_PCIE_1_CFG 534
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#define SLAVE_PDM 535
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#define SLAVE_PIMEM_CFG 536
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#define SLAVE_QDSS_CFG 537
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#define SLAVE_QSPI_0 538
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#define SLAVE_QUP_0 539
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#define SLAVE_QUP_1 540
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#define SLAVE_QUP_2 541
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#define SLAVE_SDCC_2 542
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#define SLAVE_SDCC_4 543
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#define SLAVE_TCSR 544
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#define SLAVE_UFS_CARD_CFG 545
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#define SLAVE_UFS_MEM_CFG 546
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#define SLAVE_USB3_0 547
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#define SLAVE_USB3_1 548
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#define SLAVE_VENUS_CFG 549
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#define SLAVE_VSENSE_CTRL_CFG 550
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#define SLAVE_A1NOC_CFG 551
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#define SLAVE_A1NOC_SNOC 552
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#define SLAVE_A2NOC_CFG 553
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#define SLAVE_A2NOC_SNOC 554
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#define SLAVE_GEM_NOC_CFG 555
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#define SLAVE_SNOC_GEM_NOC_GC 556
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#define SLAVE_SNOC_GEM_NOC_SF 557
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#define SLAVE_LLCC 558
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#define SLAVE_MNOC_HF_MEM_NOC 559
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#define SLAVE_MNOC_SF_MEM_NOC 560
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#define SLAVE_CNOC_MNOC_CFG 561
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#define SLAVE_CDSP_MEM_NOC 562
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#define SLAVE_MEM_NOC_PCIE_SNOC 563
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#define SLAVE_ANOC_PCIE_GEM_NOC 564
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#define SLAVE_SNOC_CFG 565
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#define SLAVE_QUP_CORE_0 566
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#define SLAVE_QUP_CORE_1 567
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#define SLAVE_QUP_CORE_2 568
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#define SLAVE_IMEM 569
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#define SLAVE_PIMEM 570
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#define SLAVE_SERVICE_NSP_NOC 571
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#define SLAVE_SERVICE_A1NOC 572
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#define SLAVE_SERVICE_A2NOC 573
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#define SLAVE_SERVICE_CNOC 574
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#define SLAVE_SERVICE_GEM_NOC_1 575
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#define SLAVE_SERVICE_MNOC 576
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#define SLAVE_SERVICE_GEM_NOC_2 577
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#define SLAVE_SERVICE_SNOC 578
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#define SLAVE_SERVICE_GEM_NOC 579
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#define SLAVE_PCIE_0 580
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#define SLAVE_PCIE_1 581
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#define SLAVE_QDSS_STM 582
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#define SLAVE_TCU 583
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#define SLAVE_ANOC_PCIE_GEM_NOC_1 584
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#define SLAVE_CNOC_DDRSS 585
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#define SLAVE_NPU_CFG 586
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#define SLAVE_PCIE_2_CFG 587
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#define SLAVE_PRNG 588
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#define SLAVE_TLMM_NORTH 589
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#define SLAVE_TLMM_SOUTH 590
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#define SLAVE_TLMM_WEST 591
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#define SLAVE_TSIF 592
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#define SLAVE_CNOC_A2NOC 593
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#define SLAVE_IPA_CORE 594
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#define SLAVE_OCIMEM 595
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#define SLAVE_SNOC_CNOC 596
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#define SLAVE_SNOC_MEM_NOC_GC 597
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#define SLAVE_PCIE_2 598
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#define SLAVE_GEM_NOC_SNOC 599
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#define SLAVE_NPU_CAL_DP0 600
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#define SLAVE_NPU_CAL_DP1 601
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#define SLAVE_NPU_CP 602
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#define SLAVE_NPU_INT_DMA_BWMON_CFG 603
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#define SLAVE_NPU_DPM 604
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#define SLAVE_ISENSE_CFG 605
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#define SLAVE_NPU_LLM_CFG 606
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#define SLAVE_NPU_TCM 607
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#define SLAVE_NPU_COMPUTE_NOC 608
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#define SLAVE_SERVICE_NPU_NOC 609
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#define MASTER_LLCC_DISP 1000
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#define MASTER_MNOC_HF_MEM_NOC_DISP 1001
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#define MASTER_MNOC_SF_MEM_NOC_DISP 1002
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#define MASTER_MDP0_DISP 1003
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#define MASTER_MDP1_DISP 1004
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#define MASTER_ROTATOR_DISP 1005
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#define SLAVE_EBI1_DISP 1512
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#define SLAVE_LLCC_DISP 1513
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#define SLAVE_MNOC_HF_MEM_NOC_DISP 1514
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#define SLAVE_MNOC_SF_MEM_NOC_DISP 1515
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#endif
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