Rtwo/kernel/motorola/sm8550/include/dt-bindings/interconnect/qcom,lemans.h
2025-09-30 19:22:48 -05:00

203 lines
6.3 KiB
C

/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2021, Qualcomm Innovation Center, Inc. All rights reserved.
*/
#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_LEMANS_H
#define __DT_BINDINGS_INTERCONNECT_QCOM_LEMANS_H
#define MASTER_GPU_TCU 0
#define MASTER_PCIE_TCU 1
#define MASTER_SYS_TCU 2
#define MASTER_APPSS_PROC 3
#define MASTER_LLCC 4
#define MASTER_CNOC_LPASS_AG_NOC 5
#define MASTER_GIC_AHB 6
#define MASTER_CDSP_NOC_CFG 7
#define MASTER_CDSPB_NOC_CFG 8
#define MASTER_QDSS_BAM 9
#define MASTER_QUP_0 10
#define MASTER_QUP_1 11
#define MASTER_QUP_2 12
#define MASTER_A1NOC_SNOC 13
#define MASTER_A2NOC_SNOC 14
#define MASTER_CAMNOC_HF 15
#define MASTER_CAMNOC_ICP 16
#define MASTER_CAMNOC_SF 17
#define MASTER_COMPUTE_NOC 18
#define MASTER_COMPUTE_NOC_1 19
#define MASTER_CNOC_A2NOC 20
#define MASTER_CNOC_DC_NOC 21
#define MASTER_GEM_NOC_CFG 22
#define MASTER_GEM_NOC_CNOC 23
#define MASTER_GEM_NOC_PCIE_SNOC 24
#define MASTER_GPDSP_SAIL 25
#define MASTER_GFX3D 26
#define MASTER_LPASS_ANOC 27
#define MASTER_MDP0 28
#define MASTER_MDP1 29
#define MASTER_MDP_CORE1_0 30
#define MASTER_MDP_CORE1_1 31
#define MASTER_MNOC_HF_MEM_NOC 32
#define MASTER_CNOC_MNOC_HF_CFG 33
#define MASTER_MNOC_SF_MEM_NOC 34
#define MASTER_CNOC_MNOC_SF_CFG 35
#define MASTER_ANOC_PCIE_GEM_NOC 36
#define MASTER_SNOC_CFG 37
#define MASTER_SNOC_GC_MEM_NOC 38
#define MASTER_SNOC_SF_MEM_NOC 39
#define MASTER_VIDEO_P0 40
#define MASTER_VIDEO_P1 41
#define MASTER_VIDEO_PROC 42
#define MASTER_VIDEO_V_PROC 43
#define MASTER_QUP_CORE_0 44
#define MASTER_QUP_CORE_1 45
#define MASTER_QUP_CORE_2 46
#define MASTER_QUP_CORE_3 47
#define MASTER_CRYPTO_CORE0 48
#define MASTER_CRYPTO_CORE1 49
#define MASTER_DSP0 50
#define MASTER_DSP1 51
#define MASTER_IPA 52
#define MASTER_LPASS_PROC 53
#define MASTER_CDSP_PROC 54
#define MASTER_CDSP_PROC_B 55
#define MASTER_PIMEM 56
#define MASTER_QUP_3 57
#define MASTER_EMAC 58
#define MASTER_EMAC_1 59
#define MASTER_GIC 60
#define MASTER_PCIE_0 61
#define MASTER_PCIE_1 62
#define MASTER_QDSS_ETR_0 63
#define MASTER_QDSS_ETR_1 64
#define MASTER_SDC 65
#define MASTER_UFS_CARD 66
#define MASTER_UFS_MEM 67
#define MASTER_USB2 68
#define MASTER_USB3_0 69
#define MASTER_USB3_1 70
#define SLAVE_EBI1 512
#define SLAVE_AHB2PHY_0 513
#define SLAVE_AHB2PHY_1 514
#define SLAVE_AHB2PHY_2 515
#define SLAVE_AHB2PHY_3 516
#define SLAVE_ANOC_THROTTLE_CFG 517
#define SLAVE_AOSS 518
#define SLAVE_APPSS 519
#define SLAVE_BOOT_ROM 520
#define SLAVE_CAMERA_CFG 521
#define SLAVE_CAMERA_NRT_THROTTLE_CFG 522
#define SLAVE_CAMERA_RT_THROTTLE_CFG 523
#define SLAVE_CLK_CTL 524
#define SLAVE_CDSP_CFG 525
#define SLAVE_CDSP1_CFG 526
#define SLAVE_RBCPR_CX_CFG 527
#define SLAVE_RBCPR_MMCX_CFG 528
#define SLAVE_RBCPR_MX_CFG 529
#define SLAVE_CPR_NSPCX 530
#define SLAVE_CRYPTO_0_CFG 531
#define SLAVE_CX_RDPM 532
#define SLAVE_DISPLAY_CFG 533
#define SLAVE_DISPLAY_RT_THROTTLE_CFG 534
#define SLAVE_DISPLAY1_CFG 535
#define SLAVE_DISPLAY1_RT_THROTTLE_CFG 536
#define SLAVE_EMAC_CFG 537
#define SLAVE_EMAC1_CFG 538
#define SLAVE_GP_DSP0_CFG 539
#define SLAVE_GP_DSP1_CFG 540
#define SLAVE_GPDSP0_THROTTLE_CFG 541
#define SLAVE_GPDSP1_THROTTLE_CFG 542
#define SLAVE_GPU_TCU_THROTTLE_CFG 543
#define SLAVE_GFX3D_CFG 544
#define SLAVE_HWKM 545
#define SLAVE_IMEM_CFG 546
#define SLAVE_IPA_CFG 547
#define SLAVE_IPC_ROUTER_CFG 548
#define SLAVE_LLCC_CFG 549
#define SLAVE_LPASS 550
#define SLAVE_LPASS_CORE_CFG 551
#define SLAVE_LPASS_LPI_CFG 552
#define SLAVE_LPASS_MPU_CFG 553
#define SLAVE_LPASS_THROTTLE_CFG 554
#define SLAVE_LPASS_TOP_CFG 555
#define SLAVE_MX_RDPM 556
#define SLAVE_MXC_RDPM 557
#define SLAVE_PCIE_0_CFG 558
#define SLAVE_PCIE_1_CFG 559
#define SLAVE_PCIE_RSC_CFG 560
#define SLAVE_PCIE_TCU_THROTTLE_CFG 561
#define SLAVE_PCIE_THROTTLE_CFG 562
#define SLAVE_PDM 563
#define SLAVE_PIMEM_CFG 564
#define SLAVE_PKA_WRAPPER_CFG 565
#define SLAVE_QDSS_CFG 566
#define SLAVE_QM_CFG 567
#define SLAVE_QM_MPU_CFG 568
#define SLAVE_QUP_0 569
#define SLAVE_QUP_1 570
#define SLAVE_QUP_2 571
#define SLAVE_QUP_3 572
#define SLAVE_SAIL_THROTTLE_CFG 573
#define SLAVE_SDC1 574
#define SLAVE_SECURITY 575
#define SLAVE_SNOC_THROTTLE_CFG 576
#define SLAVE_TCSR 577
#define SLAVE_TLMM 578
#define SLAVE_TSC_CFG 579
#define SLAVE_UFS_CARD_CFG 580
#define SLAVE_UFS_MEM_CFG 581
#define SLAVE_USB2 582
#define SLAVE_USB3_0 583
#define SLAVE_USB3_1 584
#define SLAVE_VENUS_CFG 585
#define SLAVE_VENUS_CVP_THROTTLE_CFG 586
#define SLAVE_VENUS_V_CPU_THROTTLE_CFG 587
#define SLAVE_VENUS_VCODEC_THROTTLE_CFG 588
#define SLAVE_A1NOC_SNOC 589
#define SLAVE_A2NOC_SNOC 590
#define SLAVE_DDRSS_CFG 591
#define SLAVE_GEM_NOC_CNOC 592
#define SLAVE_GEM_NOC_CFG 593
#define SLAVE_SNOC_GEM_NOC_GC 594
#define SLAVE_SNOC_GEM_NOC_SF 595
#define SLAVE_GP_DSP_SAIL_NOC 596
#define SLAVE_GPDSP_NOC_CFG 597
#define SLAVE_HCP_A 598
#define SLAVE_LLCC 599
#define SLAVE_MNOC_HF_MEM_NOC 600
#define SLAVE_MNOC_SF_MEM_NOC 601
#define SLAVE_CNOC_MNOC_HF_CFG 602
#define SLAVE_CNOC_MNOC_SF_CFG 603
#define SLAVE_CDSP_MEM_NOC 604
#define SLAVE_CDSPB_MEM_NOC 605
#define SLAVE_HCP_B 606
#define SLAVE_GEM_NOC_PCIE_CNOC 607
#define SLAVE_PCIE_ANOC_CFG 608
#define SLAVE_ANOC_PCIE_GEM_NOC 609
#define SLAVE_SNOC_CFG 610
#define SLAVE_LPASS_SNOC 611
#define SLAVE_QUP_CORE_0 612
#define SLAVE_QUP_CORE_1 613
#define SLAVE_QUP_CORE_2 614
#define SLAVE_QUP_CORE_3 615
#define SLAVE_BOOT_IMEM 616
#define SLAVE_IMEM 617
#define SLAVE_PIMEM 618
#define SLAVE_SERVICE_NSP_NOC 619
#define SLAVE_SERVICE_NSPB_NOC 620
#define SLAVE_SERVICE_GEM_NOC_1 621
#define SLAVE_SERVICE_MNOC_HF 622
#define SLAVE_SERVICE_MNOC_SF 623
#define SLAVE_SERVICES_LPASS_AML_NOC 624
#define SLAVE_SERVICE_LPASS_AG_NOC 625
#define SLAVE_SERVICE_GEM_NOC_2 626
#define SLAVE_SERVICE_SNOC 627
#define SLAVE_SERVICE_GEM_NOC 628
#define SLAVE_SERVICE_GEM_NOC2 629
#define SLAVE_PCIE_0 630
#define SLAVE_PCIE_1 631
#define SLAVE_QDSS_STM 632
#define SLAVE_TCU 633
#endif