301 lines
7.6 KiB
C
301 lines
7.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only WITH Linux-syscall-note */
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/*
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* Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#ifndef _UAPI_MSM_NPU_H_
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#define _UAPI_MSM_NPU_H_
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/* -------------------------------------------------------------------------
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* Includes
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* -------------------------------------------------------------------------
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*/
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#include <linux/types.h>
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/* -------------------------------------------------------------------------
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* Defines
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* -------------------------------------------------------------------------
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*/
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#define MSM_NPU_IOCTL_MAGIC 'n'
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/* get npu info */
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#define MSM_NPU_GET_INFO \
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_IOWR(MSM_NPU_IOCTL_MAGIC, 1, struct msm_npu_get_info_ioctl)
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/* map buf */
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#define MSM_NPU_MAP_BUF \
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_IOWR(MSM_NPU_IOCTL_MAGIC, 2, struct msm_npu_map_buf_ioctl)
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/* map buf */
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#define MSM_NPU_UNMAP_BUF \
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_IOWR(MSM_NPU_IOCTL_MAGIC, 3, struct msm_npu_unmap_buf_ioctl)
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/* load network */
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#define MSM_NPU_LOAD_NETWORK \
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_IOWR(MSM_NPU_IOCTL_MAGIC, 4, struct msm_npu_load_network_ioctl)
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/* unload network */
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#define MSM_NPU_UNLOAD_NETWORK \
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_IOWR(MSM_NPU_IOCTL_MAGIC, 5, struct msm_npu_unload_network_ioctl)
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/* exec network */
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#define MSM_NPU_EXEC_NETWORK \
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_IOWR(MSM_NPU_IOCTL_MAGIC, 6, struct msm_npu_exec_network_ioctl)
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/* load network v2 */
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#define MSM_NPU_LOAD_NETWORK_V2 \
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_IOWR(MSM_NPU_IOCTL_MAGIC, 7, struct msm_npu_load_network_ioctl_v2)
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/* exec network v2 */
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#define MSM_NPU_EXEC_NETWORK_V2 \
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_IOWR(MSM_NPU_IOCTL_MAGIC, 8, struct msm_npu_exec_network_ioctl_v2)
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/* receive event */
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#define MSM_NPU_RECEIVE_EVENT \
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_IOR(MSM_NPU_IOCTL_MAGIC, 9, struct msm_npu_event)
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/* set property */
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#define MSM_NPU_SET_PROP \
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_IOW(MSM_NPU_IOCTL_MAGIC, 10, struct msm_npu_property)
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/* get property */
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#define MSM_NPU_GET_PROP \
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_IOW(MSM_NPU_IOCTL_MAGIC, 11, struct msm_npu_property)
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#define MSM_NPU_EVENT_TYPE_START 0x10000000
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#define MSM_NPU_EVENT_TYPE_EXEC_DONE (MSM_NPU_EVENT_TYPE_START + 1)
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#define MSM_NPU_EVENT_TYPE_EXEC_V2_DONE (MSM_NPU_EVENT_TYPE_START + 2)
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#define MSM_NPU_EVENT_TYPE_SSR (MSM_NPU_EVENT_TYPE_START + 3)
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#define MSM_NPU_MAX_INPUT_LAYER_NUM 8
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#define MSM_NPU_MAX_OUTPUT_LAYER_NUM 4
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#define MSM_NPU_MAX_PATCH_LAYER_NUM (MSM_NPU_MAX_INPUT_LAYER_NUM +\
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MSM_NPU_MAX_OUTPUT_LAYER_NUM)
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#define MSM_NPU_PROP_ID_START 0x100
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#define MSM_NPU_PROP_ID_FW_STATE (MSM_NPU_PROP_ID_START + 0)
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#define MSM_NPU_PROP_ID_PERF_MODE (MSM_NPU_PROP_ID_START + 1)
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#define MSM_NPU_PROP_ID_PERF_MODE_MAX (MSM_NPU_PROP_ID_START + 2)
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#define MSM_NPU_PROP_ID_DRV_VERSION (MSM_NPU_PROP_ID_START + 3)
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#define MSM_NPU_PROP_ID_HARDWARE_VERSION (MSM_NPU_PROP_ID_START + 4)
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#define MSM_NPU_PROP_ID_IPC_QUEUE_INFO (MSM_NPU_PROP_ID_START + 5)
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#define MSM_NPU_PROP_ID_DRV_FEATURE (MSM_NPU_PROP_ID_START + 6)
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#define MSM_NPU_FW_PROP_ID_START 0x1000
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#define MSM_NPU_PROP_ID_DCVS_MODE (MSM_NPU_FW_PROP_ID_START + 0)
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#define MSM_NPU_PROP_ID_DCVS_MODE_MAX (MSM_NPU_FW_PROP_ID_START + 1)
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#define MSM_NPU_PROP_ID_CLK_GATING_MODE (MSM_NPU_FW_PROP_ID_START + 2)
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#define MSM_NPU_PROP_ID_HW_VERSION (MSM_NPU_FW_PROP_ID_START + 3)
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#define MSM_NPU_PROP_ID_FW_VERSION (MSM_NPU_FW_PROP_ID_START + 4)
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#define MSM_NPU_PROP_ID_FW_GETCAPS (MSM_NPU_FW_PROP_ID_START + 5)
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/* features supported by driver */
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#define MSM_NPU_FEATURE_MULTI_EXECUTE 0x1
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#define MSM_NPU_FEATURE_ASYNC_EXECUTE 0x2
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#define MSM_NPU_FEATURE_DSP_SID_MAPPED 0x8
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#define PROP_PARAM_MAX_SIZE 8
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/* -------------------------------------------------------------------------
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* Data Structures
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* -------------------------------------------------------------------------
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*/
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struct msm_npu_patch_info {
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/* chunk id */
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__u32 chunk_id;
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/* instruction size in bytes */
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__u16 instruction_size_in_bytes;
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/* variable size in bits */
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__u16 variable_size_in_bits;
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/* shift value in bits */
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__u16 shift_value_in_bits;
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/* location offset */
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__u32 loc_offset;
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};
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struct msm_npu_layer {
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/* layer id */
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__u32 layer_id;
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/* patch information*/
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struct msm_npu_patch_info patch_info;
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/* buffer handle */
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__s32 buf_hdl;
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/* buffer size */
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__u32 buf_size;
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/* physical address */
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__u64 buf_phys_addr;
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};
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struct msm_npu_patch_info_v2 {
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/* patch value */
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__u32 value;
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/* chunk id */
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__u32 chunk_id;
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/* instruction size in bytes */
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__u32 instruction_size_in_bytes;
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/* variable size in bits */
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__u32 variable_size_in_bits;
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/* shift value in bits */
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__u32 shift_value_in_bits;
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/* location offset */
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__u32 loc_offset;
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};
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struct msm_npu_patch_buf_info {
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/* physical address to be patched */
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__u64 buf_phys_addr;
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/* buffer id */
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__u32 buf_id;
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};
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/* -------------------------------------------------------------------------
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* Data Structures - IOCTLs
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* -------------------------------------------------------------------------
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*/
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struct msm_npu_map_buf_ioctl {
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/* buffer ion handle */
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__s32 buf_ion_hdl;
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/* buffer size */
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__u32 size;
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/* iommu mapped physical address */
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__u64 npu_phys_addr;
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};
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struct msm_npu_unmap_buf_ioctl {
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/* buffer ion handle */
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__s32 buf_ion_hdl;
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/* iommu mapped physical address */
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__u64 npu_phys_addr;
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};
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struct msm_npu_get_info_ioctl {
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/* firmware version */
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__u32 firmware_version;
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/* reserved */
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__u32 flags;
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};
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struct msm_npu_load_network_ioctl {
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/* buffer ion handle */
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__s32 buf_ion_hdl;
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/* physical address */
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__u64 buf_phys_addr;
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/* buffer size */
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__u32 buf_size;
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/* first block size */
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__u32 first_block_size;
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/* reserved */
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__u32 flags;
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/* network handle */
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__u32 network_hdl;
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/* priority */
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__u32 priority;
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/* perf mode */
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__u32 perf_mode;
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};
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struct msm_npu_load_network_ioctl_v2 {
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/* physical address */
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__u64 buf_phys_addr;
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/* patch info(v2) for all input/output layers */
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__u64 patch_info;
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/* buffer ion handle */
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__s32 buf_ion_hdl;
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/* buffer size */
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__u32 buf_size;
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/* first block size */
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__u32 first_block_size;
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/* load flags */
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__u32 flags;
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/* network handle */
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__u32 network_hdl;
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/* priority */
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__u32 priority;
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/* perf mode */
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__u32 perf_mode;
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/* number of layers in the network */
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__u32 num_layers;
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/* number of layers to be patched */
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__u32 patch_info_num;
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/* reserved */
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__u32 reserved;
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};
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struct msm_npu_unload_network_ioctl {
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/* network handle */
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__u32 network_hdl;
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};
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struct msm_npu_exec_network_ioctl {
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/* network handle */
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__u32 network_hdl;
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/* input layer number */
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__u32 input_layer_num;
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/* input layer info */
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struct msm_npu_layer input_layers[MSM_NPU_MAX_INPUT_LAYER_NUM];
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/* output layer number */
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__u32 output_layer_num;
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/* output layer info */
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struct msm_npu_layer output_layers[MSM_NPU_MAX_OUTPUT_LAYER_NUM];
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/* patching is required */
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__u32 patching_required;
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/* asynchronous execution */
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__u32 async;
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/* reserved */
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__u32 flags;
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};
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struct msm_npu_exec_network_ioctl_v2 {
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/* stats buffer to be filled with execution stats */
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__u64 stats_buf_addr;
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/* patch buf info for both input and output layers */
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__u64 patch_buf_info;
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/* network handle */
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__u32 network_hdl;
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/* asynchronous execution */
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__u32 async;
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/* execution flags */
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__u32 flags;
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/* stats buf size allocated */
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__u32 stats_buf_size;
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/* number of layers to be patched */
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__u32 patch_buf_info_num;
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/* reserved */
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__u32 reserved;
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};
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struct msm_npu_event_execute_done {
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__u32 network_hdl;
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__s32 exec_result;
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};
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struct msm_npu_event_execute_v2_done {
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__u32 network_hdl;
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__s32 exec_result;
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/* stats buf size filled */
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__u32 stats_buf_size;
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};
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struct msm_npu_event_ssr {
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__u32 network_hdl;
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};
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struct msm_npu_event {
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__u32 type;
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union {
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struct msm_npu_event_execute_done exec_done;
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struct msm_npu_event_execute_v2_done exec_v2_done;
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struct msm_npu_event_ssr ssr;
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__u8 data[128];
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} u;
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__u32 reserved[4];
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};
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struct msm_npu_property {
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__u32 prop_id;
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__u32 num_of_params;
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__u32 network_hdl;
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__u32 prop_param[PROP_PARAM_MAX_SIZE];
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};
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#endif /*_UAPI_MSM_NPU_H_*/
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