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These are the pinctrl changes for v3.10:

Browse source 
- Patrice Chotard contributed a new configuration debugfs interface
   and reintroduced fine-grained locking into the core: instead of
   having a "big pinctrl lock" we have a per-controller lock and
   specialized locks for the global controller and pinctrl handle
   lists.
 - Haoijan Zhuang deleted all the PXA and MMP2 pinctrl drivers and
   replaced them with pinctrl-single (which is also used by other SoCs)
   so we are gaining consolidation. The platform particulars now come
   in through the device tree.
 - Haoijan also added support for generic pin config into the
   pinctrl-single driver which is another big consolidation win.
 - Finally also GPIO ranges are now supported by the pinctrl-single
   driver.
 - Tomasz Figa contributed a new Samsung S3C pinctrl driver, bringing
   more of the older Samsung platforms under the pinctrl umbrella and
   out of arch/arm.
 - Maxime Ripard contributed new Allwinner A10/A13 drivers.
 - Sachin Kamat, Wei Yongjun and Axel Lin did a lot of cleanups.
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Merge tag 'pinctrl-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Pull pinctrl update from Linus Walleij:
 "These are the pinctrl changes for v3.10:

   - Patrice Chotard contributed a new configuration debugfs interface
     and reintroduced fine-grained locking into the core: instead of
     having a "big pinctrl lock" we have a per-controller lock and
     specialized locks for the global controller and pinctrl handle
     lists.

   - Haoijan Zhuang deleted all the PXA and MMP2 pinctrl drivers and
     replaced them with pinctrl-single (which is also used by other
     SoCs) so we are gaining consolidation.  The platform particulars
     now come in through the device tree.

   - Haoijan also added support for generic pin config into the
     pinctrl-single driver which is another big consolidation win.

   - Finally also GPIO ranges are now supported by the pinctrl-single
     driver.

   - Tomasz Figa contributed a new Samsung S3C pinctrl driver, bringing
     more of the older Samsung platforms under the pinctrl umbrella and
     out of arch/arm.

   - Maxime Ripard contributed new Allwinner A10/A13 drivers.

   - Sachin Kamat, Wei Yongjun and Axel Lin did a lot of cleanups."

* tag 'pinctrl-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (66 commits)
  pinctrl: move subsystem mutex to pinctrl_dev struct
  pinctrl/pinconfig: fix misplaced goto
  pinctrl: s3c64xx: Fix build error caused by undefined chained_irq_enter
  pinctrl/pinconfig: add debug interface
  pinctrl: abx500: fix issue when no pdata
  pinctrl: pinctrl-single: add missing double quote
  pinctrl: sunxi: Rename wemac functions to emac
  pinctrl: exynos5440: add gpio interrupt support
  pinctrl: exynos5440: fix probe failure due to missing pin-list in config nodes
  pinctrl: ab8505: Staticize some symbols
  pinctrl: ab8540: Staticize some symbols
  pinctrl: ab9540: Staticize some symbols
  pinctrl: ab8500: Staticize some symbols
  pinctrl: abx500: Staticize some symbols
  pinctrl: Add pinctrl-s3c64xx driver
  pinctrl: samsung: Handle banks with two configuration registers
  pinctrl: samsung: Remove hardcoded register offsets
  pinctrl: samsung: Split pin bank description into two structures
  pinctrl: samsung: Include pinctrl-exynos driver data conditionally
  pinctrl: samsung: Protect bank registers with a spinlock
  ...
This commit is contained in:
Linus Torvalds 2013-04-29 09:40:35 -07:00
commit 000a74f41e
55 changed files with 3228 additions and 3696 deletions
Download patch file Download diff file Expand all files Collapse all files

129
drivers/gpio/gpio-pl061.c
View file

@ -15,6 +15,7 @@
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/bitops.h>
#include <linux/workqueue.h>
#include <linux/gpio.h>
@ -22,6 +23,7 @@
#include <linux/amba/bus.h>
#include <linux/amba/pl061.h>
#include <linux/slab.h>
#include <linux/pinctrl/consumer.h>
#include <linux/pm.h>
#include <asm/mach/irq.h>
@ -51,8 +53,7 @@ struct pl061_gpio {
spinlock_t lock;
void __iomem *base;
int irq_base;
struct irq_chip_generic *irq_gc;
struct irq_domain *domain;
struct gpio_chip gc;
#ifdef CONFIG_PM
@ -60,6 +61,24 @@ struct pl061_gpio {
#endif
};
static int pl061_gpio_request(struct gpio_chip *chip, unsigned offset)
{
/*
* Map back to global GPIO space and request muxing, the direction
* parameter does not matter for this controller.
*/
int gpio = chip->base + offset;
return pinctrl_request_gpio(gpio);
}
static void pl061_gpio_free(struct gpio_chip *chip, unsigned offset)
{
int gpio = chip->base + offset;
pinctrl_free_gpio(gpio);
}
static int pl061_direction_input(struct gpio_chip *gc, unsigned offset)
{
struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
@ -122,24 +141,20 @@ static int pl061_to_irq(struct gpio_chip *gc, unsigned offset)
{
struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
if (chip->irq_base <= 0)
return -EINVAL;
return chip->irq_base + offset;
return irq_create_mapping(chip->domain, offset);
}
static int pl061_irq_type(struct irq_data *d, unsigned trigger)
{
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
struct pl061_gpio *chip = gc->private;
int offset = d->irq - chip->irq_base;
struct pl061_gpio *chip = irq_data_get_irq_chip_data(d);
int offset = irqd_to_hwirq(d);
unsigned long flags;
u8 gpiois, gpioibe, gpioiev;
if (offset < 0 || offset >= PL061_GPIO_NR)
return -EINVAL;
raw_spin_lock_irqsave(&gc->lock, flags);
spin_lock_irqsave(&chip->lock, flags);
gpioiev = readb(chip->base + GPIOIEV);
@ -168,7 +183,7 @@ static int pl061_irq_type(struct irq_data *d, unsigned trigger)
writeb(gpioiev, chip->base + GPIOIEV);
raw_spin_unlock_irqrestore(&gc->lock, flags);
spin_unlock_irqrestore(&chip->lock, flags);
return 0;
}
@ -192,31 +207,61 @@ static void pl061_irq_handler(unsigned irq, struct irq_desc *desc)
chained_irq_exit(irqchip, desc);
}
static void __init pl061_init_gc(struct pl061_gpio *chip, int irq_base)
static void pl061_irq_mask(struct irq_data *d)
{
struct irq_chip_type *ct;
struct pl061_gpio *chip = irq_data_get_irq_chip_data(d);
u8 mask = 1 << (irqd_to_hwirq(d) % PL061_GPIO_NR);
u8 gpioie;
chip->irq_gc = irq_alloc_generic_chip("gpio-pl061", 1, irq_base,
chip->base, handle_simple_irq);
chip->irq_gc->private = chip;
ct = chip->irq_gc->chip_types;
ct->chip.irq_mask = irq_gc_mask_clr_bit;
ct->chip.irq_unmask = irq_gc_mask_set_bit;
ct->chip.irq_set_type = pl061_irq_type;
ct->chip.irq_set_wake = irq_gc_set_wake;
ct->regs.mask = GPIOIE;
irq_setup_generic_chip(chip->irq_gc, IRQ_MSK(PL061_GPIO_NR),
IRQ_GC_INIT_NESTED_LOCK, IRQ_NOREQUEST, 0);
spin_lock(&chip->lock);
gpioie = readb(chip->base + GPIOIE) & ~mask;
writeb(gpioie, chip->base + GPIOIE);
spin_unlock(&chip->lock);
}
static void pl061_irq_unmask(struct irq_data *d)
{
struct pl061_gpio *chip = irq_data_get_irq_chip_data(d);
u8 mask = 1 << (irqd_to_hwirq(d) % PL061_GPIO_NR);
u8 gpioie;
spin_lock(&chip->lock);
gpioie = readb(chip->base + GPIOIE) | mask;
writeb(gpioie, chip->base + GPIOIE);
spin_unlock(&chip->lock);
}
static struct irq_chip pl061_irqchip = {
.name = "pl061 gpio",
.irq_mask = pl061_irq_mask,
.irq_unmask = pl061_irq_unmask,
.irq_set_type = pl061_irq_type,
};
static int pl061_irq_map(struct irq_domain *d, unsigned int virq,
irq_hw_number_t hw)
{
struct pl061_gpio *chip = d->host_data;
irq_set_chip_and_handler_name(virq, &pl061_irqchip, handle_simple_irq,
"pl061");
irq_set_chip_data(virq, chip);
irq_set_irq_type(virq, IRQ_TYPE_NONE);
return 0;
}
static const struct irq_domain_ops pl061_domain_ops = {
.map = pl061_irq_map,
.xlate = irq_domain_xlate_twocell,
};
static int pl061_probe(struct amba_device *adev, const struct amba_id *id)
{
struct device *dev = &adev->dev;
struct pl061_platform_data *pdata = dev->platform_data;
struct pl061_gpio *chip;
int ret, irq, i;
int ret, irq, i, irq_base;
chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
if (chip == NULL)
@ -224,24 +269,32 @@ static int pl061_probe(struct amba_device *adev, const struct amba_id *id)
if (pdata) {
chip->gc.base = pdata->gpio_base;
chip->irq_base = pdata->irq_base;
} else if (adev->dev.of_node) {
irq_base = pdata->irq_base;
if (irq_base <= 0)
return -ENODEV;
} else {
chip->gc.base = -1;
chip->irq_base = 0;
} else
return -ENODEV;
irq_base = 0;
}
if (!devm_request_mem_region(dev, adev->res.start,
resource_size(&adev->res), "pl061"))
resource_size(&adev->res), "pl061"))
return -EBUSY;
chip->base = devm_ioremap(dev, adev->res.start,
resource_size(&adev->res));
if (chip->base == NULL)
resource_size(&adev->res));
if (!chip->base)
return -ENOMEM;
chip->domain = irq_domain_add_simple(adev->dev.of_node, PL061_GPIO_NR,
irq_base, &pl061_domain_ops, chip);
if (!chip->domain)
return -ENODEV;
spin_lock_init(&chip->lock);
chip->gc.request = pl061_gpio_request;
chip->gc.free = pl061_gpio_free;
chip->gc.direction_input = pl061_direction_input;
chip->gc.direction_output = pl061_direction_output;
chip->gc.get = pl061_get_value;
@ -259,12 +312,6 @@ static int pl061_probe(struct amba_device *adev, const struct amba_id *id)
/*
* irq_chip support
*/
if (chip->irq_base <= 0)
return 0;
pl061_init_gc(chip, chip->irq_base);
writeb(0, chip->base + GPIOIE); /* disable irqs */
irq = adev->irq[0];
if (irq < 0)

15
drivers/gpio/gpiolib-of.c
View file

@ -203,22 +203,11 @@ static void of_gpiochip_add_pin_range(struct gpio_chip *chip)
if (!pctldev)
break;
/*
* This assumes that the n GPIO pins are consecutive in the
* GPIO number space, and that the pins are also consecutive
* in their local number space. Currently it is not possible
* to add different ranges for one and the same GPIO chip,
* as the code assumes that we have one consecutive range
* on both, mapping 1-to-1.
*
* TODO: make the OF bindings handle multiple sparse ranges
* on the same GPIO chip.
*/
ret = gpiochip_add_pin_range(chip,
pinctrl_dev_get_devname(pctldev),
0, /* offset in gpiochip */
pinspec.args[0],
pinspec.args[1]);
pinspec.args[1],
pinspec.args[2]);
if (ret)
break;