mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-14 08:36:12 -04:00
Merge "ARM: dts: msm: Add i2c, spi, uart dtsi nodes for monaco"
This commit is contained in:
qctecmdr
Gerrit - the friendly Code Review server
commit
00d4e0854c
3 changed files with 1229 additions and 0 deletions
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@ -7,5 +7,743 @@
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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qupv3_se6_2uart_pins: qupv3_se6_2uart_pins {
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qupv3_se6_2uart_active: qupv3_se6_2uart_active {
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||||
mux {
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pins = "gpio30", "gpio31";
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function = "qup06";
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};
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||||
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||||
config {
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||||
pins = "gpio30", "gpio31";
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drive-strength = <2>;
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bias-disable;
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};
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};
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qupv3_se6_2uart_sleep: qupv3_se6_2uart_sleep {
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mux {
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pins = "gpio30", "gpio31";
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function = "gpio";
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};
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config {
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pins = "gpio30", "gpio31";
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drive-strength = <2>;
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bias-pull-down;
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};
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};
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};
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qupv3_se0_i2c_pins: qupv3_se0_i2c_pins {
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qupv3_se0_i2c_active: qupv3_se0_i2c_active {
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mux {
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pins = "gpio4", "gpio5";
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function = "qup00";
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};
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config {
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pins = "gpio4", "gpio5";
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drive-strength = <2>;
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bias-pull-up;
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};
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};
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qupv3_se0_i2c_sleep: qupv3_se0_i2c_sleep {
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mux {
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pins = "gpio4", "gpio5";
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function = "gpio";
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};
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config {
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pins = "gpio4", "gpio5";
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drive-strength = <2>;
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bias-disable;
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};
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};
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};
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qupv3_se0_spi_pins: qupv3_se0_spi_pins {
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qupv3_se0_spi_active: qupv3_se0_spi_active {
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mux {
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pins = "gpio4", "gpio5",
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"gpio6", "gpio7";
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function = "qup00";
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};
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config {
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pins = "gpio4", "gpio5",
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"gpio6", "gpio7";
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drive-strength = <6>;
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bias-disable;
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};
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};
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qupv3_se0_spi_sleep: qupv3_se0_spi_sleep {
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mux {
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pins = "gpio4", "gpio5",
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"gpio6", "gpio7";
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function = "gpio";
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};
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config {
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pins = "gpio4", "gpio5",
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"gpio6", "gpio7";
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drive-strength = <6>;
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bias-disable;
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};
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};
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};
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qupv3_se1_i2c_pins: qupv3_se1_i2c_pins {
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qupv3_se1_i2c_active: qupv3_se1_i2c_active {
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mux {
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pins = "gpio10", "gpio11";
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function = "qup01";
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};
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config {
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pins = "gpio10", "gpio11";
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drive-strength = <2>;
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bias-pull-up;
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};
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};
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qupv3_se1_i2c_sleep: qupv3_se1_i2c_sleep {
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mux {
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pins = "gpio10", "gpio11";
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function = "gpio";
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};
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config {
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pins = "gpio10", "gpio11";
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drive-strength = <2>;
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bias-disable;
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};
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};
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};
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qupv3_se1_spi_pins: qupv3_se1_spi_pins {
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qupv3_se1_spi_active: qupv3_se1_spi_active {
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mux {
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pins = "gpio10", "gpio11",
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"gpio12", "gpio13";
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function = "qup01";
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};
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config {
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pins = "gpio10", "gpio11",
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"gpio12", "gpio13";
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drive-strength = <6>;
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bias-disable;
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};
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};
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qupv3_se1_spi_sleep: qupv3_se1_spi_sleep {
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mux {
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pins = "gpio10", "gpio11",
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"gpio12", "gpio13";
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function = "gpio";
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};
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config {
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pins = "gpio10", "gpio11",
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"gpio12", "gpio13";
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drive-strength = <6>;
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bias-disable;
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};
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};
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};
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qupv3_se2_i2c_pins: qupv3_se2_i2c_pins {
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qupv3_se2_i2c_active: qupv3_se2_i2c_active {
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mux {
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pins = "gpio0", "gpio1";
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function = "qup02";
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};
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config {
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pins = "gpio0", "gpio1";
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drive-strength = <2>;
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bias-pull-up;
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};
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};
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qupv3_se2_i2c_sleep: qupv3_se2_i2c_sleep {
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mux {
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pins = "gpio0", "gpio1";
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function = "gpio";
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};
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config {
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pins = "gpio0", "gpio1";
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drive-strength = <2>;
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bias-disable;
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};
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};
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};
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qupv3_se2_spi_pins: qupv3_se2_spi_pins {
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qupv3_se2_spi_active: qupv3_se2_spi_active {
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mux {
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pins = "gpio0", "gpio1",
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"gpio2", "gpio3";
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function = "qup02";
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};
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config {
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pins = "gpio0", "gpio1",
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"gpio2", "gpio3";
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drive-strength = <6>;
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bias-disable;
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};
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};
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qupv3_se2_spi_sleep: qupv3_se2_spi_sleep {
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mux {
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pins = "gpio0", "gpio1",
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"gpio2", "gpio3";
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function = "gpio";
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};
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config {
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pins = "gpio0", "gpio1",
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"gpio2", "gpio3";
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drive-strength = <6>;
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bias-disable;
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};
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};
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};
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qupv3_se3_i2c_pins: qupv3_se3_i2c_pins {
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qupv3_se3_i2c_active: qupv3_se3_i2c_active {
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mux {
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pins = "gpio14", "gpio15";
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function = "qup03";
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};
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config {
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pins = "gpio14", "gpio15";
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drive-strength = <2>;
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bias-pull-up;
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};
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};
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qupv3_se3_i2c_sleep: qupv3_se3_i2c_sleep {
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mux {
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pins = "gpio14", "gpio15";
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function = "gpio";
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};
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config {
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pins = "gpio14", "gpio15";
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drive-strength = <2>;
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bias-disable;
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};
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};
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};
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qupv3_se3_spi_pins: qupv3_se3_spi_pins {
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qupv3_se3_spi_active: qupv3_se3_spi_active {
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mux {
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pins = "gpio14", "gpio15",
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"gpio16", "gpio17";
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function = "qup03";
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};
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config {
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pins = "gpio14", "gpio15",
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"gpio16", "gpio17";
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drive-strength = <6>;
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bias-disable;
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};
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};
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qupv3_se3_spi_sleep: qupv3_se3_spi_sleep {
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mux {
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pins = "gpio14", "gpio15",
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"gpio16", "gpio17";
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function = "gpio";
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};
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config {
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pins = "gpio14", "gpio15",
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"gpio16", "gpio17";
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drive-strength = <6>;
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bias-disable;
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};
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};
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};
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qupv3_se4_i2c_pins: qupv3_se4_i2c_pins {
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qupv3_se4_i2c_active: qupv3_se4_i2c_active {
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mux {
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pins = "gpio20", "gpio21";
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function = "qup04";
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};
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config {
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pins = "gpio20", "gpio21";
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drive-strength = <2>;
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bias-pull-up;
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};
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};
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qupv3_se4_i2c_sleep: qupv3_se4_i2c_sleep {
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mux {
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pins = "gpio20", "gpio21";
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function = "gpio";
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};
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config {
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pins = "gpio20", "gpio21";
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drive-strength = <2>;
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bias-disable;
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};
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};
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};
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qupv3_se4_spi_pins: qupv3_se4_spi_pins {
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qupv3_se4_spi_active: qupv3_se4_spi_active {
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mux {
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pins = "gpio20", "gpio21",
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"gpio22", "gpio23";
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function = "qup04";
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};
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config {
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pins = "gpio20", "gpio21",
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"gpio22", "gpio23";
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drive-strength = <6>;
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bias-disable;
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};
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};
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qupv3_se4_spi_sleep: qupv3_se4_spi_sleep {
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mux {
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pins = "gpio20", "gpio21",
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"gpio22", "gpio23";
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function = "gpio";
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};
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config {
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pins = "gpio20", "gpio21",
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"gpio22", "gpio23";
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drive-strength = <6>;
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bias-disable;
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};
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};
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};
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qupv3_se5_i2c_pins: qupv3_se5_i2c_pins {
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qupv3_se5_i2c_active: qupv3_se5_i2c_active {
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mux {
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pins = "gpio26", "gpio27";
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function = "qup05";
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};
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config {
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pins = "gpio26", "gpio27";
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drive-strength = <2>;
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bias-pull-up;
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};
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};
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qupv3_se5_i2c_sleep: qupv3_se5_i2c_sleep {
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||||
mux {
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||||
pins = "gpio26", "gpio27";
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||||
function = "gpio";
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||||
};
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||||
|
||||
config {
|
||||
pins = "gpio26", "gpio27";
|
||||
drive-strength = <2>;
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||||
bias-disable;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
qupv3_se5_spi_pins: qupv3_se5_spi_pins {
|
||||
qupv3_se5_spi_active: qupv3_se5_spi_active {
|
||||
mux {
|
||||
pins = "gpio26", "gpio27",
|
||||
"gpio28", "gpio29";
|
||||
function = "qup05";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio26", "gpio27",
|
||||
"gpio28", "gpio29";
|
||||
drive-strength = <6>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
qupv3_se5_spi_sleep: qupv3_se5_spi_sleep {
|
||||
mux {
|
||||
pins = "gpio26", "gpio27",
|
||||
"gpio28", "gpio29";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio26", "gpio27",
|
||||
"gpio28", "gpio29";
|
||||
drive-strength = <6>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
qupv3_se6_i2c_pins: qupv3_se6_i2c_pins {
|
||||
qupv3_se6_i2c_active: qupv3_se6_i2c_active {
|
||||
mux {
|
||||
pins = "gpio24", "gpio25";
|
||||
function = "qup06";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio24", "gpio25";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
qupv3_se6_i2c_sleep: qupv3_se6_i2c_sleep {
|
||||
mux {
|
||||
pins = "gpio24", "gpio25";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio24", "gpio25";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
qupv3_se6_spi_pins: qupv3_se6_spi_pins {
|
||||
qupv3_se6_spi_active: qupv3_se6_spi_active {
|
||||
mux {
|
||||
pins = "gpio24", "gpio25",
|
||||
"gpio30", "gpio31";
|
||||
function = "qup06";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio24", "gpio25",
|
||||
"gpio30", "gpio31";
|
||||
drive-strength = <6>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
qupv3_se6_spi_sleep: qupv3_se6_spi_sleep {
|
||||
mux {
|
||||
pins = "gpio24", "gpio25",
|
||||
"gpio30", "gpio31";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio24", "gpio25",
|
||||
"gpio30", "gpio31";
|
||||
drive-strength = <6>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
qupv3_se7_i2c_pins_a: qupv3_se7_i2c_pins_a {
|
||||
qupv3_se7_i2c_active_L0_a: qupv3_se7_i2c_active_L0_a {
|
||||
mux {
|
||||
pins = "gpio101";
|
||||
function = "QUP0_L0";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio101";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
qupv3_se7_i2c_active_L1_a: qupv3_se7_i2c_active_L1_a {
|
||||
mux {
|
||||
pins = "gpio102";
|
||||
function = "QUP0_L1";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio102";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
qupv3_se7_i2c_sleep_a: qupv3_se7_i2c_sleep_a {
|
||||
mux {
|
||||
pins = "gpio101", "gpio102";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio101", "gpio102";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
qupv3_se7_spi_pins_a: qupv3_se7_spi_pins_a {
|
||||
qupv3_se7_spi_active_L0_a: qupv3_se7_spi_active_L0_a {
|
||||
mux {
|
||||
pins = "gpio101";
|
||||
function = "QUP0_L0";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio101";
|
||||
drive-strength = <6>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
qupv3_se7_spi_active_L1_a: qupv3_se7_spi_active_L1_a {
|
||||
mux {
|
||||
pins = "gpio102";
|
||||
function = "QUP0_L1";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio102";
|
||||
drive-strength = <6>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
qupv3_se7_spi_active_L2_a: qupv3_se7_spi_active_L2_a {
|
||||
mux {
|
||||
pins = "gpio104";
|
||||
function = "QUP0_L2";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio104";
|
||||
drive-strength = <6>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
qupv3_se7_spi_active_L3_a: qupv3_se7_spi_active_L3_a {
|
||||
mux {
|
||||
pins = "gpio105";
|
||||
function = "QUP0_L3";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio105";
|
||||
drive-strength = <6>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
qupv3_se7_spi_sleep_a: qupv3_se7_spi_sleep_a {
|
||||
mux {
|
||||
pins = "gpio101", "gpio102",
|
||||
"gpio104", "gpio105";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio101", "gpio102",
|
||||
"gpio104", "gpio105";
|
||||
drive-strength = <6>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
qupv3_se7_i2c_pins_b: qupv3_se7_i2c_pins_b {
|
||||
qupv3_se7_i2c_active_L0_b: qupv3_se7_i2c_active_L0_b {
|
||||
mux {
|
||||
pins = "gpio104";
|
||||
function = "QUP0_L0";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio104";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
qupv3_se7_i2c_active_L1_b: qupv3_se7_i2c_active_L1_b {
|
||||
mux {
|
||||
pins = "gpio105";
|
||||
function = "QUP0_L1";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio105";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
qupv3_se7_i2c_sleep_b: qupv3_se7_i2c_sleep_b {
|
||||
mux {
|
||||
pins = "gpio104", "gpio105";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio104", "gpio105";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
qupv3_se7_spi_pins_b: qupv3_se7_spi_pins_b {
|
||||
qupv3_se7_spi_active_L0_b: qupv3_se7_spi_active_L0_b {
|
||||
mux {
|
||||
pins = "gpio104";
|
||||
function = "QUP0_L0";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio104";
|
||||
drive-strength = <6>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
qupv3_se7_spi_active_L1_b: qupv3_se7_spi_active_L1_b {
|
||||
mux {
|
||||
pins = "gpio105";
|
||||
function = "QUP0_L1";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio105";
|
||||
drive-strength = <6>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
qupv3_se7_spi_active_L2_b: qupv3_se7_spi_active_L2_b {
|
||||
mux {
|
||||
pins = "gpio101";
|
||||
function = "QUP0_L2";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio101";
|
||||
drive-strength = <6>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
qupv3_se7_spi_active_L3_b: qupv3_se7_spi_active_L3_b {
|
||||
mux {
|
||||
pins = "gpio102";
|
||||
function = "QUP0_L3";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio102";
|
||||
drive-strength = <6>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
qupv3_se7_spi_sleep_b: qupv3_se7_spi_sleep_b {
|
||||
mux {
|
||||
pins = "gpio104", "gpio105",
|
||||
"gpio101", "gpio102";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio104", "gpio105",
|
||||
"gpio101", "gpio102";
|
||||
drive-strength = <6>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
qupv3_se5_4uart_pins: qupv3_se5_4uart_pins {
|
||||
qupv3_se5_default_ctsrtsrx:
|
||||
qupv3_se5_default_ctsrtsrx {
|
||||
mux {
|
||||
pins = "gpio26", "gpio27", "gpio79";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio26", "gpio27", "gpio79";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
|
||||
qupv3_se5_default_tx: qupv3_se5_default_tx {
|
||||
mux {
|
||||
pins = "gpio28";
|
||||
function = "gpio";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio28";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
|
||||
qupv3_se5_ctsrx: qupv3_se5_ctsrx {
|
||||
mux {
|
||||
pins = "gpio26", "gpio79";
|
||||
function = "qup05";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio26", "gpio79";
|
||||
drive-strength = <2>;
|
||||
bias-disable;
|
||||
};
|
||||
};
|
||||
|
||||
qupv3_se5_rts: qupv3_se5_rts {
|
||||
mux {
|
||||
pins = "gpio27";
|
||||
function = "qup05";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio27";
|
||||
drive-strength = <2>;
|
||||
bias-pull-down;
|
||||
};
|
||||
};
|
||||
|
||||
qupv3_se5_tx: qupv3_se5_tx {
|
||||
mux {
|
||||
pins = "gpio28";
|
||||
function = "qup05";
|
||||
};
|
||||
|
||||
config {
|
||||
pins = "gpio28";
|
||||
drive-strength = <2>;
|
||||
bias-pull-up;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
481
qcom/monaco-qupv3.dtsi
Normal file
481
qcom/monaco-qupv3.dtsi
Normal file
|
|
@ -0,0 +1,481 @@
|
|||
#include <dt-bindings/interconnect/qcom,monaco.h>
|
||||
|
||||
&soc {
|
||||
/* QUPv3 SE Instances
|
||||
* Qup0 0: SE 0
|
||||
* Qup0 1: SE 1
|
||||
* Qup0 2: SE 2
|
||||
* Qup0 3: SE 3
|
||||
* Qup0 4: SE 4
|
||||
* Qup0 5: SE 5
|
||||
* Qup0 6: SE 6
|
||||
* Qup0 7: SE 7
|
||||
*/
|
||||
|
||||
/* QUPv3_0 wrapper instance */
|
||||
qupv3_0: qcom,qupv3_0_geni_se@4ac0000 {
|
||||
compatible = "qcom,qupv3-geni-se";
|
||||
reg = <0x4ac0000 0x2000>;
|
||||
qcom,msm-bus,num-paths = <2>;
|
||||
qcom,msm-bus,vectors-bus-ids =
|
||||
<MASTER_QUP_CORE_0 SLAVE_QUP_CORE_0>,
|
||||
<MASTER_QUP_0 SLAVE_EBI_CH0>;
|
||||
qcom,vote-for-bw;
|
||||
iommus = <&apps_smmu 0xe3 0x0>;
|
||||
qcom,iommu-dma-addr-pool = <0x40000000 0xc0000000>;
|
||||
qcom,iommu-geometry = <0x40000000 0x10000000>;
|
||||
qcom,iommu-dma = "fastmap";
|
||||
status = "ok"
|
||||
};
|
||||
|
||||
/* GPI Instance */
|
||||
gpi_dma0: qcom,gpi-dma@4a00000 {
|
||||
compatible = "qcom,gpi-dma";
|
||||
#dma-cells = <5>;
|
||||
reg = <0x4a00000 0x60000>;
|
||||
reg-names = "gpi-top";
|
||||
iommus = <&apps_smmu 0xf6 0x0>;
|
||||
qcom,max-num-gpii = <12>;
|
||||
interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>;
|
||||
qcom,gpii-mask = <0xf>;
|
||||
qcom,ev-factor = <2>;
|
||||
qcom,iommu-dma-addr-pool = <0x100000 0x100000>;
|
||||
qcom,gpi-ee-offset = <0x10000>;
|
||||
status = "ok"
|
||||
};
|
||||
|
||||
/* Debug UART Instance */
|
||||
qupv3_se6_2uart: qcom,qup_uart@4a98000 {
|
||||
compatible = "qcom,msm-geni-console";
|
||||
reg = <0x4a98000 0x4000>;
|
||||
reg-names = "se_phys";
|
||||
interrupts = <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "se-clk", "m-ahb", "s-ahb";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se6_2uart_active>;
|
||||
pinctrl-1 = <&qupv3_se6_2uart_sleep>;
|
||||
qcom,wrapper-core = <&qupv3_0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se0_i2c: i2c@4a80000 {
|
||||
compatible = "qcom,i2c-geni";
|
||||
reg = <0x4a80000 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "se-clk", "m-ahb", "s-ahb";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se0_i2c_active>;
|
||||
pinctrl-1 = <&qupv3_se0_i2c_sleep>;
|
||||
dmas = <&gpi_dma0 0 0 3 64 0>,
|
||||
<&gpi_dma0 1 0 3 64 0>;
|
||||
dma-names = "tx", "rx";
|
||||
qcom,wrapper-core = <&qupv3_0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se0_spi: spi@4a80000 {
|
||||
compatible = "qcom,spi-geni";
|
||||
reg = <0x4a80000 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg-names = "se_phys";
|
||||
interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "se-clk", "m-ahb", "s-ahb";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se0_spi_active>;
|
||||
pinctrl-1 = <&qupv3_se0_spi_sleep>;
|
||||
dmas = <&gpi_dma0 0 0 1 64 0>,
|
||||
<&gpi_dma0 1 0 1 64 0>;
|
||||
dma-names = "tx", "rx";
|
||||
spi-max-frequency = <50000000>;
|
||||
qcom,wrapper-core = <&qupv3_0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se1_i2c: i2c@4a84000 {
|
||||
compatible = "qcom,i2c-geni";
|
||||
reg = <0x4a84000 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "se-clk", "m-ahb", "s-ahb";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se1_i2c_active>;
|
||||
pinctrl-1 = <&qupv3_se1_i2c_sleep>;
|
||||
dmas = <&gpi_dma0 0 1 3 64 0>,
|
||||
<&gpi_dma0 1 1 3 64 0>;
|
||||
dma-names = "tx", "rx";
|
||||
qcom,wrapper-core = <&qupv3_0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se1_spi: spi@4a84000 {
|
||||
compatible = "qcom,spi-geni";
|
||||
reg = <0x4a84000 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg-names = "se_phys";
|
||||
interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "se-clk", "m-ahb", "s-ahb";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se1_spi_active>;
|
||||
pinctrl-1 = <&qupv3_se1_spi_sleep>;
|
||||
dmas = <&gpi_dma0 0 1 1 64 0>,
|
||||
<&gpi_dma0 1 1 1 64 0>;
|
||||
dma-names = "tx", "rx";
|
||||
spi-max-frequency = <50000000>;
|
||||
qcom,wrapper-core = <&qupv3_0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se2_i2c: i2c@4a88000 {
|
||||
compatible = "qcom,i2c-geni";
|
||||
reg = <0x4a88000 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "se-clk", "m-ahb", "s-ahb";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se2_i2c_active>;
|
||||
pinctrl-1 = <&qupv3_se2_i2c_sleep>;
|
||||
dmas = <&gpi_dma0 0 2 3 64 0>,
|
||||
<&gpi_dma0 1 2 3 64 0>;
|
||||
dma-names = "tx", "rx";
|
||||
qcom,wrapper-core = <&qupv3_0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se2_spi: spi@4a88000 {
|
||||
compatible = "qcom,spi-geni";
|
||||
reg = <0x4a88000 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg-names = "se_phys";
|
||||
interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "se-clk", "m-ahb", "s-ahb";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se2_spi_active>;
|
||||
pinctrl-1 = <&qupv3_se2_spi_sleep>;
|
||||
dmas = <&gpi_dma0 0 2 1 64 0>,
|
||||
<&gpi_dma0 1 2 1 64 0>;
|
||||
dma-names = "tx", "rx";
|
||||
spi-max-frequency = <50000000>;
|
||||
qcom,wrapper-core = <&qupv3_0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se3_i2c: i2c@4a8c000 {
|
||||
compatible = "qcom,i2c-geni";
|
||||
reg = <0x4a8c000 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "se-clk", "m-ahb", "s-ahb";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se3_i2c_active>;
|
||||
pinctrl-1 = <&qupv3_se3_i2c_sleep>;
|
||||
dmas = <&gpi_dma0 0 3 3 64 0>,
|
||||
<&gpi_dma0 1 3 3 64 0>;
|
||||
dma-names = "tx", "rx";
|
||||
qcom,wrapper-core = <&qupv3_0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se3_spi: spi@4a8c000 {
|
||||
compatible = "qcom,spi-geni";
|
||||
reg = <0x4a8c000 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg-names = "se_phys";
|
||||
interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "se-clk", "m-ahb", "s-ahb";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se3_spi_active>;
|
||||
pinctrl-1 = <&qupv3_se3_spi_sleep>;
|
||||
dmas = <&gpi_dma0 0 3 1 64 0>,
|
||||
<&gpi_dma0 1 3 1 64 0>;
|
||||
dma-names = "tx", "rx";
|
||||
spi-max-frequency = <50000000>;
|
||||
qcom,wrapper-core = <&qupv3_0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se4_i2c: i2c@4a90000 {
|
||||
compatible = "qcom,i2c-geni";
|
||||
reg = <0x4a90000 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "se-clk", "m-ahb", "s-ahb";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se4_i2c_active>;
|
||||
pinctrl-1 = <&qupv3_se4_i2c_sleep>;
|
||||
dmas = <&gpi_dma0 0 4 3 64 0>,
|
||||
<&gpi_dma0 1 4 3 64 0>;
|
||||
dma-names = "tx", "rx";
|
||||
qcom,wrapper-core = <&qupv3_0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se4_spi: spi@4a90000 {
|
||||
compatible = "qcom,spi-geni";
|
||||
reg = <0x4a90000 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg-names = "se_phys";
|
||||
interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "se-clk", "m-ahb", "s-ahb";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se4_spi_active>;
|
||||
pinctrl-1 = <&qupv3_se4_spi_sleep>;
|
||||
dmas = <&gpi_dma0 0 4 1 64 0>,
|
||||
<&gpi_dma0 1 4 1 64 0>;
|
||||
dma-names = "tx", "rx";
|
||||
spi-max-frequency = <50000000>;
|
||||
qcom,wrapper-core = <&qupv3_0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se5_i2c: i2c@4a94000 {
|
||||
compatible = "qcom,i2c-geni";
|
||||
reg = <0x4a94000 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "se-clk", "m-ahb", "s-ahb";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se5_i2c_active>;
|
||||
pinctrl-1 = <&qupv3_se5_i2c_sleep>;
|
||||
dmas = <&gpi_dma0 0 5 3 64 0>,
|
||||
<&gpi_dma0 1 5 3 64 0>;
|
||||
dma-names = "tx", "rx";
|
||||
qcom,wrapper-core = <&qupv3_0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se5_spi: spi@4a94000 {
|
||||
compatible = "qcom,spi-geni";
|
||||
reg = <0x4a94000 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg-names = "se_phys";
|
||||
interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "se-clk", "m-ahb", "s-ahb";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se5_spi_active>;
|
||||
pinctrl-1 = <&qupv3_se5_spi_sleep>;
|
||||
dmas = <&gpi_dma0 0 5 1 64 0>,
|
||||
<&gpi_dma0 1 5 1 64 0>;
|
||||
dma-names = "tx", "rx";
|
||||
spi-max-frequency = <50000000>;
|
||||
qcom,wrapper-core = <&qupv3_0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se6_i2c: i2c@4a98000 {
|
||||
compatible = "qcom,i2c-geni";
|
||||
reg = <0x4a98000 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "se-clk", "m-ahb", "s-ahb";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se6_i2c_active>;
|
||||
pinctrl-1 = <&qupv3_se6_i2c_sleep>;
|
||||
dmas = <&gpi_dma0 0 6 3 64 0>,
|
||||
<&gpi_dma0 1 6 3 64 0>;
|
||||
dma-names = "tx", "rx";
|
||||
qcom,wrapper-core = <&qupv3_0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se6_spi: spi@4a98000 {
|
||||
compatible = "qcom,spi-geni";
|
||||
reg = <0x4a98000 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg-names = "se_phys";
|
||||
interrupts = <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "se-clk", "m-ahb", "s-ahb";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se6_spi_active>;
|
||||
pinctrl-1 = <&qupv3_se6_spi_sleep>;
|
||||
dmas = <&gpi_dma0 0 6 1 64 0>,
|
||||
<&gpi_dma0 1 6 1 64 0>;
|
||||
dma-names = "tx", "rx";
|
||||
spi-max-frequency = <50000000>;
|
||||
qcom,wrapper-core = <&qupv3_0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se7_i2c_a: i2c@4a9c000 {
|
||||
compatible = "qcom,i2c-geni";
|
||||
reg = <0x4a9c000 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "se-clk", "m-ahb", "s-ahb";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se7_i2c_active_L0_a
|
||||
&qupv3_se7_i2c_active_L1_a>;
|
||||
pinctrl-1 = <&qupv3_se7_i2c_sleep_a>;
|
||||
dmas = <&gpi_dma0 0 7 3 64 0>,
|
||||
<&gpi_dma0 1 7 3 64 0>;
|
||||
dma-names = "tx", "rx";
|
||||
qcom,wrapper-core = <&qupv3_0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se7_spi_a: spi@4a9c000 {
|
||||
compatible = "qcom,spi-geni";
|
||||
reg = <0x4a9c000 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg-names = "se_phys";
|
||||
interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "se-clk", "m-ahb", "s-ahb";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se7_spi_active_L0_a
|
||||
&qupv3_se7_spi_active_L1_a &qupv3_se7_spi_active_L2_a
|
||||
&qupv3_se7_spi_active_L3_a>;
|
||||
pinctrl-1 = <&qupv3_se7_spi_sleep_a>;
|
||||
dmas = <&gpi_dma0 0 7 1 64 0>,
|
||||
<&gpi_dma0 1 7 1 64 0>;
|
||||
dma-names = "tx", "rx";
|
||||
spi-max-frequency = <75000000>;
|
||||
qcom,wrapper-core = <&qupv3_0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se7_i2c_b: i2c@4a9c000 {
|
||||
compatible = "qcom,i2c-geni";
|
||||
reg = <0x4a9c000 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "se-clk", "m-ahb", "s-ahb";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se7_i2c_active_L0_b
|
||||
&qupv3_se7_i2c_active_L1_b>;
|
||||
pinctrl-1 = <&qupv3_se7_i2c_sleep_b>;
|
||||
dmas = <&gpi_dma0 0 7 3 64 0>,
|
||||
<&gpi_dma0 1 7 3 64 0>;
|
||||
dma-names = "tx", "rx";
|
||||
qcom,wrapper-core = <&qupv3_0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qupv3_se7_spi_b: spi@4a9c000 {
|
||||
compatible = "qcom,spi-geni";
|
||||
reg = <0x4a9c000 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg-names = "se_phys";
|
||||
interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "se-clk", "m-ahb", "s-ahb";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qupv3_se7_spi_active_L0_b
|
||||
&qupv3_se7_spi_active_L1_b &qupv3_se7_spi_active_L2_b
|
||||
&qupv3_se7_spi_active_L3_b>;
|
||||
pinctrl-1 = <&qupv3_se7_spi_sleep_b>;
|
||||
dmas = <&gpi_dma0 0 7 1 64 0>,
|
||||
<&gpi_dma0 1 7 1 64 0>;
|
||||
dma-names = "tx", "rx";
|
||||
spi-max-frequency = <75000000>;
|
||||
qcom,wrapper-core = <&qupv3_0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/* HS UART Instance */
|
||||
qupv3_se5_4uart: qcom,qup_uart@4a94000 {
|
||||
compatible = "qcom,msm-geni-serial-hs";
|
||||
reg = <0x4a94000 0x4000>;
|
||||
reg-names = "se_phys";
|
||||
interrupts-extended = <&intc GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&tlmm 29 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-names = "se-clk", "m-ahb", "s-ahb";
|
||||
clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
|
||||
<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
|
||||
pinctrl-names = "default", "active", "sleep";
|
||||
pinctrl-0 = <&qupv3_se5_default_ctsrtsrx>,
|
||||
<&qupv3_se5_default_tx>;
|
||||
pinctrl-1 = <&qupv3_se5_ctsrx>, <&qupv3_se5_rts>,
|
||||
<&qupv3_se5_tx>;
|
||||
pinctrl-2 = <&qupv3_se5_ctsrx>, <&qupv3_se5_rts>,
|
||||
<&qupv3_se5_tx>;
|
||||
qcom,wakeup-byte = <0xFD>;
|
||||
qcom,wrapper-core = <&qupv3_0>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
|
@ -17,6 +17,11 @@
|
|||
#size-cells = <2>;
|
||||
memory { device_type = "memory"; reg = <0 0 0 0>; };
|
||||
|
||||
aliases {
|
||||
serial0 = &qupv3_se6_2uart;
|
||||
hsuart0 = &qupv3_se5_4uart;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -820,6 +825,11 @@
|
|||
#include "msm-arm-smmu-monaco.dtsi"
|
||||
#include "monaco-ion.dtsi"
|
||||
#include "monaco-gdsc.dtsi"
|
||||
#include "monaco-qupv3.dtsi"
|
||||
|
||||
&qupv3_se6_2uart {
|
||||
status = "ok"
|
||||
};
|
||||
|
||||
&gcc_camss_top_gdsc {
|
||||
status = "ok"
|
||||
|
|
|
|||
Loading…
Reference in a new issue