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mtd: spi-nor: cadence-quadspi: Add new binding to enable loop-back circuit

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Cadence QSPI IP has a adapted loop-back circuit which can be enabled by
setting BYPASS field to 0 in READCAPTURE register. It enables use of
QSPI return clock to latch the data rather than the internal QSPI
reference clock. For high speed operations, adapted loop-back circuit
using QSPI return clock helps to increase data valid window.

Add DT parameter cdns,rclk-en to help enable adapted loop-back circuit
for boards which do have QSPI return clock provided. Update binding
documentation for the same.

Signed-off-by: Vignesh R <[email protected]>
Acked-by: Rob Herring <[email protected]>
Acked-by: Marek Vasut <[email protected]>
Signed-off-by: Cyrille Pitchen <[email protected]>
This commit is contained in:
Vignesh R 2017-10-03 10:49:22 +05:30 • committed by Cyrille Pitchen
commit 00df263560
1 changed files with 3 additions and 0 deletions
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3
Documentation/devicetree/bindings/mtd/cadence-quadspi.txt
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@ -16,6 +16,9 @@ Required properties:
Optional properties:
- cdns,is-decoded-cs : Flag to indicate whether decoder is used or not.
- cdns,rclk-en : Flag to indicate that QSPI return clock is used to latch
the read data rather than the QSPI clock. Make sure that QSPI return
clock is populated on the board before using this property.
Optional subnodes:
Subnodes of the Cadence Quad SPI controller are spi slave nodes with additional