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Merge git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6

Browse source 
* git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6: (28 commits)
  mm/hugetlb.c must #include <asm/io.h>
  video: Fix up hp6xx driver build regressions.
  sh: defconfig updates.
  sh: Kill off stray mach-rsk7203 reference.
  serial: sh-sci: Fix up SH7760/SH7780/SH7785 early printk regression.
  sh: Move out individual boards without mach groups.
  sh: Make sure AT_SYSINFO_EHDR is exposed to userspace in asm/auxvec.h.
  sh: Allow SH-3 and SH-5 to use common headers.
  sh: Provide common CPU headers, prune the SH-2 and SH-2A directories.
  sh/maple: clean maple bus code
  sh: More header path fixups for mach dir refactoring.
  sh: Move out the solution engine headers to arch/sh/include/mach-se/
  sh: I2C fix for AP325RXA and Migo-R
  sh: Shuffle the board directories in to mach groups.
  sh: dma-sh: Fix up dreamcast dma.h mach path.
  sh: Switch KBUILD_DEFCONFIG to shx3_defconfig.
  sh: Add ARCH_DEFCONFIG entries for sh and sh64.
  sh: Fix compile error of Solution Engine
  sh: Proper __put_user_asm() size mismatch fix.
  sh: Stub in a dummy ENTRY_OFFSET for uImage offset calculation.
  ...
This commit is contained in:
Linus Torvalds 2008-08-01 10:53:43 -07:00
commit 00e9028a95
420 changed files with 3357 additions and 2942 deletions
Download patch file Download diff file Expand all files Collapse all files

3
include/asm-sh/.gitignore vendored
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cpu
mach
machtypes.h

8
include/asm-sh/Kbuild
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include include/asm-generic/Kbuild.asm
header-y += cpu-features.h
unifdef-y += unistd_32.h
unifdef-y += unistd_64.h
unifdef-y += posix_types_32.h
unifdef-y += posix_types_64.h

20
include/asm-sh/a.out.h
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#ifndef __ASM_SH_A_OUT_H
#define __ASM_SH_A_OUT_H
struct exec
{
unsigned long a_info; /* Use macros N_MAGIC, etc for access */
unsigned a_text; /* length of text, in bytes */
unsigned a_data; /* length of data, in bytes */
unsigned a_bss; /* length of uninitialized data area for file, in bytes */
unsigned a_syms; /* length of symbol table data in file, in bytes */
unsigned a_entry; /* start address */
unsigned a_trsize; /* length of relocation info for text, in bytes */
unsigned a_drsize; /* length of relocation info for data, in bytes */
};
#define N_TRSIZE(a) ((a).a_trsize)
#define N_DRSIZE(a) ((a).a_drsize)
#define N_SYMSIZE(a) ((a).a_syms)
#endif /* __ASM_SH_A_OUT_H */

13
include/asm-sh/adc.h
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#ifndef __ASM_ADC_H
#define __ASM_ADC_H
#ifdef __KERNEL__
/*
* Copyright (C) 2004 Andriy Skulysh
*/
#include <asm/cpu/adc.h>
int adc_single(unsigned int channel);
#endif /* __KERNEL__ */
#endif /* __ASM_ADC_H */

53
include/asm-sh/addrspace.h
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/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1999 by Kaz Kojima
*
* Defitions for the address spaces of the SH CPUs.
*/
#ifndef __ASM_SH_ADDRSPACE_H
#define __ASM_SH_ADDRSPACE_H
#ifdef __KERNEL__
#include <asm/cpu/addrspace.h>
/* If this CPU supports segmentation, hook up the helpers */
#ifdef P1SEG
/*
[ P0/U0 (virtual) ] 0x00000000 <------ User space
[ P1 (fixed) cached ] 0x80000000 <------ Kernel space
[ P2 (fixed) non-cachable] 0xA0000000 <------ Physical access
[ P3 (virtual) cached] 0xC0000000 <------ vmalloced area
[ P4 control ] 0xE0000000
*/
/* Returns the privileged segment base of a given address */
#define PXSEG(a) (((unsigned long)(a)) & 0xe0000000)
/* Returns the physical address of a PnSEG (n=1,2) address */
#define PHYSADDR(a) (((unsigned long)(a)) & 0x1fffffff)
#ifdef CONFIG_29BIT
/*
* Map an address to a certain privileged segment
*/
#define P1SEGADDR(a) \
((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P1SEG))
#define P2SEGADDR(a) \
((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P2SEG))
#define P3SEGADDR(a) \
((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P3SEG))
#define P4SEGADDR(a) \
((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P4SEG))
#endif /* 29BIT */
#endif /* P1SEG */
/* Check if an address can be reached in 29 bits */
#define IS_29BIT(a) (((unsigned long)(a)) < 0x20000000)
#endif /* __KERNEL__ */
#endif /* __ASM_SH_ADDRSPACE_H */

169
include/asm-sh/atomic-grb.h
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#ifndef __ASM_SH_ATOMIC_GRB_H
#define __ASM_SH_ATOMIC_GRB_H
static inline void atomic_add(int i, atomic_t *v)
{
int tmp;
__asm__ __volatile__ (
" .align 2 \n\t"
" mova 1f, r0 \n\t" /* r0 = end point */
" mov r15, r1 \n\t" /* r1 = saved sp */
" mov #-6, r15 \n\t" /* LOGIN: r15 = size */
" mov.l @%1, %0 \n\t" /* load old value */
" add %2, %0 \n\t" /* add */
" mov.l %0, @%1 \n\t" /* store new value */
"1: mov r1, r15 \n\t" /* LOGOUT */
: "=&r" (tmp),
"+r" (v)
: "r" (i)
: "memory" , "r0", "r1");
}
static inline void atomic_sub(int i, atomic_t *v)
{
int tmp;
__asm__ __volatile__ (
" .align 2 \n\t"
" mova 1f, r0 \n\t" /* r0 = end point */
" mov r15, r1 \n\t" /* r1 = saved sp */
" mov #-6, r15 \n\t" /* LOGIN: r15 = size */
" mov.l @%1, %0 \n\t" /* load old value */
" sub %2, %0 \n\t" /* sub */
" mov.l %0, @%1 \n\t" /* store new value */
"1: mov r1, r15 \n\t" /* LOGOUT */
: "=&r" (tmp),
"+r" (v)
: "r" (i)
: "memory" , "r0", "r1");
}
static inline int atomic_add_return(int i, atomic_t *v)
{
int tmp;
__asm__ __volatile__ (
" .align 2 \n\t"
" mova 1f, r0 \n\t" /* r0 = end point */
" mov r15, r1 \n\t" /* r1 = saved sp */
" mov #-6, r15 \n\t" /* LOGIN: r15 = size */
" mov.l @%1, %0 \n\t" /* load old value */
" add %2, %0 \n\t" /* add */
" mov.l %0, @%1 \n\t" /* store new value */
"1: mov r1, r15 \n\t" /* LOGOUT */
: "=&r" (tmp),
"+r" (v)
: "r" (i)
: "memory" , "r0", "r1");
return tmp;
}
static inline int atomic_sub_return(int i, atomic_t *v)
{
int tmp;
__asm__ __volatile__ (
" .align 2 \n\t"
" mova 1f, r0 \n\t" /* r0 = end point */
" mov r15, r1 \n\t" /* r1 = saved sp */
" mov #-6, r15 \n\t" /* LOGIN: r15 = size */
" mov.l @%1, %0 \n\t" /* load old value */
" sub %2, %0 \n\t" /* sub */
" mov.l %0, @%1 \n\t" /* store new value */
"1: mov r1, r15 \n\t" /* LOGOUT */
: "=&r" (tmp),
"+r" (v)
: "r" (i)
: "memory", "r0", "r1");
return tmp;
}
static inline void atomic_clear_mask(unsigned int mask, atomic_t *v)
{
int tmp;
unsigned int _mask = ~mask;
__asm__ __volatile__ (
" .align 2 \n\t"
" mova 1f, r0 \n\t" /* r0 = end point */
" mov r15, r1 \n\t" /* r1 = saved sp */
" mov #-6, r15 \n\t" /* LOGIN: r15 = size */
" mov.l @%1, %0 \n\t" /* load old value */
" and %2, %0 \n\t" /* add */
" mov.l %0, @%1 \n\t" /* store new value */
"1: mov r1, r15 \n\t" /* LOGOUT */
: "=&r" (tmp),
"+r" (v)
: "r" (_mask)
: "memory" , "r0", "r1");
}
static inline void atomic_set_mask(unsigned int mask, atomic_t *v)
{
int tmp;
__asm__ __volatile__ (
" .align 2 \n\t"
" mova 1f, r0 \n\t" /* r0 = end point */
" mov r15, r1 \n\t" /* r1 = saved sp */
" mov #-6, r15 \n\t" /* LOGIN: r15 = size */
" mov.l @%1, %0 \n\t" /* load old value */
" or %2, %0 \n\t" /* or */
" mov.l %0, @%1 \n\t" /* store new value */
"1: mov r1, r15 \n\t" /* LOGOUT */
: "=&r" (tmp),
"+r" (v)
: "r" (mask)
: "memory" , "r0", "r1");
}
static inline int atomic_cmpxchg(atomic_t *v, int old, int new)
{
int ret;
__asm__ __volatile__ (
" .align 2 \n\t"
" mova 1f, r0 \n\t"
" nop \n\t"
" mov r15, r1 \n\t"
" mov #-8, r15 \n\t"
" mov.l @%1, %0 \n\t"
" cmp/eq %2, %0 \n\t"
" bf 1f \n\t"
" mov.l %3, @%1 \n\t"
"1: mov r1, r15 \n\t"
: "=&r" (ret)
: "r" (v), "r" (old), "r" (new)
: "memory" , "r0", "r1" , "t");
return ret;
}
static inline int atomic_add_unless(atomic_t *v, int a, int u)
{
int ret;
unsigned long tmp;
__asm__ __volatile__ (
" .align 2 \n\t"
" mova 1f, r0 \n\t"
" nop \n\t"
" mov r15, r1 \n\t"
" mov #-12, r15 \n\t"
" mov.l @%2, %1 \n\t"
" mov %1, %0 \n\t"
" cmp/eq %4, %0 \n\t"
" bt/s 1f \n\t"
" add %3, %1 \n\t"
" mov.l %1, @%2 \n\t"
"1: mov r1, r15 \n\t"
: "=&r" (ret), "=&r" (tmp)
: "r" (v), "r" (a), "r" (u)
: "memory" , "r0", "r1" , "t");
return ret != u;
}
#endif /* __ASM_SH_ATOMIC_GRB_H */

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include/asm-sh/atomic-irq.h
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#ifndef __ASM_SH_ATOMIC_IRQ_H
#define __ASM_SH_ATOMIC_IRQ_H
/*
* To get proper branch prediction for the main line, we must branch
* forward to code at the end of this object's .text section, then
* branch back to restart the operation.
*/
static inline void atomic_add(int i, atomic_t *v)
{
unsigned long flags;
local_irq_save(flags);
*(long *)v += i;
local_irq_restore(flags);
}
static inline void atomic_sub(int i, atomic_t *v)
{
unsigned long flags;
local_irq_save(flags);
*(long *)v -= i;
local_irq_restore(flags);
}
static inline int atomic_add_return(int i, atomic_t *v)
{
unsigned long temp, flags;
local_irq_save(flags);
temp = *(long *)v;
temp += i;
*(long *)v = temp;
local_irq_restore(flags);
return temp;
}
static inline int atomic_sub_return(int i, atomic_t *v)
{
unsigned long temp, flags;
local_irq_save(flags);
temp = *(long *)v;
temp -= i;
*(long *)v = temp;
local_irq_restore(flags);
return temp;
}
static inline void atomic_clear_mask(unsigned int mask, atomic_t *v)
{
unsigned long flags;
local_irq_save(flags);
*(long *)v &= ~mask;
local_irq_restore(flags);
}
static inline void atomic_set_mask(unsigned int mask, atomic_t *v)
{
unsigned long flags;
local_irq_save(flags);
*(long *)v |= mask;
local_irq_restore(flags);
}
#endif /* __ASM_SH_ATOMIC_IRQ_H */

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include/asm-sh/atomic-llsc.h
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#ifndef __ASM_SH_ATOMIC_LLSC_H
#define __ASM_SH_ATOMIC_LLSC_H
/*
* To get proper branch prediction for the main line, we must branch
* forward to code at the end of this object's .text section, then
* branch back to restart the operation.
*/
static inline void atomic_add(int i, atomic_t *v)
{
unsigned long tmp;
__asm__ __volatile__ (
"1: movli.l @%2, %0 ! atomic_add \n"
" add %1, %0 \n"
" movco.l %0, @%2 \n"
" bf 1b \n"
: "=&z" (tmp)
: "r" (i), "r" (&v->counter)
: "t");
}
static inline void atomic_sub(int i, atomic_t *v)
{
unsigned long tmp;
__asm__ __volatile__ (
"1: movli.l @%2, %0 ! atomic_sub \n"
" sub %1, %0 \n"
" movco.l %0, @%2 \n"
" bf 1b \n"
: "=&z" (tmp)
: "r" (i), "r" (&v->counter)
: "t");
}
/*
* SH-4A note:
*
* We basically get atomic_xxx_return() for free compared with
* atomic_xxx(). movli.l/movco.l require r0 due to the instruction
* encoding, so the retval is automatically set without having to
* do any special work.
*/
static inline int atomic_add_return(int i, atomic_t *v)
{
unsigned long temp;
__asm__ __volatile__ (
"1: movli.l @%2, %0 ! atomic_add_return \n"
" add %1, %0 \n"
" movco.l %0, @%2 \n"
" bf 1b \n"
" synco \n"
: "=&z" (temp)
: "r" (i), "r" (&v->counter)
: "t");
return temp;
}
static inline int atomic_sub_return(int i, atomic_t *v)
{
unsigned long temp;
__asm__ __volatile__ (
"1: movli.l @%2, %0 ! atomic_sub_return \n"
" sub %1, %0 \n"
" movco.l %0, @%2 \n"
" bf 1b \n"
" synco \n"
: "=&z" (temp)
: "r" (i), "r" (&v->counter)
: "t");
return temp;
}
static inline void atomic_clear_mask(unsigned int mask, atomic_t *v)
{
unsigned long tmp;
__asm__ __volatile__ (
"1: movli.l @%2, %0 ! atomic_clear_mask \n"
" and %1, %0 \n"
" movco.l %0, @%2 \n"
" bf 1b \n"
: "=&z" (tmp)
: "r" (~mask), "r" (&v->counter)
: "t");
}
static inline void atomic_set_mask(unsigned int mask, atomic_t *v)
{
unsigned long tmp;
__asm__ __volatile__ (
"1: movli.l @%2, %0 ! atomic_set_mask \n"
" or %1, %0 \n"
" movco.l %0, @%2 \n"
" bf 1b \n"
: "=&z" (tmp)
: "r" (mask), "r" (&v->counter)
: "t");
}
#endif /* __ASM_SH_ATOMIC_LLSC_H */

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include/asm-sh/atomic.h
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#ifndef __ASM_SH_ATOMIC_H
#define __ASM_SH_ATOMIC_H
/*
* Atomic operations that C can't guarantee us. Useful for
* resource counting etc..
*
*/
typedef struct { volatile int counter; } atomic_t;
#define ATOMIC_INIT(i) ( (atomic_t) { (i) } )
#define atomic_read(v) ((v)->counter)
#define atomic_set(v,i) ((v)->counter = (i))
#include <linux/compiler.h>
#include <asm/system.h>
#if defined(CONFIG_GUSA_RB)
#include <asm/atomic-grb.h>
#elif defined(CONFIG_CPU_SH4A)
#include <asm/atomic-llsc.h>
#else
#include <asm/atomic-irq.h>
#endif
#define atomic_add_negative(a, v) (atomic_add_return((a), (v)) < 0)
#define atomic_dec_return(v) atomic_sub_return(1,(v))
#define atomic_inc_return(v) atomic_add_return(1,(v))
/*
* atomic_inc_and_test - increment and test
* @v: pointer of type atomic_t
*
* Atomically increments @v by 1
* and returns true if the result is zero, or false for all
* other cases.
*/
#define atomic_inc_and_test(v) (atomic_inc_return(v) == 0)
#define atomic_sub_and_test(i,v) (atomic_sub_return((i), (v)) == 0)
#define atomic_dec_and_test(v) (atomic_sub_return(1, (v)) == 0)
#define atomic_inc(v) atomic_add(1,(v))
#define atomic_dec(v) atomic_sub(1,(v))
#ifndef CONFIG_GUSA_RB
static inline int atomic_cmpxchg(atomic_t *v, int old, int new)
{
int ret;
unsigned long flags;
local_irq_save(flags);
ret = v->counter;
if (likely(ret == old))
v->counter = new;
local_irq_restore(flags);
return ret;
}
static inline int atomic_add_unless(atomic_t *v, int a, int u)
{
int ret;
unsigned long flags;
local_irq_save(flags);
ret = v->counter;
if (ret != u)
v->counter += a;
local_irq_restore(flags);
return ret != u;
}
#endif
#define atomic_xchg(v, new) (xchg(&((v)->counter), new))
#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)
/* Atomic operations are already serializing on SH */
#define smp_mb__before_atomic_dec() barrier()
#define smp_mb__after_atomic_dec() barrier()
#define smp_mb__before_atomic_inc() barrier()
#define smp_mb__after_atomic_inc() barrier()
#include <asm-generic/atomic.h>
#endif /* __ASM_SH_ATOMIC_H */

36
include/asm-sh/auxvec.h
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#ifndef __ASM_SH_AUXVEC_H
#define __ASM_SH_AUXVEC_H
/*
* Architecture-neutral AT_ values in 0-17, leave some room
* for more of them.
*/
/*
* This entry gives some information about the FPU initialization
* performed by the kernel.
*/
#define AT_FPUCW 18 /* Used FPU control word. */
#ifdef CONFIG_VSYSCALL
/*
* Only define this in the vsyscall case, the entry point to
* the vsyscall page gets placed here. The kernel will attempt
* to build a gate VMA we don't care about otherwise..
*/
#define AT_SYSINFO_EHDR 33
#endif
/*
* More complete cache descriptions than AT_[DIU]CACHEBSIZE. If the
* value is -1, then the cache doesn't exist. Otherwise:
*
* bit 0-3: Cache set-associativity; 0 means fully associative.
* bit 4-7: Log2 of cacheline size.
* bit 8-31: Size of the entire cache >> 8.
*/
#define AT_L1I_CACHESHAPE 34
#define AT_L1D_CACHESHAPE 35
#define AT_L2_CACHESHAPE 36
#endif /* __ASM_SH_AUXVEC_H */

169
include/asm-sh/bitops-grb.h
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#ifndef __ASM_SH_BITOPS_GRB_H
#define __ASM_SH_BITOPS_GRB_H
static inline void set_bit(int nr, volatile void * addr)
{
int mask;
volatile unsigned int *a = addr;
unsigned long tmp;
a += nr >> 5;
mask = 1 << (nr & 0x1f);
__asm__ __volatile__ (
" .align 2 \n\t"
" mova 1f, r0 \n\t" /* r0 = end point */
" mov r15, r1 \n\t" /* r1 = saved sp */
" mov #-6, r15 \n\t" /* LOGIN: r15 = size */
" mov.l @%1, %0 \n\t" /* load old value */
" or %2, %0 \n\t" /* or */
" mov.l %0, @%1 \n\t" /* store new value */
"1: mov r1, r15 \n\t" /* LOGOUT */
: "=&r" (tmp),
"+r" (a)
: "r" (mask)
: "memory" , "r0", "r1");
}
static inline void clear_bit(int nr, volatile void * addr)
{
int mask;
volatile unsigned int *a = addr;
unsigned long tmp;
a += nr >> 5;
mask = ~(1 << (nr & 0x1f));
__asm__ __volatile__ (
" .align 2 \n\t"
" mova 1f, r0 \n\t" /* r0 = end point */
" mov r15, r1 \n\t" /* r1 = saved sp */
" mov #-6, r15 \n\t" /* LOGIN: r15 = size */
" mov.l @%1, %0 \n\t" /* load old value */
" and %2, %0 \n\t" /* and */
" mov.l %0, @%1 \n\t" /* store new value */
"1: mov r1, r15 \n\t" /* LOGOUT */
: "=&r" (tmp),
"+r" (a)
: "r" (mask)
: "memory" , "r0", "r1");
}
static inline void change_bit(int nr, volatile void * addr)
{
int mask;
volatile unsigned int *a = addr;
unsigned long tmp;
a += nr >> 5;
mask = 1 << (nr & 0x1f);
__asm__ __volatile__ (
" .align 2 \n\t"
" mova 1f, r0 \n\t" /* r0 = end point */
" mov r15, r1 \n\t" /* r1 = saved sp */
" mov #-6, r15 \n\t" /* LOGIN: r15 = size */
" mov.l @%1, %0 \n\t" /* load old value */
" xor %2, %0 \n\t" /* xor */
" mov.l %0, @%1 \n\t" /* store new value */
"1: mov r1, r15 \n\t" /* LOGOUT */
: "=&r" (tmp),
"+r" (a)
: "r" (mask)
: "memory" , "r0", "r1");
}
static inline int test_and_set_bit(int nr, volatile void * addr)
{
int mask, retval;
volatile unsigned int *a = addr;
unsigned long tmp;
a += nr >> 5;
mask = 1 << (nr & 0x1f);
__asm__ __volatile__ (
" .align 2 \n\t"
" mova 1f, r0 \n\t" /* r0 = end point */
" mov r15, r1 \n\t" /* r1 = saved sp */
" mov #-14, r15 \n\t" /* LOGIN: r15 = size */
" mov.l @%2, %0 \n\t" /* load old value */
" mov %0, %1 \n\t"
" tst %1, %3 \n\t" /* T = ((*a & mask) == 0) */
" mov #-1, %1 \n\t" /* retvat = -1 */
" negc %1, %1 \n\t" /* retval = (mask & *a) != 0 */
" or %3, %0 \n\t"
" mov.l %0, @%2 \n\t" /* store new value */
"1: mov r1, r15 \n\t" /* LOGOUT */
: "=&r" (tmp),
"=&r" (retval),
"+r" (a)
: "r" (mask)
: "memory" , "r0", "r1" ,"t");
return retval;
}
static inline int test_and_clear_bit(int nr, volatile void * addr)
{
int mask, retval,not_mask;
volatile unsigned int *a = addr;
unsigned long tmp;
a += nr >> 5;
mask = 1 << (nr & 0x1f);
not_mask = ~mask;
__asm__ __volatile__ (
" .align 2 \n\t"
" mova 1f, r0 \n\t" /* r0 = end point */
" mov r15, r1 \n\t" /* r1 = saved sp */
" mov #-14, r15 \n\t" /* LOGIN */
" mov.l @%2, %0 \n\t" /* load old value */
" mov %0, %1 \n\t" /* %1 = *a */
" tst %1, %3 \n\t" /* T = ((*a & mask) == 0) */
" mov #-1, %1 \n\t" /* retvat = -1 */
" negc %1, %1 \n\t" /* retval = (mask & *a) != 0 */
" and %4, %0 \n\t"
" mov.l %0, @%2 \n\t" /* store new value */
"1: mov r1, r15 \n\t" /* LOGOUT */
: "=&r" (tmp),
"=&r" (retval),
"+r" (a)
: "r" (mask),
"r" (not_mask)
: "memory" , "r0", "r1", "t");
return retval;
}
static inline int test_and_change_bit(int nr, volatile void * addr)
{
int mask, retval;
volatile unsigned int *a = addr;
unsigned long tmp;
a += nr >> 5;
mask = 1 << (nr & 0x1f);
__asm__ __volatile__ (
" .align 2 \n\t"
" mova 1f, r0 \n\t" /* r0 = end point */
" mov r15, r1 \n\t" /* r1 = saved sp */
" mov #-14, r15 \n\t" /* LOGIN */
" mov.l @%2, %0 \n\t" /* load old value */
" mov %0, %1 \n\t" /* %1 = *a */
" tst %1, %3 \n\t" /* T = ((*a & mask) == 0) */
" mov #-1, %1 \n\t" /* retvat = -1 */
" negc %1, %1 \n\t" /* retval = (mask & *a) != 0 */
" xor %3, %0 \n\t"
" mov.l %0, @%2 \n\t" /* store new value */
"1: mov r1, r15 \n\t" /* LOGOUT */
: "=&r" (tmp),
"=&r" (retval),
"+r" (a)
: "r" (mask)
: "memory" , "r0", "r1", "t");
return retval;
}
#endif /* __ASM_SH_BITOPS_GRB_H */

91
include/asm-sh/bitops-irq.h
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@ -1,91 +0,0 @@
#ifndef __ASM_SH_BITOPS_IRQ_H
#define __ASM_SH_BITOPS_IRQ_H
static inline void set_bit(int nr, volatile void *addr)
{
int mask;
volatile unsigned int *a = addr;
unsigned long flags;
a += nr >> 5;
mask = 1 << (nr & 0x1f);
local_irq_save(flags);
*a |= mask;
local_irq_restore(flags);
}
static inline void clear_bit(int nr, volatile void *addr)
{
int mask;
volatile unsigned int *a = addr;
unsigned long flags;
a += nr >> 5;
mask = 1 << (nr & 0x1f);
local_irq_save(flags);
*a &= ~mask;
local_irq_restore(flags);
}
static inline void change_bit(int nr, volatile void *addr)
{
int mask;
volatile unsigned int *a = addr;
unsigned long flags;
a += nr >> 5;
mask = 1 << (nr & 0x1f);
local_irq_save(flags);
*a ^= mask;
local_irq_restore(flags);
}
static inline int test_and_set_bit(int nr, volatile void *addr)
{
int mask, retval;
volatile unsigned int *a = addr;
unsigned long flags;
a += nr >> 5;
mask = 1 << (nr & 0x1f);
local_irq_save(flags);
retval = (mask & *a) != 0;
*a |= mask;
local_irq_restore(flags);
return retval;
}
static inline int test_and_clear_bit(int nr, volatile void *addr)
{
int mask, retval;
volatile unsigned int *a = addr;
unsigned long flags;
a += nr >> 5;
mask = 1 << (nr & 0x1f);
local_irq_save(flags);
retval = (mask & *a) != 0;
*a &= ~mask;
local_irq_restore(flags);
return retval;
}
static inline int test_and_change_bit(int nr, volatile void *addr)
{
int mask, retval;
volatile unsigned int *a = addr;
unsigned long flags;
a += nr >> 5;
mask = 1 << (nr & 0x1f);
local_irq_save(flags);
retval = (mask & *a) != 0;
*a ^= mask;
local_irq_restore(flags);
return retval;
}
#endif /* __ASM_SH_BITOPS_IRQ_H */

103
include/asm-sh/bitops.h
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@ -1,103 +0,0 @@
#ifndef __ASM_SH_BITOPS_H
#define __ASM_SH_BITOPS_H
#ifdef __KERNEL__
#ifndef _LINUX_BITOPS_H
#error only <linux/bitops.h> can be included directly
#endif
#include <asm/system.h>
/* For __swab32 */
#include <asm/byteorder.h>
#ifdef CONFIG_GUSA_RB
#include <asm/bitops-grb.h>
#else
#include <asm/bitops-irq.h>
#endif
/*
* clear_bit() doesn't provide any barrier for the compiler.
*/
#define smp_mb__before_clear_bit() barrier()
#define smp_mb__after_clear_bit() barrier()
#include <asm-generic/bitops/non-atomic.h>
#ifdef CONFIG_SUPERH32
static inline unsigned long ffz(unsigned long word)
{
unsigned long result;
__asm__("1:\n\t"
"shlr %1\n\t"
"bt/s 1b\n\t"
" add #1, %0"
: "=r" (result), "=r" (word)
: "0" (~0L), "1" (word)
: "t");
return result;
}
/**
* __ffs - find first bit in word.
* @word: The word to search
*
* Undefined if no bit exists, so code should check against 0 first.
*/
static inline unsigned long __ffs(unsigned long word)
{
unsigned long result;
__asm__("1:\n\t"
"shlr %1\n\t"
"bf/s 1b\n\t"
" add #1, %0"
: "=r" (result), "=r" (word)
: "0" (~0L), "1" (word)
: "t");
return result;
}
#else
static inline unsigned long ffz(unsigned long word)
{
unsigned long result, __d2, __d3;
__asm__("gettr tr0, %2\n\t"
"pta $+32, tr0\n\t"
"andi %1, 1, %3\n\t"
"beq %3, r63, tr0\n\t"
"pta $+4, tr0\n"
"0:\n\t"
"shlri.l %1, 1, %1\n\t"
"addi %0, 1, %0\n\t"
"andi %1, 1, %3\n\t"
"beqi %3, 1, tr0\n"
"1:\n\t"
"ptabs %2, tr0\n\t"
: "=r" (result), "=r" (word), "=r" (__d2), "=r" (__d3)
: "0" (0L), "1" (word));
return result;
}
#include <asm-generic/bitops/__ffs.h>
#endif
#include <asm-generic/bitops/find.h>
#include <asm-generic/bitops/ffs.h>
#include <asm-generic/bitops/hweight.h>
#include <asm-generic/bitops/lock.h>
#include <asm-generic/bitops/sched.h>
#include <asm-generic/bitops/ext2-non-atomic.h>
#include <asm-generic/bitops/ext2-atomic.h>
#include <asm-generic/bitops/minix.h>
#include <asm-generic/bitops/fls.h>
#include <asm-generic/bitops/__fls.h>
#include <asm-generic/bitops/fls64.h>
#endif /* __KERNEL__ */
#endif /* __ASM_SH_BITOPS_H */

79
include/asm-sh/bug.h
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@ -1,79 +0,0 @@
#ifndef __ASM_SH_BUG_H
#define __ASM_SH_BUG_H
#define TRAPA_BUG_OPCODE 0xc33e /* trapa #0x3e */
#ifdef CONFIG_GENERIC_BUG
#define HAVE_ARCH_BUG
#define HAVE_ARCH_WARN_ON
/**
* _EMIT_BUG_ENTRY
* %1 - __FILE__
* %2 - __LINE__
* %3 - trap type
* %4 - sizeof(struct bug_entry)
*
* The trapa opcode itself sits in %0.
* The %O notation is used to avoid # generation.
*
* The offending file and line are encoded in the __bug_table section.
*/
#ifdef CONFIG_DEBUG_BUGVERBOSE
#define _EMIT_BUG_ENTRY \
"\t.pushsection __bug_table,\"a\"\n" \
"2:\t.long 1b, %O1\n" \
"\t.short %O2, %O3\n" \
"\t.org 2b+%O4\n" \
"\t.popsection\n"
#else
#define _EMIT_BUG_ENTRY \
"\t.pushsection __bug_table,\"a\"\n" \
"2:\t.long 1b\n" \
"\t.short %O3\n" \
"\t.org 2b+%O4\n" \
"\t.popsection\n"
#endif
#define BUG() \
do { \
__asm__ __volatile__ ( \
"1:\t.short %O0\n" \
_EMIT_BUG_ENTRY \
: \
: "n" (TRAPA_BUG_OPCODE), \
"i" (__FILE__), \
"i" (__LINE__), "i" (0), \
"i" (sizeof(struct bug_entry))); \
} while (0)
#define __WARN() \
do { \
__asm__ __volatile__ ( \
"1:\t.short %O0\n" \
_EMIT_BUG_ENTRY \
: \
: "n" (TRAPA_BUG_OPCODE), \
"i" (__FILE__), \
"i" (__LINE__), \
"i" (BUGFLAG_WARNING), \
"i" (sizeof(struct bug_entry))); \
} while (0)
#define WARN_ON(x) ({ \
int __ret_warn_on = !!(x); \
if (__builtin_constant_p(__ret_warn_on)) { \
if (__ret_warn_on) \
__WARN(); \
} else { \
if (unlikely(__ret_warn_on)) \
__WARN(); \
} \
unlikely(__ret_warn_on); \
})
#endif /* CONFIG_GENERIC_BUG */
#include <asm-generic/bug.h>
#endif /* __ASM_SH_BUG_H */

73
include/asm-sh/bugs.h
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@ -1,73 +0,0 @@
#ifndef __ASM_SH_BUGS_H
#define __ASM_SH_BUGS_H
/*
* This is included by init/main.c to check for architecture-dependent bugs.
*
* Needs:
* void check_bugs(void);
*/
/*
* I don't know of any Super-H bugs yet.
*/
#include <asm/processor.h>
static void __init check_bugs(void)
{
extern unsigned long loops_per_jiffy;
char *p = &init_utsname()->machine[2]; /* "sh" */
current_cpu_data.loops_per_jiffy = loops_per_jiffy;
switch (current_cpu_data.type) {
case CPU_SH7619:
*p++ = '2';
break;
case CPU_SH7203 ... CPU_MXG:
*p++ = '2';
*p++ = 'a';
break;
case CPU_SH7705 ... CPU_SH7729:
*p++ = '3';
break;
case CPU_SH7750 ... CPU_SH4_501:
*p++ = '4';
break;
case CPU_SH7763 ... CPU_SHX3:
*p++ = '4';
*p++ = 'a';
break;
case CPU_SH7343 ... CPU_SH7366:
*p++ = '4';
*p++ = 'a';
*p++ = 'l';
*p++ = '-';
*p++ = 'd';
*p++ = 's';
*p++ = 'p';
break;
case CPU_SH5_101 ... CPU_SH5_103:
*p++ = '6';
*p++ = '4';
break;
case CPU_SH_NONE:
/*
* Specifically use CPU_SH_NONE rather than default:,
* so we're able to have the compiler whine about
* unhandled enumerations.
*/
break;
}
printk("CPU: %s\n", get_cpu_subtype(&current_cpu_data));
#ifndef __LITTLE_ENDIAN__
/* 'eb' means 'Endian Big' */
*p++ = 'e';
*p++ = 'b';
#endif
*p = '\0';
}
#endif /* __ASM_SH_BUGS_H */

70
include/asm-sh/byteorder.h
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@ -1,70 +0,0 @@
#ifndef __ASM_SH_BYTEORDER_H
#define __ASM_SH_BYTEORDER_H
/*
* Copyright (C) 1999 Niibe Yutaka
* Copyright (C) 2000, 2001 Paolo Alberelli
*/
#include <linux/compiler.h>
#include <linux/types.h>
static inline __attribute_const__ __u32 ___arch__swab32(__u32 x)
{
__asm__(
#ifdef __SH5__
"byterev %0, %0\n\t"
"shari %0, 32, %0"
#else
"swap.b %0, %0\n\t"
"swap.w %0, %0\n\t"
"swap.b %0, %0"
#endif
: "=r" (x)
: "0" (x));
return x;
}
static inline __attribute_const__ __u16 ___arch__swab16(__u16 x)
{
__asm__(
#ifdef __SH5__
"byterev %0, %0\n\t"
"shari %0, 32, %0"
#else
"swap.b %0, %0"
#endif
: "=r" (x)
: "0" (x));
return x;
}
static inline __u64 ___arch__swab64(__u64 val)
{
union {
struct { __u32 a,b; } s;
__u64 u;
} v, w;
v.u = val;
w.s.b = ___arch__swab32(v.s.a);
w.s.a = ___arch__swab32(v.s.b);
return w.u;
}
#define __arch__swab64(x) ___arch__swab64(x)
#define __arch__swab32(x) ___arch__swab32(x)
#define __arch__swab16(x) ___arch__swab16(x)
#if !defined(__STRICT_ANSI__) || defined(__KERNEL__)
# define __BYTEORDER_HAS_U64__
# define __SWAB_64_THRU_32__
#endif
#ifdef __LITTLE_ENDIAN__
#include <linux/byteorder/little_endian.h>
#else
#include <linux/byteorder/big_endian.h>
#endif
#endif /* __ASM_SH_BYTEORDER_H */

51
include/asm-sh/cache.h
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@ -1,51 +0,0 @@
/* $Id: cache.h,v 1.6 2004/03/11 18:08:05 lethal Exp $
*
* include/asm-sh/cache.h
*
* Copyright 1999 (C) Niibe Yutaka
* Copyright 2002, 2003 (C) Paul Mundt
*/
#ifndef __ASM_SH_CACHE_H
#define __ASM_SH_CACHE_H
#ifdef __KERNEL__
#include <linux/init.h>
#include <asm/cpu/cache.h>
#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
#define __read_mostly __attribute__((__section__(".data.read_mostly")))
#ifndef __ASSEMBLY__
struct cache_info {
unsigned int ways; /* Number of cache ways */
unsigned int sets; /* Number of cache sets */
unsigned int linesz; /* Cache line size (bytes) */
unsigned int way_size; /* sets * line size */
/*
* way_incr is the address offset for accessing the next way
* in memory mapped cache array ops.
*/
unsigned int way_incr;
unsigned int entry_shift;
unsigned int entry_mask;
/*
* Compute a mask which selects the address bits which overlap between
* 1. those used to select the cache set during indexing
* 2. those in the physical page number.
*/
unsigned int alias_mask;
unsigned int n_aliases; /* Number of aliases */
unsigned long flags;
};
int __init detect_cpu_and_cache_system(void);
#endif /* __ASSEMBLY__ */
#endif /* __KERNEL__ */
#endif /* __ASM_SH_CACHE_H */

81
include/asm-sh/cacheflush.h
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#ifndef __ASM_SH_CACHEFLUSH_H
#define __ASM_SH_CACHEFLUSH_H
#ifdef __KERNEL__
#ifdef CONFIG_CACHE_OFF
/*
* Nothing to do when the cache is disabled, initial flush and explicit
* disabling is handled at CPU init time.
*
* See arch/sh/kernel/cpu/init.c:cache_init().
*/
#define p3_cache_init() do { } while (0)
#define flush_cache_all() do { } while (0)
#define flush_cache_mm(mm) do { } while (0)
#define flush_cache_dup_mm(mm) do { } while (0)
#define flush_cache_range(vma, start, end) do { } while (0)
#define flush_cache_page(vma, vmaddr, pfn) do { } while (0)
#define flush_dcache_page(page) do { } while (0)
#define flush_icache_range(start, end) do { } while (0)
#define flush_icache_page(vma,pg) do { } while (0)
#define flush_dcache_mmap_lock(mapping) do { } while (0)
#define flush_dcache_mmap_unlock(mapping) do { } while (0)
#define flush_cache_sigtramp(vaddr) do { } while (0)
#define flush_icache_user_range(vma,pg,adr,len) do { } while (0)
#define __flush_wback_region(start, size) do { (void)(start); } while (0)
#define __flush_purge_region(start, size) do { (void)(start); } while (0)
#define __flush_invalidate_region(start, size) do { (void)(start); } while (0)
#else
#include <asm/cpu/cacheflush.h>
/*
* Consistent DMA requires that the __flush_xxx() primitives must be set
* for any of the enabled non-coherent caches (most of the UP CPUs),
* regardless of PIPT or VIPT cache configurations.
*/
/* Flush (write-back only) a region (smaller than a page) */
extern void __flush_wback_region(void *start, int size);
/* Flush (write-back & invalidate) a region (smaller than a page) */
extern void __flush_purge_region(void *start, int size);
/* Flush (invalidate only) a region (smaller than a page) */
extern void __flush_invalidate_region(void *start, int size);
#endif
#define ARCH_HAS_FLUSH_KERNEL_DCACHE_PAGE
static inline void flush_kernel_dcache_page(struct page *page)
{
flush_dcache_page(page);
}
#if defined(CONFIG_CPU_SH4) && !defined(CONFIG_CACHE_OFF)
extern void copy_to_user_page(struct vm_area_struct *vma,
struct page *page, unsigned long vaddr, void *dst, const void *src,
unsigned long len);
extern void copy_from_user_page(struct vm_area_struct *vma,
struct page *page, unsigned long vaddr, void *dst, const void *src,
unsigned long len);
#else
#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
do { \
flush_cache_page(vma, vaddr, page_to_pfn(page));\
memcpy(dst, src, len); \
flush_icache_user_range(vma, page, vaddr, len); \
} while (0)
#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
do { \
flush_cache_page(vma, vaddr, page_to_pfn(page));\
memcpy(dst, src, len); \
} while (0)
#endif
#define flush_cache_vmap(start, end) flush_cache_all()
#define flush_cache_vunmap(start, end) flush_cache_all()
#define HAVE_ARCH_UNMAPPED_AREA
#endif /* __KERNEL__ */
#endif /* __ASM_SH_CACHEFLUSH_H */

5
include/asm-sh/checksum.h
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@ -1,5 +0,0 @@
#ifdef CONFIG_SUPERH32
# include "checksum_32.h"
#else
# include "checksum_64.h"
#endif

215
include/asm-sh/checksum_32.h
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@ -1,215 +0,0 @@
#ifndef __ASM_SH_CHECKSUM_H
#define __ASM_SH_CHECKSUM_H
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1999 by Kaz Kojima & Niibe Yutaka
*/
#include <linux/in6.h>
/*
* computes the checksum of a memory block at buff, length len,
* and adds in "sum" (32-bit)
*
* returns a 32-bit number suitable for feeding into itself
* or csum_tcpudp_magic
*
* this function must be called with even lengths, except
* for the last fragment, which may be odd
*
* it's best to have buff aligned on a 32-bit boundary
*/
asmlinkage __wsum csum_partial(const void *buff, int len, __wsum sum);
/*
* the same as csum_partial, but copies from src while it
* checksums, and handles user-space pointer exceptions correctly, when needed.
*
* here even more important to align src and dst on a 32-bit (or even
* better 64-bit) boundary
*/
asmlinkage __wsum csum_partial_copy_generic(const void *src, void *dst,
int len, __wsum sum,
int *src_err_ptr, int *dst_err_ptr);
/*
* Note: when you get a NULL pointer exception here this means someone
* passed in an incorrect kernel address to one of these functions.
*
* If you use these functions directly please don't forget the
* access_ok().
*/
static inline
__wsum csum_partial_copy_nocheck(const void *src, void *dst,
int len, __wsum sum)
{
return csum_partial_copy_generic(src, dst, len, sum, NULL, NULL);
}
static inline
__wsum csum_partial_copy_from_user(const void __user *src, void *dst,
int len, __wsum sum, int *err_ptr)
{
return csum_partial_copy_generic((__force const void *)src, dst,
len, sum, err_ptr, NULL);
}
/*
* Fold a partial checksum
*/
static inline __sum16 csum_fold(__wsum sum)
{
unsigned int __dummy;
__asm__("swap.w %0, %1\n\t"
"extu.w %0, %0\n\t"
"extu.w %1, %1\n\t"
"add %1, %0\n\t"
"swap.w %0, %1\n\t"
"add %1, %0\n\t"
"not %0, %0\n\t"
: "=r" (sum), "=&r" (__dummy)
: "0" (sum)
: "t");
return (__force __sum16)sum;
}
/*
* This is a version of ip_compute_csum() optimized for IP headers,
* which always checksum on 4 octet boundaries.
*
* i386 version by Jorge Cwik <jorge@laser.satlink.net>, adapted
* for linux by * Arnt Gulbrandsen.
*/
static inline __sum16 ip_fast_csum(const void *iph, unsigned int ihl)
{
unsigned int sum, __dummy0, __dummy1;
__asm__ __volatile__(
"mov.l @%1+, %0\n\t"
"mov.l @%1+, %3\n\t"
"add #-2, %2\n\t"
"clrt\n\t"
"1:\t"
"addc %3, %0\n\t"
"movt %4\n\t"
"mov.l @%1+, %3\n\t"
"dt %2\n\t"
"bf/s 1b\n\t"
" cmp/eq #1, %4\n\t"
"addc %3, %0\n\t"
"addc %2, %0" /* Here %2 is 0, add carry-bit */
/* Since the input registers which are loaded with iph and ihl
are modified, we must also specify them as outputs, or gcc
will assume they contain their original values. */
: "=r" (sum), "=r" (iph), "=r" (ihl), "=&r" (__dummy0), "=&z" (__dummy1)
: "1" (iph), "2" (ihl)
: "t", "memory");
return csum_fold(sum);
}
static inline __wsum csum_tcpudp_nofold(__be32 saddr, __be32 daddr,
unsigned short len,
unsigned short proto,
__wsum sum)
{
#ifdef __LITTLE_ENDIAN__
unsigned long len_proto = (proto + len) << 8;
#else
unsigned long len_proto = proto + len;
#endif
__asm__("clrt\n\t"
"addc %0, %1\n\t"
"addc %2, %1\n\t"
"addc %3, %1\n\t"
"movt %0\n\t"
"add %1, %0"
: "=r" (sum), "=r" (len_proto)
: "r" (daddr), "r" (saddr), "1" (len_proto), "0" (sum)
: "t");
return sum;
}
/*
* computes the checksum of the TCP/UDP pseudo-header
* returns a 16-bit checksum, already complemented
*/
static inline __sum16 csum_tcpudp_magic(__be32 saddr, __be32 daddr,
unsigned short len,
unsigned short proto,
__wsum sum)
{
return csum_fold(csum_tcpudp_nofold(saddr, daddr, len, proto, sum));
}
/*
* this routine is used for miscellaneous IP-like checksums, mainly
* in icmp.c
*/
static inline __sum16 ip_compute_csum(const void *buff, int len)
{
return csum_fold(csum_partial(buff, len, 0));
}
#define _HAVE_ARCH_IPV6_CSUM
static inline __sum16 csum_ipv6_magic(const struct in6_addr *saddr,
const struct in6_addr *daddr,
__u32 len, unsigned short proto,
__wsum sum)
{
unsigned int __dummy;
__asm__("clrt\n\t"
"mov.l @(0,%2), %1\n\t"
"addc %1, %0\n\t"
"mov.l @(4,%2), %1\n\t"
"addc %1, %0\n\t"
"mov.l @(8,%2), %1\n\t"
"addc %1, %0\n\t"
"mov.l @(12,%2), %1\n\t"
"addc %1, %0\n\t"
"mov.l @(0,%3), %1\n\t"
"addc %1, %0\n\t"
"mov.l @(4,%3), %1\n\t"
"addc %1, %0\n\t"
"mov.l @(8,%3), %1\n\t"
"addc %1, %0\n\t"
"mov.l @(12,%3), %1\n\t"
"addc %1, %0\n\t"
"addc %4, %0\n\t"
"addc %5, %0\n\t"
"movt %1\n\t"
"add %1, %0\n"
: "=r" (sum), "=&r" (__dummy)
: "r" (saddr), "r" (daddr),
"r" (htonl(len)), "r" (htonl(proto)), "0" (sum)
: "t");
return csum_fold(sum);
}
/*
* Copy and checksum to user
*/
#define HAVE_CSUM_COPY_USER
static inline __wsum csum_and_copy_to_user(const void *src,
void __user *dst,
int len, __wsum sum,
int *err_ptr)
{
if (access_ok(VERIFY_WRITE, dst, len))
return csum_partial_copy_generic((__force const void *)src,
dst, len, sum, NULL, err_ptr);
if (len)
*err_ptr = -EFAULT;
return (__force __wsum)-1; /* invalid checksum */
}
#endif /* __ASM_SH_CHECKSUM_H */

78
include/asm-sh/checksum_64.h
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@ -1,78 +0,0 @@
#ifndef __ASM_SH_CHECKSUM_64_H
#define __ASM_SH_CHECKSUM_64_H
/*
* include/asm-sh/checksum_64.h
*
* Copyright (C) 2000, 2001 Paolo Alberelli
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
/*
* computes the checksum of a memory block at buff, length len,
* and adds in "sum" (32-bit)
*
* returns a 32-bit number suitable for feeding into itself
* or csum_tcpudp_magic
*
* this function must be called with even lengths, except
* for the last fragment, which may be odd
*
* it's best to have buff aligned on a 32-bit boundary
*/
asmlinkage __wsum csum_partial(const void *buff, int len, __wsum sum);
/*
* Note: when you get a NULL pointer exception here this means someone
* passed in an incorrect kernel address to one of these functions.
*
* If you use these functions directly please don't forget the
* access_ok().
*/
__wsum csum_partial_copy_nocheck(const void *src, void *dst, int len,
__wsum sum);
__wsum csum_partial_copy_from_user(const void __user *src, void *dst,
int len, __wsum sum, int *err_ptr);
static inline __sum16 csum_fold(__wsum csum)
{
u32 sum = (__force u32)csum;
sum = (sum & 0xffff) + (sum >> 16);
sum = (sum & 0xffff) + (sum >> 16);
return (__force __sum16)~sum;
}
__sum16 ip_fast_csum(const void *iph, unsigned int ihl);
__wsum csum_tcpudp_nofold(__be32 saddr, __be32 daddr,
unsigned short len, unsigned short proto,
__wsum sum);
/*
* computes the checksum of the TCP/UDP pseudo-header
* returns a 16-bit checksum, already complemented
*/
static inline __sum16 csum_tcpudp_magic(__be32 saddr, __be32 daddr,
unsigned short len,
unsigned short proto,
__wsum sum)
{
return csum_fold(csum_tcpudp_nofold(saddr,daddr,len,proto,sum));
}
/*
* this routine is used for miscellaneous IP-like checksums, mainly
* in icmp.c
*/
static inline __sum16 ip_compute_csum(const void *buff, int len)
{
return csum_fold(csum_partial(buff, len, 0));
}
#endif /* __ASM_SH_CHECKSUM_64_H */

97
include/asm-sh/clock.h
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@ -1,97 +0,0 @@
#ifndef __ASM_SH_CLOCK_H
#define __ASM_SH_CLOCK_H
#include <linux/kref.h>
#include <linux/list.h>
#include <linux/seq_file.h>
#include <linux/clk.h>
#include <linux/err.h>
struct clk;
struct clk_ops {
void (*init)(struct clk *clk);
void (*enable)(struct clk *clk);
void (*disable)(struct clk *clk);
void (*recalc)(struct clk *clk);
int (*set_rate)(struct clk *clk, unsigned long rate, int algo_id);
long (*round_rate)(struct clk *clk, unsigned long rate);
};
struct clk {
struct list_head node;
const char *name;
int id;
struct module *owner;
struct clk *parent;
struct clk_ops *ops;
struct kref kref;
unsigned long rate;
unsigned long flags;
unsigned long arch_flags;
};
#define CLK_ALWAYS_ENABLED (1 << 0)
#define CLK_RATE_PROPAGATES (1 << 1)
/* Should be defined by processor-specific code */
void arch_init_clk_ops(struct clk_ops **, int type);
/* arch/sh/kernel/cpu/clock.c */
int clk_init(void);
void clk_recalc_rate(struct clk *);
int clk_register(struct clk *);
void clk_unregister(struct clk *);
static inline int clk_always_enable(const char *id)
{
struct clk *clk;
int ret;
clk = clk_get(NULL, id);
if (IS_ERR(clk))
return PTR_ERR(clk);
ret = clk_enable(clk);
if (ret)
clk_put(clk);
return ret;
}
/* the exported API, in addition to clk_set_rate */
/**
* clk_set_rate_ex - set the clock rate for a clock source, with additional parameter
* @clk: clock source
* @rate: desired clock rate in Hz
* @algo_id: algorithm id to be passed down to ops->set_rate
*
* Returns success (0) or negative errno.
*/
int clk_set_rate_ex(struct clk *clk, unsigned long rate, int algo_id);
enum clk_sh_algo_id {
NO_CHANGE = 0,
IUS_N1_N1,
IUS_322,
IUS_522,
IUS_N11,
SB_N1,
SB3_N1,
SB3_32,
SB3_43,
SB3_54,
BP_N1,
IP_N1,
};
#endif /* __ASM_SH_CLOCK_H */

70
include/asm-sh/cmpxchg-grb.h
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@ -1,70 +0,0 @@
#ifndef __ASM_SH_CMPXCHG_GRB_H
#define __ASM_SH_CMPXCHG_GRB_H
static inline unsigned long xchg_u32(volatile u32 *m, unsigned long val)
{
unsigned long retval;
__asm__ __volatile__ (
" .align 2 \n\t"
" mova 1f, r0 \n\t" /* r0 = end point */
" nop \n\t"
" mov r15, r1 \n\t" /* r1 = saved sp */
" mov #-4, r15 \n\t" /* LOGIN */
" mov.l @%1, %0 \n\t" /* load old value */
" mov.l %2, @%1 \n\t" /* store new value */
"1: mov r1, r15 \n\t" /* LOGOUT */
: "=&r" (retval),
"+r" (m)
: "r" (val)
: "memory", "r0", "r1");
return retval;
}
static inline unsigned long xchg_u8(volatile u8 *m, unsigned long val)
{
unsigned long retval;
__asm__ __volatile__ (
" .align 2 \n\t"
" mova 1f, r0 \n\t" /* r0 = end point */
" mov r15, r1 \n\t" /* r1 = saved sp */
" mov #-6, r15 \n\t" /* LOGIN */
" mov.b @%1, %0 \n\t" /* load old value */
" extu.b %0, %0 \n\t" /* extend as unsigned */
" mov.b %2, @%1 \n\t" /* store new value */
"1: mov r1, r15 \n\t" /* LOGOUT */
: "=&r" (retval),
"+r" (m)
: "r" (val)
: "memory" , "r0", "r1");
return retval;
}
static inline unsigned long __cmpxchg_u32(volatile int *m, unsigned long old,
unsigned long new)
{
unsigned long retval;
__asm__ __volatile__ (
" .align 2 \n\t"
" mova 1f, r0 \n\t" /* r0 = end point */
" nop \n\t"
" mov r15, r1 \n\t" /* r1 = saved sp */
" mov #-8, r15 \n\t" /* LOGIN */
" mov.l @%1, %0 \n\t" /* load old value */
" cmp/eq %0, %2 \n\t"
" bf 1f \n\t" /* if not equal */
" mov.l %2, @%1 \n\t" /* store new value */
"1: mov r1, r15 \n\t" /* LOGOUT */
: "=&r" (retval),
"+r" (m)
: "r" (new)
: "memory" , "r0", "r1", "t");
return retval;
}
#endif /* __ASM_SH_CMPXCHG_GRB_H */

40
include/asm-sh/cmpxchg-irq.h
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@ -1,40 +0,0 @@
#ifndef __ASM_SH_CMPXCHG_IRQ_H
#define __ASM_SH_CMPXCHG_IRQ_H
static inline unsigned long xchg_u32(volatile u32 *m, unsigned long val)
{
unsigned long flags, retval;
local_irq_save(flags);
retval = *m;
*m = val;
local_irq_restore(flags);
return retval;
}
static inline unsigned long xchg_u8(volatile u8 *m, unsigned long val)
{
unsigned long flags, retval;
local_irq_save(flags);
retval = *m;
*m = val & 0xff;
local_irq_restore(flags);
return retval;
}
static inline unsigned long __cmpxchg_u32(volatile int *m, unsigned long old,
unsigned long new)
{
__u32 retval;
unsigned long flags;
local_irq_save(flags);
retval = *m;
if (retval == old)
*m = new;
local_irq_restore(flags); /* implies memory barrier */
return retval;
}
#endif /* __ASM_SH_CMPXCHG_IRQ_H */

25
include/asm-sh/cpu-features.h
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@ -1,25 +0,0 @@
#ifndef __ASM_SH_CPU_FEATURES_H
#define __ASM_SH_CPU_FEATURES_H
/*
* Processor flags
*
* Note: When adding a new flag, keep cpu_flags[] in
* arch/sh/kernel/setup.c in sync so symbolic name
* mapping of the processor flags has a chance of being
* reasonably accurate.
*
* These flags are also available through the ELF
* auxiliary vector as AT_HWCAP.
*/
#define CPU_HAS_FPU 0x0001 /* Hardware FPU support */
#define CPU_HAS_P2_FLUSH_BUG 0x0002 /* Need to flush the cache in P2 area */
#define CPU_HAS_MMU_PAGE_ASSOC 0x0004 /* SH3: TLB way selection bit support */
#define CPU_HAS_DSP 0x0008 /* SH-DSP: DSP support */
#define CPU_HAS_PERF_COUNTER 0x0010 /* Hardware performance counters */
#define CPU_HAS_PTEA 0x0020 /* PTEA register */
#define CPU_HAS_LLSC 0x0040 /* movli.l/movco.l */
#define CPU_HAS_L2_CACHE 0x0080 /* Secondary cache / URAM */
#define CPU_HAS_OP32 0x0100 /* 32-bit instruction support */
#endif /* __ASM_SH_CPU_FEATURES_H */

19
include/asm-sh/cpu-sh2/addrspace.h
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@ -1,19 +0,0 @@
/*
* Definitions for the address spaces of the SH-2 CPUs.
*
* Copyright (C) 2003 Paul Mundt
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#ifndef __ASM_CPU_SH2_ADDRSPACE_H
#define __ASM_CPU_SH2_ADDRSPACE_H
#define P0SEG 0x00000000
#define P1SEG 0x80000000
#define P2SEG 0xa0000000
#define P3SEG 0xc0000000
#define P4SEG 0xe0000000
#endif /* __ASM_CPU_SH2_ADDRSPACE_H */

41
include/asm-sh/cpu-sh2/cache.h
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@ -1,41 +0,0 @@
/*
* include/asm-sh/cpu-sh2/cache.h
*
* Copyright (C) 2003 Paul Mundt
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#ifndef __ASM_CPU_SH2_CACHE_H
#define __ASM_CPU_SH2_CACHE_H
#define L1_CACHE_SHIFT 4
#define SH_CACHE_VALID 1
#define SH_CACHE_UPDATED 2
#define SH_CACHE_COMBINED 4
#define SH_CACHE_ASSOC 8
#if defined(CONFIG_CPU_SUBTYPE_SH7619)
#define CCR 0xffffffec
#define CCR_CACHE_CE 0x01 /* Cache enable */
#define CCR_CACHE_WT 0x06 /* CCR[bit1=1,bit2=1] */
/* 0x00000000-0x7fffffff: Write-through */
/* 0x80000000-0x9fffffff: Write-back */
/* 0xc0000000-0xdfffffff: Write-through */
#define CCR_CACHE_CB 0x00 /* CCR[bit1=0,bit2=0] */
/* 0x00000000-0x7fffffff: Write-back */
/* 0x80000000-0x9fffffff: Write-through */
/* 0xc0000000-0xdfffffff: Write-back */
#define CCR_CACHE_CF 0x08 /* Cache invalidate */
#define CACHE_OC_ADDRESS_ARRAY 0xf0000000
#define CACHE_OC_DATA_ARRAY 0xf1000000
#define CCR_CACHE_ENABLE CCR_CACHE_CE
#define CCR_CACHE_INVALIDATE CCR_CACHE_CF
#endif
#endif /* __ASM_CPU_SH2_CACHE_H */

44
include/asm-sh/cpu-sh2/cacheflush.h
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@ -1,44 +0,0 @@
/*
* include/asm-sh/cpu-sh2/cacheflush.h
*
* Copyright (C) 2003 Paul Mundt
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#ifndef __ASM_CPU_SH2_CACHEFLUSH_H
#define __ASM_CPU_SH2_CACHEFLUSH_H
/*
* Cache flushing:
*
* - flush_cache_all() flushes entire cache
* - flush_cache_mm(mm) flushes the specified mm context's cache lines
* - flush_cache_dup mm(mm) handles cache flushing when forking
* - flush_cache_page(mm, vmaddr, pfn) flushes a single page
* - flush_cache_range(vma, start, end) flushes a range of pages
*
* - flush_dcache_page(pg) flushes(wback&invalidates) a page for dcache
* - flush_icache_range(start, end) flushes(invalidates) a range for icache
* - flush_icache_page(vma, pg) flushes(invalidates) a page for icache
*
* Caches are indexed (effectively) by physical address on SH-2, so
* we don't need them.
*/
#define flush_cache_all() do { } while (0)
#define flush_cache_mm(mm) do { } while (0)
#define flush_cache_dup_mm(mm) do { } while (0)
#define flush_cache_range(vma, start, end) do { } while (0)
#define flush_cache_page(vma, vmaddr, pfn) do { } while (0)
#define flush_dcache_page(page) do { } while (0)
#define flush_dcache_mmap_lock(mapping) do { } while (0)
#define flush_dcache_mmap_unlock(mapping) do { } while (0)
#define flush_icache_range(start, end) do { } while (0)
#define flush_icache_page(vma,pg) do { } while (0)
#define flush_icache_user_range(vma,pg,adr,len) do { } while (0)
#define flush_cache_sigtramp(vaddr) do { } while (0)
#define p3_cache_init() do { } while (0)
#endif /* __ASM_CPU_SH2_CACHEFLUSH_H */

23
include/asm-sh/cpu-sh2/dma.h
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@ -1,23 +0,0 @@
/*
* Definitions for the SH-2 DMAC.
*
* Copyright (C) 2003 Paul Mundt
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#ifndef __ASM_CPU_SH2_DMA_H
#define __ASM_CPU_SH2_DMA_H
#define SH_MAX_DMA_CHANNELS 2
#define SAR ((unsigned long[]){ 0xffffff80, 0xffffff90 })
#define DAR ((unsigned long[]){ 0xffffff84, 0xffffff94 })
#define DMATCR ((unsigned long[]){ 0xffffff88, 0xffffff98 })
#define CHCR ((unsigned long[]){ 0xfffffffc, 0xffffff9c })
#define DMAOR 0xffffffb0
#endif /* __ASM_CPU_SH2_DMA_H */

18
include/asm-sh/cpu-sh2/freq.h
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@ -1,18 +0,0 @@
/*
* include/asm-sh/cpu-sh2/freq.h
*
* Copyright (C) 2006 Yoshinori Sato
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#ifndef __ASM_CPU_SH2_FREQ_H
#define __ASM_CPU_SH2_FREQ_H
#if defined(CONFIG_CPU_SUBTYPE_SH7619)
#define FREQCR 0xf815ff80
#endif
#endif /* __ASM_CPU_SH2_FREQ_H */

16
include/asm-sh/cpu-sh2/mmu_context.h
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@ -1,16 +0,0 @@
/*
* include/asm-sh/cpu-sh2/mmu_context.h
*
* Copyright (C) 2003 Paul Mundt
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#ifndef __ASM_CPU_SH2_MMU_CONTEXT_H
#define __ASM_CPU_SH2_MMU_CONTEXT_H
/* No MMU */
#endif /* __ASM_CPU_SH2_MMU_CONTEXT_H */

8
include/asm-sh/cpu-sh2/rtc.h
View file

@ -1,8 +0,0 @@
#ifndef __ASM_SH_CPU_SH2_RTC_H
#define __ASM_SH_CPU_SH2_RTC_H
#define rtc_reg_size sizeof(u16)
#define RTC_BIT_INVERTED 0
#define RTC_DEF_CAPABILITIES 0UL
#endif /* __ASM_SH_CPU_SH2_RTC_H */

17
include/asm-sh/cpu-sh2/sigcontext.h
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@ -1,17 +0,0 @@
#ifndef __ASM_CPU_SH2_SIGCONTEXT_H
#define __ASM_CPU_SH2_SIGCONTEXT_H
struct sigcontext {
unsigned long oldmask;
/* CPU registers */
unsigned long sc_regs[16];
unsigned long sc_pc;
unsigned long sc_pr;
unsigned long sc_sr;
unsigned long sc_gbr;
unsigned long sc_mach;
unsigned long sc_macl;
};
#endif /* __ASM_CPU_SH2_SIGCONTEXT_H */

6
include/asm-sh/cpu-sh2/timer.h
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@ -1,6 +0,0 @@
#ifndef __ASM_CPU_SH2_TIMER_H
#define __ASM_CPU_SH2_TIMER_H
/* Nothing needed yet */
#endif /* __ASM_CPU_SH2_TIMER_H */

32
include/asm-sh/cpu-sh2/ubc.h
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@ -1,32 +0,0 @@
/*
* include/asm-sh/cpu-sh2/ubc.h
*
* Copyright (C) 2003 Paul Mundt
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#ifndef __ASM_CPU_SH2_UBC_H
#define __ASM_CPU_SH2_UBC_H
#define UBC_BARA 0xffffff40
#define UBC_BAMRA 0xffffff44
#define UBC_BBRA 0xffffff48
#define UBC_BARB 0xffffff60
#define UBC_BAMRB 0xffffff64
#define UBC_BBRB 0xffffff68
#define UBC_BDRB 0xffffff70
#define UBC_BDMRB 0xffffff74
#define UBC_BRCR 0xffffff78
/*
* We don't have any ASID changes to make in the UBC on the SH-2.
*
* Make these purposely invalid to track misuse.
*/
#define UBC_BASRA 0x00000000
#define UBC_BASRB 0x00000000
#endif /* __ASM_CPU_SH2_UBC_H */

69
include/asm-sh/cpu-sh2/watchdog.h
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@ -1,69 +0,0 @@
/*
* include/asm-sh/cpu-sh2/watchdog.h
*
* Copyright (C) 2002, 2003 Paul Mundt
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#ifndef __ASM_CPU_SH2_WATCHDOG_H
#define __ASM_CPU_SH2_WATCHDOG_H
/*
* More SH-2 brilliance .. its not good enough that we can't read
* and write the same sizes to WTCNT, now we have to read and write
* with different sizes at different addresses for WTCNT _and_ RSTCSR.
*
* At least on the bright side no one has managed to screw over WTCSR
* in this fashion .. yet.
*/
/* Register definitions */
#define WTCNT 0xfffffe80
#define WTCSR 0xfffffe80
#define RSTCSR 0xfffffe82
#define WTCNT_R (WTCNT + 1)
#define RSTCSR_R (RSTCSR + 1)
/* Bit definitions */
#define WTCSR_IOVF 0x80
#define WTCSR_WT 0x40
#define WTCSR_TME 0x20
#define WTCSR_RSTS 0x00
#define RSTCSR_RSTS 0x20
/**
* sh_wdt_read_rstcsr - Read from Reset Control/Status Register
*
* Reads back the RSTCSR value.
*/
static inline __u8 sh_wdt_read_rstcsr(void)
{
/*
* Same read/write brain-damage as for WTCNT here..
*/
return ctrl_inb(RSTCSR_R);
}
/**
* sh_wdt_write_csr - Write to Reset Control/Status Register
*
* @val: Value to write
*
* Writes the given value @val to the lower byte of the control/status
* register. The upper byte is set manually on each write.
*/
static inline void sh_wdt_write_rstcsr(__u8 val)
{
/*
* Note: Due to the brain-damaged nature of this register,
* we can't presently touch the WOVF bit, since the upper byte
* has to be swapped for this. So just leave it alone..
*/
ctrl_outw((WTCNT_HIGH << 8) | (__u16)val, RSTCSR);
}
#endif /* __ASM_CPU_SH2_WATCHDOG_H */

10
include/asm-sh/cpu-sh2a/addrspace.h
View file

@ -1,10 +0,0 @@
#ifndef __ASM_SH_CPU_SH2A_ADDRSPACE_H
#define __ASM_SH_CPU_SH2A_ADDRSPACE_H
#define P0SEG 0x00000000
#define P1SEG 0x00000000
#define P2SEG 0x20000000
#define P3SEG 0x00000000
#define P4SEG 0x80000000
#endif /* __ASM_SH_CPU_SH2A_ADDRSPACE_H */

40
include/asm-sh/cpu-sh2a/cache.h
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@ -1,40 +0,0 @@
/*
* include/asm-sh/cpu-sh2a/cache.h
*
* Copyright (C) 2004 Paul Mundt
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#ifndef __ASM_CPU_SH2A_CACHE_H
#define __ASM_CPU_SH2A_CACHE_H
#define L1_CACHE_SHIFT 4
#define SH_CACHE_VALID 1
#define SH_CACHE_UPDATED 2
#define SH_CACHE_COMBINED 4
#define SH_CACHE_ASSOC 8
#define CCR 0xfffc1000 /* CCR1 */
#define CCR2 0xfffc1004
/*
* Most of the SH-2A CCR1 definitions resemble the SH-4 ones. All others not
* listed here are reserved.
*/
#define CCR_CACHE_CB 0x0000 /* Hack */
#define CCR_CACHE_OCE 0x0001
#define CCR_CACHE_WT 0x0002
#define CCR_CACHE_OCI 0x0008 /* OCF */
#define CCR_CACHE_ICE 0x0100
#define CCR_CACHE_ICI 0x0800 /* ICF */
#define CACHE_IC_ADDRESS_ARRAY 0xf0000000
#define CACHE_OC_ADDRESS_ARRAY 0xf0800000
#define CCR_CACHE_ENABLE (CCR_CACHE_OCE | CCR_CACHE_ICE)
#define CCR_CACHE_INVALIDATE (CCR_CACHE_OCI | CCR_CACHE_ICI)
#endif /* __ASM_CPU_SH2A_CACHE_H */

1
include/asm-sh/cpu-sh2a/cacheflush.h
View file

@ -1 +0,0 @@
#include <asm/cpu-sh2/cacheflush.h>

1
include/asm-sh/cpu-sh2a/dma.h
View file

@ -1 +0,0 @@
#include <asm/cpu-sh2/dma.h>

16
include/asm-sh/cpu-sh2a/freq.h
View file

@ -1,16 +0,0 @@
/*
* include/asm-sh/cpu-sh2a/freq.h
*
* Copyright (C) 2006 Yoshinori Sato
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#ifndef __ASM_CPU_SH2A_FREQ_H
#define __ASM_CPU_SH2A_FREQ_H
#define FREQCR 0xfffe0010
#endif /* __ASM_CPU_SH2A_FREQ_H */

1
include/asm-sh/cpu-sh2a/mmu_context.h
View file

@ -1 +0,0 @@
#include <asm/cpu-sh2/mmu_context.h>

8
include/asm-sh/cpu-sh2a/rtc.h
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@ -1,8 +0,0 @@
#ifndef __ASM_SH_CPU_SH2A_RTC_H
#define __ASM_SH_CPU_SH2A_RTC_H
#define rtc_reg_size sizeof(u16)
#define RTC_BIT_INVERTED 0
#define RTC_DEF_CAPABILITIES RTC_CAP_4_DIGIT_YEAR
#endif /* __ASM_SH_CPU_SH2A_RTC_H */

1
include/asm-sh/cpu-sh2a/timer.h
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@ -1 +0,0 @@
#include <asm/cpu-sh2/timer.h>

1
include/asm-sh/cpu-sh2a/ubc.h
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@ -1 +0,0 @@
#include <asm/cpu-sh2/ubc.h>

1
include/asm-sh/cpu-sh2a/watchdog.h
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@ -1 +0,0 @@
#include <asm/cpu-sh2/watchdog.h>

28
include/asm-sh/cpu-sh3/adc.h
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@ -1,28 +0,0 @@
#ifndef __ASM_CPU_SH3_ADC_H
#define __ASM_CPU_SH3_ADC_H
/*
* Copyright (C) 2004 Andriy Skulysh
*/
#define ADDRAH 0xa4000080
#define ADDRAL 0xa4000082
#define ADDRBH 0xa4000084
#define ADDRBL 0xa4000086
#define ADDRCH 0xa4000088
#define ADDRCL 0xa400008a
#define ADDRDH 0xa400008c
#define ADDRDL 0xa400008e
#define ADCSR 0xa4000090
#define ADCSR_ADF 0x80
#define ADCSR_ADIE 0x40
#define ADCSR_ADST 0x20
#define ADCSR_MULTI 0x10
#define ADCSR_CKS 0x08
#define ADCSR_CH_MASK 0x07
#define ADCR 0xa4000092
#endif /* __ASM_CPU_SH3_ADC_H */

19
include/asm-sh/cpu-sh3/addrspace.h
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@ -1,19 +0,0 @@
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1999 by Kaz Kojima
*
* Defitions for the address spaces of the SH-3 CPUs.
*/
#ifndef __ASM_CPU_SH3_ADDRSPACE_H
#define __ASM_CPU_SH3_ADDRSPACE_H
#define P0SEG 0x00000000
#define P1SEG 0x80000000
#define P2SEG 0xa0000000
#define P3SEG 0xc0000000
#define P4SEG 0xe0000000
#endif /* __ASM_CPU_SH3_ADDRSPACE_H */

43
include/asm-sh/cpu-sh3/cache.h
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@ -1,43 +0,0 @@
/*
* include/asm-sh/cpu-sh3/cache.h
*
* Copyright (C) 1999 Niibe Yutaka
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#ifndef __ASM_CPU_SH3_CACHE_H
#define __ASM_CPU_SH3_CACHE_H
#define L1_CACHE_SHIFT 4
#define SH_CACHE_VALID 1
#define SH_CACHE_UPDATED 2
#define SH_CACHE_COMBINED 4
#define SH_CACHE_ASSOC 8
#define CCR 0xffffffec /* Address of Cache Control Register */
#define CCR_CACHE_CE 0x01 /* Cache Enable */
#define CCR_CACHE_WT 0x02 /* Write-Through (for P0,U0,P3) (else writeback) */
#define CCR_CACHE_CB 0x04 /* Write-Back (for P1) (else writethrough) */
#define CCR_CACHE_CF 0x08 /* Cache Flush */
#define CCR_CACHE_ORA 0x20 /* RAM mode */
#define CACHE_OC_ADDRESS_ARRAY 0xf0000000
#define CACHE_PHYSADDR_MASK 0x1ffffc00
#define CCR_CACHE_ENABLE CCR_CACHE_CE
#define CCR_CACHE_INVALIDATE CCR_CACHE_CF
#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
defined(CONFIG_CPU_SUBTYPE_SH7710) || \
defined(CONFIG_CPU_SUBTYPE_SH7720) || \
defined(CONFIG_CPU_SUBTYPE_SH7721)
#define CCR3_REG 0xa40000b4
#define CCR_CACHE_16KB 0x00010000
#define CCR_CACHE_32KB 0x00020000
#endif
#endif /* __ASM_CPU_SH3_CACHE_H */

70
include/asm-sh/cpu-sh3/cacheflush.h
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@ -1,70 +0,0 @@
/*
* include/asm-sh/cpu-sh3/cacheflush.h
*
* Copyright (C) 1999 Niibe Yutaka
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#ifndef __ASM_CPU_SH3_CACHEFLUSH_H
#define __ASM_CPU_SH3_CACHEFLUSH_H
/*
* Cache flushing:
*
* - flush_cache_all() flushes entire cache
* - flush_cache_mm(mm) flushes the specified mm context's cache lines
* - flush_cache_dup mm(mm) handles cache flushing when forking
* - flush_cache_page(mm, vmaddr, pfn) flushes a single page
* - flush_cache_range(vma, start, end) flushes a range of pages
*
* - flush_dcache_page(pg) flushes(wback&invalidates) a page for dcache
* - flush_icache_range(start, end) flushes(invalidates) a range for icache
* - flush_icache_page(vma, pg) flushes(invalidates) a page for icache
*
* Caches are indexed (effectively) by physical address on SH-3, so
* we don't need them.
*/
#if defined(CONFIG_SH7705_CACHE_32KB)
/* SH7705 is an SH3 processor with 32KB cache. This has alias issues like the
* SH4. Unlike the SH4 this is a unified cache so we need to do some work
* in mmap when 'exec'ing a new binary
*/
/* 32KB cache, 4kb PAGE sizes need to check bit 12 */
#define CACHE_ALIAS 0x00001000
#define PG_mapped PG_arch_1
void flush_cache_all(void);
void flush_cache_mm(struct mm_struct *mm);
#define flush_cache_dup_mm(mm) flush_cache_mm(mm)
void flush_cache_range(struct vm_area_struct *vma, unsigned long start,
unsigned long end);
void flush_cache_page(struct vm_area_struct *vma, unsigned long addr, unsigned long pfn);
void flush_dcache_page(struct page *pg);
void flush_icache_range(unsigned long start, unsigned long end);
void flush_icache_page(struct vm_area_struct *vma, struct page *page);
#else
#define flush_cache_all() do { } while (0)
#define flush_cache_mm(mm) do { } while (0)
#define flush_cache_dup_mm(mm) do { } while (0)
#define flush_cache_range(vma, start, end) do { } while (0)
#define flush_cache_page(vma, vmaddr, pfn) do { } while (0)
#define flush_dcache_page(page) do { } while (0)
#define flush_icache_range(start, end) do { } while (0)
#define flush_icache_page(vma,pg) do { } while (0)
#endif
#define flush_dcache_mmap_lock(mapping) do { } while (0)
#define flush_dcache_mmap_unlock(mapping) do { } while (0)
/* SH3 has unified cache so no special action needed here */
#define flush_cache_sigtramp(vaddr) do { } while (0)
#define flush_icache_user_range(vma,pg,adr,len) do { } while (0)
#define p3_cache_init() do { } while (0)
#endif /* __ASM_CPU_SH3_CACHEFLUSH_H */

41
include/asm-sh/cpu-sh3/dac.h
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@ -1,41 +0,0 @@
#ifndef __ASM_CPU_SH3_DAC_H
#define __ASM_CPU_SH3_DAC_H
/*
* Copyright (C) 2003 Andriy Skulysh
*/
#define DADR0 0xa40000a0
#define DADR1 0xa40000a2
#define DACR 0xa40000a4
#define DACR_DAOE1 0x80
#define DACR_DAOE0 0x40
#define DACR_DAE 0x20
static __inline__ void sh_dac_enable(int channel)
{
unsigned char v;
v = ctrl_inb(DACR);
if(channel) v |= DACR_DAOE1;
else v |= DACR_DAOE0;
ctrl_outb(v,DACR);
}
static __inline__ void sh_dac_disable(int channel)
{
unsigned char v;
v = ctrl_inb(DACR);
if(channel) v &= ~DACR_DAOE1;
else v &= ~DACR_DAOE0;
ctrl_outb(v,DACR);
}
static __inline__ void sh_dac_output(u8 value, int channel)
{
if(channel) ctrl_outb(value,DADR1);
else ctrl_outb(value,DADR0);
}
#endif /* __ASM_CPU_SH3_DAC_H */

51
include/asm-sh/cpu-sh3/dma.h
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@ -1,51 +0,0 @@
#ifndef __ASM_CPU_SH3_DMA_H
#define __ASM_CPU_SH3_DMA_H
#if defined(CONFIG_CPU_SUBTYPE_SH7720) || \
defined(CONFIG_CPU_SUBTYPE_SH7721)
#define SH_DMAC_BASE 0xa4010020
#else
#define SH_DMAC_BASE 0xa4000020
#endif
#if defined(CONFIG_CPU_SUBTYPE_SH7720) || defined(CONFIG_CPU_SUBTYPE_SH7709)
#define DMTE0_IRQ 48
#define DMTE1_IRQ 49
#define DMTE2_IRQ 50
#define DMTE3_IRQ 51
#define DMTE4_IRQ 76
#define DMTE5_IRQ 77
#endif
/* Definitions for the SuperH DMAC */
#define TM_BURST 0x00000020
#define TS_8 0x00000000
#define TS_16 0x00000008
#define TS_32 0x00000010
#define TS_128 0x00000018
#define CHCR_TS_MASK 0x18
#define CHCR_TS_SHIFT 3
#define DMAOR_INIT DMAOR_DME
/*
* The SuperH DMAC supports a number of transmit sizes, we list them here,
* with their respective values as they appear in the CHCR registers.
*/
enum {
XMIT_SZ_8BIT,
XMIT_SZ_16BIT,
XMIT_SZ_32BIT,
XMIT_SZ_128BIT,
};
static unsigned int ts_shift[] __maybe_unused = {
[XMIT_SZ_8BIT] = 0,
[XMIT_SZ_16BIT] = 1,
[XMIT_SZ_32BIT] = 2,
[XMIT_SZ_128BIT] = 4,
};
#endif /* __ASM_CPU_SH3_DMA_H */

27
include/asm-sh/cpu-sh3/freq.h
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@ -1,27 +0,0 @@
/*
* include/asm-sh/cpu-sh3/freq.h
*
* Copyright (C) 2002, 2003 Paul Mundt
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#ifndef __ASM_CPU_SH3_FREQ_H
#define __ASM_CPU_SH3_FREQ_H
#ifdef CONFIG_CPU_SUBTYPE_SH7712
#define FRQCR 0xA415FF80
#else
#define FRQCR 0xffffff80
#endif
#define MIN_DIVISOR_NR 0
#define MAX_DIVISOR_NR 4
#define FRQCR_CKOEN 0x0100
#define FRQCR_PLLEN 0x0080
#define FRQCR_PSTBY 0x0040
#endif /* __ASM_CPU_SH3_FREQ_H */

67
include/asm-sh/cpu-sh3/gpio.h
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@ -1,67 +0,0 @@
/*
* include/asm-sh/cpu-sh3/gpio.h
*
* Copyright (C) 2007 Markus Brunner, Mark Jonas
*
* Addresses for the Pin Function Controller
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#ifndef _CPU_SH3_GPIO_H
#define _CPU_SH3_GPIO_H
#if defined(CONFIG_CPU_SUBTYPE_SH7720) || \
defined(CONFIG_CPU_SUBTYPE_SH7721)
/* Control registers */
#define PORT_PACR 0xA4050100UL
#define PORT_PBCR 0xA4050102UL
#define PORT_PCCR 0xA4050104UL
#define PORT_PDCR 0xA4050106UL
#define PORT_PECR 0xA4050108UL
#define PORT_PFCR 0xA405010AUL
#define PORT_PGCR 0xA405010CUL
#define PORT_PHCR 0xA405010EUL
#define PORT_PJCR 0xA4050110UL
#define PORT_PKCR 0xA4050112UL
#define PORT_PLCR 0xA4050114UL
#define PORT_PMCR 0xA4050116UL
#define PORT_PPCR 0xA4050118UL
#define PORT_PRCR 0xA405011AUL
#define PORT_PSCR 0xA405011CUL
#define PORT_PTCR 0xA405011EUL
#define PORT_PUCR 0xA4050120UL
#define PORT_PVCR 0xA4050122UL
/* Data registers */
#define PORT_PADR 0xA4050140UL
/* Address of PORT_PBDR is wrong in the datasheet, see errata 2005-09-21 */
#define PORT_PBDR 0xA4050142UL
#define PORT_PCDR 0xA4050144UL
#define PORT_PDDR 0xA4050146UL
#define PORT_PEDR 0xA4050148UL
#define PORT_PFDR 0xA405014AUL
#define PORT_PGDR 0xA405014CUL
#define PORT_PHDR 0xA405014EUL
#define PORT_PJDR 0xA4050150UL
#define PORT_PKDR 0xA4050152UL
#define PORT_PLDR 0xA4050154UL
#define PORT_PMDR 0xA4050156UL
#define PORT_PPDR 0xA4050158UL
#define PORT_PRDR 0xA405015AUL
#define PORT_PSDR 0xA405015CUL
#define PORT_PTDR 0xA405015EUL
#define PORT_PUDR 0xA4050160UL
#define PORT_PVDR 0xA4050162UL
/* Pin Select Registers */
#define PORT_PSELA 0xA4050124UL
#define PORT_PSELB 0xA4050126UL
#define PORT_PSELC 0xA4050128UL
#define PORT_PSELD 0xA405012AUL
#endif
#endif

44
include/asm-sh/cpu-sh3/mmu_context.h
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@ -1,44 +0,0 @@
/*
* include/asm-sh/cpu-sh3/mmu_context.h
*
* Copyright (C) 1999 Niibe Yutaka
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#ifndef __ASM_CPU_SH3_MMU_CONTEXT_H
#define __ASM_CPU_SH3_MMU_CONTEXT_H
#define MMU_PTEH 0xFFFFFFF0 /* Page table entry register HIGH */
#define MMU_PTEL 0xFFFFFFF4 /* Page table entry register LOW */
#define MMU_TTB 0xFFFFFFF8 /* Translation table base register */
#define MMU_TEA 0xFFFFFFFC /* TLB Exception Address */
#define MMUCR 0xFFFFFFE0 /* MMU Control Register */
#define MMU_TLB_ADDRESS_ARRAY 0xF2000000
#define MMU_PAGE_ASSOC_BIT 0x80
#define MMU_NTLB_ENTRIES 128 /* for 7708 */
#define MMU_NTLB_WAYS 4
#define MMU_CONTROL_INIT 0x007 /* SV=0, TF=1, IX=1, AT=1 */
#define TRA 0xffffffd0
#define EXPEVT 0xffffffd4
#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
defined(CONFIG_CPU_SUBTYPE_SH7706) || \
defined(CONFIG_CPU_SUBTYPE_SH7707) || \
defined(CONFIG_CPU_SUBTYPE_SH7709) || \
defined(CONFIG_CPU_SUBTYPE_SH7710) || \
defined(CONFIG_CPU_SUBTYPE_SH7712) || \
defined(CONFIG_CPU_SUBTYPE_SH7720) || \
defined(CONFIG_CPU_SUBTYPE_SH7721)
#define INTEVT 0xa4000000 /* INTEVTE2(0xa4000000) */
#else
#define INTEVT 0xffffffd8
#endif
#endif /* __ASM_CPU_SH3_MMU_CONTEXT_H */

8
include/asm-sh/cpu-sh3/rtc.h
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@ -1,8 +0,0 @@
#ifndef __ASM_SH_CPU_SH3_RTC_H
#define __ASM_SH_CPU_SH3_RTC_H
#define rtc_reg_size sizeof(u16)
#define RTC_BIT_INVERTED 0 /* No bug on SH7708, SH7709A */
#define RTC_DEF_CAPABILITIES 0UL
#endif /* __ASM_SH_CPU_SH3_RTC_H */

17
include/asm-sh/cpu-sh3/sigcontext.h
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@ -1,17 +0,0 @@
#ifndef __ASM_CPU_SH3_SIGCONTEXT_H
#define __ASM_CPU_SH3_SIGCONTEXT_H
struct sigcontext {
unsigned long oldmask;
/* CPU registers */
unsigned long sc_regs[16];
unsigned long sc_pc;
unsigned long sc_pr;
unsigned long sc_sr;
unsigned long sc_gbr;
unsigned long sc_mach;
unsigned long sc_macl;
};
#endif /* __ASM_CPU_SH3_SIGCONTEXT_H */

67
include/asm-sh/cpu-sh3/timer.h
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@ -1,67 +0,0 @@
/*
* include/asm-sh/cpu-sh3/timer.h
*
* Copyright (C) 2004 Lineo Solutions, Inc.
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#ifndef __ASM_CPU_SH3_TIMER_H
#define __ASM_CPU_SH3_TIMER_H
/*
* ---------------------------------------------------------------------------
* TMU Common definitions for SH3 processors
* SH7706
* SH7709S
* SH7727
* SH7729R
* SH7710
* SH7720
* SH7710
* ---------------------------------------------------------------------------
*/
#if !defined(CONFIG_CPU_SUBTYPE_SH7720) && !defined(CONFIG_CPU_SUBTYPE_SH7721)
#define TMU_TOCR 0xfffffe90 /* Byte access */
#endif
#if defined(CONFIG_CPU_SUBTYPE_SH7710) || \
defined(CONFIG_CPU_SUBTYPE_SH7720) || \
defined(CONFIG_CPU_SUBTYPE_SH7721)
#define TMU_012_TSTR 0xa412fe92 /* Byte access */
#define TMU0_TCOR 0xa412fe94 /* Long access */
#define TMU0_TCNT 0xa412fe98 /* Long access */
#define TMU0_TCR 0xa412fe9c /* Word access */
#define TMU1_TCOR 0xa412fea0 /* Long access */
#define TMU1_TCNT 0xa412fea4 /* Long access */
#define TMU1_TCR 0xa412fea8 /* Word access */
#define TMU2_TCOR 0xa412feac /* Long access */
#define TMU2_TCNT 0xa412feb0 /* Long access */
#define TMU2_TCR 0xa412feb4 /* Word access */
#else
#define TMU_012_TSTR 0xfffffe92 /* Byte access */
#define TMU0_TCOR 0xfffffe94 /* Long access */
#define TMU0_TCNT 0xfffffe98 /* Long access */
#define TMU0_TCR 0xfffffe9c /* Word access */
#define TMU1_TCOR 0xfffffea0 /* Long access */
#define TMU1_TCNT 0xfffffea4 /* Long access */
#define TMU1_TCR 0xfffffea8 /* Word access */
#define TMU2_TCOR 0xfffffeac /* Long access */
#define TMU2_TCNT 0xfffffeb0 /* Long access */
#define TMU2_TCR 0xfffffeb4 /* Word access */
#if !defined(CONFIG_CPU_SUBTYPE_SH7720) && !defined(CONFIG_CPU_SUBTYPE_SH7721)
#define TMU2_TCPR2 0xfffffeb8 /* Long access */
#endif
#endif
#endif /* __ASM_CPU_SH3_TIMER_H */

42
include/asm-sh/cpu-sh3/ubc.h
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@ -1,42 +0,0 @@
/*
* include/asm-sh/cpu-sh3/ubc.h
*
* Copyright (C) 1999 Niibe Yutaka
* Copyright (C) 2003 Paul Mundt
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#ifndef __ASM_CPU_SH3_UBC_H
#define __ASM_CPU_SH3_UBC_H
#if defined(CONFIG_CPU_SUBTYPE_SH7710) || \
defined(CONFIG_CPU_SUBTYPE_SH7720) || \
defined(CONFIG_CPU_SUBTYPE_SH7721)
#define UBC_BARA 0xa4ffffb0
#define UBC_BAMRA 0xa4ffffb4
#define UBC_BBRA 0xa4ffffb8
#define UBC_BASRA 0xffffffe4
#define UBC_BARB 0xa4ffffa0
#define UBC_BAMRB 0xa4ffffa4
#define UBC_BBRB 0xa4ffffa8
#define UBC_BASRB 0xffffffe8
#define UBC_BDRB 0xa4ffff90
#define UBC_BDMRB 0xa4ffff94
#define UBC_BRCR 0xa4ffff98
#else
#define UBC_BARA 0xffffffb0
#define UBC_BAMRA 0xffffffb4
#define UBC_BBRA 0xffffffb8
#define UBC_BASRA 0xffffffe4
#define UBC_BARB 0xffffffa0
#define UBC_BAMRB 0xffffffa4
#define UBC_BBRB 0xffffffa8
#define UBC_BASRB 0xffffffe8
#define UBC_BDRB 0xffffff90
#define UBC_BDMRB 0xffffff94
#define UBC_BRCR 0xffffff98
#endif
#endif /* __ASM_CPU_SH3_UBC_H */

25
include/asm-sh/cpu-sh3/watchdog.h
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/*
* include/asm-sh/cpu-sh3/watchdog.h
*
* Copyright (C) 2002, 2003 Paul Mundt
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#ifndef __ASM_CPU_SH3_WATCHDOG_H
#define __ASM_CPU_SH3_WATCHDOG_H
/* Register definitions */
#define WTCNT 0xffffff84
#define WTCSR 0xffffff86
/* Bit definitions */
#define WTCSR_TME 0x80
#define WTCSR_WT 0x40
#define WTCSR_RSTS 0x20
#define WTCSR_WOVF 0x10
#define WTCSR_IOVF 0x08
#endif /* __ASM_CPU_SH3_WATCHDOG_H */

35
include/asm-sh/cpu-sh4/addrspace.h
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@ -1,35 +0,0 @@
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1999 by Kaz Kojima
*
* Defitions for the address spaces of the SH-4 CPUs.
*/
#ifndef __ASM_CPU_SH4_ADDRSPACE_H
#define __ASM_CPU_SH4_ADDRSPACE_H
#define P0SEG 0x00000000
#define P1SEG 0x80000000
#define P2SEG 0xa0000000
#define P3SEG 0xc0000000
#define P4SEG 0xe0000000
/* Detailed P4SEG */
#define P4SEG_STORE_QUE (P4SEG)
#define P4SEG_IC_ADDR 0xf0000000
#define P4SEG_IC_DATA 0xf1000000
#define P4SEG_ITLB_ADDR 0xf2000000
#define P4SEG_ITLB_DATA 0xf3000000
#define P4SEG_OC_ADDR 0xf4000000
#define P4SEG_OC_DATA 0xf5000000
#define P4SEG_TLB_ADDR 0xf6000000
#define P4SEG_TLB_DATA 0xf7000000
#define P4SEG_REG_BASE 0xff000000
#define PA_AREA5_IO 0xb4000000 /* Area 5 IO Memory */
#define PA_AREA6_IO 0xb8000000 /* Area 6 IO Memory */
#endif /* __ASM_CPU_SH4_ADDRSPACE_H */

42
include/asm-sh/cpu-sh4/cache.h
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@ -1,42 +0,0 @@
/*
* include/asm-sh/cpu-sh4/cache.h
*
* Copyright (C) 1999 Niibe Yutaka
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#ifndef __ASM_CPU_SH4_CACHE_H
#define __ASM_CPU_SH4_CACHE_H
#define L1_CACHE_SHIFT 5
#define SH_CACHE_VALID 1
#define SH_CACHE_UPDATED 2
#define SH_CACHE_COMBINED 4
#define SH_CACHE_ASSOC 8
#define CCR 0xff00001c /* Address of Cache Control Register */
#define CCR_CACHE_OCE 0x0001 /* Operand Cache Enable */
#define CCR_CACHE_WT 0x0002 /* Write-Through (for P0,U0,P3) (else writeback)*/
#define CCR_CACHE_CB 0x0004 /* Copy-Back (for P1) (else writethrough) */
#define CCR_CACHE_OCI 0x0008 /* OC Invalidate */
#define CCR_CACHE_ORA 0x0020 /* OC RAM Mode */
#define CCR_CACHE_OIX 0x0080 /* OC Index Enable */
#define CCR_CACHE_ICE 0x0100 /* Instruction Cache Enable */
#define CCR_CACHE_ICI 0x0800 /* IC Invalidate */
#define CCR_CACHE_IIX 0x8000 /* IC Index Enable */
#ifndef CONFIG_CPU_SH4A
#define CCR_CACHE_EMODE 0x80000000 /* EMODE Enable */
#endif
/* Default CCR setup: 8k+16k-byte cache,P1-wb,enable */
#define CCR_CACHE_ENABLE (CCR_CACHE_OCE|CCR_CACHE_ICE)
#define CCR_CACHE_INVALIDATE (CCR_CACHE_OCI|CCR_CACHE_ICI)
#define CACHE_IC_ADDRESS_ARRAY 0xf0000000
#define CACHE_OC_ADDRESS_ARRAY 0xf4000000
#endif /* __ASM_CPU_SH4_CACHE_H */

43
include/asm-sh/cpu-sh4/cacheflush.h
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/*
* include/asm-sh/cpu-sh4/cacheflush.h
*
* Copyright (C) 1999 Niibe Yutaka
* Copyright (C) 2003 Paul Mundt
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#ifndef __ASM_CPU_SH4_CACHEFLUSH_H
#define __ASM_CPU_SH4_CACHEFLUSH_H
/*
* Caches are broken on SH-4 (unless we use write-through
* caching; in which case they're only semi-broken),
* so we need them.
*/
void flush_cache_all(void);
void flush_dcache_all(void);
void flush_cache_mm(struct mm_struct *mm);
#define flush_cache_dup_mm(mm) flush_cache_mm(mm)
void flush_cache_range(struct vm_area_struct *vma, unsigned long start,
unsigned long end);
void flush_cache_page(struct vm_area_struct *vma, unsigned long addr,
unsigned long pfn);
void flush_dcache_page(struct page *pg);
#define flush_dcache_mmap_lock(mapping) do { } while (0)
#define flush_dcache_mmap_unlock(mapping) do { } while (0)
void flush_icache_range(unsigned long start, unsigned long end);
void flush_icache_user_range(struct vm_area_struct *vma, struct page *page,
unsigned long addr, int len);
#define flush_icache_page(vma,pg) do { } while (0)
/* Initialization of P3 area for copy_user_page */
void p3_cache_init(void);
#define PG_mapped PG_arch_1
#endif /* __ASM_CPU_SH4_CACHEFLUSH_H */

39
include/asm-sh/cpu-sh4/dma-sh7780.h
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@ -1,39 +0,0 @@
#ifndef __ASM_SH_CPU_SH4_DMA_SH7780_H
#define __ASM_SH_CPU_SH4_DMA_SH7780_H
#define REQ_HE 0x000000C0
#define REQ_H 0x00000080
#define REQ_LE 0x00000040
#define TM_BURST 0x0000020
#define TS_8 0x00000000
#define TS_16 0x00000008
#define TS_32 0x00000010
#define TS_16BLK 0x00000018
#define TS_32BLK 0x00100000
/*
* The SuperH DMAC supports a number of transmit sizes, we list them here,
* with their respective values as they appear in the CHCR registers.
*
* Defaults to a 64-bit transfer size.
*/
enum {
XMIT_SZ_8BIT,
XMIT_SZ_16BIT,
XMIT_SZ_32BIT,
XMIT_SZ_128BIT,
XMIT_SZ_256BIT,
};
/*
* The DMA count is defined as the number of bytes to transfer.
*/
static unsigned int ts_shift[] __maybe_unused = {
[XMIT_SZ_8BIT] = 0,
[XMIT_SZ_16BIT] = 1,
[XMIT_SZ_32BIT] = 2,
[XMIT_SZ_128BIT] = 4,
[XMIT_SZ_256BIT] = 5,
};
#endif /* __ASM_SH_CPU_SH4_DMA_SH7780_H */

65
include/asm-sh/cpu-sh4/dma.h
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@ -1,65 +0,0 @@
#ifndef __ASM_CPU_SH4_DMA_H
#define __ASM_CPU_SH4_DMA_H
#define DMAOR_INIT ( 0x8000 | DMAOR_DME )
/* SH7751/7760/7780 DMA IRQ sources */
#define DMTE0_IRQ 34
#define DMTE1_IRQ 35
#define DMTE2_IRQ 36
#define DMTE3_IRQ 37
#define DMTE4_IRQ 44
#define DMTE5_IRQ 45
#define DMTE6_IRQ 46
#define DMTE7_IRQ 47
#define DMAE_IRQ 38
#ifdef CONFIG_CPU_SH4A
#define SH_DMAC_BASE 0xfc808020
#define CHCR_TS_MASK 0x18
#define CHCR_TS_SHIFT 3
#include <asm/cpu/dma-sh7780.h>
#else
#define SH_DMAC_BASE 0xffa00000
/* Definitions for the SuperH DMAC */
#define TM_BURST 0x0000080
#define TS_8 0x00000010
#define TS_16 0x00000020
#define TS_32 0x00000030
#define TS_64 0x00000000
#define CHCR_TS_MASK 0x70
#define CHCR_TS_SHIFT 4
#define DMAOR_COD 0x00000008
/*
* The SuperH DMAC supports a number of transmit sizes, we list them here,
* with their respective values as they appear in the CHCR registers.
*
* Defaults to a 64-bit transfer size.
*/
enum {
XMIT_SZ_64BIT,
XMIT_SZ_8BIT,
XMIT_SZ_16BIT,
XMIT_SZ_32BIT,
XMIT_SZ_256BIT,
};
/*
* The DMA count is defined as the number of bytes to transfer.
*/
static unsigned int ts_shift[] __maybe_unused = {
[XMIT_SZ_64BIT] = 3,
[XMIT_SZ_8BIT] = 0,
[XMIT_SZ_16BIT] = 1,
[XMIT_SZ_32BIT] = 2,
[XMIT_SZ_256BIT] = 5,
};
#endif
#endif /* __ASM_CPU_SH4_DMA_H */

32
include/asm-sh/cpu-sh4/fpu.h
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@ -1,32 +0,0 @@
/*
* linux/arch/sh/kernel/cpu/sh4/sh4_fpu.h
*
* Copyright (C) 2006 STMicroelectronics Limited
* Author: Carl Shaw <carl.shaw@st.com>
*
* May be copied or modified under the terms of the GNU General Public
* License Version 2. See linux/COPYING for more information.
*
* Definitions for SH4 FPU operations
*/
#ifndef __CPU_SH4_FPU_H
#define __CPU_SH4_FPU_H
#define FPSCR_ENABLE_MASK 0x00000f80UL
#define FPSCR_FMOV_DOUBLE (1<<1)
#define FPSCR_CAUSE_INEXACT (1<<12)
#define FPSCR_CAUSE_UNDERFLOW (1<<13)
#define FPSCR_CAUSE_OVERFLOW (1<<14)
#define FPSCR_CAUSE_DIVZERO (1<<15)
#define FPSCR_CAUSE_INVALID (1<<16)
#define FPSCR_CAUSE_ERROR (1<<17)
#define FPSCR_DBL_PRECISION (1<<19)
#define FPSCR_ROUNDING_MODE(x) ((x >> 20) & 3)
#define FPSCR_RM_NEAREST (0)
#define FPSCR_RM_ZERO (1)
#endif

44
include/asm-sh/cpu-sh4/freq.h
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@ -1,44 +0,0 @@
/*
* include/asm-sh/cpu-sh4/freq.h
*
* Copyright (C) 2002, 2003 Paul Mundt
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#ifndef __ASM_CPU_SH4_FREQ_H
#define __ASM_CPU_SH4_FREQ_H
#if defined(CONFIG_CPU_SUBTYPE_SH7722) || \
defined(CONFIG_CPU_SUBTYPE_SH7723) || \
defined(CONFIG_CPU_SUBTYPE_SH7343) || \
defined(CONFIG_CPU_SUBTYPE_SH7366)
#define FRQCR 0xa4150000
#define VCLKCR 0xa4150004
#define SCLKACR 0xa4150008
#define SCLKBCR 0xa415000c
#define IrDACLKCR 0xa4150010
#define MSTPCR0 0xa4150030
#define MSTPCR1 0xa4150034
#define MSTPCR2 0xa4150038
#elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \
defined(CONFIG_CPU_SUBTYPE_SH7780)
#define FRQCR 0xffc80000
#elif defined(CONFIG_CPU_SUBTYPE_SH7785)
#define FRQCR0 0xffc80000
#define FRQCR1 0xffc80004
#define FRQMR1 0xffc80014
#elif defined(CONFIG_CPU_SUBTYPE_SHX3)
#define FRQCR 0xffc00014
#else
#define FRQCR 0xffc00000
#define FRQCR_PSTBY 0x0200
#define FRQCR_PLLEN 0x0400
#define FRQCR_CKOEN 0x0800
#endif
#define MIN_DIVISOR_NR 0
#define MAX_DIVISOR_NR 3
#endif /* __ASM_CPU_SH4_FREQ_H */

63
include/asm-sh/cpu-sh4/mmu_context.h
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@ -1,63 +0,0 @@
/*
* include/asm-sh/cpu-sh4/mmu_context.h
*
* Copyright (C) 1999 Niibe Yutaka
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#ifndef __ASM_CPU_SH4_MMU_CONTEXT_H
#define __ASM_CPU_SH4_MMU_CONTEXT_H
#define MMU_PTEH 0xFF000000 /* Page table entry register HIGH */
#define MMU_PTEL 0xFF000004 /* Page table entry register LOW */
#define MMU_TTB 0xFF000008 /* Translation table base register */
#define MMU_TEA 0xFF00000C /* TLB Exception Address */
#define MMU_PTEA 0xFF000034 /* Page table entry assistance register */
#define MMUCR 0xFF000010 /* MMU Control Register */
#define MMU_ITLB_ADDRESS_ARRAY 0xF2000000
#define MMU_UTLB_ADDRESS_ARRAY 0xF6000000
#define MMU_PAGE_ASSOC_BIT 0x80
#define MMUCR_TI (1<<2)
#ifdef CONFIG_X2TLB
#define MMUCR_ME (1 << 7)
#else
#define MMUCR_ME (0)
#endif
#if defined(CONFIG_32BIT) && defined(CONFIG_CPU_SUBTYPE_ST40)
#define MMUCR_SE (1 << 4)
#else
#define MMUCR_SE (0)
#endif
#ifdef CONFIG_SH_STORE_QUEUES
#define MMUCR_SQMD (1 << 9)
#else
#define MMUCR_SQMD (0)
#endif
#define MMU_NTLB_ENTRIES 64
#define MMU_CONTROL_INIT (0x05|MMUCR_SQMD|MMUCR_ME|MMUCR_SE)
#define MMU_ITLB_DATA_ARRAY 0xF3000000
#define MMU_UTLB_DATA_ARRAY 0xF7000000
#define MMU_UTLB_ENTRIES 64
#define MMU_U_ENTRY_SHIFT 8
#define MMU_UTLB_VALID 0x100
#define MMU_ITLB_ENTRIES 4
#define MMU_I_ENTRY_SHIFT 8
#define MMU_ITLB_VALID 0x100
#define TRA 0xff000020
#define EXPEVT 0xff000024
#define INTEVT 0xff000028
#endif /* __ASM_CPU_SH4_MMU_CONTEXT_H */

13
include/asm-sh/cpu-sh4/rtc.h
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@ -1,13 +0,0 @@
#ifndef __ASM_SH_CPU_SH4_RTC_H
#define __ASM_SH_CPU_SH4_RTC_H
#ifdef CONFIG_CPU_SUBTYPE_SH7723
#define rtc_reg_size sizeof(u16)
#else
#define rtc_reg_size sizeof(u32)
#endif
#define RTC_BIT_INVERTED 0x40 /* bug on SH7750, SH7750S */
#define RTC_DEF_CAPABILITIES RTC_CAP_4_DIGIT_YEAR
#endif /* __ASM_SH_CPU_SH4_RTC_H */

24
include/asm-sh/cpu-sh4/sigcontext.h
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@ -1,24 +0,0 @@
#ifndef __ASM_CPU_SH4_SIGCONTEXT_H
#define __ASM_CPU_SH4_SIGCONTEXT_H
struct sigcontext {
unsigned long oldmask;
/* CPU registers */
unsigned long sc_regs[16];
unsigned long sc_pc;
unsigned long sc_pr;
unsigned long sc_sr;
unsigned long sc_gbr;
unsigned long sc_mach;
unsigned long sc_macl;
/* FPU registers */
unsigned long sc_fpregs[16];
unsigned long sc_xfpregs[16];
unsigned int sc_fpscr;
unsigned int sc_fpul;
unsigned int sc_ownedfp;
};
#endif /* __ASM_CPU_SH4_SIGCONTEXT_H */

35
include/asm-sh/cpu-sh4/sq.h
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@ -1,35 +0,0 @@
/*
* include/asm-sh/cpu-sh4/sq.h
*
* Copyright (C) 2001, 2002, 2003 Paul Mundt
* Copyright (C) 2001, 2002 M. R. Brown
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#ifndef __ASM_CPU_SH4_SQ_H
#define __ASM_CPU_SH4_SQ_H
#include <asm/addrspace.h>
/*
* Store queues range from e0000000-e3fffffc, allowing approx. 64MB to be
* mapped to any physical address space. Since data is written (and aligned)
* to 32-byte boundaries, we need to be sure that all allocations are aligned.
*/
#define SQ_SIZE 32
#define SQ_ALIGN_MASK (~(SQ_SIZE - 1))
#define SQ_ALIGN(addr) (((addr)+SQ_SIZE-1) & SQ_ALIGN_MASK)
#define SQ_QACR0 (P4SEG_REG_BASE + 0x38)
#define SQ_QACR1 (P4SEG_REG_BASE + 0x3c)
#define SQ_ADDRMAX (P4SEG_STORE_QUE + 0x04000000)
/* arch/sh/kernel/cpu/sh4/sq.c */
unsigned long sq_remap(unsigned long phys, unsigned int size,
const char *name, unsigned long flags);
void sq_unmap(unsigned long vaddr);
void sq_flush_range(unsigned long start, unsigned int len);
#endif /* __ASM_CPU_SH4_SQ_H */

60
include/asm-sh/cpu-sh4/timer.h
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@ -1,60 +0,0 @@
/*
* include/asm-sh/cpu-sh4/timer.h
*
* Copyright (C) 2004 Lineo Solutions, Inc.
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#ifndef __ASM_CPU_SH4_TIMER_H
#define __ASM_CPU_SH4_TIMER_H
/*
* ---------------------------------------------------------------------------
* TMU Common definitions for SH4 processors
* SH7750S/SH7750R
* SH7751/SH7751R
* SH7760
* SH-X3
* ---------------------------------------------------------------------------
*/
#ifdef CONFIG_CPU_SUBTYPE_SHX3
#define TMU_012_BASE 0xffc10000
#define TMU_345_BASE 0xffc20000
#else
#define TMU_012_BASE 0xffd80000
#define TMU_345_BASE 0xfe100000
#endif
#define TMU_TOCR TMU_012_BASE /* Not supported on all CPUs */
#define TMU_012_TSTR (TMU_012_BASE + 0x04)
#define TMU_345_TSTR (TMU_345_BASE + 0x04)
#define TMU0_TCOR (TMU_012_BASE + 0x08)
#define TMU0_TCNT (TMU_012_BASE + 0x0c)
#define TMU0_TCR (TMU_012_BASE + 0x10)
#define TMU1_TCOR (TMU_012_BASE + 0x14)
#define TMU1_TCNT (TMU_012_BASE + 0x18)
#define TMU1_TCR (TMU_012_BASE + 0x1c)
#define TMU2_TCOR (TMU_012_BASE + 0x20)
#define TMU2_TCNT (TMU_012_BASE + 0x24)
#define TMU2_TCR (TMU_012_BASE + 0x28)
#define TMU2_TCPR (TMU_012_BASE + 0x2c)
#define TMU3_TCOR (TMU_345_BASE + 0x08)
#define TMU3_TCNT (TMU_345_BASE + 0x0c)
#define TMU3_TCR (TMU_345_BASE + 0x10)
#define TMU4_TCOR (TMU_345_BASE + 0x14)
#define TMU4_TCNT (TMU_345_BASE + 0x18)
#define TMU4_TCR (TMU_345_BASE + 0x1c)
#define TMU5_TCOR (TMU_345_BASE + 0x20)
#define TMU5_TCNT (TMU_345_BASE + 0x24)
#define TMU5_TCR (TMU_345_BASE + 0x28)
#endif /* __ASM_CPU_SH4_TIMER_H */

64
include/asm-sh/cpu-sh4/ubc.h
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@ -1,64 +0,0 @@
/*
* include/asm-sh/cpu-sh4/ubc.h
*
* Copyright (C) 1999 Niibe Yutaka
* Copyright (C) 2003 Paul Mundt
* Copyright (C) 2006 Lineo Solutions Inc. support SH4A UBC
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#ifndef __ASM_CPU_SH4_UBC_H
#define __ASM_CPU_SH4_UBC_H
#if defined(CONFIG_CPU_SH4A)
#define UBC_CBR0 0xff200000
#define UBC_CRR0 0xff200004
#define UBC_CAR0 0xff200008
#define UBC_CAMR0 0xff20000c
#define UBC_CBR1 0xff200020
#define UBC_CRR1 0xff200024
#define UBC_CAR1 0xff200028
#define UBC_CAMR1 0xff20002c
#define UBC_CDR1 0xff200030
#define UBC_CDMR1 0xff200034
#define UBC_CETR1 0xff200038
#define UBC_CCMFR 0xff200600
#define UBC_CBCR 0xff200620
/* CBR */
#define UBC_CBR_AIE (0x01<<30)
#define UBC_CBR_ID_INST (0x01<<4)
#define UBC_CBR_RW_READ (0x01<<1)
#define UBC_CBR_CE (0x01)
#define UBC_CBR_AIV_MASK (0x00FF0000)
#define UBC_CBR_AIV_SHIFT (16)
#define UBC_CBR_AIV_SET(asid) (((asid)<<UBC_CBR_AIV_SHIFT) & UBC_CBR_AIV_MASK)
#define UBC_CBR_INIT 0x20000000
/* CRR */
#define UBC_CRR_RES (0x01<<13)
#define UBC_CRR_PCB (0x01<<1)
#define UBC_CRR_BIE (0x01)
#define UBC_CRR_INIT 0x00002000
#else /* CONFIG_CPU_SH4 */
#define UBC_BARA 0xff200000
#define UBC_BAMRA 0xff200004
#define UBC_BBRA 0xff200008
#define UBC_BASRA 0xff000014
#define UBC_BARB 0xff20000c
#define UBC_BAMRB 0xff200010
#define UBC_BBRB 0xff200014
#define UBC_BASRB 0xff000018
#define UBC_BDRB 0xff200018
#define UBC_BDMRB 0xff20001c
#define UBC_BRCR 0xff200020
#endif /* CONFIG_CPU_SH4 */
#endif /* __ASM_CPU_SH4_UBC_H */

25
include/asm-sh/cpu-sh4/watchdog.h
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@ -1,25 +0,0 @@
/*
* include/asm-sh/cpu-sh4/watchdog.h
*
* Copyright (C) 2002, 2003 Paul Mundt
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#ifndef __ASM_CPU_SH4_WATCHDOG_H
#define __ASM_CPU_SH4_WATCHDOG_H
/* Register definitions */
#define WTCNT 0xffc00008
#define WTCSR 0xffc0000c
/* Bit definitions */
#define WTCSR_TME 0x80
#define WTCSR_WT 0x40
#define WTCSR_RSTS 0x20
#define WTCSR_WOVF 0x10
#define WTCSR_IOVF 0x08
#endif /* __ASM_CPU_SH4_WATCHDOG_H */

11
include/asm-sh/cpu-sh5/addrspace.h
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@ -1,11 +0,0 @@
#ifndef __ASM_SH_CPU_SH5_ADDRSPACE_H
#define __ASM_SH_CPU_SH5_ADDRSPACE_H
#define PHYS_PERIPHERAL_BLOCK 0x09000000
#define PHYS_DMAC_BLOCK 0x0e000000
#define PHYS_PCI_BLOCK 0x60000000
#define PHYS_EMI_BLOCK 0xff000000
/* No segmentation.. */
#endif /* __ASM_SH_CPU_SH5_ADDRSPACE_H */

97
include/asm-sh/cpu-sh5/cache.h
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#ifndef __ASM_SH_CPU_SH5_CACHE_H
#define __ASM_SH_CPU_SH5_CACHE_H
/*
* include/asm-sh/cpu-sh5/cache.h
*
* Copyright (C) 2000, 2001 Paolo Alberelli
* Copyright (C) 2003, 2004 Paul Mundt
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#define L1_CACHE_SHIFT 5
/* Valid and Dirty bits */
#define SH_CACHE_VALID (1LL<<0)
#define SH_CACHE_UPDATED (1LL<<57)
/* Unimplemented compat bits.. */
#define SH_CACHE_COMBINED 0
#define SH_CACHE_ASSOC 0
/* Cache flags */
#define SH_CACHE_MODE_WT (1LL<<0)
#define SH_CACHE_MODE_WB (1LL<<1)
/*
* Control Registers.
*/
#define ICCR_BASE 0x01600000 /* Instruction Cache Control Register */
#define ICCR_REG0 0 /* Register 0 offset */
#define ICCR_REG1 1 /* Register 1 offset */
#define ICCR0 ICCR_BASE+ICCR_REG0
#define ICCR1 ICCR_BASE+ICCR_REG1
#define ICCR0_OFF 0x0 /* Set ICACHE off */
#define ICCR0_ON 0x1 /* Set ICACHE on */
#define ICCR0_ICI 0x2 /* Invalidate all in IC */
#define ICCR1_NOLOCK 0x0 /* Set No Locking */
#define OCCR_BASE 0x01E00000 /* Operand Cache Control Register */
#define OCCR_REG0 0 /* Register 0 offset */
#define OCCR_REG1 1 /* Register 1 offset */
#define OCCR0 OCCR_BASE+OCCR_REG0
#define OCCR1 OCCR_BASE+OCCR_REG1
#define OCCR0_OFF 0x0 /* Set OCACHE off */
#define OCCR0_ON 0x1 /* Set OCACHE on */
#define OCCR0_OCI 0x2 /* Invalidate all in OC */
#define OCCR0_WT 0x4 /* Set OCACHE in WT Mode */
#define OCCR0_WB 0x0 /* Set OCACHE in WB Mode */
#define OCCR1_NOLOCK 0x0 /* Set No Locking */
/*
* SH-5
* A bit of description here, for neff=32.
*
* |<--- tag (19 bits) --->|
* +-----------------------------+-----------------+------+----------+------+
* | | | ways |set index |offset|
* +-----------------------------+-----------------+------+----------+------+
* ^ 2 bits 8 bits 5 bits
* +- Bit 31
*
* Cacheline size is based on offset: 5 bits = 32 bytes per line
* A cache line is identified by a tag + set but OCACHETAG/ICACHETAG
* have a broader space for registers. These are outlined by
* CACHE_?C_*_STEP below.
*
*/
/* Instruction cache */
#define CACHE_IC_ADDRESS_ARRAY 0x01000000
/* Operand Cache */
#define CACHE_OC_ADDRESS_ARRAY 0x01800000
/* These declarations relate to cache 'synonyms' in the operand cache. A
'synonym' occurs where effective address bits overlap between those used for
indexing the cache sets and those passed to the MMU for translation. In the
case of SH5-101 & SH5-103, only bit 12 is affected for 4k pages. */
#define CACHE_OC_N_SYNBITS 1 /* Number of synonym bits */
#define CACHE_OC_SYN_SHIFT 12
/* Mask to select synonym bit(s) */
#define CACHE_OC_SYN_MASK (((1UL<<CACHE_OC_N_SYNBITS)-1)<<CACHE_OC_SYN_SHIFT)
/*
* Instruction cache can't be invalidated based on physical addresses.
* No Instruction Cache defines required, then.
*/
#endif /* __ASM_SH_CPU_SH5_CACHE_H */

33
include/asm-sh/cpu-sh5/cacheflush.h
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@ -1,33 +0,0 @@
#ifndef __ASM_SH_CPU_SH5_CACHEFLUSH_H
#define __ASM_SH_CPU_SH5_CACHEFLUSH_H
#ifndef __ASSEMBLY__
struct vm_area_struct;
struct page;
struct mm_struct;
extern void flush_cache_all(void);
extern void flush_cache_mm(struct mm_struct *mm);
extern void flush_cache_sigtramp(unsigned long vaddr);
extern void flush_cache_range(struct vm_area_struct *vma, unsigned long start,
unsigned long end);
extern void flush_cache_page(struct vm_area_struct *vma, unsigned long addr, unsigned long pfn);
extern void flush_dcache_page(struct page *pg);
extern void flush_icache_range(unsigned long start, unsigned long end);
extern void flush_icache_user_range(struct vm_area_struct *vma,
struct page *page, unsigned long addr,
int len);
#define flush_cache_dup_mm(mm) flush_cache_mm(mm)
#define flush_dcache_mmap_lock(mapping) do { } while (0)
#define flush_dcache_mmap_unlock(mapping) do { } while (0)
#define flush_icache_page(vma, page) do { } while (0)
void p3_cache_init(void);
#endif /* __ASSEMBLY__ */
#endif /* __ASM_SH_CPU_SH5_CACHEFLUSH_H */

6
include/asm-sh/cpu-sh5/dma.h
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@ -1,6 +0,0 @@
#ifndef __ASM_SH_CPU_SH5_DMA_H
#define __ASM_SH_CPU_SH5_DMA_H
/* Nothing yet */
#endif /* __ASM_SH_CPU_SH5_DMA_H */

117
include/asm-sh/cpu-sh5/irq.h
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#ifndef __ASM_SH_CPU_SH5_IRQ_H
#define __ASM_SH_CPU_SH5_IRQ_H
/*
* include/asm-sh/cpu-sh5/irq.h
*
* Copyright (C) 2000, 2001 Paolo Alberelli
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
/*
* Encoded IRQs are not considered worth to be supported.
* Main reason is that there's no per-encoded-interrupt
* enable/disable mechanism (as there was in SH3/4).
* An all enabled/all disabled is worth only if there's
* a cascaded IC to disable/enable/ack on. Until such
* IC is available there's no such support.
*
* Presumably Encoded IRQs may use extra IRQs beyond 64,
* below. Some logic must be added to cope with IRQ_IRL?
* in an exclusive way.
*
* Priorities are set at Platform level, when IRQ_IRL0-3
* are set to 0 Encoding is allowed. Otherwise it's not
* allowed.
*/
/* Independent IRQs */
#define IRQ_IRL0 0
#define IRQ_IRL1 1
#define IRQ_IRL2 2
#define IRQ_IRL3 3
#define IRQ_INTA 4
#define IRQ_INTB 5
#define IRQ_INTC 6
#define IRQ_INTD 7
#define IRQ_SERR 12
#define IRQ_ERR 13
#define IRQ_PWR3 14
#define IRQ_PWR2 15
#define IRQ_PWR1 16
#define IRQ_PWR0 17
#define IRQ_DMTE0 18
#define IRQ_DMTE1 19
#define IRQ_DMTE2 20
#define IRQ_DMTE3 21
#define IRQ_DAERR 22
#define IRQ_TUNI0 32
#define IRQ_TUNI1 33
#define IRQ_TUNI2 34
#define IRQ_TICPI2 35
#define IRQ_ATI 36
#define IRQ_PRI 37
#define IRQ_CUI 38
#define IRQ_ERI 39
#define IRQ_RXI 40
#define IRQ_BRI 41
#define IRQ_TXI 42
#define IRQ_ITI 63
#define NR_INTC_IRQS 64
#ifdef CONFIG_SH_CAYMAN
#define NR_EXT_IRQS 32
#define START_EXT_IRQS 64
/* PCI bus 2 uses encoded external interrupts on the Cayman board */
#define IRQ_P2INTA (START_EXT_IRQS + (3*8) + 0)
#define IRQ_P2INTB (START_EXT_IRQS + (3*8) + 1)
#define IRQ_P2INTC (START_EXT_IRQS + (3*8) + 2)
#define IRQ_P2INTD (START_EXT_IRQS + (3*8) + 3)
#define I8042_KBD_IRQ (START_EXT_IRQS + 2)
#define I8042_AUX_IRQ (START_EXT_IRQS + 6)
#define IRQ_CFCARD (START_EXT_IRQS + 7)
#define IRQ_PCMCIA (0)
#else
#define NR_EXT_IRQS 0
#endif
/* Default IRQs, fixed */
#define TIMER_IRQ IRQ_TUNI0
#define RTC_IRQ IRQ_CUI
/* Default Priorities, Platform may choose differently */
#define NO_PRIORITY 0 /* Disabled */
#define TIMER_PRIORITY 2
#define RTC_PRIORITY TIMER_PRIORITY
#define SCIF_PRIORITY 3
#define INTD_PRIORITY 3
#define IRL3_PRIORITY 4
#define INTC_PRIORITY 6
#define IRL2_PRIORITY 7
#define INTB_PRIORITY 9
#define IRL1_PRIORITY 10
#define INTA_PRIORITY 12
#define IRL0_PRIORITY 13
#define TOP_PRIORITY 15
extern int intc_evt_to_irq[(0xE20/0x20)+1];
int intc_irq_describe(char* p, int irq);
extern int platform_int_priority[NR_INTC_IRQS];
#endif /* __ASM_SH_CPU_SH5_IRQ_H */

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include/asm-sh/cpu-sh5/mmu_context.h
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#ifndef __ASM_SH_CPU_SH5_MMU_CONTEXT_H
#define __ASM_SH_CPU_SH5_MMU_CONTEXT_H
/* Common defines */
#define TLB_STEP 0x00000010
#define TLB_PTEH 0x00000000
#define TLB_PTEL 0x00000008
/* PTEH defines */
#define PTEH_ASID_SHIFT 2
#define PTEH_VALID 0x0000000000000001
#define PTEH_SHARED 0x0000000000000002
#define PTEH_MATCH_ASID 0x00000000000003ff
#ifndef __ASSEMBLY__
/* This has to be a common function because the next location to fill
* information is shared. */
extern void __do_tlb_refill(unsigned long address, unsigned long long is_text_not_data, pte_t *pte);
#endif /* __ASSEMBLY__ */
#endif /* __ASM_SH_CPU_SH5_MMU_CONTEXT_H */

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include/asm-sh/cpu-sh5/registers.h
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#ifndef __ASM_SH_CPU_SH5_REGISTERS_H
#define __ASM_SH_CPU_SH5_REGISTERS_H
/*
* include/asm-sh/cpu-sh5/registers.h
*
* Copyright (C) 2000, 2001 Paolo Alberelli
* Copyright (C) 2004 Richard Curnow
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#ifdef __ASSEMBLY__
/* =====================================================================
**
** Section 1: acts on assembly sources pre-processed by GPP ( <source.S>).
** Assigns symbolic names to control & target registers.
*/
/*
* Define some useful aliases for control registers.
*/
#define SR cr0
#define SSR cr1
#define PSSR cr2
/* cr3 UNDEFINED */
#define INTEVT cr4
#define EXPEVT cr5
#define PEXPEVT cr6
#define TRA cr7
#define SPC cr8
#define PSPC cr9
#define RESVEC cr10
#define VBR cr11
/* cr12 UNDEFINED */
#define TEA cr13
/* cr14-cr15 UNDEFINED */
#define DCR cr16
#define KCR0 cr17
#define KCR1 cr18
/* cr19-cr31 UNDEFINED */
/* cr32-cr61 RESERVED */
#define CTC cr62
#define USR cr63
/*
* ABI dependent registers (general purpose set)
*/
#define RET r2
#define ARG1 r2
#define ARG2 r3
#define ARG3 r4
#define ARG4 r5
#define ARG5 r6
#define ARG6 r7
#define SP r15
#define LINK r18
#define ZERO r63
/*
* Status register defines: used only by assembly sources (and
* syntax independednt)
*/
#define SR_RESET_VAL 0x0000000050008000
#define SR_HARMLESS 0x00000000500080f0 /* Write ignores for most */
#define SR_ENABLE_FPU 0xffffffffffff7fff /* AND with this */
#if defined (CONFIG_SH64_SR_WATCH)
#define SR_ENABLE_MMU 0x0000000084000000 /* OR with this */
#else
#define SR_ENABLE_MMU 0x0000000080000000 /* OR with this */
#endif
#define SR_UNBLOCK_EXC 0xffffffffefffffff /* AND with this */
#define SR_BLOCK_EXC 0x0000000010000000 /* OR with this */
#else /* Not __ASSEMBLY__ syntax */
/*
** Stringify reg. name
*/
#define __str(x) #x
/* Stringify control register names for use in inline assembly */
#define __SR __str(SR)
#define __SSR __str(SSR)
#define __PSSR __str(PSSR)
#define __INTEVT __str(INTEVT)
#define __EXPEVT __str(EXPEVT)
#define __PEXPEVT __str(PEXPEVT)
#define __TRA __str(TRA)
#define __SPC __str(SPC)
#define __PSPC __str(PSPC)
#define __RESVEC __str(RESVEC)
#define __VBR __str(VBR)
#define __TEA __str(TEA)
#define __DCR __str(DCR)
#define __KCR0 __str(KCR0)
#define __KCR1 __str(KCR1)
#define __CTC __str(CTC)
#define __USR __str(USR)
#endif /* __ASSEMBLY__ */
#endif /* __ASM_SH_CPU_SH5_REGISTERS_H */

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include/asm-sh/cpu-sh5/rtc.h
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#ifndef __ASM_SH_CPU_SH5_RTC_H
#define __ASM_SH_CPU_SH5_RTC_H
#define rtc_reg_size sizeof(u32)
#define RTC_BIT_INVERTED 0 /* The SH-5 RTC is surprisingly sane! */
#define RTC_DEF_CAPABILITIES RTC_CAP_4_DIGIT_YEAR
#endif /* __ASM_SH_CPU_SH5_RTC_H */

4
include/asm-sh/cpu-sh5/timer.h
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@ -1,4 +0,0 @@
#ifndef __ASM_SH_CPU_SH5_TIMER_H
#define __ASM_SH_CPU_SH5_TIMER_H
#endif /* __ASM_SH_CPU_SH5_TIMER_H */

6
include/asm-sh/cputime.h
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#ifndef __SH_CPUTIME_H
#define __SH_CPUTIME_H
#include <asm-generic/cputime.h>
#endif /* __SH_CPUTIME_H */

20
include/asm-sh/current.h
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#ifndef __ASM_SH_CURRENT_H
#define __ASM_SH_CURRENT_H
/*
* Copyright (C) 1999 Niibe Yutaka
*
*/
#include <linux/thread_info.h>
struct task_struct;
static __inline__ struct task_struct * get_current(void)
{
return current_thread_info()->task;
}
#define current get_current()
#endif /* __ASM_SH_CURRENT_H */

26
include/asm-sh/delay.h
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#ifndef __ASM_SH_DELAY_H
#define __ASM_SH_DELAY_H
/*
* Copyright (C) 1993 Linus Torvalds
*
* Delay routines calling functions in arch/sh/lib/delay.c
*/
extern void __bad_udelay(void);
extern void __bad_ndelay(void);
extern void __udelay(unsigned long usecs);
extern void __ndelay(unsigned long nsecs);
extern void __const_udelay(unsigned long xloops);
extern void __delay(unsigned long loops);
#define udelay(n) (__builtin_constant_p(n) ? \
((n) > 20000 ? __bad_udelay() : __const_udelay((n) * 0x10c6ul)) : \
__udelay(n))
#define ndelay(n) (__builtin_constant_p(n) ? \
((n) > 20000 ? __bad_ndelay() : __const_udelay((n) * 5ul)) : \
__ndelay(n))
#endif /* __ASM_SH_DELAY_H */

12
include/asm-sh/device.h
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/*
* Arch specific extensions to struct device
*
* This file is released under the GPLv2
*/
#include <asm-generic/device.h>
struct platform_device;
/* allocate contiguous memory chunk and fill in struct resource */
int platform_resource_setup_memory(struct platform_device *pdev,
char *name, unsigned long memsize);

1
include/asm-sh/div64.h
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#include <asm-generic/div64.h>

193
include/asm-sh/dma-mapping.h
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#ifndef __ASM_SH_DMA_MAPPING_H
#define __ASM_SH_DMA_MAPPING_H
#include <linux/mm.h>
#include <linux/scatterlist.h>
#include <asm/cacheflush.h>
#include <asm/io.h>
#include <asm-generic/dma-coherent.h>
extern struct bus_type pci_bus_type;
#define dma_supported(dev, mask) (1)
static inline int dma_set_mask(struct device *dev, u64 mask)
{
if (!dev->dma_mask || !dma_supported(dev, mask))
return -EIO;
*dev->dma_mask = mask;
return 0;
}
void *dma_alloc_coherent(struct device *dev, size_t size,
dma_addr_t *dma_handle, gfp_t flag);
void dma_free_coherent(struct device *dev, size_t size,
void *vaddr, dma_addr_t dma_handle);
void dma_cache_sync(struct device *dev, void *vaddr, size_t size,
enum dma_data_direction dir);
#define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f)
#define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h)
#define dma_is_consistent(d, h) (1)
static inline dma_addr_t dma_map_single(struct device *dev,
void *ptr, size_t size,
enum dma_data_direction dir)
{
#if defined(CONFIG_PCI) && !defined(CONFIG_SH_PCIDMA_NONCOHERENT)
if (dev->bus == &pci_bus_type)
return virt_to_phys(ptr);
#endif
dma_cache_sync(dev, ptr, size, dir);
return virt_to_phys(ptr);
}
#define dma_unmap_single(dev, addr, size, dir) do { } while (0)
static inline int dma_map_sg(struct device *dev, struct scatterlist *sg,
int nents, enum dma_data_direction dir)
{
int i;
for (i = 0; i < nents; i++) {
#if !defined(CONFIG_PCI) || defined(CONFIG_SH_PCIDMA_NONCOHERENT)
dma_cache_sync(dev, sg_virt(&sg[i]), sg[i].length, dir);
#endif
sg[i].dma_address = sg_phys(&sg[i]);
}
return nents;
}
#define dma_unmap_sg(dev, sg, nents, dir) do { } while (0)
static inline dma_addr_t dma_map_page(struct device *dev, struct page *page,
unsigned long offset, size_t size,
enum dma_data_direction dir)
{
return dma_map_single(dev, page_address(page) + offset, size, dir);
}
static inline void dma_unmap_page(struct device *dev, dma_addr_t dma_address,
size_t size, enum dma_data_direction dir)
{
dma_unmap_single(dev, dma_address, size, dir);
}
static inline void dma_sync_single(struct device *dev, dma_addr_t dma_handle,
size_t size, enum dma_data_direction dir)
{
#if defined(CONFIG_PCI) && !defined(CONFIG_SH_PCIDMA_NONCOHERENT)
if (dev->bus == &pci_bus_type)
return;
#endif
dma_cache_sync(dev, phys_to_virt(dma_handle), size, dir);
}
static inline void dma_sync_single_range(struct device *dev,
dma_addr_t dma_handle,
unsigned long offset, size_t size,
enum dma_data_direction dir)
{
#if defined(CONFIG_PCI) && !defined(CONFIG_SH_PCIDMA_NONCOHERENT)
if (dev->bus == &pci_bus_type)
return;
#endif
dma_cache_sync(dev, phys_to_virt(dma_handle) + offset, size, dir);
}
static inline void dma_sync_sg(struct device *dev, struct scatterlist *sg,
int nelems, enum dma_data_direction dir)
{
int i;
for (i = 0; i < nelems; i++) {
#if !defined(CONFIG_PCI) || defined(CONFIG_SH_PCIDMA_NONCOHERENT)
dma_cache_sync(dev, sg_virt(&sg[i]), sg[i].length, dir);
#endif
sg[i].dma_address = sg_phys(&sg[i]);
}
}
static inline void dma_sync_single_for_cpu(struct device *dev,
dma_addr_t dma_handle, size_t size,
enum dma_data_direction dir)
{
dma_sync_single(dev, dma_handle, size, dir);
}
static inline void dma_sync_single_for_device(struct device *dev,
dma_addr_t dma_handle,
size_t size,
enum dma_data_direction dir)
{
dma_sync_single(dev, dma_handle, size, dir);
}
static inline void dma_sync_single_range_for_cpu(struct device *dev,
dma_addr_t dma_handle,
unsigned long offset,
size_t size,
enum dma_data_direction direction)
{
dma_sync_single_for_cpu(dev, dma_handle+offset, size, direction);
}
static inline void dma_sync_single_range_for_device(struct device *dev,
dma_addr_t dma_handle,
unsigned long offset,
size_t size,
enum dma_data_direction direction)
{
dma_sync_single_for_device(dev, dma_handle+offset, size, direction);
}
static inline void dma_sync_sg_for_cpu(struct device *dev,
struct scatterlist *sg, int nelems,
enum dma_data_direction dir)
{
dma_sync_sg(dev, sg, nelems, dir);
}
static inline void dma_sync_sg_for_device(struct device *dev,
struct scatterlist *sg, int nelems,
enum dma_data_direction dir)
{
dma_sync_sg(dev, sg, nelems, dir);
}
static inline int dma_get_cache_alignment(void)
{
/*
* Each processor family will define its own L1_CACHE_SHIFT,
* L1_CACHE_BYTES wraps to this, so this is always safe.
*/
return L1_CACHE_BYTES;
}
static inline int dma_mapping_error(struct device *dev, dma_addr_t dma_addr)
{
return dma_addr == 0;
}
#define ARCH_HAS_DMA_DECLARE_COHERENT_MEMORY
extern int
dma_declare_coherent_memory(struct device *dev, dma_addr_t bus_addr,
dma_addr_t device_addr, size_t size, int flags);
extern void
dma_release_declared_memory(struct device *dev);
extern void *
dma_mark_declared_memory_occupied(struct device *dev,
dma_addr_t device_addr, size_t size);
#endif /* __ASM_SH_DMA_MAPPING_H */

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include/asm-sh/dma.h
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/*
* include/asm-sh/dma.h
*
* Copyright (C) 2003, 2004 Paul Mundt
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#ifndef __ASM_SH_DMA_H
#define __ASM_SH_DMA_H
#ifdef __KERNEL__
#include <linux/spinlock.h>
#include <linux/wait.h>
#include <linux/sched.h>
#include <linux/sysdev.h>
#include <asm/cpu/dma.h>
/* The maximum address that we can perform a DMA transfer to on this platform */
/* Don't define MAX_DMA_ADDRESS; it's useless on the SuperH and any
occurrence should be flagged as an error. */
/* But... */
/* XXX: This is not applicable to SuperH, just needed for alloc_bootmem */
#define MAX_DMA_ADDRESS (PAGE_OFFSET+0x10000000)
#ifdef CONFIG_NR_DMA_CHANNELS
# define MAX_DMA_CHANNELS (CONFIG_NR_DMA_CHANNELS)
#else
# define MAX_DMA_CHANNELS (CONFIG_NR_ONCHIP_DMA_CHANNELS)
#endif
/*
* Read and write modes can mean drastically different things depending on the
* channel configuration. Consult your DMAC documentation and module
* implementation for further clues.
*/
#define DMA_MODE_READ 0x00
#define DMA_MODE_WRITE 0x01
#define DMA_MODE_MASK 0x01
#define DMA_AUTOINIT 0x10
/*
* DMAC (dma_info) flags
*/
enum {
DMAC_CHANNELS_CONFIGURED = 0x01,
DMAC_CHANNELS_TEI_CAPABLE = 0x02, /* Transfer end interrupt */
};
/*
* DMA channel capabilities / flags
*/
enum {
DMA_CONFIGURED = 0x01,
/*
* Transfer end interrupt, inherited from DMAC.
* wait_queue used in dma_wait_for_completion.
*/
DMA_TEI_CAPABLE = 0x02,
};
extern spinlock_t dma_spin_lock;
struct dma_channel;
struct dma_ops {
int (*request)(struct dma_channel *chan);
void (*free)(struct dma_channel *chan);
int (*get_residue)(struct dma_channel *chan);
int (*xfer)(struct dma_channel *chan);
int (*configure)(struct dma_channel *chan, unsigned long flags);
int (*extend)(struct dma_channel *chan, unsigned long op, void *param);
};
struct dma_channel {
char dev_id[16]; /* unique name per DMAC of channel */
unsigned int chan; /* DMAC channel number */
unsigned int vchan; /* Virtual channel number */
unsigned int mode;
unsigned int count;
unsigned long sar;
unsigned long dar;
const char **caps;
unsigned long flags;
atomic_t busy;
wait_queue_head_t wait_queue;
struct sys_device dev;
void *priv_data;
};
struct dma_info {
struct platform_device *pdev;
const char *name;
unsigned int nr_channels;
unsigned long flags;
struct dma_ops *ops;
struct dma_channel *channels;
struct list_head list;
int first_channel_nr;
int first_vchannel_nr;
};
struct dma_chan_caps {
int ch_num;
const char **caplist;
};
#define to_dma_channel(channel) container_of(channel, struct dma_channel, dev)
/* arch/sh/drivers/dma/dma-api.c */
extern int dma_xfer(unsigned int chan, unsigned long from,
unsigned long to, size_t size, unsigned int mode);
#define dma_write(chan, from, to, size) \
dma_xfer(chan, from, to, size, DMA_MODE_WRITE)
#define dma_write_page(chan, from, to) \
dma_write(chan, from, to, PAGE_SIZE)
#define dma_read(chan, from, to, size) \
dma_xfer(chan, from, to, size, DMA_MODE_READ)
#define dma_read_page(chan, from, to) \
dma_read(chan, from, to, PAGE_SIZE)
extern int request_dma_bycap(const char **dmac, const char **caps,
const char *dev_id);
extern int request_dma(unsigned int chan, const char *dev_id);
extern void free_dma(unsigned int chan);
extern int get_dma_residue(unsigned int chan);
extern struct dma_info *get_dma_info(unsigned int chan);
extern struct dma_channel *get_dma_channel(unsigned int chan);
extern void dma_wait_for_completion(unsigned int chan);
extern void dma_configure_channel(unsigned int chan, unsigned long flags);
extern int register_dmac(struct dma_info *info);
extern void unregister_dmac(struct dma_info *info);
extern struct dma_info *get_dma_info_by_name(const char *dmac_name);
extern int dma_extend(unsigned int chan, unsigned long op, void *param);
extern int register_chan_caps(const char *dmac, struct dma_chan_caps *capslist);
/* arch/sh/drivers/dma/dma-sysfs.c */
extern int dma_create_sysfs_files(struct dma_channel *, struct dma_info *);
extern void dma_remove_sysfs_files(struct dma_channel *, struct dma_info *);
#ifdef CONFIG_PCI
extern int isa_dma_bridge_buggy;
#else
#define isa_dma_bridge_buggy (0)
#endif
#endif /* __KERNEL__ */
#endif /* __ASM_SH_DMA_H */

23
include/asm-sh/dmabrg.h
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/*
* SH7760 DMABRG (USB/Audio) support
*/
#ifndef _DMABRG_H_
#define _DMABRG_H_
/* IRQ sources */
#define DMABRGIRQ_USBDMA 0
#define DMABRGIRQ_USBDMAERR 1
#define DMABRGIRQ_A0TXF 2
#define DMABRGIRQ_A0TXH 3
#define DMABRGIRQ_A0RXF 4
#define DMABRGIRQ_A0RXH 5
#define DMABRGIRQ_A1TXF 6
#define DMABRGIRQ_A1TXH 7
#define DMABRGIRQ_A1RXF 8
#define DMABRGIRQ_A1RXH 9
extern int dmabrg_request_irq(unsigned int, void(*)(void *), void *);
extern void dmabrg_free_irq(unsigned int);
#endif

34
include/asm-sh/dreamcast/dma.h
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/*
* include/asm-sh/dreamcast/dma.h
*
* Copyright (C) 2003 Paul Mundt
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#ifndef __ASM_SH_DREAMCAST_DMA_H
#define __ASM_SH_DREAMCAST_DMA_H
/* Number of DMA channels */
#define ONCHIP_NR_DMA_CHANNELS 4
#define G2_NR_DMA_CHANNELS 4
#define PVR2_NR_DMA_CHANNELS 1
/* Channels for cascading */
#define PVR2_CASCADE_CHAN 2
#define G2_CASCADE_CHAN 3
/* PVR2 DMA Registers */
#define PVR2_DMA_BASE 0xa05f6800
#define PVR2_DMA_ADDR (PVR2_DMA_BASE + 0)
#define PVR2_DMA_COUNT (PVR2_DMA_BASE + 4)
#define PVR2_DMA_MODE (PVR2_DMA_BASE + 8)
#define PVR2_DMA_LMMODE0 (PVR2_DMA_BASE + 132)
#define PVR2_DMA_LMMODE1 (PVR2_DMA_BASE + 136)
/* G2 DMA Register */
#define G2_DMA_BASE 0xa05f7800
#endif /* __ASM_SH_DREAMCAST_DMA_H */

37
include/asm-sh/dreamcast/maple.h
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#ifndef __ASM_MAPLE_H
#define __ASM_MAPLE_H
#define MAPLE_PORTS 4
#define MAPLE_PNP_INTERVAL HZ
#define MAPLE_MAXPACKETS 8
#define MAPLE_DMA_ORDER 14
#define MAPLE_DMA_SIZE (1 << MAPLE_DMA_ORDER)
#define MAPLE_DMA_PAGES ((MAPLE_DMA_ORDER > PAGE_SHIFT) ? \
MAPLE_DMA_ORDER - PAGE_SHIFT : 0)
/* Maple Bus registers */
#define MAPLE_BASE 0xa05f6c00
#define MAPLE_DMAADDR (MAPLE_BASE+0x04)
#define MAPLE_TRIGTYPE (MAPLE_BASE+0x10)
#define MAPLE_ENABLE (MAPLE_BASE+0x14)
#define MAPLE_STATE (MAPLE_BASE+0x18)
#define MAPLE_SPEED (MAPLE_BASE+0x80)
#define MAPLE_RESET (MAPLE_BASE+0x8c)
#define MAPLE_MAGIC 0x6155404f
#define MAPLE_2MBPS 0
#define MAPLE_TIMEOUT(n) ((n)<<15)
/* Function codes */
#define MAPLE_FUNC_CONTROLLER 0x001
#define MAPLE_FUNC_MEMCARD 0x002
#define MAPLE_FUNC_LCD 0x004
#define MAPLE_FUNC_CLOCK 0x008
#define MAPLE_FUNC_MICROPHONE 0x010
#define MAPLE_FUNC_ARGUN 0x020
#define MAPLE_FUNC_KEYBOARD 0x040
#define MAPLE_FUNC_LIGHTGUN 0x080
#define MAPLE_FUNC_PURUPURU 0x100
#define MAPLE_FUNC_MOUSE 0x200
#endif /* __ASM_MAPLE_H */

25
include/asm-sh/dreamcast/pci.h
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/*
* include/asm-sh/dreamcast/pci.h
*
* Copyright (C) 2001, 2002 M. R. Brown
* Copyright (C) 2002, 2003 Paul Mundt
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#ifndef __ASM_SH_DREAMCAST_PCI_H
#define __ASM_SH_DREAMCAST_PCI_H
#include <asm/mach/sysasic.h>
#define GAPSPCI_REGS 0x01001400
#define GAPSPCI_DMA_BASE 0x01840000
#define GAPSPCI_DMA_SIZE 32768
#define GAPSPCI_BBA_CONFIG 0x01001600
#define GAPSPCI_BBA_CONFIG_SIZE 0x2000
#define GAPSPCI_IRQ HW_EVENT_EXTERNAL
#endif /* __ASM_SH_DREAMCAST_PCI_H */

43
include/asm-sh/dreamcast/sysasic.h
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/* include/asm-sh/dreamcast/sysasic.h
*
* Definitions for the Dreamcast System ASIC and related peripherals.
*
* Copyright (c) 2001 M. R. Brown <mrbrown@linuxdc.org>
* Copyright (C) 2003 Paul Mundt <lethal@linux-sh.org>
*
* This file is part of the LinuxDC project (www.linuxdc.org)
*
* Released under the terms of the GNU GPL v2.0.
*
*/
#ifndef __ASM_SH_DREAMCAST_SYSASIC_H
#define __ASM_SH_DREAMCAST_SYSASIC_H
#include <asm/irq.h>
/* Hardware events -
Each of these events correspond to a bit within the Event Mask Registers/
Event Status Registers. Because of the virtual IRQ numbering scheme, a
base offset must be used when calculating the virtual IRQ that each event
takes.
*/
#define HW_EVENT_IRQ_BASE 48
/* IRQ 13 */
#define HW_EVENT_VSYNC (HW_EVENT_IRQ_BASE + 5) /* VSync */
#define HW_EVENT_MAPLE_DMA (HW_EVENT_IRQ_BASE + 12) /* Maple DMA complete */
#define HW_EVENT_GDROM_DMA (HW_EVENT_IRQ_BASE + 14) /* GD-ROM DMA complete */
#define HW_EVENT_G2_DMA (HW_EVENT_IRQ_BASE + 15) /* G2 DMA complete */
#define HW_EVENT_PVR2_DMA (HW_EVENT_IRQ_BASE + 19) /* PVR2 DMA complete */
/* IRQ 11 */
#define HW_EVENT_GDROM_CMD (HW_EVENT_IRQ_BASE + 32) /* GD-ROM cmd. complete */
#define HW_EVENT_AICA_SYS (HW_EVENT_IRQ_BASE + 33) /* AICA-related */
#define HW_EVENT_EXTERNAL (HW_EVENT_IRQ_BASE + 35) /* Ext. (expansion) */
#define HW_EVENT_IRQ_MAX (HW_EVENT_IRQ_BASE + 95)
#endif /* __ASM_SH_DREAMCAST_SYSASIC_H */

30
include/asm-sh/edosk7705.h
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/*
* include/asm-sh/edosk7705.h
*
* Modified version of io_se.h for the EDOSK7705 specific functions.
*
* May be copied or modified under the terms of the GNU General Public
* License. See linux/COPYING for more information.
*
* IO functions for an Hitachi EDOSK7705 development board
*/
#ifndef __ASM_SH_EDOSK7705_IO_H
#define __ASM_SH_EDOSK7705_IO_H
#include <asm/io_generic.h>
extern unsigned char sh_edosk7705_inb(unsigned long port);
extern unsigned int sh_edosk7705_inl(unsigned long port);
extern void sh_edosk7705_outb(unsigned char value, unsigned long port);
extern void sh_edosk7705_outl(unsigned int value, unsigned long port);
extern void sh_edosk7705_insb(unsigned long port, void *addr, unsigned long count);
extern void sh_edosk7705_insl(unsigned long port, void *addr, unsigned long count);
extern void sh_edosk7705_outsb(unsigned long port, const void *addr, unsigned long count);
extern void sh_edosk7705_outsl(unsigned long port, const void *addr, unsigned long count);
extern unsigned long sh_edosk7705_isa_port2addr(unsigned long offset);
#endif /* __ASM_SH_EDOSK7705_IO_H */

244
include/asm-sh/elf.h
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#ifndef __ASM_SH_ELF_H
#define __ASM_SH_ELF_H
#include <linux/utsname.h>
#include <asm/auxvec.h>
#include <asm/ptrace.h>
#include <asm/user.h>
/* ELF header e_flags defines */
#define EF_SH_PIC 0x100 /* -fpic */
#define EF_SH_FDPIC 0x8000 /* -mfdpic */
/* SH (particularly SHcompact) relocation types */
#define R_SH_NONE 0
#define R_SH_DIR32 1
#define R_SH_REL32 2
#define R_SH_DIR8WPN 3
#define R_SH_IND12W 4
#define R_SH_DIR8WPL 5
#define R_SH_DIR8WPZ 6
#define R_SH_DIR8BP 7
#define R_SH_DIR8W 8
#define R_SH_DIR8L 9
#define R_SH_SWITCH16 25
#define R_SH_SWITCH32 26
#define R_SH_USES 27
#define R_SH_COUNT 28
#define R_SH_ALIGN 29
#define R_SH_CODE 30
#define R_SH_DATA 31
#define R_SH_LABEL 32
#define R_SH_SWITCH8 33
#define R_SH_GNU_VTINHERIT 34
#define R_SH_GNU_VTENTRY 35
#define R_SH_TLS_GD_32 144
#define R_SH_TLS_LD_32 145
#define R_SH_TLS_LDO_32 146
#define R_SH_TLS_IE_32 147
#define R_SH_TLS_LE_32 148
#define R_SH_TLS_DTPMOD32 149
#define R_SH_TLS_DTPOFF32 150
#define R_SH_TLS_TPOFF32 151
#define R_SH_GOT32 160
#define R_SH_PLT32 161
#define R_SH_COPY 162
#define R_SH_GLOB_DAT 163
#define R_SH_JMP_SLOT 164
#define R_SH_RELATIVE 165
#define R_SH_GOTOFF 166
#define R_SH_GOTPC 167
/* FDPIC relocs */
#define R_SH_GOT20 70
#define R_SH_GOTOFF20 71
#define R_SH_GOTFUNCDESC 72
#define R_SH_GOTFUNCDESC20 73
#define R_SH_GOTOFFFUNCDESC 74
#define R_SH_GOTOFFFUNCDESC20 75
#define R_SH_FUNCDESC 76
#define R_SH_FUNCDESC_VALUE 77
#if 0 /* XXX - later .. */
#define R_SH_GOT20 198
#define R_SH_GOTOFF20 199
#define R_SH_GOTFUNCDESC 200
#define R_SH_GOTFUNCDESC20 201
#define R_SH_GOTOFFFUNCDESC 202
#define R_SH_GOTOFFFUNCDESC20 203
#define R_SH_FUNCDESC 204
#define R_SH_FUNCDESC_VALUE 205
#endif
/* SHmedia relocs */
#define R_SH_IMM_LOW16 246
#define R_SH_IMM_LOW16_PCREL 247
#define R_SH_IMM_MEDLOW16 248
#define R_SH_IMM_MEDLOW16_PCREL 249
/* Keep this the last entry. */
#define R_SH_NUM 256
/*
* ELF register definitions..
*/
typedef unsigned long elf_greg_t;
#define ELF_NGREG (sizeof (struct pt_regs) / sizeof(elf_greg_t))
typedef elf_greg_t elf_gregset_t[ELF_NGREG];
typedef struct user_fpu_struct elf_fpregset_t;
/*
* These are used to set parameters in the core dumps.
*/
#define ELF_CLASS ELFCLASS32
#ifdef __LITTLE_ENDIAN__
#define ELF_DATA ELFDATA2LSB
#else
#define ELF_DATA ELFDATA2MSB
#endif
#define ELF_ARCH EM_SH
#ifdef __KERNEL__
/*
* This is used to ensure we don't load something for the wrong architecture.
*/
#define elf_check_arch(x) ((x)->e_machine == EM_SH)
#define elf_check_fdpic(x) ((x)->e_flags & EF_SH_FDPIC)
#define elf_check_const_displacement(x) ((x)->e_flags & EF_SH_PIC)
#define USE_ELF_CORE_DUMP
#define ELF_FDPIC_CORE_EFLAGS EF_SH_FDPIC
#define ELF_EXEC_PAGESIZE PAGE_SIZE
/* This is the location that an ET_DYN program is loaded if exec'ed. Typical
use of this is to invoke "./ld.so someprog" to test out a new version of
the loader. We need to make sure that it is out of the way of the program
that it will "exec", and that there is sufficient room for the brk. */
#define ELF_ET_DYN_BASE (2 * TASK_SIZE / 3)
#define ELF_CORE_COPY_REGS(_dest,_regs) \
memcpy((char *) &_dest, (char *) _regs, \
sizeof(struct pt_regs));
/* This yields a mask that user programs can use to figure out what
instruction set this CPU supports. This could be done in user space,
but it's not easy, and we've already done it here. */
#define ELF_HWCAP (boot_cpu_data.flags)
/* This yields a string that ld.so will use to load implementation
specific libraries for optimization. This is more specific in
intent than poking at uname or /proc/cpuinfo.
For the moment, we have only optimizations for the Intel generations,
but that could change... */
#define ELF_PLATFORM (utsname()->machine)
#ifdef __SH5__
#define ELF_PLAT_INIT(_r, load_addr) \
do { _r->regs[0]=0; _r->regs[1]=0; _r->regs[2]=0; _r->regs[3]=0; \
_r->regs[4]=0; _r->regs[5]=0; _r->regs[6]=0; _r->regs[7]=0; \
_r->regs[8]=0; _r->regs[9]=0; _r->regs[10]=0; _r->regs[11]=0; \
_r->regs[12]=0; _r->regs[13]=0; _r->regs[14]=0; _r->regs[15]=0; \
_r->regs[16]=0; _r->regs[17]=0; _r->regs[18]=0; _r->regs[19]=0; \
_r->regs[20]=0; _r->regs[21]=0; _r->regs[22]=0; _r->regs[23]=0; \
_r->regs[24]=0; _r->regs[25]=0; _r->regs[26]=0; _r->regs[27]=0; \
_r->regs[28]=0; _r->regs[29]=0; _r->regs[30]=0; _r->regs[31]=0; \
_r->regs[32]=0; _r->regs[33]=0; _r->regs[34]=0; _r->regs[35]=0; \
_r->regs[36]=0; _r->regs[37]=0; _r->regs[38]=0; _r->regs[39]=0; \
_r->regs[40]=0; _r->regs[41]=0; _r->regs[42]=0; _r->regs[43]=0; \
_r->regs[44]=0; _r->regs[45]=0; _r->regs[46]=0; _r->regs[47]=0; \
_r->regs[48]=0; _r->regs[49]=0; _r->regs[50]=0; _r->regs[51]=0; \
_r->regs[52]=0; _r->regs[53]=0; _r->regs[54]=0; _r->regs[55]=0; \
_r->regs[56]=0; _r->regs[57]=0; _r->regs[58]=0; _r->regs[59]=0; \
_r->regs[60]=0; _r->regs[61]=0; _r->regs[62]=0; \
_r->tregs[0]=0; _r->tregs[1]=0; _r->tregs[2]=0; _r->tregs[3]=0; \
_r->tregs[4]=0; _r->tregs[5]=0; _r->tregs[6]=0; _r->tregs[7]=0; \
_r->sr = SR_FD | SR_MMU; } while (0)
#else
#define ELF_PLAT_INIT(_r, load_addr) \
do { _r->regs[0]=0; _r->regs[1]=0; _r->regs[2]=0; _r->regs[3]=0; \
_r->regs[4]=0; _r->regs[5]=0; _r->regs[6]=0; _r->regs[7]=0; \
_r->regs[8]=0; _r->regs[9]=0; _r->regs[10]=0; _r->regs[11]=0; \
_r->regs[12]=0; _r->regs[13]=0; _r->regs[14]=0; \
_r->sr = SR_FD; } while (0)
#define ELF_FDPIC_PLAT_INIT(_r, _exec_map_addr, _interp_map_addr, \
_dynamic_addr) \
do { \
_r->regs[0] = 0; \
_r->regs[1] = 0; \
_r->regs[2] = 0; \
_r->regs[3] = 0; \
_r->regs[4] = 0; \
_r->regs[5] = 0; \
_r->regs[6] = 0; \
_r->regs[7] = 0; \
_r->regs[8] = _exec_map_addr; \
_r->regs[9] = _interp_map_addr; \
_r->regs[10] = _dynamic_addr; \
_r->regs[11] = 0; \
_r->regs[12] = 0; \
_r->regs[13] = 0; \
_r->regs[14] = 0; \
_r->sr = SR_FD; \
} while (0)
#endif
#define SET_PERSONALITY(ex, ibcs2) set_personality(PER_LINUX_32BIT)
struct task_struct;
extern int dump_task_regs (struct task_struct *, elf_gregset_t *);
extern int dump_task_fpu (struct task_struct *, elf_fpregset_t *);
#define ELF_CORE_COPY_TASK_REGS(tsk, elf_regs) dump_task_regs(tsk, elf_regs)
#define ELF_CORE_COPY_FPREGS(tsk, elf_fpregs) dump_task_fpu(tsk, elf_fpregs)
#ifdef CONFIG_VSYSCALL
/* vDSO has arch_setup_additional_pages */
#define ARCH_HAS_SETUP_ADDITIONAL_PAGES
struct linux_binprm;
extern int arch_setup_additional_pages(struct linux_binprm *bprm,
int executable_stack);
extern unsigned int vdso_enabled;
extern void __kernel_vsyscall;
#define VDSO_BASE ((unsigned long)current->mm->context.vdso)
#define VDSO_SYM(x) (VDSO_BASE + (unsigned long)(x))
#define VSYSCALL_AUX_ENT \
if (vdso_enabled) \
NEW_AUX_ENT(AT_SYSINFO_EHDR, VDSO_BASE);
#else
#define VSYSCALL_AUX_ENT
#endif /* CONFIG_VSYSCALL */
#ifdef CONFIG_SH_FPU
#define FPU_AUX_ENT NEW_AUX_ENT(AT_FPUCW, FPSCR_INIT)
#else
#define FPU_AUX_ENT
#endif
extern int l1i_cache_shape, l1d_cache_shape, l2_cache_shape;
/* update AT_VECTOR_SIZE_ARCH if the number of NEW_AUX_ENT entries changes */
#define ARCH_DLINFO \
do { \
/* Optional FPU initialization */ \
FPU_AUX_ENT; \
\
/* Optional vsyscall entry */ \
VSYSCALL_AUX_ENT; \
\
/* Cache desc */ \
NEW_AUX_ENT(AT_L1I_CACHESHAPE, l1i_cache_shape); \
NEW_AUX_ENT(AT_L1D_CACHESHAPE, l1d_cache_shape); \
NEW_AUX_ENT(AT_L2_CACHESHAPE, l2_cache_shape); \
} while (0)
#endif /* __KERNEL__ */
#endif /* __ASM_SH_ELF_H */

6
include/asm-sh/emergency-restart.h
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@ -1,6 +0,0 @@
#ifndef _ASM_EMERGENCY_RESTART_H
#define _ASM_EMERGENCY_RESTART_H
#include <asm-generic/emergency-restart.h>
#endif /* _ASM_EMERGENCY_RESTART_H */

33
include/asm-sh/entry-macros.S
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@ -1,33 +0,0 @@
! entry.S macro define
.macro cli
stc sr, r0
or #0xf0, r0
ldc r0, sr
.endm
.macro sti
mov #0xf0, r11
extu.b r11, r11
not r11, r11
stc sr, r10
and r11, r10
#ifdef CONFIG_CPU_HAS_SR_RB
stc k_g_imask, r11
or r11, r10
#endif
ldc r10, sr
.endm
.macro get_current_thread_info, ti, tmp
#ifdef CONFIG_CPU_HAS_SR_RB
stc r7_bank, \ti
#else
mov #((THREAD_SIZE - 1) >> 10) ^ 0xff, \tmp
shll8 \tmp
shll2 \tmp
mov r15, \ti
and \tmp, \ti
#endif
.endm

6
include/asm-sh/errno.h
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@ -1,6 +0,0 @@
#ifndef __ASM_SH_ERRNO_H
#define __ASM_SH_ERRNO_H
#include <asm-generic/errno.h>
#endif /* __ASM_SH_ERRNO_H */

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