From 5a8e0343b81260f79018c0a222027c9a41109c22 Mon Sep 17 00:00:00 2001 From: Akshay Chandrashekhar Kalghatgi Date: Wed, 29 Jan 2020 13:43:42 -0800 Subject: [PATCH] ARM: dts: msm: vidc: Add register value mask Add a register value mask which will specify which bits of the register will be updated with the value. For instance, if mask is 0x11, then only bit 0 & bit 4 will be updated with the corresponding bits of the specified value. Change-Id: I27471c3afee72ac99f955030ab2100f3685d46d9 --- qcom/lahaina-vidc.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/lahaina-vidc.dtsi b/qcom/lahaina-vidc.dtsi index cabb8dc5350d..d258e1f7799c 100644 --- a/qcom/lahaina-vidc.dtsi +++ b/qcom/lahaina-vidc.dtsi @@ -32,7 +32,7 @@ <&clock_videocc VIDEO_CC_MVS0C_CLK_ARES>; reset-names = "video_axi_reset", "video_core_reset"; - qcom,reg-presets = <0xB0088 0x0>; + qcom,reg-presets = <0xB0088 0x0 0x11>; /* Bus Interconnects */ interconnect-names = "venus-cnoc", "venus-ddr", "venus-llcc";