diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa_flt.c b/drivers/platform/msm/ipa/ipa_v3/ipa_flt.c index 7931a8e491a0..d294bac51a79 100644 --- a/drivers/platform/msm/ipa/ipa_v3/ipa_flt.c +++ b/drivers/platform/msm/ipa/ipa_v3/ipa_flt.c @@ -227,6 +227,9 @@ static int ipa_translate_flt_tbl_to_hw_fmt(enum ipa_ip_type ip, /* only body (no header) */ tbl_mem.size = tbl->sz[rlt] - ipahal_get_hw_tbl_hdr_width(); + /* Add prefetech buf size. */ + tbl_mem.size += + ipahal_get_hw_prefetch_buf_size(); if (ipahal_fltrt_allocate_hw_sys_tbl(&tbl_mem)) { IPAERR("fail to alloc sys tbl of size %d\n", tbl_mem.size); diff --git a/drivers/platform/msm/ipa/ipa_v3/ipa_rt.c b/drivers/platform/msm/ipa/ipa_v3/ipa_rt.c index 213184590249..c39678af1af2 100644 --- a/drivers/platform/msm/ipa/ipa_v3/ipa_rt.c +++ b/drivers/platform/msm/ipa/ipa_v3/ipa_rt.c @@ -169,6 +169,9 @@ static int ipa_translate_rt_tbl_to_hw_fmt(enum ipa_ip_type ip, /* only body (no header) */ tbl_mem.size = tbl->sz[rlt] - ipahal_get_hw_tbl_hdr_width(); + /* Add prefetech buf size. */ + tbl_mem.size += + ipahal_get_hw_prefetch_buf_size(); if (ipahal_fltrt_allocate_hw_sys_tbl(&tbl_mem)) { IPAERR_RL("fail to alloc sys tbl of size %d\n", tbl_mem.size); diff --git a/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_fltrt.c b/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_fltrt.c index 5a2fc92985e6..d62f191f66d8 100644 --- a/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_fltrt.c +++ b/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_fltrt.c @@ -44,6 +44,7 @@ * @flt_parse_hw_rule: Parse flt rule read from H/W * @eq_bitfield: Array of the bit fields of the support equations. * 0xFF means the equation is not supported + * @prefetech_buf_size: Prefetch buf size; */ struct ipahal_fltrt_obj { bool support_hash; @@ -73,6 +74,7 @@ struct ipahal_fltrt_obj { int (*rt_parse_hw_rule)(u8 *addr, struct ipahal_rt_rule_entry *rule); int (*flt_parse_hw_rule)(u8 *addr, struct ipahal_flt_rule_entry *rule); u8 eq_bitfield[IPA_EQ_MAX]; + u32 prefetech_buf_size; }; @@ -654,6 +656,7 @@ static struct ipahal_fltrt_obj ipahal_fltrt_objs[IPA_HW_MAX] = { [IPA_IS_FRAG] = 15, [IPA_IS_PURE_ACK] = 0xFF, }, + IPA3_0_HW_RULE_PREFETCH_BUF_SIZE, }, /* IPAv4 */ @@ -699,6 +702,7 @@ static struct ipahal_fltrt_obj ipahal_fltrt_objs[IPA_HW_MAX] = { [IPA_IS_FRAG] = 15, [IPA_IS_PURE_ACK] = 0xFF, }, + IPA3_0_HW_RULE_PREFETCH_BUF_SIZE, }, /* IPAv4.2 */ @@ -744,6 +748,7 @@ static struct ipahal_fltrt_obj ipahal_fltrt_objs[IPA_HW_MAX] = { [IPA_IS_FRAG] = 15, [IPA_IS_PURE_ACK] = 0xFF, }, + IPA3_0_HW_RULE_PREFETCH_BUF_SIZE, }, /* IPAv4.5 */ @@ -789,6 +794,7 @@ static struct ipahal_fltrt_obj ipahal_fltrt_objs[IPA_HW_MAX] = { [IPA_IS_FRAG] = 15, [IPA_IS_PURE_ACK] = 0, }, + IPA3_0_HW_RULE_PREFETCH_BUF_SIZE, }, }; @@ -3593,6 +3599,12 @@ u32 ipahal_get_lcl_tbl_addr_alignment(void) return ipahal_fltrt_objs[ipahal_ctx->hw_type].lcladdr_alignment; } +/* Get the H/W (flt/rt) prefetch buf size */ +u32 ipahal_get_hw_prefetch_buf_size(void) +{ + return ipahal_fltrt_objs[ipahal_ctx->hw_type].prefetech_buf_size; +} + /* * Rule priority is used to distinguish rules order * at the integrated table consisting from hashable and diff --git a/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_fltrt.h b/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_fltrt.h index 6328f64f154e..e3799b7d84e1 100644 --- a/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_fltrt.h +++ b/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_fltrt.h @@ -140,6 +140,9 @@ u32 ipahal_get_hw_tbl_hdr_width(void); */ u32 ipahal_get_lcl_tbl_addr_alignment(void); +/* Get the H/W (flt/rt) prefetch buf size */ +u32 ipahal_get_hw_prefetch_buf_size(void); + /* * Rule priority is used to distinguish rules order * at the integrated table consisting from hashable and diff --git a/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_fltrt_i.h b/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_fltrt_i.h index a36ede1a2924..5626d78255ef 100644 --- a/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_fltrt_i.h +++ b/drivers/platform/msm/ipa/ipa_v3/ipahal/ipahal_fltrt_i.h @@ -44,6 +44,7 @@ enum ipa_fltrt_equations { #define IPA3_0_HW_TBL_ADDR_MASK (127) #define IPA3_0_HW_RULE_BUF_SIZE (256) #define IPA3_0_HW_RULE_START_ALIGNMENT (7) +#define IPA3_0_HW_RULE_PREFETCH_BUF_SIZE (128) /*