mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-12 15:49:17 -04:00
dts/panel: Rhodep: remove tianma nt37701 v2 panel od code
As the request of KP, OD fuction with the side effect, remove tianma nt37701 v2 panel OD code for Rhodep Change-Id: I527e5fb8b51b3c3c373a6126704b47b824427d53 Signed-off-by: houdz1 <houdz1@lenovo.com> Reviewed-on: https://gerrit.mot.com/2178448 SME-Granted: SME Approvals Granted SLTApproved: Slta Waiver Tested-by: Jira Key Reviewed-by: Hua Tan <tanhua1@motorola.com> Reviewed-by: Guobin Zhang <zhanggb@motorola.com> Submit-Approved: Jira Key
This commit is contained in:
parent
3f7dce0acb
commit
021b038b20
1 changed files with 5 additions and 198 deletions
|
|
@ -121,25 +121,7 @@ qcom,mdss-dsi-display-timings {
|
|||
qcom,mdss-dsi-panel-jitter = <0x20 0xa>; /* 90fps +/- 2 */
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
15 01 00 00 14 00 02 2F 08 //08:48Hz 03:60Hz 07:90Hz 02:120Hz 04:144Hz
|
||||
// FFD2.0 RGB OFS CTRL
|
||||
39 00 00 00 00 00 06 F0 55 AA 52 08 08
|
||||
39 00 00 00 00 00 14 E2 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
39 00 00 00 00 00 14 E3 C0 6B 03 A8 33 33 32 02 10 00 40 00 00 04 00 04 00 00 B8
|
||||
39 00 00 00 00 00 14 E4 00 00 00 00 00 00 00 40 00 00 00 00 00 00 00 00 00 00 00
|
||||
39 00 00 00 00 00 13 E5 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
39 00 00 00 00 00 13 E6 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
39 00 00 00 00 00 13 E7 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
//FFD SPR Pixel Type Setting
|
||||
15 00 00 00 00 00 02 6F 04
|
||||
15 00 00 00 00 00 02 C1 00
|
||||
//FFD RAM Setting, RAMOFF_IDLE_DMR
|
||||
39 00 00 00 00 00 06 F0 55 AA 52 08 00
|
||||
39 00 00 00 00 00 04 C0 0E B3 20
|
||||
//ODS part
|
||||
39 00 00 00 00 00 06 F0 55 AA 52 08 08
|
||||
15 00 00 00 00 00 02 6F 03
|
||||
15 00 00 00 00 00 02 C1 03
|
||||
39 00 00 00 00 00 1C CE 22 00 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00];
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-on-command = [
|
||||
39 00 00 00 00 00 06 F0 55 AA 52 08 00
|
||||
|
|
@ -192,29 +174,8 @@ qcom,mdss-dsi-display-timings {
|
|||
39 01 00 00 00 00 05 2B 00 00 09 5F
|
||||
|
||||
15 01 00 00 00 00 02 2F 08 //08:48Hz 03:60Hz 07:90Hz 02:120Hz 04:144Hz
|
||||
// FFD2.0 RGB OFS CTRL
|
||||
39 00 00 00 00 00 06 F0 55 AA 52 08 08
|
||||
39 00 00 00 00 00 14 E2 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
39 00 00 00 00 00 14 E3 C0 6B 03 A8 33 33 32 02 10 00 40 00 00 04 00 04 00 00 B8
|
||||
39 00 00 00 00 00 14 E4 00 00 00 00 00 00 00 40 00 00 00 00 00 00 00 00 00 00 00
|
||||
39 00 00 00 00 00 13 E5 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
39 00 00 00 00 00 13 E6 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
39 00 00 00 00 00 13 E7 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
//FFD SPR Pixel Type Setting
|
||||
15 00 00 00 00 00 02 6F 04
|
||||
15 00 00 00 00 00 02 C1 00
|
||||
//FFD RAM Setting, RAMOFF_IDLE_DMR
|
||||
39 00 00 00 00 00 06 F0 55 AA 52 08 00
|
||||
39 00 00 00 00 00 04 C0 0E B3 20
|
||||
//ODS part
|
||||
39 00 00 00 00 00 06 F0 55 AA 52 08 08
|
||||
15 00 00 00 00 00 02 6F 03
|
||||
15 00 00 00 00 00 02 C1 03
|
||||
39 00 00 00 00 00 1C CE 22 00 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
|
||||
05 01 00 00 78 00 01 11
|
||||
39 01 00 00 00 00 06 F0 55 AA 52 08 08
|
||||
39 01 00 00 00 00 02 E1 A1
|
||||
05 01 00 00 00 00 01 29]; /* display on */
|
||||
qcom,mdss-dsi-off-command = [
|
||||
05 01 00 00 00 00 01 28 /* display_off */
|
||||
|
|
@ -256,25 +217,7 @@ qcom,mdss-dsi-display-timings {
|
|||
qcom,mdss-dsi-panel-jitter = <0x20 0xa>; /* 90fps +/- 2 */
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
15 01 00 00 10 00 02 2F 03 //08:48Hz 03:60Hz 07:90Hz 02:120Hz 04:144Hz
|
||||
// FFD2.0 RGB OFS CTRL
|
||||
39 00 00 00 00 00 06 F0 55 AA 52 08 08
|
||||
39 00 00 00 00 00 14 E2 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
39 00 00 00 00 00 14 E3 C0 6B 03 A8 33 33 32 02 10 00 40 00 00 04 00 04 00 00 B8
|
||||
39 00 00 00 00 00 14 E4 00 00 00 00 00 00 00 40 00 00 00 00 00 00 00 00 00 00 00
|
||||
39 00 00 00 00 00 13 E5 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
39 00 00 00 00 00 13 E6 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
39 00 00 00 00 00 13 E7 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
//FFD SPR Pixel Type Setting
|
||||
15 00 00 00 00 00 02 6F 04
|
||||
15 00 00 00 00 00 02 C1 00
|
||||
//FFD RAM Setting, RAMOFF_IDLE_DMR
|
||||
39 00 00 00 00 00 06 F0 55 AA 52 08 00
|
||||
39 00 00 00 00 00 04 C0 0E B3 20
|
||||
//ODS part
|
||||
39 00 00 00 00 00 06 F0 55 AA 52 08 08
|
||||
15 00 00 00 00 00 02 6F 03
|
||||
15 00 00 00 00 00 02 C1 03
|
||||
39 01 00 00 00 00 1C CE 22 00 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00];
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-on-command = [
|
||||
39 00 00 00 00 00 06 F0 55 AA 52 08 00
|
||||
|
|
@ -327,29 +270,8 @@ qcom,mdss-dsi-display-timings {
|
|||
39 01 00 00 00 00 05 2B 00 00 09 5F
|
||||
|
||||
15 01 00 00 00 00 02 2F 03 //08:48Hz 03:60Hz 07:90Hz 02:120Hz 04:144Hz
|
||||
// FFD2.0 RGB OFS CTRL
|
||||
39 00 00 00 00 00 06 F0 55 AA 52 08 08
|
||||
39 00 00 00 00 00 14 E2 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
39 00 00 00 00 00 14 E3 C0 6B 03 A8 33 33 32 02 10 00 40 00 00 04 00 04 00 00 B8
|
||||
39 00 00 00 00 00 14 E4 00 00 00 00 00 00 00 40 00 00 00 00 00 00 00 00 00 00 00
|
||||
39 00 00 00 00 00 13 E5 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
39 00 00 00 00 00 13 E6 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
39 00 00 00 00 00 13 E7 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
//FFD SPR Pixel Type Setting
|
||||
15 00 00 00 00 00 02 6F 04
|
||||
15 00 00 00 00 00 02 C1 00
|
||||
//FFD RAM Setting, RAMOFF_IDLE_DMR
|
||||
39 00 00 00 00 00 06 F0 55 AA 52 08 00
|
||||
39 00 00 00 00 00 04 C0 0E B3 20
|
||||
//ODS part
|
||||
39 00 00 00 00 00 06 F0 55 AA 52 08 08
|
||||
15 00 00 00 00 00 02 6F 03
|
||||
15 00 00 00 00 00 02 C1 03
|
||||
39 01 00 00 00 00 1C CE 22 00 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
|
||||
05 01 00 00 78 00 01 11
|
||||
39 01 00 00 00 00 06 F0 55 AA 52 08 08
|
||||
39 01 00 00 00 00 02 E1 A1
|
||||
05 01 00 00 00 00 01 29]; /* display on */
|
||||
qcom,mdss-dsi-off-command = [
|
||||
05 01 00 00 00 00 01 28 /* display_off */
|
||||
|
|
@ -391,24 +313,7 @@ qcom,mdss-dsi-display-timings {
|
|||
qcom,mdss-dsi-panel-jitter = <0x20 0xa>; /* 90fps +/- 2 */
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
15 01 00 00 0b 00 02 2F 07 //08:48Hz 03:60Hz 07:90Hz 02:120Hz 04:144Hz
|
||||
39 00 00 00 00 00 06 F0 55 AA 52 08 08
|
||||
39 00 00 00 00 00 14 E2 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
39 00 00 00 00 00 14 E3 C0 6B 03 A8 33 33 32 02 10 00 40 00 00 04 00 04 00 00 B8
|
||||
39 00 00 00 00 00 14 E4 00 00 00 00 00 00 00 40 00 00 00 00 00 00 00 00 00 00 00
|
||||
39 00 00 00 00 00 13 E5 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
39 00 00 00 00 00 13 E6 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
39 00 00 00 00 00 13 E7 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
//FFD SPR Pixel Type Setting
|
||||
15 00 00 00 00 00 02 6F 04
|
||||
15 00 00 00 00 00 02 C1 00
|
||||
//FFD RAM Setting, RAMOFF_IDLE_DMR
|
||||
39 00 00 00 00 00 06 F0 55 AA 52 08 00
|
||||
39 00 00 00 00 00 04 C0 0E B3 20
|
||||
//ODS part
|
||||
39 00 00 00 00 00 06 F0 55 AA 52 08 08
|
||||
15 00 00 00 00 00 02 6F 03
|
||||
15 00 00 00 00 00 02 C1 03
|
||||
39 00 00 00 00 00 1C CE 22 00 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00];
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-on-command = [
|
||||
39 01 00 00 00 00 06 F0 55 AA 52 08 00
|
||||
|
|
@ -461,28 +366,8 @@ qcom,mdss-dsi-display-timings {
|
|||
39 01 00 00 00 00 05 2B 00 00 09 5F
|
||||
|
||||
15 01 00 00 00 00 02 2F 07 //08:48Hz 03:60Hz 07:90Hz 02:120Hz 04:144Hz
|
||||
39 00 00 00 00 00 06 F0 55 AA 52 08 08
|
||||
39 00 00 00 00 00 14 E2 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
39 00 00 00 00 00 14 E3 C0 6B 03 A8 33 33 32 02 10 00 40 00 00 04 00 04 00 00 B8
|
||||
39 00 00 00 00 00 14 E4 00 00 00 00 00 00 00 40 00 00 00 00 00 00 00 00 00 00 00
|
||||
39 00 00 00 00 00 13 E5 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
39 00 00 00 00 00 13 E6 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
39 00 00 00 00 00 13 E7 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
//FFD SPR Pixel Type Setting
|
||||
15 00 00 00 00 00 02 6F 04
|
||||
15 00 00 00 00 00 02 C1 00
|
||||
//FFD RAM Setting, RAMOFF_IDLE_DMR
|
||||
39 00 00 00 00 00 06 F0 55 AA 52 08 00
|
||||
39 00 00 00 00 00 04 C0 0E B3 20
|
||||
//ODS part
|
||||
39 00 00 00 00 00 06 F0 55 AA 52 08 08
|
||||
15 00 00 00 00 00 02 6F 03
|
||||
15 00 00 00 00 00 02 C1 03
|
||||
39 00 00 00 00 00 1C CE 22 00 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
|
||||
05 01 00 00 78 00 01 11
|
||||
39 01 00 00 00 00 06 F0 55 AA 52 08 08
|
||||
39 01 00 00 00 00 02 E1 A1
|
||||
05 01 00 00 00 00 01 29]; /* display on */
|
||||
qcom,mdss-dsi-off-command = [
|
||||
05 01 00 00 00 00 01 28 /* display_off */
|
||||
|
|
@ -524,25 +409,7 @@ qcom,mdss-dsi-display-timings {
|
|||
qcom,mdss-dsi-panel-jitter = <0x20 0xa>; /* 90fps +/- 2 */
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
15 01 00 00 08 00 02 2F 02 //08:48Hz 03:60Hz 07:90Hz 02:120Hz 04:144Hz
|
||||
// FFD2.0 RGB OFS CTRL
|
||||
39 00 00 00 00 00 06 F0 55 AA 52 08 08
|
||||
39 00 00 00 00 00 14 E2 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
39 00 00 00 00 00 14 E3 C0 6B 03 A8 33 33 32 02 10 00 40 00 00 04 00 04 00 00 B8
|
||||
39 00 00 00 00 00 14 E4 00 00 00 00 00 00 00 40 00 00 00 00 00 00 00 00 00 00 00
|
||||
39 00 00 00 00 00 13 E5 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
39 00 00 00 00 00 13 E6 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
39 00 00 00 00 00 13 E7 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
//FFD SPR Pixel Type Setting
|
||||
15 00 00 00 00 00 02 6F 04
|
||||
15 00 00 00 00 00 02 C1 00
|
||||
//FFD RAM Setting, RAMOFF_IDLE_DMR
|
||||
39 00 00 00 00 00 06 F0 55 AA 52 08 00
|
||||
39 00 00 00 00 00 04 C0 0E B3 20
|
||||
//ODS part
|
||||
39 00 00 00 00 00 06 F0 55 AA 52 08 08
|
||||
15 00 00 00 00 00 02 6F 03
|
||||
15 00 00 00 00 00 02 C1 03
|
||||
39 01 00 00 00 00 1C CE 22 00 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00];
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-on-command = [
|
||||
39 00 00 00 00 00 06 F0 55 AA 52 08 00
|
||||
|
|
@ -595,29 +462,8 @@ qcom,mdss-dsi-display-timings {
|
|||
39 01 00 00 00 00 05 2B 00 00 09 5F
|
||||
|
||||
15 01 00 00 00 00 02 2F 02 //08:48Hz 03:60Hz 07:90Hz 02:120Hz 04:144Hz
|
||||
// FFD2.0 RGB OFS CTRL
|
||||
39 00 00 00 00 00 06 F0 55 AA 52 08 08
|
||||
39 00 00 00 00 00 14 E2 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
39 00 00 00 00 00 14 E3 C0 6B 03 A8 33 33 32 02 10 00 40 00 00 04 00 04 00 00 B8
|
||||
39 00 00 00 00 00 14 E4 00 00 00 00 00 00 00 40 00 00 00 00 00 00 00 00 00 00 00
|
||||
39 00 00 00 00 00 13 E5 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
39 00 00 00 00 00 13 E6 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
39 00 00 00 00 00 13 E7 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
//FFD SPR Pixel Type Setting
|
||||
15 00 00 00 00 00 02 6F 04
|
||||
15 00 00 00 00 00 02 C1 00
|
||||
//FFD RAM Setting, RAMOFF_IDLE_DMR
|
||||
39 00 00 00 00 00 06 F0 55 AA 52 08 00
|
||||
39 00 00 00 00 00 04 C0 0E B3 20
|
||||
//ODS part
|
||||
39 00 00 00 00 00 06 F0 55 AA 52 08 08
|
||||
15 00 00 00 00 00 02 6F 03
|
||||
15 00 00 00 00 00 02 C1 03
|
||||
39 01 00 00 00 00 1C CE 22 00 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
|
||||
05 01 00 00 78 00 01 11
|
||||
39 01 00 00 00 00 06 F0 55 AA 52 08 08
|
||||
39 01 00 00 00 00 02 E1 A1
|
||||
05 01 00 00 00 00 01 29]; /* display on */
|
||||
qcom,mdss-dsi-off-command = [
|
||||
05 01 00 00 00 00 01 28 /* display_off */
|
||||
|
|
@ -659,25 +505,7 @@ qcom,mdss-dsi-display-timings {
|
|||
qcom,mdss-dsi-panel-jitter = <0x20 0xa>; // 90fps +/- 2
|
||||
qcom,mdss-dsi-timing-switch-command = [
|
||||
15 01 00 00 06 00 02 2F 04 //08:48Hz 03:60Hz 07:90Hz 02:120Hz 04:144Hz
|
||||
// FFD2.0 RGB OFS CTRL
|
||||
39 00 00 00 00 00 06 F0 55 AA 52 08 08
|
||||
39 00 00 00 00 00 14 E2 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
39 00 00 00 00 00 14 E3 86 86 06 F8 54 34 33 12 01 11 51 00 00 03 00 04 40 00 BC
|
||||
39 00 00 00 00 00 14 E4 00 00 00 00 00 00 00 00 00 00 00 00 00 05 00 00 00 00 00
|
||||
39 00 00 00 00 00 13 E5 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
39 00 00 00 00 00 13 E6 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
39 00 00 00 00 00 13 E7 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
//FFD SPR Pixel Type Setting
|
||||
15 00 00 00 00 00 02 6F 04
|
||||
15 00 00 00 00 00 02 C1 00
|
||||
//FFD RAM Setting, RAMOFF_IDLE_DMR
|
||||
39 00 00 00 00 00 06 F0 55 AA 52 08 00
|
||||
39 00 00 00 00 00 04 C0 0E B3 20
|
||||
//ODS part
|
||||
39 00 00 00 00 00 06 F0 55 AA 52 08 08
|
||||
15 00 00 00 00 00 02 6F 03
|
||||
15 00 00 00 00 00 02 C1 03
|
||||
39 01 00 00 00 00 1C CE 22 00 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00];
|
||||
];
|
||||
|
||||
qcom,mdss-dsi-on-command = [
|
||||
39 00 00 00 00 00 06 F0 55 AA 52 08 00
|
||||
|
|
@ -730,29 +558,8 @@ qcom,mdss-dsi-display-timings {
|
|||
39 01 00 00 00 00 05 2B 00 00 09 5F
|
||||
|
||||
15 01 00 00 00 00 02 2F 04 //08:48Hz 03:60Hz 07:90Hz 02:120Hz 04:144Hz
|
||||
// FFD2.0 RGB OFS CTRL
|
||||
39 00 00 00 00 00 06 F0 55 AA 52 08 08
|
||||
39 00 00 00 00 00 14 E2 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
39 00 00 00 00 00 14 E3 86 86 06 F8 54 34 33 12 01 11 51 00 00 03 00 04 40 00 BC
|
||||
39 00 00 00 00 00 14 E4 00 00 00 00 00 00 00 00 00 00 00 00 00 05 00 00 00 00 00
|
||||
39 00 00 00 00 00 13 E5 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
39 00 00 00 00 00 13 E6 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
39 00 00 00 00 00 13 E7 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
//FFD SPR Pixel Type Setting
|
||||
15 00 00 00 00 00 02 6F 04
|
||||
15 00 00 00 00 00 02 C1 00
|
||||
//FFD RAM Setting, RAMOFF_IDLE_DMR
|
||||
39 00 00 00 00 00 06 F0 55 AA 52 08 00
|
||||
39 00 00 00 00 00 04 C0 0E B3 20
|
||||
//ODS part
|
||||
39 00 00 00 00 00 06 F0 55 AA 52 08 08
|
||||
15 00 00 00 00 00 02 6F 03
|
||||
15 00 00 00 00 00 02 C1 03
|
||||
39 01 00 00 00 00 1C CE 22 00 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
|
||||
|
||||
05 01 00 00 78 00 01 11
|
||||
39 01 00 00 00 00 06 F0 55 AA 52 08 08
|
||||
39 01 00 00 00 00 02 E1 A1
|
||||
05 01 00 00 00 00 01 29]; // display on
|
||||
qcom,mdss-dsi-off-command = [
|
||||
05 01 00 00 00 00 01 28 // display_off
|
||||
|
|
|
|||
Loading…
Reference in a new issue