mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-25 22:23:14 -04:00
Merge branch 'next-spi' of git://git.secretlab.ca/git/linux-2.6
* 'next-spi' of git://git.secretlab.ca/git/linux-2.6: (77 commits) spi/omap: Fix DMA API usage in OMAP MCSPI driver spi/imx: correct the test on platform_get_irq() return value spi/topcliff: Typo fix threhold to threshold spi/dw_spi Typo change diable to disable. spi/fsl_espi: change the read behaviour of the SPIRF spi/mpc52xx-psc-spi: move probe/remove to proper sections spi/dw_spi: add DMA support spi/dw_spi: change to EXPORT_SYMBOL_GPL for exported APIs spi/dw_spi: Fix too short timeout in spi polling loop spi/pl022: convert running variable spi/pl022: convert busy flag to a bool spi/pl022: pass the returned sglen to the DMA engine spi/pl022: map the buffers on the DMA engine spi/topcliff_pch: Fix data transfer issue spi/imx: remove autodetection spi/pxa2xx: pass of_node to spi device and set a parent device spi/pxa2xx: Modify RX-Tresh instead of busy-loop for the remaining RX bytes. spi/pxa2xx: Add chipselect support for Sodaville spi/pxa2xx: Consider CE4100's FIFO depth spi/pxa2xx: Add CE4100 support ...
This commit is contained in:
Linus Torvalds
commit
021db8e2bd
45 changed files with 1596 additions and 1365 deletions
209
include/linux/pxa2xx_ssp.h
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209
include/linux/pxa2xx_ssp.h
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@ -0,0 +1,209 @@
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/*
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* pxa2xx_ssp.h
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*
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* Copyright (C) 2003 Russell King, All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
|
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* published by the Free Software Foundation.
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*
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* This driver supports the following PXA CPU/SSP ports:-
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*
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* PXA250 SSP
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* PXA255 SSP, NSSP
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* PXA26x SSP, NSSP, ASSP
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* PXA27x SSP1, SSP2, SSP3
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* PXA3xx SSP1, SSP2, SSP3, SSP4
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*/
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#ifndef __LINUX_SSP_H
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#define __LINUX_SSP_H
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#include <linux/list.h>
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#include <linux/io.h>
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/*
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* SSP Serial Port Registers
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* PXA250, PXA255, PXA26x and PXA27x SSP controllers are all slightly different.
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* PXA255, PXA26x and PXA27x have extra ports, registers and bits.
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*/
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#define SSCR0 (0x00) /* SSP Control Register 0 */
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#define SSCR1 (0x04) /* SSP Control Register 1 */
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#define SSSR (0x08) /* SSP Status Register */
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#define SSITR (0x0C) /* SSP Interrupt Test Register */
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#define SSDR (0x10) /* SSP Data Write/Data Read Register */
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#define SSTO (0x28) /* SSP Time Out Register */
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#define SSPSP (0x2C) /* SSP Programmable Serial Protocol */
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#define SSTSA (0x30) /* SSP Tx Timeslot Active */
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#define SSRSA (0x34) /* SSP Rx Timeslot Active */
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#define SSTSS (0x38) /* SSP Timeslot Status */
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#define SSACD (0x3C) /* SSP Audio Clock Divider */
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#define SSACDD (0x40) /* SSP Audio Clock Dither Divider */
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/* Common PXA2xx bits first */
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#define SSCR0_DSS (0x0000000f) /* Data Size Select (mask) */
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#define SSCR0_DataSize(x) ((x) - 1) /* Data Size Select [4..16] */
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#define SSCR0_FRF (0x00000030) /* FRame Format (mask) */
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#define SSCR0_Motorola (0x0 << 4) /* Motorola's Serial Peripheral Interface (SPI) */
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#define SSCR0_TI (0x1 << 4) /* Texas Instruments' Synchronous Serial Protocol (SSP) */
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#define SSCR0_National (0x2 << 4) /* National Microwire */
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#define SSCR0_ECS (1 << 6) /* External clock select */
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#define SSCR0_SSE (1 << 7) /* Synchronous Serial Port Enable */
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#define SSCR0_SCR(x) ((x) << 8) /* Serial Clock Rate (mask) */
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/* PXA27x, PXA3xx */
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#define SSCR0_EDSS (1 << 20) /* Extended data size select */
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#define SSCR0_NCS (1 << 21) /* Network clock select */
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#define SSCR0_RIM (1 << 22) /* Receive FIFO overrrun interrupt mask */
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#define SSCR0_TUM (1 << 23) /* Transmit FIFO underrun interrupt mask */
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#define SSCR0_FRDC (0x07000000) /* Frame rate divider control (mask) */
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#define SSCR0_SlotsPerFrm(x) (((x) - 1) << 24) /* Time slots per frame [1..8] */
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#define SSCR0_FPCKE (1 << 29) /* FIFO packing enable */
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#define SSCR0_ACS (1 << 30) /* Audio clock select */
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#define SSCR0_MOD (1 << 31) /* Mode (normal or network) */
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#define SSCR1_RIE (1 << 0) /* Receive FIFO Interrupt Enable */
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#define SSCR1_TIE (1 << 1) /* Transmit FIFO Interrupt Enable */
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#define SSCR1_LBM (1 << 2) /* Loop-Back Mode */
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#define SSCR1_SPO (1 << 3) /* Motorola SPI SSPSCLK polarity setting */
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#define SSCR1_SPH (1 << 4) /* Motorola SPI SSPSCLK phase setting */
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#define SSCR1_MWDS (1 << 5) /* Microwire Transmit Data Size */
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#define SSSR_ALT_FRM_MASK 3 /* Masks the SFRM signal number */
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#define SSSR_TNF (1 << 2) /* Transmit FIFO Not Full */
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#define SSSR_RNE (1 << 3) /* Receive FIFO Not Empty */
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#define SSSR_BSY (1 << 4) /* SSP Busy */
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#define SSSR_TFS (1 << 5) /* Transmit FIFO Service Request */
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#define SSSR_RFS (1 << 6) /* Receive FIFO Service Request */
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#define SSSR_ROR (1 << 7) /* Receive FIFO Overrun */
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#ifdef CONFIG_ARCH_PXA
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#define RX_THRESH_DFLT 8
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#define TX_THRESH_DFLT 8
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#define SSSR_TFL_MASK (0xf << 8) /* Transmit FIFO Level mask */
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#define SSSR_RFL_MASK (0xf << 12) /* Receive FIFO Level mask */
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#define SSCR1_TFT (0x000003c0) /* Transmit FIFO Threshold (mask) */
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#define SSCR1_TxTresh(x) (((x) - 1) << 6) /* level [1..16] */
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#define SSCR1_RFT (0x00003c00) /* Receive FIFO Threshold (mask) */
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#define SSCR1_RxTresh(x) (((x) - 1) << 10) /* level [1..16] */
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#else
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#define RX_THRESH_DFLT 2
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#define TX_THRESH_DFLT 2
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#define SSSR_TFL_MASK (0x3 << 8) /* Transmit FIFO Level mask */
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#define SSSR_RFL_MASK (0x3 << 12) /* Receive FIFO Level mask */
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#define SSCR1_TFT (0x000000c0) /* Transmit FIFO Threshold (mask) */
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#define SSCR1_TxTresh(x) (((x) - 1) << 6) /* level [1..4] */
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#define SSCR1_RFT (0x00000c00) /* Receive FIFO Threshold (mask) */
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#define SSCR1_RxTresh(x) (((x) - 1) << 10) /* level [1..4] */
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#endif
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/* extra bits in PXA255, PXA26x and PXA27x SSP ports */
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#define SSCR0_TISSP (1 << 4) /* TI Sync Serial Protocol */
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#define SSCR0_PSP (3 << 4) /* PSP - Programmable Serial Protocol */
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#define SSCR1_TTELP (1 << 31) /* TXD Tristate Enable Last Phase */
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#define SSCR1_TTE (1 << 30) /* TXD Tristate Enable */
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#define SSCR1_EBCEI (1 << 29) /* Enable Bit Count Error interrupt */
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#define SSCR1_SCFR (1 << 28) /* Slave Clock free Running */
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#define SSCR1_ECRA (1 << 27) /* Enable Clock Request A */
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#define SSCR1_ECRB (1 << 26) /* Enable Clock request B */
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#define SSCR1_SCLKDIR (1 << 25) /* Serial Bit Rate Clock Direction */
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#define SSCR1_SFRMDIR (1 << 24) /* Frame Direction */
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#define SSCR1_RWOT (1 << 23) /* Receive Without Transmit */
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#define SSCR1_TRAIL (1 << 22) /* Trailing Byte */
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#define SSCR1_TSRE (1 << 21) /* Transmit Service Request Enable */
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#define SSCR1_RSRE (1 << 20) /* Receive Service Request Enable */
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#define SSCR1_TINTE (1 << 19) /* Receiver Time-out Interrupt enable */
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#define SSCR1_PINTE (1 << 18) /* Peripheral Trailing Byte Interupt Enable */
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#define SSCR1_IFS (1 << 16) /* Invert Frame Signal */
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#define SSCR1_STRF (1 << 15) /* Select FIFO or EFWR */
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#define SSCR1_EFWR (1 << 14) /* Enable FIFO Write/Read */
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#define SSSR_BCE (1 << 23) /* Bit Count Error */
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#define SSSR_CSS (1 << 22) /* Clock Synchronisation Status */
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#define SSSR_TUR (1 << 21) /* Transmit FIFO Under Run */
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#define SSSR_EOC (1 << 20) /* End Of Chain */
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#define SSSR_TINT (1 << 19) /* Receiver Time-out Interrupt */
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#define SSSR_PINT (1 << 18) /* Peripheral Trailing Byte Interrupt */
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#define SSPSP_SCMODE(x) ((x) << 0) /* Serial Bit Rate Clock Mode */
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#define SSPSP_SFRMP (1 << 2) /* Serial Frame Polarity */
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#define SSPSP_ETDS (1 << 3) /* End of Transfer data State */
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#define SSPSP_STRTDLY(x) ((x) << 4) /* Start Delay */
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#define SSPSP_DMYSTRT(x) ((x) << 7) /* Dummy Start */
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#define SSPSP_SFRMDLY(x) ((x) << 9) /* Serial Frame Delay */
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#define SSPSP_SFRMWDTH(x) ((x) << 16) /* Serial Frame Width */
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#define SSPSP_DMYSTOP(x) ((x) << 23) /* Dummy Stop */
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#define SSPSP_FSRT (1 << 25) /* Frame Sync Relative Timing */
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/* PXA3xx */
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#define SSPSP_EDMYSTRT(x) ((x) << 26) /* Extended Dummy Start */
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#define SSPSP_EDMYSTOP(x) ((x) << 28) /* Extended Dummy Stop */
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#define SSPSP_TIMING_MASK (0x7f8001f0)
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#define SSACD_SCDB (1 << 3) /* SSPSYSCLK Divider Bypass */
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#define SSACD_ACPS(x) ((x) << 4) /* Audio clock PLL select */
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#define SSACD_ACDS(x) ((x) << 0) /* Audio clock divider select */
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#define SSACD_SCDX8 (1 << 7) /* SYSCLK division ratio select */
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enum pxa_ssp_type {
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SSP_UNDEFINED = 0,
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PXA25x_SSP, /* pxa 210, 250, 255, 26x */
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PXA25x_NSSP, /* pxa 255, 26x (including ASSP) */
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PXA27x_SSP,
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PXA168_SSP,
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CE4100_SSP,
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};
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struct ssp_device {
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struct platform_device *pdev;
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struct list_head node;
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struct clk *clk;
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void __iomem *mmio_base;
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unsigned long phys_base;
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const char *label;
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int port_id;
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int type;
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int use_count;
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int irq;
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int drcmr_rx;
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int drcmr_tx;
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};
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/**
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* pxa_ssp_write_reg - Write to a SSP register
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*
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* @dev: SSP device to access
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* @reg: Register to write to
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* @val: Value to be written.
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*/
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static inline void pxa_ssp_write_reg(struct ssp_device *dev, u32 reg, u32 val)
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{
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__raw_writel(val, dev->mmio_base + reg);
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}
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/**
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* pxa_ssp_read_reg - Read from a SSP register
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*
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* @dev: SSP device to access
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* @reg: Register to read from
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*/
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static inline u32 pxa_ssp_read_reg(struct ssp_device *dev, u32 reg)
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{
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return __raw_readl(dev->mmio_base + reg);
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}
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struct ssp_device *pxa_ssp_request(int port, const char *label);
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void pxa_ssp_free(struct ssp_device *);
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#endif
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@ -1,5 +1,6 @@
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#ifndef DW_SPI_HEADER_H
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#define DW_SPI_HEADER_H
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#include <linux/io.h>
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/* Bit fields in CTRLR0 */
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@ -82,6 +83,13 @@ struct dw_spi_reg {
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though only low 16 bits matters */
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} __packed;
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struct dw_spi;
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struct dw_spi_dma_ops {
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int (*dma_init)(struct dw_spi *dws);
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void (*dma_exit)(struct dw_spi *dws);
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int (*dma_transfer)(struct dw_spi *dws, int cs_change);
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};
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struct dw_spi {
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struct spi_master *master;
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struct spi_device *cur_dev;
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@ -136,13 +144,15 @@ struct dw_spi {
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/* Dma info */
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int dma_inited;
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struct dma_chan *txchan;
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struct scatterlist tx_sgl;
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struct dma_chan *rxchan;
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int txdma_done;
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int rxdma_done;
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u64 tx_param;
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u64 rx_param;
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struct scatterlist rx_sgl;
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int dma_chan_done;
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struct device *dma_dev;
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dma_addr_t dma_addr;
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dma_addr_t dma_addr; /* phy address of the Data register */
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struct dw_spi_dma_ops *dma_ops;
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void *dma_priv; /* platform relate info */
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struct pci_dev *dmac;
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/* Bus interface info */
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void *priv;
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|
|
@ -216,4 +226,8 @@ extern int dw_spi_add_host(struct dw_spi *dws);
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extern void dw_spi_remove_host(struct dw_spi *dws);
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extern int dw_spi_suspend_host(struct dw_spi *dws);
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extern int dw_spi_resume_host(struct dw_spi *dws);
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extern void dw_spi_xfer_done(struct dw_spi *dws);
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/* platform related setup */
|
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extern int dw_spi_mid_init(struct dw_spi *dws); /* Intel MID platforms */
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#endif /* DW_SPI_HEADER_H */
|
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|
|
|
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152
include/linux/spi/pxa2xx_spi.h
Normal file
152
include/linux/spi/pxa2xx_spi.h
Normal file
|
|
@ -0,0 +1,152 @@
|
|||
/*
|
||||
* Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*/
|
||||
#ifndef __linux_pxa2xx_spi_h
|
||||
#define __linux_pxa2xx_spi_h
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#include <linux/pxa2xx_ssp.h>
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#define PXA2XX_CS_ASSERT (0x01)
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#define PXA2XX_CS_DEASSERT (0x02)
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/* device.platform_data for SSP controller devices */
|
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struct pxa2xx_spi_master {
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u32 clock_enable;
|
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u16 num_chipselect;
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u8 enable_dma;
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};
|
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|
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/* spi_board_info.controller_data for SPI slave devices,
|
||||
* copied to spi_device.platform_data ... mostly for dma tuning
|
||||
*/
|
||||
struct pxa2xx_spi_chip {
|
||||
u8 tx_threshold;
|
||||
u8 rx_threshold;
|
||||
u8 dma_burst_size;
|
||||
u32 timeout;
|
||||
u8 enable_loopback;
|
||||
int gpio_cs;
|
||||
void (*cs_control)(u32 command);
|
||||
};
|
||||
|
||||
#ifdef CONFIG_ARCH_PXA
|
||||
|
||||
#include <linux/clk.h>
|
||||
#include <mach/dma.h>
|
||||
|
||||
extern void pxa2xx_set_spi_info(unsigned id, struct pxa2xx_spi_master *info);
|
||||
|
||||
#else
|
||||
/*
|
||||
* This is the implemtation for CE4100 on x86. ARM defines them in mach/ or
|
||||
* plat/ include path.
|
||||
* The CE4100 does not provide DMA support. This bits are here to let the driver
|
||||
* compile and will never be used. Maybe we get DMA support at a later point in
|
||||
* time.
|
||||
*/
|
||||
|
||||
#define DCSR(n) (n)
|
||||
#define DSADR(n) (n)
|
||||
#define DTADR(n) (n)
|
||||
#define DCMD(n) (n)
|
||||
#define DRCMR(n) (n)
|
||||
|
||||
#define DCSR_RUN (1 << 31) /* Run Bit */
|
||||
#define DCSR_NODESC (1 << 30) /* No-Descriptor Fetch */
|
||||
#define DCSR_STOPIRQEN (1 << 29) /* Stop Interrupt Enable */
|
||||
#define DCSR_REQPEND (1 << 8) /* Request Pending (read-only) */
|
||||
#define DCSR_STOPSTATE (1 << 3) /* Stop State (read-only) */
|
||||
#define DCSR_ENDINTR (1 << 2) /* End Interrupt */
|
||||
#define DCSR_STARTINTR (1 << 1) /* Start Interrupt */
|
||||
#define DCSR_BUSERR (1 << 0) /* Bus Error Interrupt */
|
||||
|
||||
#define DCSR_EORIRQEN (1 << 28) /* End of Receive Interrupt Enable */
|
||||
#define DCSR_EORJMPEN (1 << 27) /* Jump to next descriptor on EOR */
|
||||
#define DCSR_EORSTOPEN (1 << 26) /* STOP on an EOR */
|
||||
#define DCSR_SETCMPST (1 << 25) /* Set Descriptor Compare Status */
|
||||
#define DCSR_CLRCMPST (1 << 24) /* Clear Descriptor Compare Status */
|
||||
#define DCSR_CMPST (1 << 10) /* The Descriptor Compare Status */
|
||||
#define DCSR_EORINTR (1 << 9) /* The end of Receive */
|
||||
|
||||
#define DRCMR_MAPVLD (1 << 7) /* Map Valid */
|
||||
#define DRCMR_CHLNUM 0x1f /* mask for Channel Number */
|
||||
|
||||
#define DDADR_DESCADDR 0xfffffff0 /* Address of next descriptor */
|
||||
#define DDADR_STOP (1 << 0) /* Stop */
|
||||
|
||||
#define DCMD_INCSRCADDR (1 << 31) /* Source Address Increment Setting. */
|
||||
#define DCMD_INCTRGADDR (1 << 30) /* Target Address Increment Setting. */
|
||||
#define DCMD_FLOWSRC (1 << 29) /* Flow Control by the source. */
|
||||
#define DCMD_FLOWTRG (1 << 28) /* Flow Control by the target. */
|
||||
#define DCMD_STARTIRQEN (1 << 22) /* Start Interrupt Enable */
|
||||
#define DCMD_ENDIRQEN (1 << 21) /* End Interrupt Enable */
|
||||
#define DCMD_ENDIAN (1 << 18) /* Device Endian-ness. */
|
||||
#define DCMD_BURST8 (1 << 16) /* 8 byte burst */
|
||||
#define DCMD_BURST16 (2 << 16) /* 16 byte burst */
|
||||
#define DCMD_BURST32 (3 << 16) /* 32 byte burst */
|
||||
#define DCMD_WIDTH1 (1 << 14) /* 1 byte width */
|
||||
#define DCMD_WIDTH2 (2 << 14) /* 2 byte width (HalfWord) */
|
||||
#define DCMD_WIDTH4 (3 << 14) /* 4 byte width (Word) */
|
||||
#define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */
|
||||
|
||||
/*
|
||||
* Descriptor structure for PXA's DMA engine
|
||||
* Note: this structure must always be aligned to a 16-byte boundary.
|
||||
*/
|
||||
|
||||
typedef enum {
|
||||
DMA_PRIO_HIGH = 0,
|
||||
DMA_PRIO_MEDIUM = 1,
|
||||
DMA_PRIO_LOW = 2
|
||||
} pxa_dma_prio;
|
||||
|
||||
/*
|
||||
* DMA registration
|
||||
*/
|
||||
|
||||
static inline int pxa_request_dma(char *name,
|
||||
pxa_dma_prio prio,
|
||||
void (*irq_handler)(int, void *),
|
||||
void *data)
|
||||
{
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
static inline void pxa_free_dma(int dma_ch)
|
||||
{
|
||||
}
|
||||
|
||||
/*
|
||||
* The CE4100 does not have the clk framework implemented and SPI clock can
|
||||
* not be switched on/off or the divider changed.
|
||||
*/
|
||||
static inline void clk_disable(struct clk *clk)
|
||||
{
|
||||
}
|
||||
|
||||
static inline int clk_enable(struct clk *clk)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline unsigned long clk_get_rate(struct clk *clk)
|
||||
{
|
||||
return 3686400;
|
||||
}
|
||||
|
||||
#endif
|
||||
#endif
|
||||
Loading…
Reference in a new issue