mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-28 18:51:56 -04:00
Merge master.kernel.org:/pub/scm/linux/kernel/git/davem/sparc-2.6
* master.kernel.org:/pub/scm/linux/kernel/git/davem/sparc-2.6: (67 commits)
[SCSI] SUNESP: Complete driver rewrite to version 2.0
[SPARC64]: Convert PCI over to generic struct iommu/strbuf.
[SPARC]: device_node name constification fallout
[SPARC64]: Convert SBUS over to generic iommu/strbuf structs.
[SPARC64]: Add generic iommu and strbuf structs to iommu.h
[SPARC64]: Consolidate {sbus,pci}_iommu_arena.
[SPARC]: Make device_node name and type const
[SPARC64]: constify some paramaters of OF routines
[TIGON3]: of_get_property() returns const.
[SPARC64]: Fix PCI rework to adhere to of_get_property() const return.
[SPARC64]: Document and fix calculation of pages_avail.
[SPARC64]: Make sure pbm->prom_node is setup easly enough in psycho.c
[SPARC64]: Use bootmem_bootmap_pages() in choose_bootmap_pfn().
[SPARC64]: Add proper header file extern for cmdline_memory_size.
[SPARC64]: Kill sparc_ultra_dump_{i,d}tlb()
[SPARC64]: Use DECLARE_BITMAP and BITS_TO_LONGS in mm/init.c
[SPARC64]: Give move verbose show_mem() output just like i386.
[SPARC64]: Mark show_mem() printk's with KERN_INFO.
[SPARC64]: Kill kvaddr_to_phys() and friends.
[SPARC64]: Privatize sun4u_get_pte() and fix name.
...
This commit is contained in:
Linus Torvalds
commit
0278ef8b48
94 changed files with 5648 additions and 8101 deletions
|
|
@ -61,8 +61,6 @@ extern void * __memsetw(void *dest, unsigned short, size_t count);
|
|||
? __constant_c_memset((s),0x0001000100010001UL*(unsigned short)(c),(n)) \
|
||||
: __memsetw((s),(c),(n)))
|
||||
|
||||
extern int strcasecmp(const char *, const char *);
|
||||
|
||||
#endif /* __KERNEL__ */
|
||||
|
||||
#endif /* __ALPHA_STRING_H__ */
|
||||
|
|
|
|||
|
|
@ -14,8 +14,6 @@
|
|||
#define __HAVE_ARCH_MEMCMP
|
||||
#define __HAVE_ARCH_MEMCHR
|
||||
|
||||
extern int strcasecmp(const char *, const char *);
|
||||
extern int strncasecmp(const char *, const char *, __kernel_size_t);
|
||||
extern char * strcpy(char *,const char *);
|
||||
extern char * strncpy(char *,const char *, __kernel_size_t);
|
||||
extern __kernel_size_t strlen(const char *);
|
||||
|
|
|
|||
|
|
@ -126,9 +126,6 @@ extern void *memchr(const void *__s, int __c, size_t __n);
|
|||
#define __HAVE_ARCH_STRLEN
|
||||
extern size_t strlen(const char *);
|
||||
|
||||
/* arch/sh/lib/strcasecmp.c */
|
||||
extern int strcasecmp(const char *, const char *);
|
||||
|
||||
#endif /* __KERNEL__ */
|
||||
|
||||
#endif /* __ASM_SH_STRING_H */
|
||||
|
|
|
|||
|
|
@ -35,8 +35,8 @@ struct property {
|
|||
};
|
||||
|
||||
struct device_node {
|
||||
char *name;
|
||||
char *type;
|
||||
const char *name;
|
||||
const char *type;
|
||||
phandle node;
|
||||
char *path_component_name;
|
||||
char *full_name;
|
||||
|
|
@ -85,12 +85,14 @@ extern struct device_node *of_find_node_by_phandle(phandle handle);
|
|||
extern struct device_node *of_get_parent(const struct device_node *node);
|
||||
extern struct device_node *of_get_next_child(const struct device_node *node,
|
||||
struct device_node *prev);
|
||||
extern struct property *of_find_property(struct device_node *np,
|
||||
extern struct property *of_find_property(const struct device_node *np,
|
||||
const char *name,
|
||||
int *lenp);
|
||||
extern int of_device_is_compatible(struct device_node *device, const char *);
|
||||
extern void *of_get_property(struct device_node *node, const char *name,
|
||||
int *lenp);
|
||||
extern int of_device_is_compatible(const struct device_node *device,
|
||||
const char *);
|
||||
extern const void *of_get_property(const struct device_node *node,
|
||||
const char *name,
|
||||
int *lenp);
|
||||
#define get_property(node,name,lenp) of_get_property(node,name,lenp)
|
||||
extern int of_set_property(struct device_node *node, const char *name, void *val, int len);
|
||||
extern int of_getintprop_default(struct device_node *np,
|
||||
|
|
|
|||
|
|
@ -17,8 +17,8 @@
|
|||
typedef struct {
|
||||
/* Dcache line 1 */
|
||||
unsigned int __softirq_pending; /* must be 1st, see rtrap.S */
|
||||
unsigned int multiplier;
|
||||
unsigned int counter;
|
||||
unsigned int __pad0_1;
|
||||
unsigned int __pad0_2;
|
||||
unsigned int __pad1;
|
||||
unsigned long clock_tick; /* %tick's per second */
|
||||
unsigned long udelay_val;
|
||||
|
|
|
|||
|
|
@ -3,5 +3,21 @@
|
|||
*
|
||||
* This file is released under the GPLv2
|
||||
*/
|
||||
#include <asm-generic/device.h>
|
||||
#ifndef _ASM_SPARC64_DEVICE_H
|
||||
#define _ASM_SPARC64_DEVICE_H
|
||||
|
||||
struct device_node;
|
||||
struct of_device;
|
||||
|
||||
struct dev_archdata {
|
||||
void *iommu;
|
||||
void *stc;
|
||||
void *host_controller;
|
||||
|
||||
struct device_node *prom_node;
|
||||
struct of_device *op;
|
||||
|
||||
unsigned int msi_num;
|
||||
};
|
||||
|
||||
#endif /* _ASM_SPARC64_DEVICE_H */
|
||||
|
|
|
|||
|
|
@ -8,7 +8,6 @@
|
|||
#ifndef __SPARC64_EBUS_H
|
||||
#define __SPARC64_EBUS_H
|
||||
|
||||
#include <asm/pbm.h>
|
||||
#include <asm/oplib.h>
|
||||
#include <asm/prom.h>
|
||||
#include <asm/of_device.h>
|
||||
|
|
@ -41,7 +40,6 @@ struct linux_ebus {
|
|||
struct of_device ofdev;
|
||||
struct linux_ebus *next;
|
||||
struct linux_ebus_device *devices;
|
||||
struct pci_pbm_info *parent;
|
||||
struct pci_dev *self;
|
||||
int index;
|
||||
int is_rio;
|
||||
|
|
|
|||
|
|
@ -549,7 +549,7 @@ static int __init ebus_fdthree_p(struct linux_ebus_device *edev)
|
|||
if (!strcmp(edev->prom_node->name, "fdthree"))
|
||||
return 1;
|
||||
if (!strcmp(edev->prom_node->name, "floppy")) {
|
||||
char *compat;
|
||||
const char *compat;
|
||||
|
||||
compat = of_get_property(edev->prom_node,
|
||||
"compatible", NULL);
|
||||
|
|
@ -661,7 +661,7 @@ static unsigned long __init sun_floppy_init(void)
|
|||
struct linux_ebus_device *edev = NULL;
|
||||
unsigned long config = 0;
|
||||
void __iomem *auxio_reg;
|
||||
char *state_prop;
|
||||
const char *state_prop;
|
||||
|
||||
for_each_ebus(ebus) {
|
||||
for_each_ebusdev(edev, ebus) {
|
||||
|
|
|
|||
|
|
@ -24,14 +24,6 @@ extern unsigned long kern_base, kern_size;
|
|||
#define page_to_phys(page) (page_to_pfn(page) << PAGE_SHIFT)
|
||||
#define BIO_VMERGE_BOUNDARY 8192
|
||||
|
||||
/* Different PCI controllers we support have their PCI MEM space
|
||||
* mapped to an either 2GB (Psycho) or 4GB (Sabre) aligned area,
|
||||
* so need to chop off the top 33 or 32 bits.
|
||||
*/
|
||||
extern unsigned long pci_memspace_mask;
|
||||
|
||||
#define bus_dvma_to_mem(__vaddr) ((__vaddr) & pci_memspace_mask)
|
||||
|
||||
static __inline__ u8 _inb(unsigned long addr)
|
||||
{
|
||||
u8 ret;
|
||||
|
|
|
|||
|
|
@ -7,15 +7,50 @@
|
|||
#define _SPARC64_IOMMU_H
|
||||
|
||||
/* The format of an iopte in the page tables. */
|
||||
#define IOPTE_VALID 0x8000000000000000UL /* IOPTE is valid */
|
||||
#define IOPTE_64K 0x2000000000000000UL /* IOPTE is for 64k page */
|
||||
#define IOPTE_STBUF 0x1000000000000000UL /* DVMA can use streaming buffer */
|
||||
#define IOPTE_INTRA 0x0800000000000000UL /* SBUS slot-->slot direct transfer*/
|
||||
#define IOPTE_CONTEXT 0x07ff800000000000UL /* Context number */
|
||||
#define IOPTE_PAGE 0x00007fffffffe000UL /* Physical page number (PA[42:13])*/
|
||||
#define IOPTE_CACHE 0x0000000000000010UL /* Cached (in UPA E-cache) */
|
||||
#define IOPTE_WRITE 0x0000000000000002UL /* Writeable */
|
||||
#define IOPTE_VALID 0x8000000000000000UL
|
||||
#define IOPTE_64K 0x2000000000000000UL
|
||||
#define IOPTE_STBUF 0x1000000000000000UL
|
||||
#define IOPTE_INTRA 0x0800000000000000UL
|
||||
#define IOPTE_CONTEXT 0x07ff800000000000UL
|
||||
#define IOPTE_PAGE 0x00007fffffffe000UL
|
||||
#define IOPTE_CACHE 0x0000000000000010UL
|
||||
#define IOPTE_WRITE 0x0000000000000002UL
|
||||
|
||||
#define IOMMU_NUM_CTXS 4096
|
||||
|
||||
struct iommu_arena {
|
||||
unsigned long *map;
|
||||
unsigned int hint;
|
||||
unsigned int limit;
|
||||
};
|
||||
|
||||
struct iommu {
|
||||
spinlock_t lock;
|
||||
struct iommu_arena arena;
|
||||
iopte_t *page_table;
|
||||
u32 page_table_map_base;
|
||||
unsigned long iommu_control;
|
||||
unsigned long iommu_tsbbase;
|
||||
unsigned long iommu_flush;
|
||||
unsigned long iommu_ctxflush;
|
||||
unsigned long write_complete_reg;
|
||||
unsigned long dummy_page;
|
||||
unsigned long dummy_page_pa;
|
||||
unsigned long ctx_lowest_free;
|
||||
DECLARE_BITMAP(ctx_bitmap, IOMMU_NUM_CTXS);
|
||||
u32 dma_addr_mask;
|
||||
};
|
||||
|
||||
struct strbuf {
|
||||
int strbuf_enabled;
|
||||
unsigned long strbuf_control;
|
||||
unsigned long strbuf_pflush;
|
||||
unsigned long strbuf_fsync;
|
||||
unsigned long strbuf_ctxflush;
|
||||
unsigned long strbuf_ctxmatch_base;
|
||||
unsigned long strbuf_flushflag_pa;
|
||||
volatile unsigned long *strbuf_flushflag;
|
||||
volatile unsigned long __flushflag_buf[(64+(64-1)) / sizeof(long)];
|
||||
};
|
||||
|
||||
#endif /* !(_SPARC_IOMMU_H) */
|
||||
|
|
|
|||
|
|
@ -7,7 +7,6 @@
|
|||
#ifndef __SPARC64_ISA_H
|
||||
#define __SPARC64_ISA_H
|
||||
|
||||
#include <asm/pbm.h>
|
||||
#include <asm/oplib.h>
|
||||
#include <asm/prom.h>
|
||||
#include <asm/of_device.h>
|
||||
|
|
@ -29,7 +28,6 @@ struct sparc_isa_bridge {
|
|||
struct of_device ofdev;
|
||||
struct sparc_isa_bridge *next;
|
||||
struct sparc_isa_device *devices;
|
||||
struct pci_pbm_info *parent;
|
||||
struct pci_dev *self;
|
||||
int index;
|
||||
struct device_node *prom_node;
|
||||
|
|
|
|||
|
|
@ -103,7 +103,7 @@ static int ebus_ecpp_p(struct linux_ebus_device *edev)
|
|||
if (!strcmp(edev->prom_node->name, "ecpp"))
|
||||
return 1;
|
||||
if (!strcmp(edev->prom_node->name, "parallel")) {
|
||||
char *compat;
|
||||
const char *compat;
|
||||
|
||||
compat = of_get_property(edev->prom_node,
|
||||
"compatible", NULL);
|
||||
|
|
|
|||
|
|
@ -1,7 +1,6 @@
|
|||
/* $Id: pbm.h,v 1.27 2001/08/12 13:18:23 davem Exp $
|
||||
* pbm.h: UltraSparc PCI controller software state.
|
||||
/* pbm.h: UltraSparc PCI controller software state.
|
||||
*
|
||||
* Copyright (C) 1997, 1998, 1999 David S. Miller (davem@redhat.com)
|
||||
* Copyright (C) 1997, 1998, 1999, 2007 David S. Miller (davem@davemloft.net)
|
||||
*/
|
||||
|
||||
#ifndef __SPARC64_PBM_H
|
||||
|
|
@ -30,90 +29,7 @@
|
|||
* PCI bus.
|
||||
*/
|
||||
|
||||
struct pci_controller_info;
|
||||
|
||||
/* This contains the software state necessary to drive a PCI
|
||||
* controller's IOMMU.
|
||||
*/
|
||||
struct pci_iommu_arena {
|
||||
unsigned long *map;
|
||||
unsigned int hint;
|
||||
unsigned int limit;
|
||||
};
|
||||
|
||||
struct pci_iommu {
|
||||
/* This protects the controller's IOMMU and all
|
||||
* streaming buffers underneath.
|
||||
*/
|
||||
spinlock_t lock;
|
||||
|
||||
struct pci_iommu_arena arena;
|
||||
|
||||
/* IOMMU page table, a linear array of ioptes. */
|
||||
iopte_t *page_table; /* The page table itself. */
|
||||
|
||||
/* Base PCI memory space address where IOMMU mappings
|
||||
* begin.
|
||||
*/
|
||||
u32 page_table_map_base;
|
||||
|
||||
/* IOMMU Controller Registers */
|
||||
unsigned long iommu_control; /* IOMMU control register */
|
||||
unsigned long iommu_tsbbase; /* IOMMU page table base register */
|
||||
unsigned long iommu_flush; /* IOMMU page flush register */
|
||||
unsigned long iommu_ctxflush; /* IOMMU context flush register */
|
||||
|
||||
/* This is a register in the PCI controller, which if
|
||||
* read will have no side-effects but will guarantee
|
||||
* completion of all previous writes into IOMMU/STC.
|
||||
*/
|
||||
unsigned long write_complete_reg;
|
||||
|
||||
/* In order to deal with some buggy third-party PCI bridges that
|
||||
* do wrong prefetching, we never mark valid mappings as invalid.
|
||||
* Instead we point them at this dummy page.
|
||||
*/
|
||||
unsigned long dummy_page;
|
||||
unsigned long dummy_page_pa;
|
||||
|
||||
/* CTX allocation. */
|
||||
unsigned long ctx_lowest_free;
|
||||
unsigned long ctx_bitmap[IOMMU_NUM_CTXS / (sizeof(unsigned long) * 8)];
|
||||
|
||||
/* Here a PCI controller driver describes the areas of
|
||||
* PCI memory space where DMA to/from physical memory
|
||||
* are addressed. Drivers interrogate the PCI layer
|
||||
* if their device has addressing limitations. They
|
||||
* do so via pci_dma_supported, and pass in a mask of
|
||||
* DMA address bits their device can actually drive.
|
||||
*
|
||||
* The test for being usable is:
|
||||
* (device_mask & dma_addr_mask) == dma_addr_mask
|
||||
*/
|
||||
u32 dma_addr_mask;
|
||||
};
|
||||
|
||||
extern void pci_iommu_table_init(struct pci_iommu *iommu, int tsbsize, u32 dma_offset, u32 dma_addr_mask);
|
||||
|
||||
/* This describes a PCI bus module's streaming buffer. */
|
||||
struct pci_strbuf {
|
||||
int strbuf_enabled; /* Present and using it? */
|
||||
|
||||
/* Streaming Buffer Control Registers */
|
||||
unsigned long strbuf_control; /* STC control register */
|
||||
unsigned long strbuf_pflush; /* STC page flush register */
|
||||
unsigned long strbuf_fsync; /* STC flush synchronization reg */
|
||||
unsigned long strbuf_ctxflush; /* STC context flush register */
|
||||
unsigned long strbuf_ctxmatch_base; /* STC context flush match reg */
|
||||
unsigned long strbuf_flushflag_pa; /* Physical address of flush flag */
|
||||
volatile unsigned long *strbuf_flushflag; /* The flush flag itself */
|
||||
|
||||
/* And this is the actual flush flag area.
|
||||
* We allocate extra because the chips require
|
||||
* a 64-byte aligned area.
|
||||
*/
|
||||
volatile unsigned long __flushflag_buf[(64 + (64 - 1)) / sizeof(long)];
|
||||
};
|
||||
extern void pci_iommu_table_init(struct iommu *iommu, int tsbsize, u32 dma_offset, u32 dma_addr_mask);
|
||||
|
||||
#define PCI_STC_FLUSHFLAG_INIT(STC) \
|
||||
(*((STC)->strbuf_flushflag) = 0UL)
|
||||
|
|
@ -126,6 +42,8 @@ struct pci_strbuf {
|
|||
#define PROM_PCIRNG_MAX 64
|
||||
#define PROM_PCIIMAP_MAX 64
|
||||
|
||||
struct pci_controller_info;
|
||||
|
||||
struct pci_pbm_info {
|
||||
/* PCI controller we sit under. */
|
||||
struct pci_controller_info *parent;
|
||||
|
|
@ -160,11 +78,6 @@ struct pci_pbm_info {
|
|||
|
||||
/* OBP specific information. */
|
||||
struct device_node *prom_node;
|
||||
struct linux_prom_pci_ranges *pbm_ranges;
|
||||
int num_pbm_ranges;
|
||||
struct linux_prom_pci_intmap *pbm_intmap;
|
||||
int num_pbm_intmap;
|
||||
struct linux_prom_pci_intmask *pbm_intmask;
|
||||
u64 ino_bitmap;
|
||||
|
||||
/* PBM I/O and Memory space resources. */
|
||||
|
|
@ -197,13 +110,10 @@ struct pci_pbm_info {
|
|||
#endif /* !(CONFIG_PCI_MSI) */
|
||||
|
||||
/* This PBM's streaming buffer. */
|
||||
struct pci_strbuf stc;
|
||||
struct strbuf stc;
|
||||
|
||||
/* IOMMU state, potentially shared by both PBM segments. */
|
||||
struct pci_iommu *iommu;
|
||||
|
||||
/* PCI slot mapping. */
|
||||
unsigned int pci_first_slot;
|
||||
struct iommu *iommu;
|
||||
|
||||
/* Now things for the actual PCI bus probes. */
|
||||
unsigned int pci_first_busno;
|
||||
|
|
@ -220,17 +130,12 @@ struct pci_controller_info {
|
|||
*/
|
||||
int index;
|
||||
|
||||
/* Do the PBMs both exist in the same PCI domain? */
|
||||
int pbms_same_domain;
|
||||
|
||||
/* The PCI bus modules controlled by us. */
|
||||
struct pci_pbm_info pbm_A;
|
||||
struct pci_pbm_info pbm_B;
|
||||
|
||||
/* Operations which are controller specific. */
|
||||
void (*scan_bus)(struct pci_controller_info *);
|
||||
void (*base_address_update)(struct pci_dev *, int);
|
||||
void (*resource_adjust)(struct pci_dev *, struct resource *, struct resource *);
|
||||
|
||||
#ifdef CONFIG_PCI_MSI
|
||||
int (*setup_msi_irq)(unsigned int *virt_irq_p, struct pci_dev *pdev,
|
||||
|
|
@ -244,27 +149,4 @@ struct pci_controller_info {
|
|||
unsigned int pci_last_busno;
|
||||
};
|
||||
|
||||
/* PCI devices which are not bridges have this placed in their pci_dev
|
||||
* sysdata member. This makes OBP aware PCI device drivers easier to
|
||||
* code.
|
||||
*/
|
||||
struct pcidev_cookie {
|
||||
struct pci_pbm_info *pbm;
|
||||
struct device_node *prom_node;
|
||||
struct of_device *op;
|
||||
struct linux_prom_pci_registers prom_regs[PROMREG_MAX];
|
||||
int num_prom_regs;
|
||||
struct linux_prom_pci_registers prom_assignments[PROMREG_MAX];
|
||||
int num_prom_assignments;
|
||||
#ifdef CONFIG_PCI_MSI
|
||||
unsigned int msi_num;
|
||||
#endif
|
||||
};
|
||||
|
||||
/* Currently these are the same across all PCI controllers
|
||||
* we support. Someday they may not be...
|
||||
*/
|
||||
#define PCI_IRQ_IGN 0x000007c0 /* Interrupt Group Number */
|
||||
#define PCI_IRQ_INO 0x0000003f /* Interrupt Number */
|
||||
|
||||
#endif /* !(__SPARC64_PBM_H) */
|
||||
|
|
|
|||
|
|
@ -54,7 +54,7 @@ struct pci_iommu_ops {
|
|||
void (*dma_sync_sg_for_cpu)(struct pci_dev *, struct scatterlist *, int, int);
|
||||
};
|
||||
|
||||
extern struct pci_iommu_ops *pci_iommu_ops;
|
||||
extern const struct pci_iommu_ops *pci_iommu_ops;
|
||||
|
||||
/* Allocate and map kernel buffer using consistent mode DMA for a device.
|
||||
* hwdev should be valid struct pci_dev pointer for PCI devices.
|
||||
|
|
|
|||
|
|
@ -737,20 +737,6 @@ extern unsigned long pte_file(pte_t);
|
|||
extern pte_t pgoff_to_pte(unsigned long);
|
||||
#define PTE_FILE_MAX_BITS (64UL - PAGE_SHIFT - 1UL)
|
||||
|
||||
extern unsigned long prom_virt_to_phys(unsigned long, int *);
|
||||
|
||||
extern unsigned long sun4u_get_pte(unsigned long);
|
||||
|
||||
static inline unsigned long __get_phys(unsigned long addr)
|
||||
{
|
||||
return sun4u_get_pte(addr);
|
||||
}
|
||||
|
||||
static inline int __get_iospace(unsigned long addr)
|
||||
{
|
||||
return ((sun4u_get_pte(addr) & 0xf0000000) >> 28);
|
||||
}
|
||||
|
||||
extern unsigned long *sparc64_valid_addr_bitmap;
|
||||
|
||||
/* Needs to be defined here and not in linux/mm.h, as it is arch dependent */
|
||||
|
|
@ -791,6 +777,8 @@ extern void pgtable_cache_init(void);
|
|||
extern void sun4v_register_fault_status(void);
|
||||
extern void sun4v_ktsb_register(void);
|
||||
|
||||
extern unsigned long cmdline_memory_size;
|
||||
|
||||
#endif /* !(__ASSEMBLY__) */
|
||||
|
||||
#endif /* !(_SPARC64_PGTABLE_H) */
|
||||
|
|
|
|||
|
|
@ -36,8 +36,8 @@ struct property {
|
|||
|
||||
struct of_irq_controller;
|
||||
struct device_node {
|
||||
char *name;
|
||||
char *type;
|
||||
const char *name;
|
||||
const char *type;
|
||||
phandle node;
|
||||
char *path_component_name;
|
||||
char *full_name;
|
||||
|
|
@ -93,11 +93,13 @@ extern struct device_node *of_find_node_by_phandle(phandle handle);
|
|||
extern struct device_node *of_get_parent(const struct device_node *node);
|
||||
extern struct device_node *of_get_next_child(const struct device_node *node,
|
||||
struct device_node *prev);
|
||||
extern struct property *of_find_property(struct device_node *np,
|
||||
extern struct property *of_find_property(const struct device_node *np,
|
||||
const char *name,
|
||||
int *lenp);
|
||||
extern int of_device_is_compatible(struct device_node *device, const char *);
|
||||
extern void *of_get_property(struct device_node *node, const char *name,
|
||||
extern int of_device_is_compatible(const struct device_node *device,
|
||||
const char *);
|
||||
extern const void *of_get_property(const struct device_node *node,
|
||||
const char *name,
|
||||
int *lenp);
|
||||
#define get_property(node,name,lenp) of_get_property(node,name,lenp)
|
||||
extern int of_set_property(struct device_node *node, const char *name, void *val, int len);
|
||||
|
|
|
|||
|
|
@ -42,15 +42,15 @@ extern int hard_smp_processor_id(void);
|
|||
#define raw_smp_processor_id() (current_thread_info()->cpu)
|
||||
|
||||
extern void smp_setup_cpu_possible_map(void);
|
||||
extern unsigned char boot_cpu_id;
|
||||
|
||||
#endif /* !(__ASSEMBLY__) */
|
||||
|
||||
#else
|
||||
|
||||
#define smp_setup_cpu_possible_map() do { } while (0)
|
||||
#define boot_cpu_id (0)
|
||||
|
||||
#endif /* !(CONFIG_SMP) */
|
||||
|
||||
#define NO_PROC_ID 0xFF
|
||||
|
||||
#endif /* !(_SPARC64_SMP_H) */
|
||||
|
|
|
|||
|
|
@ -3,7 +3,7 @@
|
|||
|
||||
#ifdef __KERNEL__
|
||||
|
||||
#define SECTION_SIZE_BITS 26
|
||||
#define SECTION_SIZE_BITS 31
|
||||
#define MAX_PHYSADDR_BITS 42
|
||||
#define MAX_PHYSMEM_BITS 42
|
||||
|
||||
|
|
|
|||
|
|
@ -11,22 +11,19 @@
|
|||
|
||||
|
||||
struct sparc64_tick_ops {
|
||||
void (*init_tick)(unsigned long);
|
||||
unsigned long (*get_tick)(void);
|
||||
unsigned long (*get_compare)(void);
|
||||
unsigned long (*add_tick)(unsigned long, unsigned long);
|
||||
unsigned long (*add_compare)(unsigned long);
|
||||
int (*add_compare)(unsigned long);
|
||||
unsigned long softint_mask;
|
||||
void (*disable_irq)(void);
|
||||
|
||||
void (*init_tick)(void);
|
||||
unsigned long (*add_tick)(unsigned long);
|
||||
|
||||
char *name;
|
||||
};
|
||||
|
||||
extern struct sparc64_tick_ops *tick_ops;
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
extern unsigned long timer_tick_offset;
|
||||
struct pt_regs;
|
||||
extern void timer_tick_interrupt(struct pt_regs *);
|
||||
#endif
|
||||
|
||||
extern unsigned long sparc64_get_clock_tick(unsigned int cpu);
|
||||
|
||||
#endif /* _SPARC64_TIMER_H */
|
||||
|
|
|
|||
|
|
@ -157,23 +157,6 @@
|
|||
ba,a,pt %xcc, rtrap_irq; \
|
||||
.previous;
|
||||
|
||||
#define TICK_SMP_IRQ \
|
||||
rdpr %pil, %g2; \
|
||||
wrpr %g0, 15, %pil; \
|
||||
sethi %hi(1f-4), %g7; \
|
||||
ba,pt %xcc, etrap_irq; \
|
||||
or %g7, %lo(1f-4), %g7; \
|
||||
nop; \
|
||||
nop; \
|
||||
nop; \
|
||||
.subsection 2; \
|
||||
1: call trace_hardirqs_off; \
|
||||
nop; \
|
||||
call smp_percpu_timer_interrupt; \
|
||||
add %sp, PTREGS_OFF, %o0; \
|
||||
ba,a,pt %xcc, rtrap_irq; \
|
||||
.previous;
|
||||
|
||||
#else
|
||||
|
||||
#define TRAP_IRQ(routine, level) \
|
||||
|
|
@ -186,16 +169,6 @@
|
|||
add %sp, PTREGS_OFF, %o1; \
|
||||
ba,a,pt %xcc, rtrap_irq;
|
||||
|
||||
#define TICK_SMP_IRQ \
|
||||
rdpr %pil, %g2; \
|
||||
wrpr %g0, 15, %pil; \
|
||||
sethi %hi(109f), %g7; \
|
||||
ba,pt %xcc, etrap_irq; \
|
||||
109: or %g7, %lo(109b), %g7; \
|
||||
call smp_percpu_timer_interrupt; \
|
||||
add %sp, PTREGS_OFF, %o0; \
|
||||
ba,a,pt %xcc, rtrap_irq;
|
||||
|
||||
#endif
|
||||
|
||||
#define TRAP_IVEC TRAP_NOSAVE(do_ivec)
|
||||
|
|
|
|||
|
|
@ -47,6 +47,12 @@ extern int strncmp(const char *,const char *,__kernel_size_t);
|
|||
#ifndef __HAVE_ARCH_STRNICMP
|
||||
extern int strnicmp(const char *, const char *, __kernel_size_t);
|
||||
#endif
|
||||
#ifndef __HAVE_ARCH_STRCASECMP
|
||||
extern int strcasecmp(const char *s1, const char *s2);
|
||||
#endif
|
||||
#ifndef __HAVE_ARCH_STRNCASECMP
|
||||
extern int strncasecmp(const char *s1, const char *s2, size_t n);
|
||||
#endif
|
||||
#ifndef __HAVE_ARCH_STRCHR
|
||||
extern char * strchr(const char *,int);
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in a new issue