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interconnect: qcom: Add interconnect provider driver for Holi

Browse source 
Introduce Qualcomm Holi specific provider driver using the
interconnect framework.

Change-Id: I428bd3260c00f5c0e02d37d81935b55badd81305
Signed-off-by: Odelu Kukatla <[email protected]>
This commit is contained in:
Odelu Kukatla 2020-06-21 16:18:47 +05:30 • committed by Gerrit - the friendly Code Review server
commit 0320785f77
6 changed files with 2130 additions and 0 deletions
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14
drivers/interconnect/qcom/Kconfig
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@ -5,6 +5,17 @@ config INTERCONNECT_QCOM
help
Support for Qualcomm's Network-on-Chip interconnect hardware.
config INTERCONNECT_QCOM_HOLI
tristate "Qualcomm HOLI interconnect driver"
depends on INTERCONNECT_QCOM
depends on MSM_RPM_SMD
select INTERCONNECT_QCOM_RPM
help
This is a driver for the Qualcomm Technologies, Inc. Network-on-Chip
on holi-based platforms. The interconnect provider collects and
aggreagates the cosumer bandwidth requests to satisfy constraints
placed on Network-on-Chip performance states.
config INTERCONNECT_QCOM_QCS404
tristate "Qualcomm QCS404 interconnect driver"
depends on INTERCONNECT_QCOM
@ -70,3 +81,6 @@ config INTERCONNECT_QCOM_SDXLEMUR
help
This is a driver for the Qualcomm Technologies, Inc. Network-on-Chip
on sdxlemur-based platforms.
config INTERCONNECT_QCOM_RPM
tristate

4
drivers/interconnect/qcom/Makefile
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@ -1,5 +1,6 @@
# SPDX-License-Identifier: GPL-2.0
qnoc-holi-objs := holi.o
qnoc-qcs404-objs := qcs404.o
qnoc-sdm845-objs := sdm845.o
qnoc-lahaina-objs := lahaina.o qnoc-qos.o
@ -8,12 +9,15 @@ qnoc-shima-objs := shima.o
icc-smd-rpm-objs := smd-rpm.o
icc-bcm-voter-objs := bcm-voter.o
icc-rpmh-obj := icc-rpmh.o
icc-rpm-objs := icc-rpm.o
obj-$(CONFIG_INTERCONNECT_QCOM_HOLI) += qnoc-holi.o
obj-$(CONFIG_INTERCONNECT_QCOM_QCS404) += qnoc-qcs404.o
obj-$(CONFIG_INTERCONNECT_QCOM_SDM845) += qnoc-sdm845.o
obj-$(CONFIG_INTERCONNECT_QCOM_LAHAINA) += qnoc-lahaina.o
obj-$(CONFIG_INTERCONNECT_QCOM_SHIMA) += qnoc-shima.o
obj-$(CONFIG_INTERCONNECT_QCOM_SDXLEMUR) += qnoc-sdxlemur.o
obj-$(CONFIG_INTERCONNECT_QCOM_RPM) += icc-rpm.o
obj-$(CONFIG_INTERCONNECT_QCOM_SMD_RPM) += icc-smd-rpm.o
obj-$(CONFIG_INTERCONNECT_QCOM_BCM_VOTER) += icc-bcm-voter.o
obj-$(CONFIG_INTERCONNECT_QCOM_RPMH) += icc-rpmh.o

1327
drivers/interconnect/qcom/holi.c Normal file
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File diff suppressed because it is too large Load diff

199
drivers/interconnect/qcom/icc-rpm.c Normal file
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@ -0,0 +1,199 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*
*/
#include <asm/div64.h>
#include <linux/clk.h>
#include <linux/interconnect.h>
#include <linux/interconnect-provider.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/soc/qcom/smd-rpm.h>
#include "icc-rpm.h"
static int qcom_icc_rpm_smd_send_msg(int ctx, int rsc_type, int rpm_id, u64 val)
{
int ret;
struct msm_rpm_kvp rpm_kvp;
rpm_kvp.length = sizeof(uint64_t);
rpm_kvp.key = RPM_MASTER_FIELD_BW;
rpm_kvp.data = (uint8_t *)&val;
ret = msm_rpm_send_message(ctx, rsc_type, rpm_id, &rpm_kvp, 1);
return ret;
}
/**
* qcom_icc_rpm_pre_aggregate - cleans up stale values from prior icc_set
* @node: icc node to operate on
*/
void qcom_icc_rpm_pre_aggregate(struct icc_node *node)
{
size_t i;
struct qcom_icc_node *qn;
qn = node->data;
for (i = 0; i < RPM_NUM_CXT; i++) {
qn->sum_avg[i] = 0;
qn->max_peak[i] = 0;
}
}
EXPORT_SYMBOL_GPL(qcom_icc_rpm_pre_aggregate);
/**
* qcom_icc_rpm_aggregate - aggregate bw for buckets indicated by tag
* @node: node to aggregate
* @tag: tag to indicate which buckets to aggregate
* @avg_bw: new bw to sum aggregate
* @peak_bw: new bw to max aggregate
* @agg_avg: existing aggregate avg bw val
* @agg_peak: existing aggregate peak bw val
*/
int qcom_icc_rpm_aggregate(struct icc_node *node, u32 tag, u32 avg_bw,
u32 peak_bw, u32 *agg_avg, u32 *agg_peak)
{
size_t i;
struct qcom_icc_node *qn;
qn = node->data;
if (!tag)
tag = BIT(RPM_SLEEP_CXT) | BIT(RPM_ACTIVE_CXT);
else
tag = BIT(RPM_ACTIVE_CXT);
for (i = 0; i < RPM_NUM_CXT; i++) {
if (tag & BIT(i)) {
qn->sum_avg[i] += avg_bw;
qn->max_peak[i] = max_t(u32, qn->max_peak[i], peak_bw);
}
}
qn->dirty = true;
return 0;
}
EXPORT_SYMBOL_GPL(qcom_icc_rpm_aggregate);
/**
* qcom_icc_rpm_set - set the constraints based on path
* @src: source node for the path to set constraints on
* @dst: destination node for the path to set constraints on
*
* Return: 0 on success, or an error code otherwise
*/
int qcom_icc_rpm_set(struct icc_node *src, struct icc_node *dst)
{
struct qcom_icc_provider *qp;
struct qcom_icc_node *qn;
struct icc_node *n, *node;
struct icc_provider *provider;
int ret, i;
int rpm_ctx;
u64 clk_rate, sum_avg, max_peak;
u64 bus_clk_rate[RPM_NUM_CXT] = {0, 0};
if (!src)
node = dst;
else
node = src;
qp = to_qcom_provider(node->provider);
qn = node->data;
if (!qn->dirty)
return 0;
provider = node->provider;
list_for_each_entry(n, &provider->nodes, node_list) {
qn = n->data;
for (i = 0; i < RPM_NUM_CXT; i++) {
sum_avg = icc_units_to_bps(qn->sum_avg[i]);
do_div(sum_avg, qn->channels);
max_peak = icc_units_to_bps(qn->max_peak[i]);
clk_rate = max(sum_avg, max_peak);
do_div(clk_rate, qn->buswidth);
bus_clk_rate[i] = max(bus_clk_rate[i], clk_rate);
}
}
for (i = 0; i < RPM_NUM_CXT; i++) {
if (qp->bus_clk_cur_rate[i] != bus_clk_rate[i]) {
ret = clk_set_rate(qp->bus_clks[i].clk,
bus_clk_rate[i]);
if (ret) {
pr_err("%s clk_set_rate error: %d\n",
qp->bus_clks[i].id, ret);
return ret;
}
qp->bus_clk_cur_rate[i] = bus_clk_rate[i];
}
}
list_for_each_entry(n, &provider->nodes, node_list) {
qn = n->data;
if (!qn->dirty)
continue;
qn->dirty = false;
if ((qn->mas_rpm_id == -1) && (qn->slv_rpm_id == -1))
continue;
/* send bandwidth request message to the RPM processor */
for (i = 0; i < RPM_NUM_CXT; i++) {
if (qn->last_sum_avg[i] != qn->sum_avg[i]) {
rpm_ctx = (i == RPM_SLEEP_CXT) ?
RPM_SLEEP_SET : RPM_ACTIVE_SET;
sum_avg = icc_units_to_bps(qn->sum_avg[i]);
if (qn->mas_rpm_id != -1) {
ret = qcom_icc_rpm_smd_send_msg(
rpm_ctx,
RPM_BUS_MASTER_REQ,
qn->mas_rpm_id,
sum_avg);
if (ret) {
pr_err("qcom_icc_rpm_smd_send_msg mas %d error %d\n",
qn->mas_rpm_id, ret);
return ret;
}
}
if (qn->slv_rpm_id != -1) {
ret = qcom_icc_rpm_smd_send_msg(
rpm_ctx,
RPM_BUS_SLAVE_REQ,
qn->slv_rpm_id,
sum_avg);
if (ret) {
pr_err("qcom_icc_rpm_smd_send_msg slv %s error %d\n",
qn->slv_rpm_id, ret);
return ret;
}
}
qn->last_sum_avg[i] = qn->sum_avg[i];
}
}
}
return 0;
}
EXPORT_SYMBOL_GPL(qcom_icc_rpm_set);
MODULE_LICENSE("GPL v2");

102
drivers/interconnect/qcom/icc-rpm.h Normal file
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@ -0,0 +1,102 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*
*/
#ifndef __DRIVERS_INTERCONNECT_QCOM_ICC_RPM_H__
#define __DRIVERS_INTERCONNECT_QCOM_ICC_RPM_H__
#include <linux/regmap.h>
#include <soc/qcom/rpm-smd.h>
#define MAX_LINKS 64
#define RPM_BUS_MASTER_REQ 0x73616d62
#define RPM_BUS_SLAVE_REQ 0x766c7362
#define RPM_SLEEP_SET MSM_RPM_CTX_SLEEP_SET
#define RPM_ACTIVE_SET MSM_RPM_CTX_ACTIVE_SET
#define to_qcom_provider(_provider) \
container_of(_provider, struct qcom_icc_provider, provider)
enum qcom_icc_rpm_slave_field_type {
RPM_SLAVE_FIELD_BW = 0x00007762,
};
enum qcom_icc_rpm_mas_field_type {
RPM_MASTER_FIELD_BW = 0x00007762,
RPM_MASTER_FIELD_BW_T0 = 0x30747762,
RPM_MASTER_FIELD_BW_T1 = 0x31747762,
RPM_MASTER_FIELD_BW_T2 = 0x32747762,
};
enum qcom_icc_rpm_context {
RPM_SLEEP_CXT,
RPM_ACTIVE_CXT,
RPM_NUM_CXT
};
/**
* struct qcom_icc_provider - QTI specific interconnect provider
* @provider: generic interconnect provider
* @dev: reference to the NoC device
* @bus_clks: the clk_bulk_data table of bus clocks
* @num_clks: the total number of clk_bulk_data entries
* @bus_clk_cur_rate: current frequency of bus clock
*/
struct qcom_icc_provider {
struct icc_provider provider;
struct device *dev;
struct regmap *regmap;
struct clk_bulk_data *bus_clks;
int num_clks;
u64 bus_clk_cur_rate[RPM_NUM_CXT];
};
/**
* struct qcom_icc_node - QTI specific interconnect nodes
* @name: the node name used in debugfs
* @id: a unique node identifier
* @links: an array of nodes where we can go next while traversing
* @num_links: the total number of @links
* @channels: num of channels at this node
* @buswidth: width of the interconnect between a node and the bus (bytes)
* @last_sum_avg: aggregated average bandwidth from previous aggregation
* @sum_avg: current sum aggregate value of all avg bw requests
* @max_peak: current max aggregate value of all peak bw requests
* @mas_rpm_id: RPM id for devices that are bus masters
* @slv_rpm_id: RPM id for devices that are bus slaves
* @dirty: flag used to indicate whether the node needs to be committed
*/
struct qcom_icc_node {
const char *name;
u16 id;
u16 links[MAX_LINKS];
u16 num_links;
u16 channels;
u16 buswidth;
u64 last_sum_avg[RPM_NUM_CXT];
u64 sum_avg[RPM_NUM_CXT];
u64 max_peak[RPM_NUM_CXT];
int mas_rpm_id;
int slv_rpm_id;
struct regmap *regmap;
struct qcom_icc_qosbox *qosbox;
const struct qcom_icc_noc_ops *noc_ops;
bool dirty;
};
struct qcom_icc_desc {
const struct regmap_config *config;
struct qcom_icc_node **nodes;
size_t num_nodes;
};
int qcom_icc_rpm_aggregate(struct icc_node *node, u32 tag, u32 avg_bw,
u32 peak_bw, u32 *agg_avg, u32 *agg_peak);
int qcom_icc_rpm_set(struct icc_node *src, struct icc_node *dst);
void qcom_icc_rpm_pre_aggregate(struct icc_node *node);
#endif

484
drivers/interconnect/qcom/rpm-ids.h Normal file
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@ -0,0 +1,484 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*
*/
#ifndef __DRIVERS_INTERCONNECT_QCOM_RPM_IDS_H__
#define __DRIVERS_INTERCONNECT_QCOM_RPM_IDS_H__
/*
* ID's used in RPM messages
*/
#define ICBID_MASTER_APPSS_PROC 0
#define ICBID_MASTER_MSS_PROC 1
#define ICBID_MASTER_MNOC_BIMC 2
#define ICBID_MASTER_SNOC_BIMC 3
#define ICBID_MASTER_SNOC_BIMC_0 ICBID_MASTER_SNOC_BIMC
#define ICBID_MASTER_CNOC_MNOC_MMSS_CFG 4
#define ICBID_MASTER_CNOC_MNOC_CFG 5
#define ICBID_MASTER_GFX3D 6
#define ICBID_MASTER_JPEG 7
#define ICBID_MASTER_MDP 8
#define ICBID_MASTER_MDP0 ICBID_MASTER_MDP
#define ICBID_MASTER_MDPS ICBID_MASTER_MDP
#define ICBID_MASTER_VIDEO 9
#define ICBID_MASTER_VIDEO_P0 ICBID_MASTER_VIDEO
#define ICBID_MASTER_VIDEO_P1 10
#define ICBID_MASTER_VFE 11
#define ICBID_MASTER_VFE0 ICBID_MASTER_VFE
#define ICBID_MASTER_CNOC_ONOC_CFG 12
#define ICBID_MASTER_JPEG_OCMEM 13
#define ICBID_MASTER_MDP_OCMEM 14
#define ICBID_MASTER_VIDEO_P0_OCMEM 15
#define ICBID_MASTER_VIDEO_P1_OCMEM 16
#define ICBID_MASTER_VFE_OCMEM 17
#define ICBID_MASTER_LPASS_AHB 18
#define ICBID_MASTER_QDSS_BAM 19
#define ICBID_MASTER_SNOC_CFG 20
#define ICBID_MASTER_BIMC_SNOC 21
#define ICBID_MASTER_BIMC_SNOC_0 ICBID_MASTER_BIMC_SNOC
#define ICBID_MASTER_CNOC_SNOC 22
#define ICBID_MASTER_CRYPTO 23
#define ICBID_MASTER_CRYPTO_CORE0 ICBID_MASTER_CRYPTO
#define ICBID_MASTER_CRYPTO_CORE1 24
#define ICBID_MASTER_LPASS_PROC 25
#define ICBID_MASTER_MSS 26
#define ICBID_MASTER_MSS_NAV 27
#define ICBID_MASTER_OCMEM_DMA 28
#define ICBID_MASTER_PNOC_SNOC 29
#define ICBID_MASTER_WCSS 30
#define ICBID_MASTER_QDSS_ETR 31
#define ICBID_MASTER_USB3 32
#define ICBID_MASTER_USB3_0 ICBID_MASTER_USB3
#define ICBID_MASTER_SDCC_1 33
#define ICBID_MASTER_EMMC ICBID_MASTER_SDCC_1
#define ICBID_MASTER_SDCC_3 34
#define ICBID_MASTER_SDCC_2 35
#define ICBID_MASTER_SDCC_4 36
#define ICBID_MASTER_TSIF 37
#define ICBID_MASTER_BAM_DMA 38
#define ICBID_MASTER_BLSP_2 39
#define ICBID_MASTER_USB_HSIC 40
#define ICBID_MASTER_BLSP_1 41
#define ICBID_MASTER_QUP_1 ICBID_MASTER_BLSP_1
#define ICBID_MASTER_USB_HS 42
#define ICBID_MASTER_USB_HS1 ICBID_MASTER_USB_HS
#define ICBID_MASTER_PNOC_CFG 43
#define ICBID_MASTER_SNOC_PNOC 44
#define ICBID_MASTER_RPM_INST 45
#define ICBID_MASTER_RPM_DATA 46
#define ICBID_MASTER_RPM_SYS 47
#define ICBID_MASTER_DEHR 48
#define ICBID_MASTER_QDSS_DAP 49
#define ICBID_MASTER_SPDM 50
#define ICBID_MASTER_TIC 51
#define ICBID_MASTER_SNOC_CNOC 52
#define ICBID_MASTER_GFX3D_OCMEM 53
#define ICBID_MASTER_GFX3D_GMEM ICBID_MASTER_GFX3D_OCMEM
#define ICBID_MASTER_OVIRT_SNOC 54
#define ICBID_MASTER_SNOC_OVIRT 55
#define ICBID_MASTER_SNOC_GVIRT ICBID_MASTER_SNOC_OVIRT
#define ICBID_MASTER_ONOC_OVIRT 56
#define ICBID_MASTER_USB_HS2 57
#define ICBID_MASTER_QPIC 58
#define ICBID_MASTER_IPA 59
#define ICBID_MASTER_DSI 60
#define ICBID_MASTER_MDP1 61
#define ICBID_MASTER_MDPE ICBID_MASTER_MDP1
#define ICBID_MASTER_VPU_PROC 62
#define ICBID_MASTER_VPU 63
#define ICBID_MASTER_VPU0 ICBID_MASTER_VPU
#define ICBID_MASTER_CRYPTO_CORE2 64
#define ICBID_MASTER_PCIE_0 65
#define ICBID_MASTER_PCIE_1 66
#define ICBID_MASTER_SATA 67
#define ICBID_MASTER_UFS 68
#define ICBID_MASTER_USB3_1 69
#define ICBID_MASTER_VIDEO_OCMEM 70
#define ICBID_MASTER_VPU1 71
#define ICBID_MASTER_VCAP 72
#define ICBID_MASTER_EMAC 73
#define ICBID_MASTER_BCAST 74
#define ICBID_MASTER_MMSS_PROC 75
#define ICBID_MASTER_SNOC_BIMC_1 76
#define ICBID_MASTER_SNOC_PCNOC 77
#define ICBID_MASTER_AUDIO 78
#define ICBID_MASTER_MM_INT_0 79
#define ICBID_MASTER_MM_INT_1 80
#define ICBID_MASTER_MM_INT_2 81
#define ICBID_MASTER_MM_INT_BIMC 82
#define ICBID_MASTER_MSS_INT 83
#define ICBID_MASTER_PCNOC_CFG 84
#define ICBID_MASTER_PCNOC_INT_0 85
#define ICBID_MASTER_PCNOC_INT_1 86
#define ICBID_MASTER_PCNOC_M_0 87
#define ICBID_MASTER_PCNOC_M_1 88
#define ICBID_MASTER_PCNOC_S_0 89
#define ICBID_MASTER_PCNOC_S_1 90
#define ICBID_MASTER_PCNOC_S_2 91
#define ICBID_MASTER_PCNOC_S_3 92
#define ICBID_MASTER_PCNOC_S_4 93
#define ICBID_MASTER_PCNOC_S_6 94
#define ICBID_MASTER_PCNOC_S_7 95
#define ICBID_MASTER_PCNOC_S_8 96
#define ICBID_MASTER_PCNOC_S_9 97
#define ICBID_MASTER_QDSS_INT 98
#define ICBID_MASTER_SNOC_INT_0 99
#define ICBID_MASTER_SNOC_INT_1 100
#define ICBID_MASTER_SNOC_INT_BIMC 101
#define ICBID_MASTER_TCU_0 102
#define ICBID_MASTER_TCU_1 103
#define ICBID_MASTER_BIMC_INT_0 104
#define ICBID_MASTER_BIMC_INT_1 105
#define ICBID_MASTER_CAMERA 106
#define ICBID_MASTER_RICA 107
#define ICBID_MASTER_SNOC_BIMC_2 108
#define ICBID_MASTER_BIMC_SNOC_1 109
#define ICBID_MASTER_A0NOC_SNOC 110
#define ICBID_MASTER_A1NOC_SNOC 111
#define ICBID_MASTER_A2NOC_SNOC 112
#define ICBID_MASTER_PIMEM 113
#define ICBID_MASTER_SNOC_VMEM 114
#define ICBID_MASTER_CPP 115
#define ICBID_MASTER_CNOC_A1NOC 116
#define ICBID_MASTER_PNOC_A1NOC 117
#define ICBID_MASTER_HMSS 118
#define ICBID_MASTER_PCIE_2 119
#define ICBID_MASTER_ROTATOR 120
#define ICBID_MASTER_VENUS_VMEM 121
#define ICBID_MASTER_DCC 122
#define ICBID_MASTER_MCDMA 123
#define ICBID_MASTER_PCNOC_INT_2 124
#define ICBID_MASTER_PCNOC_INT_3 125
#define ICBID_MASTER_PCNOC_INT_4 126
#define ICBID_MASTER_PCNOC_INT_5 127
#define ICBID_MASTER_PCNOC_INT_6 128
#define ICBID_MASTER_PCNOC_S_5 129
#define ICBID_MASTER_SENSORS_AHB 130
#define ICBID_MASTER_SENSORS_PROC 131
#define ICBID_MASTER_QSPI 132
#define ICBID_MASTER_VFE1 133
#define ICBID_MASTER_SNOC_INT_2 134
#define ICBID_MASTER_SMMNOC_BIMC 135
#define ICBID_MASTER_CRVIRT_A1NOC 136
#define ICBID_MASTER_XM_USB_HS1 137
#define ICBID_MASTER_XI_USB_HS1 138
#define ICBID_MASTER_PCNOC_BIMC_1 139
#define ICBID_MASTER_BIMC_PCNOC 140
#define ICBID_MASTER_XI_HSIC 141
#define ICBID_MASTER_SGMII 142
#define ICBID_MASTER_SPMI_FETCHER 143
#define ICBID_MASTER_GNOC_BIMC 144
#define ICBID_MASTER_CRVIRT_A2NOC 145
#define ICBID_MASTER_CNOC_A2NOC 146
#define ICBID_MASTER_WLAN 147
#define ICBID_MASTER_MSS_CE 148
#define ICBID_MASTER_CDSP_PROC 149
#define ICBID_MASTER_GNOC_SNOC 150
#define ICBID_MASTER_MODEM_WRAPPER 151
#define ICBID_MASTER_SDIO 152
#define ICBID_MASTER_BIMC_SNOC_PCIE 153
#define ICBID_MASTER_WLAN_PROC 154
#define ICBID_MASTER_CRVIRT_PCNOC 155
#define ICBID_MASTER_WLAN_INT 156
#define ICBID_MASTER_PCNOC_S_10 157
#define ICBID_MASTER_PCNOC_S_11 158
#define ICBID_MASTER_LPASS_LPAIF 159
#define ICBID_MASTER_LPASS_LEC 160
#define ICBID_MASTER_LPASS_ANOC_BIMC 161
#define ICBID_MASTER_SNOC_BIMC_RT 163
#define ICBID_MASTER_SNOC_BIMC_NRT 164
#define ICBID_MASTER_GPU_CDSP_PROC 165
#define ICBID_MASTER_QUP_0 166
#define ICBID_MASTER_UFS_MEM 167
#define ICBID_MASTER_VIDEO_PROC 168
#define ICBID_MASTER_QUP_CORE_0 170
#define ICBID_MASTER_QUP_CORE_1 171
#define ICBID_MASTER_CAMNOC_SF 172
#define ICBID_MASTER_CAMNOC_HF 173
#define ICBID_SLAVE_EBI1 0
#define ICBID_SLAVE_APPSS_L2 1
#define ICBID_SLAVE_BIMC_SNOC 2
#define ICBID_SLAVE_BIMC_SNOC_0 ICBID_SLAVE_BIMC_SNOC
#define ICBID_SLAVE_CAMERA_CFG 3
#define ICBID_SLAVE_DISPLAY_CFG 4
#define ICBID_SLAVE_OCMEM_CFG 5
#define ICBID_SLAVE_CPR_CFG 6
#define ICBID_SLAVE_CPR_XPU_CFG 7
#define ICBID_SLAVE_MISC_CFG 8
#define ICBID_SLAVE_MISC_XPU_CFG 9
#define ICBID_SLAVE_VENUS_CFG 10
#define ICBID_SLAVE_GFX3D_CFG 11
#define ICBID_SLAVE_MMSS_CLK_CFG 12
#define ICBID_SLAVE_MMSS_CLK_XPU_CFG 13
#define ICBID_SLAVE_MNOC_MPU_CFG 14
#define ICBID_SLAVE_ONOC_MPU_CFG 15
#define ICBID_SLAVE_MNOC_BIMC 16
#define ICBID_SLAVE_SERVICE_MNOC 17
#define ICBID_SLAVE_OCMEM 18
#define ICBID_SLAVE_GMEM ICBID_SLAVE_OCMEM
#define ICBID_SLAVE_SERVICE_ONOC 19
#define ICBID_SLAVE_APPSS 20
#define ICBID_SLAVE_LPASS 21
#define ICBID_SLAVE_USB3 22
#define ICBID_SLAVE_USB3_0 ICBID_SLAVE_USB3
#define ICBID_SLAVE_WCSS 23
#define ICBID_SLAVE_SNOC_BIMC 24
#define ICBID_SLAVE_SNOC_BIMC_0 ICBID_SLAVE_SNOC_BIMC
#define ICBID_SLAVE_SNOC_CNOC 25
#define ICBID_SLAVE_IMEM 26
#define ICBID_SLAVE_OCIMEM ICBID_SLAVE_IMEM
#define ICBID_SLAVE_SNOC_OVIRT 27
#define ICBID_SLAVE_SNOC_GVIRT ICBID_SLAVE_SNOC_OVIRT
#define ICBID_SLAVE_SNOC_PNOC 28
#define ICBID_SLAVE_SNOC_PCNOC ICBID_SLAVE_SNOC_PNOC
#define ICBID_SLAVE_SERVICE_SNOC 29
#define ICBID_SLAVE_QDSS_STM 30
#define ICBID_SLAVE_SDCC_1 31
#define ICBID_SLAVE_EMMC_CFG ICBID_SLAVE_SDCC_1
#define ICBID_SLAVE_SDCC_3 32
#define ICBID_SLAVE_SDCC_2 33
#define ICBID_SLAVE_SDCC_4 34
#define ICBID_SLAVE_TSIF 35
#define ICBID_SLAVE_BAM_DMA 36
#define ICBID_SLAVE_BLSP_2 37
#define ICBID_SLAVE_USB_HSIC 38
#define ICBID_SLAVE_BLSP_1 39
#define ICBID_SLAVE_QUP_1 ICBID_SLAVE_BLSP_1
#define ICBID_SLAVE_USB_HS 40
#define ICBID_SLAVE_USB_HS1 ICBID_SLAVE_USB_HS
#define ICBID_SLAVE_PDM 41
#define ICBID_SLAVE_PERIPH_APU_CFG 42
#define ICBID_SLAVE_PNOC_MPU_CFG 43
#define ICBID_SLAVE_PRNG 44
#define ICBID_SLAVE_PNOC_SNOC 45
#define ICBID_SLAVE_PCNOC_SNOC ICBID_SLAVE_PNOC_SNOC
#define ICBID_SLAVE_SERVICE_PNOC 46
#define ICBID_SLAVE_CLK_CTL 47
#define ICBID_SLAVE_CNOC_MSS 48
#define ICBID_SLAVE_PCNOC_MSS ICBID_SLAVE_CNOC_MSS
#define ICBID_SLAVE_SECURITY 49
#define ICBID_SLAVE_TCSR 50
#define ICBID_SLAVE_TLMM 51
#define ICBID_SLAVE_CRYPTO_0_CFG 52
#define ICBID_SLAVE_CRYPTO_1_CFG 53
#define ICBID_SLAVE_IMEM_CFG 54
#define ICBID_SLAVE_MESSAGE_RAM 55
#define ICBID_SLAVE_BIMC_CFG 56
#define ICBID_SLAVE_BOOT_ROM 57
#define ICBID_SLAVE_CNOC_MNOC_MMSS_CFG 58
#define ICBID_SLAVE_PMIC_ARB 59
#define ICBID_SLAVE_SPDM_WRAPPER 60
#define ICBID_SLAVE_DEHR_CFG 61
#define ICBID_SLAVE_MPM 62
#define ICBID_SLAVE_QDSS_CFG 63
#define ICBID_SLAVE_RBCPR_CFG 64
#define ICBID_SLAVE_RBCPR_CX_CFG ICBID_SLAVE_RBCPR_CFG
#define ICBID_SLAVE_RBCPR_QDSS_APU_CFG 65
#define ICBID_SLAVE_CNOC_MNOC_CFG 66
#define ICBID_SLAVE_SNOC_MPU_CFG 67
#define ICBID_SLAVE_CNOC_ONOC_CFG 68
#define ICBID_SLAVE_PNOC_CFG 69
#define ICBID_SLAVE_SNOC_CFG 70
#define ICBID_SLAVE_EBI1_DLL_CFG 71
#define ICBID_SLAVE_PHY_APU_CFG 72
#define ICBID_SLAVE_EBI1_PHY_CFG 73
#define ICBID_SLAVE_RPM 74
#define ICBID_SLAVE_CNOC_SNOC 75
#define ICBID_SLAVE_SERVICE_CNOC 76
#define ICBID_SLAVE_OVIRT_SNOC 77
#define ICBID_SLAVE_OVIRT_OCMEM 78
#define ICBID_SLAVE_USB_HS2 79
#define ICBID_SLAVE_QPIC 80
#define ICBID_SLAVE_IPS_CFG 81
#define ICBID_SLAVE_DSI_CFG 82
#define ICBID_SLAVE_USB3_1 83
#define ICBID_SLAVE_PCIE_0 84
#define ICBID_SLAVE_PCIE_1 85
#define ICBID_SLAVE_PSS_SMMU_CFG 86
#define ICBID_SLAVE_CRYPTO_2_CFG 87
#define ICBID_SLAVE_PCIE_0_CFG 88
#define ICBID_SLAVE_PCIE_1_CFG 89
#define ICBID_SLAVE_SATA_CFG 90
#define ICBID_SLAVE_SPSS_GENI_IR 91
#define ICBID_SLAVE_UFS_CFG 92
#define ICBID_SLAVE_AVSYNC_CFG 93
#define ICBID_SLAVE_VPU_CFG 94
#define ICBID_SLAVE_USB_PHY_CFG 95
#define ICBID_SLAVE_RBCPR_MX_CFG 96
#define ICBID_SLAVE_PCIE_PARF 97
#define ICBID_SLAVE_VCAP_CFG 98
#define ICBID_SLAVE_EMAC_CFG 99
#define ICBID_SLAVE_BCAST_CFG 100
#define ICBID_SLAVE_KLM_CFG 101
#define ICBID_SLAVE_DISPLAY_PWM 102
#define ICBID_SLAVE_GENI 103
#define ICBID_SLAVE_SNOC_BIMC_1 104
#define ICBID_SLAVE_AUDIO 105
#define ICBID_SLAVE_CATS_0 106
#define ICBID_SLAVE_CATS_1 107
#define ICBID_SLAVE_MM_INT_0 108
#define ICBID_SLAVE_MM_INT_1 109
#define ICBID_SLAVE_MM_INT_2 110
#define ICBID_SLAVE_MM_INT_BIMC 111
#define ICBID_SLAVE_MMU_MODEM_XPU_CFG 112
#define ICBID_SLAVE_MSS_INT 113
#define ICBID_SLAVE_PCNOC_INT_0 114
#define ICBID_SLAVE_PCNOC_INT_1 115
#define ICBID_SLAVE_PCNOC_M_0 116
#define ICBID_SLAVE_PCNOC_M_1 117
#define ICBID_SLAVE_PCNOC_S_0 118
#define ICBID_SLAVE_PCNOC_S_1 119
#define ICBID_SLAVE_PCNOC_S_2 120
#define ICBID_SLAVE_PCNOC_S_3 121
#define ICBID_SLAVE_PCNOC_S_4 122
#define ICBID_SLAVE_PCNOC_S_6 123
#define ICBID_SLAVE_PCNOC_S_7 124
#define ICBID_SLAVE_PCNOC_S_8 125
#define ICBID_SLAVE_PCNOC_S_9 126
#define ICBID_SLAVE_PRNG_XPU_CFG 127
#define ICBID_SLAVE_QDSS_INT 128
#define ICBID_SLAVE_RPM_XPU_CFG 129
#define ICBID_SLAVE_SNOC_INT_0 130
#define ICBID_SLAVE_SNOC_INT_1 131
#define ICBID_SLAVE_SNOC_INT_BIMC 132
#define ICBID_SLAVE_TCU 133
#define ICBID_SLAVE_BIMC_INT_0 134
#define ICBID_SLAVE_BIMC_INT_1 135
#define ICBID_SLAVE_RICA_CFG 136
#define ICBID_SLAVE_SNOC_BIMC_2 137
#define ICBID_SLAVE_BIMC_SNOC_1 138
#define ICBID_SLAVE_PNOC_A1NOC 139
#define ICBID_SLAVE_SNOC_VMEM 140
#define ICBID_SLAVE_A0NOC_SNOC 141
#define ICBID_SLAVE_A1NOC_SNOC 142
#define ICBID_SLAVE_A2NOC_SNOC 143
#define ICBID_SLAVE_A0NOC_CFG 144
#define ICBID_SLAVE_A0NOC_MPU_CFG 145
#define ICBID_SLAVE_A0NOC_SMMU_CFG 146
#define ICBID_SLAVE_A1NOC_CFG 147
#define ICBID_SLAVE_A1NOC_MPU_CFG 148
#define ICBID_SLAVE_A1NOC_SMMU_CFG 149
#define ICBID_SLAVE_A2NOC_CFG 150
#define ICBID_SLAVE_A2NOC_MPU_CFG 151
#define ICBID_SLAVE_A2NOC_SMMU_CFG 152
#define ICBID_SLAVE_AHB2PHY 153
#define ICBID_SLAVE_CAMERA_THROTTLE_CFG 154
#define ICBID_SLAVE_DCC_CFG 155
#define ICBID_SLAVE_DISPLAY_THROTTLE_CFG 156
#define ICBID_SLAVE_DSA_CFG 157
#define ICBID_SLAVE_DSA_MPU_CFG 158
#define ICBID_SLAVE_SSC_MPU_CFG 159
#define ICBID_SLAVE_HMSS_L3 160
#define ICBID_SLAVE_LPASS_SMMU_CFG 161
#define ICBID_SLAVE_MMAGIC_CFG 162
#define ICBID_SLAVE_PCIE20_AHB2PHY 163
#define ICBID_SLAVE_PCIE_2 164
#define ICBID_SLAVE_PCIE_2_CFG 165
#define ICBID_SLAVE_PIMEM 166
#define ICBID_SLAVE_PIMEM_CFG 167
#define ICBID_SLAVE_QDSS_RBCPR_APU_CFG 168
#define ICBID_SLAVE_RBCPR_CX 169
#define ICBID_SLAVE_RBCPR_MX 170
#define ICBID_SLAVE_SMMU_CPP_CFG 171
#define ICBID_SLAVE_SMMU_JPEG_CFG 172
#define ICBID_SLAVE_SMMU_MDP_CFG 173
#define ICBID_SLAVE_SMMU_ROTATOR_CFG 174
#define ICBID_SLAVE_SMMU_VENUS_CFG 175
#define ICBID_SLAVE_SMMU_VFE_CFG 176
#define ICBID_SLAVE_SSC_CFG 177
#define ICBID_SLAVE_VENUS_THROTTLE_CFG 178
#define ICBID_SLAVE_VMEM 179
#define ICBID_SLAVE_VMEM_CFG 180
#define ICBID_SLAVE_QDSS_MPU_CFG 181
#define ICBID_SLAVE_USB3_PHY_CFG 182
#define ICBID_SLAVE_IPA_CFG 183
#define ICBID_SLAVE_PCNOC_INT_2 184
#define ICBID_SLAVE_PCNOC_INT_3 185
#define ICBID_SLAVE_PCNOC_INT_4 186
#define ICBID_SLAVE_PCNOC_INT_5 187
#define ICBID_SLAVE_PCNOC_INT_6 188
#define ICBID_SLAVE_PCNOC_S_5 189
#define ICBID_SLAVE_QSPI 190
#define ICBID_SLAVE_A1NOC_MS_MPU_CFG 191
#define ICBID_SLAVE_A2NOC_MS_MPU_CFG 192
#define ICBID_SLAVE_MODEM_Q6_SMMU_CFG 193
#define ICBID_SLAVE_MSS_MPU_CFG 194
#define ICBID_SLAVE_MSS_PROC_MS_MPU_CFG 195
#define ICBID_SLAVE_SKL 196
#define ICBID_SLAVE_SNOC_INT_2 197
#define ICBID_SLAVE_SMMNOC_BIMC 198
#define ICBID_SLAVE_CRVIRT_A1NOC 199
#define ICBID_SLAVE_SGMII 200
#define ICBID_SLAVE_QHS4_APPS 201
#define ICBID_SLAVE_BIMC_PCNOC 202
#define ICBID_SLAVE_PCNOC_BIMC_1 203
#define ICBID_SLAVE_SPMI_FETCHER 204
#define ICBID_SLAVE_MMSS_SMMU_CFG 205
#define ICBID_SLAVE_WLAN 206
#define ICBID_SLAVE_CRVIRT_A2NOC 207
#define ICBID_SLAVE_CNOC_A2NOC 208
#define ICBID_SLAVE_GLM 209
#define ICBID_SLAVE_GNOC_BIMC 210
#define ICBID_SLAVE_GNOC_SNOC 211
#define ICBID_SLAVE_QM_CFG 212
#define ICBID_SLAVE_TLMM_EAST 213
#define ICBID_SLAVE_TLMM_NORTH 214
#define ICBID_SLAVE_TLMM_WEST 215
#define ICBID_SLAVE_TLMM_SOUTH 216
#define ICBID_SLAVE_TLMM_CENTER 217
#define ICBID_SLAVE_MSS_NAV_CE_MPU_CFG 218
#define ICBID_SLAVE_A2NOC_THROTTLE_CFG 219
#define ICBID_SLAVE_CDSP 220
#define ICBID_SLAVE_CDSP_SMMU_CFG 221
#define ICBID_SLAVE_LPASS_MPU_CFG 222
#define ICBID_SLAVE_CSI_PHY_CFG 223
#define ICBID_SLAVE_DDRSS_CFG 224
#define ICBID_SLAVE_DDRSS_MPU_CFG 225
#define ICBID_SLAVE_SNOC_MSS_XPU_CFG 226
#define ICBID_SLAVE_BIMC_MSS_XPU_CFG 227
#define ICBID_SLAVE_MSS_SNOC_MPU_CFG 228
#define ICBID_SLAVE_MSS 229
#define ICBID_SLAVE_SDIO 230
#define ICBID_SLAVE_QM_MPU_CFG 231
#define ICBID_SLAVE_BIMC_SNOC_PCIE 232
#define ICBID_SLAVE_BOOTIMEM 233
#define ICBID_SLAVE_CDSP_CFG 234
#define ICBID_SLAVE_WLAN_DSP_CFG 235
#define ICBID_SLAVE_GENIR_XPU_CFG 236
#define ICBID_SLAVE_BOOTIMEM_MPU 237
#define ICBID_SLAVE_CRVIRT_PCNOC 238
#define ICBID_SLAVE_WLAN_INT 239
#define ICBID_SLAVE_WLAN_MPU_CFG 240
#define ICBID_SLAVE_LPASS_AGNOC_CFG 241
#define ICBID_SLAVE_LPASS_AGNOC_XPU_CFG 242
#define ICBID_SLAVE_PLL_BIAS_CFG 243
#define ICBID_SLAVE_EMAC 244
#define ICBID_SLAVE_PCNOC_S_10 245
#define ICBID_SLAVE_PCNOC_S_11 246
#define ICBID_SLAVE_LPASS_ANOC_BIMC 247
#define ICBID_SLAVE_SNOC_BIMC_NRT 259
#define ICBID_SLAVE_SNOC_BIMC_RT 260
#define ICBID_SLAVE_QUP_0 261
#define ICBID_SLAVE_UFS_MEM_CFG 262
#define ICBID_SLAVE_VSENSE_CTRL_CFG 263
#define ICBID_SLAVE_QUP_CORE_0 264
#define ICBID_SLAVE_QUP_CORE_1 265
#define ICBID_SLAVE_GPU_CDSP_BIMC 266
#define ICBID_SLAVE_AHB2PHY_USB 268
#define ICBID_SLAVE_APSS_THROTTLE_CFG 270
#define ICBID_SLAVE_CAMERA_NRT_THROTTLE_CFG 271
#define ICBID_SLAVE_CDSP_THROTTLE_CFG 272
#define ICBID_SLAVE_DDR_PHY_CFG 273
#define ICBID_SLAVE_DDR_SS_CFG 274
#define ICBID_SLAVE_GPU_CFG 275
#define ICBID_SLAVE_GPU_THROTTLE_CFG 276
#define ICBID_SLAVE_MAPSS 277
#define ICBID_SLAVE_MDSP_MPU_CFG 278
#define ICBID_SLAVE_CAMERA_RT_THROTTLE_CFG 279
#define ICBID_SLAVE_HWKM 280
#define ICBID_SLAVE_PKA_WRAPPER 281
#endif