From bef77e5704cefcfd9d2eb3331ba789dcdd586966 Mon Sep 17 00:00:00 2001
From: Sarthak Garg <sartgarg@qti.qualcomm.com>
Date: Tue, 15 Dec 2020 18:28:08 +0530
Subject: [PATCH] ARM: dts: msm: Update drive strength values for sdc1 node on
 shima

Getting CRC errors for some eMMC devices on shima.
So use the VI recommended drive strength values for sdc1 node.

Change-Id: I86ff6acaf12156cf1bc0c885acc62814606e32eb
---
 qcom/shima-pinctrl.dtsi | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/qcom/shima-pinctrl.dtsi b/qcom/shima-pinctrl.dtsi
index 5e2c03340973..672784ffdbdd 100644
--- a/qcom/shima-pinctrl.dtsi
+++ b/qcom/shima-pinctrl.dtsi
@@ -1550,19 +1550,19 @@
 			clk {
 				pins = "sdc1_clk";
 				bias-disable;
-				drive-strength = <16>;
+				drive-strength = <12>;
 			};
 
 			cmd {
 				pins = "sdc1_cmd";
 				bias-pull-up;
-				drive-strength = <10>;
+				drive-strength = <12>;
 			};
 
 			data {
 				pins = "sdc1_data";
 				bias-pull-up;
-				drive-strength = <10>;
+				drive-strength = <12>;
 			};
 
 			rclk {