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[ARM] 3266/1: S3C2400 - adds macro S3C24XX

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Patch from Lucas Correia Villa Real

This patch defines S3C2400 memory map and adds a S3C24XX macro for
common resources between S3C2400, S3C2410 and S3C2440 cpus.

Signed-off-by: Lucas Correia Villa Real <[email protected]>
Signed-off-by: Ben Dooks <[email protected]>
Signed-off-by: Russell King <[email protected]>
This commit is contained in:
Lucas Correia Villa Real 2006-01-26 15:20:50 +00:00 • committed by Russell King
commit 0367a8d37a
9 changed files with 83 additions and 43 deletions
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6
include/asm-arm/arch-s3c2410/debug-macro.S
View file

@ -25,7 +25,7 @@
.macro addruart, rx
mrc p15, 0, \rx, c1, c0
tst \rx, #1
ldreq \rx, = S3C2410_PA_UART
ldreq \rx, = S3C24XX_PA_UART
ldrne \rx, = S3C24XX_VA_UART
#if CONFIG_DEBUG_S3C2410_UART != 0
add \rx, \rx, #(S3C2410_UART1_OFF * CONFIG_DEBUG_S3C2410_UART)
@ -44,7 +44,7 @@
1003:
mrc p15, 0, \rd, c1, c0
tst \rd, #1
addeq \rd, \rx, #(S3C2410_PA_GPIO - S3C2410_PA_UART)
addeq \rd, \rx, #(S3C24XX_PA_GPIO - S3C24XX_PA_UART)
addne \rd, \rx, #(S3C24XX_VA_GPIO - S3C24XX_VA_UART)
bic \rd, \rd, #0xff000
ldr \rd, [ \rd, # S3C2410_GSTATUS1 - S3C2410_GPIOREG(0) ]
@ -75,7 +75,7 @@
1003:
mrc p15, 0, \rd, c1, c0
tst \rd, #1
addeq \rd, \rx, #(S3C2410_PA_GPIO - S3C2410_PA_UART)
addeq \rd, \rx, #(S3C24XX_PA_GPIO - S3C24XX_PA_UART)
addne \rd, \rx, #(S3C24XX_VA_GPIO - S3C24XX_VA_UART)
bic \rd, \rd, #0xff000
ldr \rd, [ \rd, # S3C2410_GSTATUS1 - S3C2410_GPIOREG(0) ]

38
include/asm-arm/arch-s3c2410/map.h
View file

@ -14,6 +14,7 @@
* 06-Jan-2003 BJD Linux 2.6.0 version, moved bast specifics out
* 10-Feb-2005 BJD Added CAMIF definition from guillaume.gourat@nexvision.tv
* 10-Mar-2005 LCVR Added support to S3C2400, changed {VA,SZ} names
* 15-Jan-2006 LCVR Added S3C24XX_PA macros for common S3C24XX resources
*/
#ifndef __ASM_ARCH_MAP_H
@ -188,5 +189,42 @@
#define S3C2400_SDRAM_PA (S3C2400_CS6)
/* Use a single interface for common resources between S3C24XX cpus */
#ifdef CONFIG_CPU_S3C2400
#define S3C24XX_PA_IRQ S3C2400_PA_IRQ
#define S3C24XX_PA_MEMCTRL S3C2400_PA_MEMCTRL
#define S3C24XX_PA_USBHOST S3C2400_PA_USBHOST
#define S3C24XX_PA_DMA S3C2400_PA_DMA
#define S3C24XX_PA_CLKPWR S3C2400_PA_CLKPWR
#define S3C24XX_PA_LCD S3C2400_PA_LCD
#define S3C24XX_PA_UART S3C2400_PA_UART
#define S3C24XX_PA_TIMER S3C2400_PA_TIMER
#define S3C24XX_PA_USBDEV S3C2400_PA_USBDEV
#define S3C24XX_PA_WATCHDOG S3C2400_PA_WATCHDOG
#define S3C24XX_PA_IIC S3C2400_PA_IIC
#define S3C24XX_PA_IIS S3C2400_PA_IIS
#define S3C24XX_PA_GPIO S3C2400_PA_GPIO
#define S3C24XX_PA_RTC S3C2400_PA_RTC
#define S3C24XX_PA_ADC S3C2400_PA_ADC
#define S3C24XX_PA_SPI S3C2400_PA_SPI
#else
#define S3C24XX_PA_IRQ S3C2410_PA_IRQ
#define S3C24XX_PA_MEMCTRL S3C2410_PA_MEMCTRL
#define S3C24XX_PA_USBHOST S3C2410_PA_USBHOST
#define S3C24XX_PA_DMA S3C2410_PA_DMA
#define S3C24XX_PA_CLKPWR S3C2410_PA_CLKPWR
#define S3C24XX_PA_LCD S3C2410_PA_LCD
#define S3C24XX_PA_UART S3C2410_PA_UART
#define S3C24XX_PA_TIMER S3C2410_PA_TIMER
#define S3C24XX_PA_USBDEV S3C2410_PA_USBDEV
#define S3C24XX_PA_WATCHDOG S3C2410_PA_WATCHDOG
#define S3C24XX_PA_IIC S3C2410_PA_IIC
#define S3C24XX_PA_IIS S3C2410_PA_IIS
#define S3C24XX_PA_GPIO S3C2410_PA_GPIO
#define S3C24XX_PA_RTC S3C2410_PA_RTC
#define S3C24XX_PA_ADC S3C2410_PA_ADC
#define S3C24XX_PA_SPI S3C2410_PA_SPI
#endif
#endif /* __ASM_ARCH_MAP_H */

6
include/asm-arm/arch-s3c2410/regs-serial.h
View file

@ -39,9 +39,9 @@
#define S3C24XX_VA_UART1 (S3C24XX_VA_UART + 0x4000 )
#define S3C24XX_VA_UART2 (S3C24XX_VA_UART + 0x8000 )
#define S3C2410_PA_UART0 (S3C2410_PA_UART)
#define S3C2410_PA_UART1 (S3C2410_PA_UART + 0x4000 )
#define S3C2410_PA_UART2 (S3C2410_PA_UART + 0x8000 )
#define S3C2410_PA_UART0 (S3C24XX_PA_UART)
#define S3C2410_PA_UART1 (S3C24XX_PA_UART + 0x4000 )
#define S3C2410_PA_UART2 (S3C24XX_PA_UART + 0x8000 )
#define S3C2410_URXH (0x24)
#define S3C2410_UTXH (0x20)

6
include/asm-arm/arch-s3c2410/uncompress.h
View file

@ -35,13 +35,13 @@
#undef S3C2410_GPIOREG
#undef S3C2410_WDOGREG
#define S3C2410_GPIOREG(x) ((S3C2410_PA_GPIO + (x)))
#define S3C2410_WDOGREG(x) ((S3C2410_PA_WATCHDOG + (x)))
#define S3C2410_GPIOREG(x) ((S3C24XX_PA_GPIO + (x)))
#define S3C2410_WDOGREG(x) ((S3C24XX_PA_WATCHDOG + (x)))
/* how many bytes we allow into the FIFO at a time in FIFO mode */
#define FIFO_MAX (14)
#define uart_base S3C2410_PA_UART + (0x4000*CONFIG_S3C2410_LOWLEVEL_UART_PORT)
#define uart_base S3C24XX_PA_UART + (0x4000*CONFIG_S3C2410_LOWLEVEL_UART_PORT)
static __inline__ void
uart_wr(unsigned int reg, unsigned int val)