A-Team_Digital_Solutions/android_kernel_motorola_sm6375
Watch
2
0
Fork
You've already forked android_kernel_motorola_sm6375
 0
mirror of https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git synced 2026-10-08 21:22:09 -04:00
Code Issues Projects Releases Packages Wiki Activity

Merge "ARM: dts: msm: Add camera device tree support for Shima camera" into camera-kernel.lnx.4.0

Browse source
This commit is contained in:
Camera Software Integration 2020-07-02 17:46:45 -07:00 • committed by Gerrit - the friendly Code Review server
commit 03e07ea7fe
1 changed files with 912 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

912
shima-camera.dtsi Normal file
View file

@ -0,0 +1,912 @@
#include <dt-bindings/msm/msm-camera.h>
&soc {
qcom,cam-req-mgr {
compatible = "qcom,cam-req-mgr";
status = "ok"
};
qcom,cam-sync {
compatible = "qcom,cam-sync";
status = "ok"
};
qcom,cam_smmu {
compatible = "qcom,msm-cam-smmu", "simple-bus";
status = "ok"
msm_cam_smmu_ife {
compatible = "qcom,msm-cam-smmu-cb";
iommus = <&apps_smmu 0x1000 0x440>,
<&apps_smmu 0x1040 0x440>,
<&apps_smmu 0x1400 0x440>,
<&apps_smmu 0x1440 0x440>;
qcom,iommu-dma-addr-pool = <0x7400000 0xd8c00000>;
label = "ife", "ife-cdm";
multiple-client-devices;
ife_iova_mem_map: iova-mem-map {
/* IO region is approximately 3.4 GB */
iova-mem-region-io {
iova-region-name = "io";
iova-region-start = <0x7400000>;
iova-region-len = <0xd8c00000>;
iova-region-id = <0x3>;
status = "ok"
};
};
};
msm_cam_smmu_jpeg {
compatible = "qcom,msm-cam-smmu-cb";
iommus = <&apps_smmu 0x2840 0x400>,
<&apps_smmu 0x2C40 0x400>;
label = "jpeg";
qcom,iommu-dma-addr-pool = <0x7400000 0xd8c00000>;
jpeg_iova_mem_map: iova-mem-map {
/* IO region is approximately 3.4 GB */
iova-mem-region-io {
iova-region-name = "io";
iova-region-start = <0x7400000>;
iova-region-len = <0xd8c00000>;
iova-region-id = <0x3>;
status = "ok"
};
};
};
msm_cam_icp_fw {
compatible = "qcom,msm-cam-smmu-fw-dev";
label="icp";
memory-region = <&pil_camera_mem>;
};
msm_cam_smmu_icp {
compatible = "qcom,msm-cam-smmu-cb";
iommus = <&apps_smmu 0x28E2 0x400>,
<&apps_smmu 0x2CE2 0x400>,
<&apps_smmu 0x2800 0x400>,
<&apps_smmu 0x2C00 0x400>,
<&apps_smmu 0x2860 0x400>,
<&apps_smmu 0x2C60 0x400>,
<&apps_smmu 0x2820 0x400>,
<&apps_smmu 0x2C20 0x400>;
label = "icp";
qcom,iommu-dma-addr-pool = <0x10c00000 0xcf300000>;
icp_iova_mem_map: iova-mem-map {
iova-mem-region-firmware {
/* Firmware region is 5MB */
iova-region-name = "firmware";
iova-region-start = <0x0>;
iova-region-len = <0x500000>;
iova-region-id = <0x0>;
status = "ok"
};
iova-mem-region-shared {
/* Shared region is 150MB long */
iova-region-name = "shared";
iova-region-start = <0x7400000>;
iova-region-len = <0x9600000>;
iova-region-id = <0x1>;
status = "ok"
};
iova-mem-region-secondary-heap {
/* Secondary heap region is 1MB long */
iova-region-name = "secheap";
iova-region-start = <0x10a00000>;
iova-region-len = <0x100000>;
iova-region-id = <0x4>;
status = "ok"
};
iova-mem-region-io {
/* IO region is approximately 3.3 GB */
iova-region-name = "io";
iova-region-start = <0x10c00000>;
iova-region-len = <0xcf300000>;
iova-region-id = <0x3>;
status = "ok"
};
iova-mem-qdss-region {
/* QDSS region is appropriate 1MB */
iova-region-name = "qdss";
iova-region-start = <0x10b00000>;
iova-region-len = <0x100000>;
iova-region-id = <0x5>;
qdss-phy-addr = <0x16790000>;
status = "ok"
};
};
};
msm_cam_smmu_cpas_cdm {
compatible = "qcom,msm-cam-smmu-cb";
iommus = <&apps_smmu 0x28C0 0x400>,
<&apps_smmu 0x2CC0 0x400>;
label = "cpas-cdm";
qcom,iommu-dma-addr-pool = <0x7400000 0xd8c00000>;
cpas_cdm_iova_mem_map: iova-mem-map {
iova-mem-region-io {
/* IO region is approximately 3.4 GB */
iova-region-name = "io";
iova-region-start = <0x7400000>;
iova-region-len = <0xd8c00000>;
iova-region-id = <0x3>;
status = "ok"
};
};
};
msm_cam_smmu_secure {
compatible = "qcom,msm-cam-smmu-cb";
label = "cam-secure";
qcom,secure-cb;
};
};
qcom,cam-cdm-intf {
compatible = "qcom,cam-cdm-intf";
cell-index = <0>;
label = "cam-cdm-intf";
num-hw-cdm = <1>;
cdm-client-names = "vfe",
"jpegdma",
"jpegenc";
status = "ok"
};
qcom,cpas-cdm0 {
cell-index = <0>;
compatible = "qcom,cam-cpas-cdm1_2";
label = "cpas-cdm";
reg = <0xac4d000 0x1000>;
reg-names = "cpas-cdm";
reg-cam-base = <0x4d000>;
interrupts = <GIC_SPI 461 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "cpas-cdm";
regulator-names = "camss";
camss-supply = <&cam_cc_titan_top_gdsc>;
clock-names = "cam_cc_cpas_slow_ahb_clk",
"cam_cc_cpas_ahb_clk";
clocks = <&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
<&camcc CAM_CC_CPAS_AHB_CLK>;
clock-rates = <0 0>;
clock-cntl-level = "svs";
cdm-client-names = "ife3", "ife4";
status = "ok"
};
qcom,ife-cdm0 {
cell-index = <0>;
compatible = "qcom,cam-ife-cdm1_2";
label = "ife-cdm";
reg = <0xacb4200 0x1000>;
reg-names = "ife-cdm0";
reg-cam-base = <0xb4200>;
interrupts = <GIC_SPI 456 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "ife-cdm0";
regulator-names = "camss","ife0";
camss-supply = <&cam_cc_titan_top_gdsc>;
ife0-supply = <&cam_cc_ife_0_gdsc>;
clock-names = "ife_0_ahb",
"ife_0_areg",
"ife_clk",
"ife_axi_clk",
"cam_cc_cpas_ahb_clk";
clocks =
<&camcc CAM_CC_IFE_0_AHB_CLK>,
<&camcc CAM_CC_IFE_0_AREG_CLK>,
<&camcc CAM_CC_IFE_0_CLK>,
<&camcc CAM_CC_IFE_0_AXI_CLK>,
<&camcc CAM_CC_CPAS_AHB_CLK>;
clock-rates =
<0 0 0 0 0>,
<0 0 0 0 0>,
<0 0 0 0 0>,
<0 0 0 0 0>;
clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo";
cdm-client-names = "ife0";
status = "ok"
};
qcom,ife-cdm1 {
cell-index = <1>;
compatible = "qcom,cam-ife-cdm1_2";
label = "ife-cdm";
reg = <0xacc3200 0x1000>;
reg-names = "ife-cdm1";
reg-cam-base = <0xc3200>;
interrupts = <GIC_SPI 287 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "ife-cdm1";
regulator-names = "camss","ife1";
camss-supply = <&cam_cc_titan_top_gdsc>;
ife1-supply = <&cam_cc_ife_1_gdsc>;
clock-names = "ife_1_ahb",
"ife_1_areg",
"ife_clk",
"ife_axi_clk",
"cam_cc_cpas_ahb_clk";
clocks =
<&camcc CAM_CC_IFE_1_AHB_CLK>,
<&camcc CAM_CC_IFE_1_AREG_CLK>,
<&camcc CAM_CC_IFE_1_CLK>,
<&camcc CAM_CC_IFE_1_AXI_CLK>,
<&camcc CAM_CC_CPAS_AHB_CLK>;
clock-rates =
<0 0 0 0 0>,
<0 0 0 0 0>,
<0 0 0 0 0>,
<0 0 0 0 0>;
clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo";
cdm-client-names = "ife1";
status = "ok"
};
qcom,ife-cdm2 {
cell-index = <2>;
compatible = "qcom,cam-ife-cdm1_2";
label = "ife-cdm";
reg = <0xacef200 0x1000>;
reg-names = "ife-cdm2";
reg-cam-base = <0xef200>;
interrupts = <GIC_SPI 642 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "ife-cdm2";
regulator-names = "camss","ife2";
camss-supply = <&cam_cc_titan_top_gdsc>;
ife2-supply = <&cam_cc_ife_2_gdsc>;
clock-names = "ife_2_ahb",
"ife_2_areg",
"ife_clk",
"ife_axi_clk",
"cam_cc_cpas_ahb_clk";
clocks =
<&camcc CAM_CC_IFE_2_AHB_CLK>,
<&camcc CAM_CC_IFE_2_AREG_CLK>,
<&camcc CAM_CC_IFE_2_CLK>,
<&camcc CAM_CC_IFE_2_AXI_CLK>,
<&camcc CAM_CC_CPAS_AHB_CLK>;
clock-rates =
<0 0 0 0 0>,
<0 0 0 0 0>,
<0 0 0 0 0>,
<0 0 0 0 0>;
clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo";
cdm-client-names = "ife2";
status = "ok"
};
qcom,cam-isp {
compatible = "qcom,cam-isp";
arch-compat = "ife";
status = "ok"
};
cam_csid0: qcom,csid0 {
cell-index = <0>;
compatible = "qcom,csid580";
reg-names = "csid";
reg = <0xacb5200 0x1000>;
reg-cam-base = <0xb5200>;
interrupt-names = "csid0";
interrupts = <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>;
regulator-names = "camss", "ife0";
camss-supply = <&cam_cc_titan_top_gdsc>;
ife0-supply = <&cam_cc_ife_0_gdsc>;
clock-names =
"ife_csid_clk_src",
"ife_csid_clk",
"cphy_rx_clk_src",
"ife_cphy_rx_clk",
"ife_clk_src",
"ife_clk",
"ife_0_areg",
"ife_0_ahb",
"ife_axi_clk";
clocks =
<&camcc CAM_CC_IFE_0_CSID_CLK_SRC>,
<&camcc CAM_CC_IFE_0_CSID_CLK>,
<&camcc CAM_CC_CPHY_RX_CLK_SRC>,
<&camcc CAM_CC_IFE_0_CPHY_RX_CLK>,
<&camcc CAM_CC_IFE_0_CLK_SRC>,
<&camcc CAM_CC_IFE_0_CLK>,
<&camcc CAM_CC_IFE_0_AREG_CLK>,
<&camcc CAM_CC_IFE_0_AHB_CLK>,
<&camcc CAM_CC_IFE_0_AXI_CLK>;
clock-rates =
<400000000 0 320000000 0 338000000 0 100000000 0 0>,
<400000000 0 400000000 0 475000000 0 200000000 0 0>,
<400000000 0 400000000 0 600000000 0 300000000 0 0>,
<400000000 0 400000000 0 720000000 0 400000000 0 0>,
<400000000 0 400000000 0 720000000 0 400000000 0 0>;
clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal",
"turbo";
src-clock-name = "ife_csid_clk_src";
clock-control-debugfs = "true";
status = "ok"
};
cam_vfe0: qcom,ife0 {
cell-index = <0>;
compatible = "qcom,vfe580";
reg-names = "ife", "cam_camnoc";
reg = <0xacb4000 0xd000>,
<0xac42000 0x8000>;
reg-cam-base = <0xb4000 0x42000>;
interrupt-names = "ife0";
interrupts = <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>;
regulator-names = "camss", "ife0";
camss-supply = <&cam_cc_titan_top_gdsc>;
ife0-supply = <&cam_cc_ife_0_gdsc>;
clock-names =
"ife_0_ahb",
"ife_0_areg",
"ife_clk_src",
"ife_clk",
"ife_axi_clk";
clocks =
<&camcc CAM_CC_IFE_0_AHB_CLK>,
<&camcc CAM_CC_IFE_0_AREG_CLK>,
<&camcc CAM_CC_IFE_0_CLK_SRC>,
<&camcc CAM_CC_IFE_0_CLK>,
<&camcc CAM_CC_IFE_0_AXI_CLK>;
clock-rates =
<0 100000000 338000000 0 0>,
<0 200000000 475000000 0 0>,
<0 300000000 600000000 0 0>,
<0 400000000 720000000 0 0>,
<0 400000000 720000000 0 0>;
clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal",
"turbo";
src-clock-name = "ife_clk_src";
scl-clk-names = "ife_0_areg";
clock-control-debugfs = "true";
clock-names-option = "ife_dsp_clk";
clocks-option = <&camcc CAM_CC_IFE_0_DSP_CLK>;
clock-rates-option = <720000000>;
ubwc-static-cfg = <0x1026 0x1036>;
status = "ok"
};
cam_csid1: qcom,csid1 {
cell-index = <1>;
compatible = "qcom,csid580";
reg-names = "csid";
reg = <0xacc4200 0x1000>;
reg-cam-base = <0xc4200>;
interrupt-names = "csid1";
interrupts = <GIC_SPI 466 IRQ_TYPE_EDGE_RISING>;
regulator-names = "camss", "ife1";
camss-supply = <&cam_cc_titan_top_gdsc>;
ife1-supply = <&cam_cc_ife_1_gdsc>;
clock-names =
"ife_csid_clk_src",
"ife_csid_clk",
"cphy_rx_clk_src",
"ife_cphy_rx_clk",
"ife_clk_src",
"ife_clk",
"ife_1_areg",
"ife_1_ahb",
"ife_axi_clk";
clocks =
<&camcc CAM_CC_IFE_1_CSID_CLK_SRC>,
<&camcc CAM_CC_IFE_1_CSID_CLK>,
<&camcc CAM_CC_CPHY_RX_CLK_SRC>,
<&camcc CAM_CC_IFE_1_CPHY_RX_CLK>,
<&camcc CAM_CC_IFE_1_CLK_SRC>,
<&camcc CAM_CC_IFE_1_CLK>,
<&camcc CAM_CC_IFE_1_AREG_CLK>,
<&camcc CAM_CC_IFE_1_AHB_CLK>,
<&camcc CAM_CC_IFE_1_AXI_CLK>;
clock-rates =
<400000000 0 320000000 0 338000000 0 100000000 0 0>,
<400000000 0 400000000 0 475000000 0 200000000 0 0>,
<400000000 0 400000000 0 600000000 0 300000000 0 0>,
<400000000 0 400000000 0 720000000 0 400000000 0 0>,
<400000000 0 400000000 0 720000000 0 400000000 0 0>;
clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal",
"turbo";
src-clock-name = "ife_csid_clk_src";
clock-control-debugfs = "true";
status = "ok"
};
cam_vfe1: qcom,ife1 {
cell-index = <1>;
compatible = "qcom,vfe580";
reg-names = "ife", "cam_camnoc";
reg = <0xacc3000 0xd000>,
<0xac42000 0x8000>;
reg-cam-base = <0xc3000 0x42000>;
interrupt-names = "ife1";
interrupts = <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>;
regulator-names = "camss", "ife1";
camss-supply = <&cam_cc_titan_top_gdsc>;
ife1-supply = <&cam_cc_ife_1_gdsc>;
clock-names =
"ife_1_ahb",
"ife_1_areg",
"ife_clk_src",
"ife_clk",
"ife_axi_clk";
clocks =
<&camcc CAM_CC_IFE_1_AHB_CLK>,
<&camcc CAM_CC_IFE_1_AREG_CLK>,
<&camcc CAM_CC_IFE_1_CLK_SRC>,
<&camcc CAM_CC_IFE_1_CLK>,
<&camcc CAM_CC_IFE_1_AXI_CLK>;
clock-rates =
<0 100000000 338000000 0 0>,
<0 200000000 475000000 0 0>,
<0 300000000 600000000 0 0>,
<0 400000000 720000000 0 0>,
<0 400000000 720000000 0 0>;
clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal",
"turbo";
src-clock-name = "ife_clk_src";
scl-clk-names = "ife_1_areg";
clock-control-debugfs = "true";
clock-names-option = "ife_dsp_clk";
clocks-option = <&camcc CAM_CC_IFE_1_DSP_CLK>;
clock-rates-option = <720000000>;
ubwc-static-cfg = <0x1026 0x1036>;
status = "ok"
};
cam_csid2: qcom,csid2 {
cell-index = <2>;
compatible = "qcom,csid580";
reg-names = "csid";
reg = <0xacf0200 0x1000>;
reg-cam-base = <0xf0200>;
interrupt-names = "csid2";
interrupts = <GIC_SPI 640 IRQ_TYPE_EDGE_RISING>;
regulator-names = "camss", "ife2";
camss-supply = <&cam_cc_titan_top_gdsc>;
ife2-supply = <&cam_cc_ife_2_gdsc>;
clock-names =
"ife_csid_clk_src",
"ife_csid_clk",
"cphy_rx_clk_src",
"ife_cphy_rx_clk",
"ife_clk_src",
"ife_clk",
"ife_2_areg",
"ife_2_ahb",
"ife_axi_clk";
clocks =
<&camcc CAM_CC_IFE_2_CSID_CLK_SRC>,
<&camcc CAM_CC_IFE_2_CSID_CLK>,
<&camcc CAM_CC_CPHY_RX_CLK_SRC>,
<&camcc CAM_CC_IFE_2_CPHY_RX_CLK>,
<&camcc CAM_CC_IFE_2_CLK_SRC>,
<&camcc CAM_CC_IFE_2_CLK>,
<&camcc CAM_CC_IFE_2_AREG_CLK>,
<&camcc CAM_CC_IFE_2_AHB_CLK>,
<&camcc CAM_CC_IFE_2_AXI_CLK>;
clock-rates =
<400000000 0 320000000 0 338000000 0 100000000 0 0>,
<400000000 0 400000000 0 475000000 0 200000000 0 0>,
<400000000 0 400000000 0 600000000 0 300000000 0 0>,
<400000000 0 400000000 0 720000000 0 400000000 0 0>,
<400000000 0 400000000 0 720000000 0 400000000 0 0>;
clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal",
"turbo";
src-clock-name = "ife_csid_clk_src";
clock-control-debugfs = "true";
status = "ok"
};
cam_vfe2: qcom,ife2 {
cell-index = <2>;
compatible = "qcom,vfe580";
reg-names = "ife", "cam_camnoc";
reg = <0xacef000 0xd000>,
<0xac42000 0x8000>;
reg-cam-base = <0xef000 0x42000>;
interrupt-names = "ife2";
interrupts = <GIC_SPI 641 IRQ_TYPE_EDGE_RISING>;
regulator-names = "camss", "ife2";
camss-supply = <&cam_cc_titan_top_gdsc>;
ife2-supply = <&cam_cc_ife_2_gdsc>;
clock-names =
"ife_2_ahb",
"ife_2_areg",
"ife_clk_src",
"ife_clk",
"ife_axi_clk";
clocks =
<&camcc CAM_CC_IFE_2_AHB_CLK>,
<&camcc CAM_CC_IFE_2_AREG_CLK>,
<&camcc CAM_CC_IFE_2_CLK_SRC>,
<&camcc CAM_CC_IFE_2_CLK>,
<&camcc CAM_CC_IFE_2_AXI_CLK>;
clock-rates =
<0 100000000 338000000 0 0>,
<0 200000000 475000000 0 0>,
<0 300000000 600000000 0 0>,
<0 400000000 720000000 0 0>,
<0 400000000 720000000 0 0>;
clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal",
"turbo";
src-clock-name = "ife_clk_src";
scl-clk-names = "ife_2_areg";
clock-control-debugfs = "true";
ubwc-static-cfg = <0x1026 0x1036>;
status = "ok"
};
cam_csid_lite0: qcom,csid-lite0 {
cell-index = <3>;
compatible = "qcom,csid-lite580";
reg-names = "csid-lite";
reg = <0xacd9200 0x1000>;
reg-cam-base = <0xd9200>;
interrupt-names = "csid-lite0";
interrupts = <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>;
regulator-names = "camss";
camss-supply = <&cam_cc_titan_top_gdsc>;
clock-names =
"ife_csid_clk_src",
"ife_csid_clk",
"cphy_rx_clk_src",
"ife_cphy_rx_clk",
"ife_clk_src",
"ife_lite_ahb",
"ife_clk";
clocks =
<&camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>,
<&camcc CAM_CC_IFE_LITE_CSID_CLK>,
<&camcc CAM_CC_CPHY_RX_CLK_SRC>,
<&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
<&camcc CAM_CC_IFE_LITE_CLK_SRC>,
<&camcc CAM_CC_IFE_LITE_AHB_CLK>,
<&camcc CAM_CC_IFE_LITE_CLK>;
clock-rates =
<400000000 0 0 0 400000000 0 0>,
<400000000 0 0 0 480000000 0 0>,
<400000000 0 0 0 480000000 0 0>,
<400000000 0 0 0 480000000 0 0>,
<400000000 0 0 0 480000000 0 0>;
clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal",
"turbo";
src-clock-name = "ife_csid_clk_src";
clock-control-debugfs = "true";
status = "ok"
};
cam_vfe_lite0: qcom,ife-lite0 {
cell-index = <3>;
compatible = "qcom,vfe-lite580";
reg-names = "ife-lite";
reg = <0xacd9000 0x2200>;
reg-cam-base = <0xd9000>;
interrupt-names = "ife-lite0";
interrupts = <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>;
regulator-names = "camss";
camss-supply = <&cam_cc_titan_top_gdsc>;
clock-names =
"ife_lite_ahb",
"ife_lite_axi",
"ife_clk_src",
"ife_clk";
clocks =
<&camcc CAM_CC_IFE_LITE_AHB_CLK>,
<&camcc CAM_CC_IFE_LITE_AXI_CLK>,
<&camcc CAM_CC_IFE_LITE_CLK_SRC>,
<&camcc CAM_CC_IFE_LITE_CLK>;
clock-rates =
<0 0 400000000 0>,
<0 0 480000000 0>,
<0 0 480000000 0>,
<0 0 480000000 0>,
<0 0 480000000 0>;
clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal",
"turbo";
src-clock-name = "ife_clk_src";
clock-control-debugfs = "true";
status = "ok"
};
cam_csid_lite1: qcom,csid-lite1 {
cell-index = <4>;
compatible = "qcom,csid-lite580";
reg-names = "csid-lite";
reg = <0xacdb400 0x1000>;
reg-cam-base = <0xdb400>;
interrupt-names = "csid-lite1";
interrupts = <GIC_SPI 359 IRQ_TYPE_EDGE_RISING>;
regulator-names = "camss";
camss-supply = <&cam_cc_titan_top_gdsc>;
clock-names =
"ife_csid_clk_src",
"ife_csid_clk",
"cphy_rx_clk_src",
"ife_cphy_rx_clk",
"ife_clk_src",
"ife_lite_ahb",
"ife_clk";
clocks =
<&camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>,
<&camcc CAM_CC_IFE_LITE_CSID_CLK>,
<&camcc CAM_CC_CPHY_RX_CLK_SRC>,
<&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
<&camcc CAM_CC_IFE_LITE_CLK_SRC>,
<&camcc CAM_CC_IFE_LITE_AHB_CLK>,
<&camcc CAM_CC_IFE_LITE_CLK>;
clock-rates =
<400000000 0 0 0 400000000 0 0>,
<400000000 0 0 0 480000000 0 0>,
<400000000 0 0 0 480000000 0 0>,
<400000000 0 0 0 480000000 0 0>,
<400000000 0 0 0 480000000 0 0>;
clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal",
"turbo";
src-clock-name = "ife_csid_clk_src";
clock-control-debugfs = "true";
status = "ok"
};
cam_vfe_lite1: qcom,ife-lite1 {
cell-index = <4>;
compatible = "qcom,vfe-lite580";
reg-names = "ife-lite";
reg = <0xacdb200 0x2200>;
reg-cam-base = <0xdb200>;
interrupt-names = "ife-lite1";
interrupts = <GIC_SPI 360 IRQ_TYPE_EDGE_RISING>;
regulator-names = "camss";
camss-supply = <&cam_cc_titan_top_gdsc>;
clock-names =
"ife_lite_ahb",
"ife_lite_axi",
"ife_clk_src",
"ife_clk";
clocks =
<&camcc CAM_CC_IFE_LITE_AHB_CLK>,
<&camcc CAM_CC_IFE_LITE_AXI_CLK>,
<&camcc CAM_CC_IFE_LITE_CLK_SRC>,
<&camcc CAM_CC_IFE_LITE_CLK>;
clock-rates =
<0 0 400000000 0>,
<0 0 480000000 0>,
<0 0 480000000 0>,
<0 0 480000000 0>,
<0 0 480000000 0>;
clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal",
"turbo";
src-clock-name = "ife_clk_src";
clock-control-debugfs = "true";
status = "ok"
};
cam_csiphy_tpg0: qcom,tpg0@ac97000 {
cell-index = <0>;
compatible = "qcom,tpg102";
reg-names = "tpg0", "cam_cpas_top";
reg = <0xac97000 0x1000>,
<0xac40000 0x1000>;
reg-cam-base = <0x97000 0x40000>;
regulator-names = "camss";
camss-supply = <&cam_cc_titan_top_gdsc>;
clock-names =
"cphy_rx_clk_src",
"csiphy0_clk",
"csi0phytimer_clk_src",
"csi0phytimer_clk";
clocks =
<&camcc CAM_CC_CPHY_RX_CLK_SRC>,
<&camcc CAM_CC_CSIPHY0_CLK>,
<&camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>,
<&camcc CAM_CC_CSI0PHYTIMER_CLK>;
clock-rates =
<400000000 0 300000000 0>;
clock-cntl-level = "nominal";
src-clock-name = "csi0phytimer_clk_src";
status = "ok"
};
cam_csiphy_tpg1: qcom,tpg1@ac98000 {
cell-index = <1>;
compatible = "qcom,tpg102";
reg-names = "tpg1", "cam_cpas_top";
reg = <0xac98000 0x1000>,
<0xac40000 0x1000>;
reg-cam-base = <0x98000 0x40000>;
regulator-names = "camss";
camss-supply = <&cam_cc_titan_top_gdsc>;
clock-names =
"cphy_rx_clk_src",
"csiphy1_clk",
"csi1phytimer_clk_src",
"csi1phytimer_clk";
clocks =
<&camcc CAM_CC_CPHY_RX_CLK_SRC>,
<&camcc CAM_CC_CSIPHY1_CLK>,
<&camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>,
<&camcc CAM_CC_CSI1PHYTIMER_CLK>;
clock-rates =
<400000000 0 300000000 0>;
clock-cntl-level = "nominal";
src-clock-name = "csi1phytimer_clk_src";
status = "ok"
};
qcom,cam-icp {
compatible = "qcom,cam-icp";
compat-hw-name = "qcom,a5",
"qcom,ipe0",
"qcom,bps";
num-a5 = <1>;
num-ipe = <1>;
num-bps = <1>;
status = "ok"
icp_pc_en;
ipe_bps_pc_en;
};
cam_a5: qcom,a5 {
cell-index = <0>;
compatible = "qcom,cam-a5";
reg = <0xac00000 0x6000>,
<0xac10000 0x8000>,
<0xac18000 0x3000>;
reg-names = "a5_qgic", "a5_sierra", "a5_csr";
reg-cam-base = <0x00000 0x10000 0x18000>;
interrupts = <GIC_SPI 463 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "a5";
regulator-names = "camss-vdd";
camss-vdd-supply = <&cam_cc_titan_top_gdsc>;
clock-names =
"soc_fast_ahb",
"icp_ahb_clk",
"icp_clk_src",
"icp_clk";
src-clock-name = "icp_clk_src";
clocks =
<&camcc CAM_CC_FAST_AHB_CLK_SRC>,
<&camcc CAM_CC_ICP_AHB_CLK>,
<&camcc CAM_CC_ICP_CLK_SRC>,
<&camcc CAM_CC_ICP_CLK>;
clock-rates =
<100000000 0 400000000 0>,
<200000000 0 480000000 0>,
<300000000 0 600000000 0>,
<400000000 0 600000000 0>,
<400000000 0 600000000 0>;
clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal",
"turbo";
fw_name = "CAMERA_ICP.elf";
ubwc-ipe-fetch-cfg = <0x707b 0x7083>;
ubwc-ipe-write-cfg = <0x161ef 0x1620f>;
ubwc-bps-fetch-cfg = <0x707b 0x7083>;
ubwc-bps-write-cfg = <0x161ef 0x1620f>;
status = "ok"
};
cam_ipe0: qcom,ipe0 {
cell-index = <0>;
compatible = "qcom,cam-ipe";
reg = <0xac9a000 0x12000>;
reg-names = "ipe0_top";
reg-cam-base = <0x9a000>;
regulator-names = "ipe0-vdd";
ipe0-vdd-supply = <&cam_cc_ipe_0_gdsc>;
clock-names =
"ipe_0_ahb_clk",
"ipe_0_areg_clk",
"ipe_0_axi_clk",
"ipe_0_clk_src",
"ipe_0_clk";
src-clock-name = "ipe_0_clk_src";
clock-control-debugfs = "true";
clocks =
<&camcc CAM_CC_IPE_0_AHB_CLK>,
<&camcc CAM_CC_IPE_0_AREG_CLK>,
<&camcc CAM_CC_IPE_0_AXI_CLK>,
<&camcc CAM_CC_IPE_0_CLK_SRC>,
<&camcc CAM_CC_IPE_0_CLK>;
clock-rates =
<0 0 0 300000000 0>,
<0 0 0 450000000 0>,
<0 0 0 525000000 0>,
<0 0 0 700000000 0>,
<0 0 0 700000000 0>;
clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal",
"turbo";
status = "ok"
};
cam_bps: qcom,bps {
cell-index = <0>;
compatible = "qcom,cam-bps";
reg = <0xac7a000 0x8000>;
reg-names = "bps_top";
reg-cam-base = <0x7a000>;
regulator-names = "bps-vdd";
bps-vdd-supply = <&cam_cc_bps_gdsc>;
clock-names =
"bps_ahb_clk",
"bps_areg_clk",
"bps_axi_clk",
"bps_clk_src",
"bps_clk";
src-clock-name = "bps_clk_src";
clock-control-debugfs = "true";
clocks =
<&camcc CAM_CC_BPS_AHB_CLK>,
<&camcc CAM_CC_BPS_AREG_CLK>,
<&camcc CAM_CC_BPS_AXI_CLK>,
<&camcc CAM_CC_BPS_CLK_SRC>,
<&camcc CAM_CC_BPS_CLK>;
clock-rates =
<0 0 0 200000000 0>,
<0 0 0 400000000 0>,
<0 0 0 480000000 0>,
<0 0 0 600000000 0>,
<0 0 0 600000000 0>;
clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal",
"turbo";
status = "ok"
};
qcom,cam-jpeg {
compatible = "qcom,cam-jpeg";
compat-hw-name = "qcom,jpegenc",
"qcom,jpegdma";
num-jpeg-enc = <1>;
num-jpeg-dma = <1>;
status = "ok"
};
cam_jpeg_enc: qcom,jpegenc {
cell-index = <0>;
compatible = "qcom,cam_jpeg_enc";
reg-names = "jpege_hw";
reg = <0xac53000 0x4000>;
reg-cam-base = <0x53000>;
interrupt-names = "jpeg";
interrupts = <GIC_SPI 474 IRQ_TYPE_EDGE_RISING>;
regulator-names = "camss-vdd";
camss-vdd-supply = <&cam_cc_titan_top_gdsc>;
clock-names =
"jpegenc_clk_src",
"jpegenc_clk";
clocks =
<&camcc CAM_CC_JPEG_CLK_SRC>,
<&camcc CAM_CC_JPEG_CLK>;
clock-rates = <600000000 0>;
src-clock-name = "jpegenc_clk_src";
clock-cntl-level = "nominal";
status = "ok"
};
cam_jpeg_dma: qcom,jpegdma {
cell-index = <0>;
compatible = "qcom,cam_jpeg_dma";
reg-names = "jpegdma_hw";
reg = <0xac57000 0x4000>;
reg-cam-base = <0x57000>;
interrupt-names = "jpegdma";
interrupts = <GIC_SPI 475 IRQ_TYPE_EDGE_RISING>;
regulator-names = "camss-vdd";
camss-vdd-supply = <&cam_cc_titan_top_gdsc>;
clock-names =
"jpegdma_clk_src",
"jpegdma_clk";
clocks =
<&camcc CAM_CC_JPEG_CLK_SRC>,
<&camcc CAM_CC_JPEG_CLK>;
clock-rates = <600000000 0>;
src-clock-name = "jpegdma_clk_src";
clock-cntl-level = "nominal";
status = "ok"
};
};