diff --git a/qcom/sa8155.dtsi b/qcom/sa8155.dtsi index a3b56e92e55a..b048176d4cbb 100644 --- a/qcom/sa8155.dtsi +++ b/qcom/sa8155.dtsi @@ -49,5 +49,9 @@ /delete-node/ rpmh-regulator-ldof6; }; +&slpi_tlmm { + status = "ok"; +}; + /* Add regulator nodes specific to SA8155 */ #include "sa8155-regulator.dtsi" diff --git a/qcom/sm8150-slpi-pinctrl.dtsi b/qcom/sm8150-slpi-pinctrl.dtsi new file mode 100644 index 000000000000..b31c153a9c41 --- /dev/null +++ b/qcom/sm8150-slpi-pinctrl.dtsi @@ -0,0 +1,186 @@ +&soc { + slpi_tlmm: slpi_pinctrl@02B40000 { + compatible = "qcom,slpi-pinctrl"; + reg = <0x2B40000 0x20000>; + qcom,num-pins = <14>; + status = "disabled"; + + qupv3_se20_i2c_pins: qupv3_se20_i2c_pins { + qupv3_se20_i2c_active: qupv3_se20_i2c_active { + mux { + pins = "gpio0", "gpio1"; + function = "func1"; + }; + + config { + pins = "gpio0", "gpio1"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se20_i2c_sleep: qupv3_se20_i2c_sleep { + mux { + pins = "gpio0", "gpio1"; + function = "gpio"; + }; + + config { + pins = "gpio0", "gpio1"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + qupv3_se21_i2c_pins: qupv3_se21_i2c_pins { + qupv3_se21_i2c_active: qupv3_se21_i2c_active { + mux { + pins = "gpi2", "gpio3"; + function = "func1"; + }; + + config { + pins = "gpio2", "gpio3"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se21_i2c_sleep: qupv3_se21_i2c_sleep { + mux { + pins = "gpio2", "gpio3"; + function = "gpio"; + }; + + config { + pins = "gpio2", "gpio3"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + qupv3_se22_i2c_pins: qupv3_se22_i2c_pins { + qupv3_se22_i2c_active: qupv3_se22_i2c_active { + mux { + pins = "gpio6", "gpio7"; + function = "func1"; + }; + + config { + pins = "gpio6", "gpio7"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se22_i2c_sleep: qupv3_se22_i2c_sleep { + mux { + pins = "gpio6", "gpio7"; + function = "gpio"; + }; + + config { + pins = "gpio6", "gpio7"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + qupv3_se23_i2c_pins: qupv3_se23_i2c_pins { + qupv3_se23_i2c_active: qupv3_se23_i2c_active { + mux { + pins = "gpio8", "gpio9"; + function = "func3"; + }; + + config { + pins = "gpio8", "gpio9"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se23_i2c_sleep: qupv3_se23_i2c_sleep { + mux { + pins = "gpio8", "gpio9"; + function = "gpio"; + }; + + config { + pins = "gpio8", "gpio9"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + /* SE21 pin mappings */ + qupv3_se21_spi_pins: qupv3_se21_spi_pins { + qupv3_se21_spi_active: qupv3_se21_spi_active { + mux { + pins = "gpio2", "gpio3", "gpio4", + "gpio5"; + function = "func1"; + }; + + config { + pins = "gpio2", "gpio3", "gpio4", + "gpio5"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se21_spi_sleep: qupv3_se21_spi_sleep { + mux { + pins = "gpio2", "gpio3", "gpio4", + "gpio5"; + function = "gpio"; + }; + + config { + pins = "gpio2", "gpio3", "gpio4", + "gpio5"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + /*SE22 pin mappings*/ + qupv3_se22_spi_pins: qupv3_se22_spi_pins { + qupv3_se22_spi_active: qupv3_se22_spi_active { + mux { + pins = "gpio6", "gpio7", "gpio8", + "gpio9"; + function = "func1"; + }; + + config { + pins = "gpio6", "gpio7", "gpio8", + "gpio9"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se22_spi_sleep: qupv3_se22_spi_sleep { + mux { + pins = "gpio6", "gpio7", "gpio8", + "gpio9"; + function = "gpio"; + }; + + config { + pins = "gpio6", "gpio7", "gpio8", + "gpio9"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + }; +}; diff --git a/qcom/sm8150.dtsi b/qcom/sm8150.dtsi index ff5b2b8814d1..395f34d5616a 100644 --- a/qcom/sm8150.dtsi +++ b/qcom/sm8150.dtsi @@ -752,3 +752,4 @@ #include "sm8150-pinctrl.dtsi" #include "sm8150-regulator.dtsi" #include "sm8150-pm.dtsi" +#include "sm8150-slpi-pinctrl.dtsi"