From 043c3d60b4f45da1f1fef764e3c74f60eef443f9 Mon Sep 17 00:00:00 2001
From: Rishabh Bhatnagar <rishabhb@quicinc.com>
Date: Mon, 4 Jan 2021 17:19:56 -0800
Subject: [PATCH] ARM: dts: msm: Add device node for ARM PMU for Olympic

Add the ARM CPU Performace measuring unit device tree node to
measure various hardware events like cache misses, cycles etc.

Change-Id: If0d1f358757586e7774ce2810c4683dbc152da66
---
 qcom/sdxlemur.dtsi | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi
index f833437c3762..cdc92be053cd 100644
--- a/qcom/sdxlemur.dtsi
+++ b/qcom/sdxlemur.dtsi
@@ -257,6 +257,11 @@
 		};
 	};
 
+	cpu_pmu: cpu-pmu {
+		compatible = "arm,cortex-a7-pmu";
+		interrupts = <GIC_PPI 8 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
 	qcom,msm-imem@1468f000 {
 		compatible = "qcom,msm-imem";
 		reg = <0x1468f000 0x1000>; /* Address and size of IMEM */