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clk: qcom: gcc: Lower the frequency for sdxlemur from 200 to 171MHz
Update the sdcc clock frequency from 200MHz to 171MHz. Change-Id: Ibada53598071e84ab600aeba9d3418d41d811357 Signed-off-by: Taniya Das <tdas@codeaurora.org>
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parent
52838777d3
commit
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1 changed files with 3 additions and 3 deletions
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@ -1,6 +1,6 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2020, The Linux Foundation. All rights reserved.
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* Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
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*/
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#include <linux/clk-provider.h>
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@ -764,7 +764,7 @@ static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = {
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F(25000000, P_GPLL0_OUT_EVEN, 12, 0, 0),
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F(50000000, P_GPLL0_OUT_EVEN, 6, 0, 0),
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F(100000000, P_GPLL0_OUT_MAIN, 6, 0, 0),
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F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
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F(171428571, P_GPLL0_OUT_MAIN, 3.5, 0, 0),
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{ }
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};
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@ -789,7 +789,7 @@ static struct clk_rcg2 gcc_sdcc1_apps_clk_src = {
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.rate_max = (unsigned long[VDD_NUM]) {
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[VDD_LOWER] = 50000000,
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[VDD_LOW] = 100000000,
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[VDD_NOMINAL] = 200000000},
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[VDD_NOMINAL] = 171428571},
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},
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};
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