From 04896ee4ec2d9bb8adfb4ac73fbef8210223f0e8 Mon Sep 17 00:00:00 2001
From: Vikash Garodia <vgarodia@qti.qualcomm.com>
Date: Mon, 11 Jan 2021 15:46:25 +0530
Subject: [PATCH] ARM: dts: msm: Update max bus vote range for Holi

Existing max bus vote range corresponds to low DDR frequency.
Now when video hardware is made to run at maximum clock and
the max bus vote, DDR is still running at low clock whereas
video hardware runs at max speed.
Update the max bandwidth so as to keep DDR to next corner.

CRs-Fixed: 2858305
Change-Id: Ia20bb6c9ae999bbc75aed627bd200b08fb592bde
---
 qcom/holi-vidc.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/qcom/holi-vidc.dtsi b/qcom/holi-vidc.dtsi
index 5b3aa57de254..3789d98f43e0 100644
--- a/qcom/holi-vidc.dtsi
+++ b/qcom/holi-vidc.dtsi
@@ -36,7 +36,7 @@
 					&bimc SLAVE_EBI>;
 		/* Bus BW range (low, high) for each bus */
 		qcom,bus-range-kbps = <1000 1000
-					1000 2128000>;
+					1000 6500000>;
 
 		/* MMUs */
 		non_secure_cb {