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Allwinner clock changes for 4.14, part 3
Conversion of the last two SoCs (A10, A20) to the sunxi-ng framework. -----BEGIN PGP SIGNATURE----- iQIcBAABAgAGBQJZno1VAAoJEBx+YmzsjxAgJ4gQALqulaGhH4rEjW5oouZ8JJwd O3s4FFazKMXlgV1q/LYbf1eYrUQhJbr4tHTbCbqm3klaMTz6jOAnRlTjSKkoIssA jrtbP6MzHcWE6RnaIA96z45T2p5ZyMGt18/ZgpdQlmmQ9GcV27I+gQs0VsLLPMY0 PGlG+r6qDnwHbCaEymvbLG16/xLVXHmqXrWQ/9GRWRK1fQ7ffgGw80X1ASuflSnE fJCqfhUc1SG3ZGho0xZXFKUvifoaHg1gyFQrrP5mVhYSeUogYSMrvQim/RwwxSVx 6GkHmNj6O15UvD2A7Y71VqjvjNi5gB054J18Nl8PxFJyHPa33ocC5DkbOXEJI6jL PESH29A6myS+v2cY6lm1PVdWIGrDNcCgocjsZSeyn4xKU6oPmFHzlISt0hZPPoQ3 lxqWZrH9rUeVLVAkX2XzMhi4xHc6wZF2eTsp+e0ylDL09c//Dt2ojKgWoN7DeUlN sRgjcPlGB5KRYMYi1ChH5RSsH8h8S4wzF2mSESkGjLCZ82r1BerRBjvaF1MaIEGd xm5yNBw4Y3HL+AoRSEZiZ9FjERfejiI3Q/oqgcLdAGiYD0pDWMU+wjrfHXnQ1yOj HITZaabZRf19D+pNdLpMlzp1UmQQbflCDfOnXaz1r1q6yuWdXvXmgIL2CfQGPqCD Yn+FyX0JEE6yq4lvJ4fA =Wce+ -----END PGP SIGNATURE----- Merge tag 'sunxi-clk-for-4.14-3' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-next Pull more Allwinner clock changes from Maxime Ripard: * Conversion of the last two SoCs (A10, A20) to the sunxi-ng framework * tag 'sunxi-clk-for-4.14-3' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: clk: sunxi-ng: Add sun4i/sun7i CCU driver dt-bindings: List devicetree binding for the CCU of Allwinner A10 dt-bindings: List devicetree binding for the CCU of Allwinner A20
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@ -11,6 +11,19 @@ config SUN50I_A64_CCU
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default ARM64 && ARCH_SUNXI
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depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST
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config SUN4I_A10_CCU
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bool "Support for the Allwinner A10/A20 CCU"
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select SUNXI_CCU_DIV
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select SUNXI_CCU_MULT
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select SUNXI_CCU_NK
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select SUNXI_CCU_NKM
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select SUNXI_CCU_NM
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select SUNXI_CCU_MP
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select SUNXI_CCU_PHASE
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default MACH_SUN4I
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default MACH_SUN7I
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depends on MACH_SUN4I || MACH_SUN7I || COMPILE_TEST
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config SUN5I_CCU
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bool "Support for the Allwinner sun5i family CCM"
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default MACH_SUN5I
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@ -19,6 +19,7 @@ lib-$(CONFIG_SUNXI_CCU) += ccu_mp.o
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# SoC support
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obj-$(CONFIG_SUN50I_A64_CCU) += ccu-sun50i-a64.o
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obj-$(CONFIG_SUN4I_A10_CCU) += ccu-sun4i-a10.o
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obj-$(CONFIG_SUN5I_CCU) += ccu-sun5i.o
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obj-$(CONFIG_SUN6I_A31_CCU) += ccu-sun6i-a31.o
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obj-$(CONFIG_SUN8I_A23_CCU) += ccu-sun8i-a23.o
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1456
drivers/clk/sunxi-ng/ccu-sun4i-a10.c
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1456
drivers/clk/sunxi-ng/ccu-sun4i-a10.c
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File diff suppressed because it is too large
Load diff
61
drivers/clk/sunxi-ng/ccu-sun4i-a10.h
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61
drivers/clk/sunxi-ng/ccu-sun4i-a10.h
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@ -0,0 +1,61 @@
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/*
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* Copyright 2017 Priit Laes
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*
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* Priit Laes <plaes@plaes.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _CCU_SUN4I_A10_H_
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#define _CCU_SUN4I_A10_H_
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#include <dt-bindings/clock/sun4i-a10-ccu.h>
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#include <dt-bindings/clock/sun7i-a20-ccu.h>
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#include <dt-bindings/reset/sun4i-a10-ccu.h>
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/* The HOSC is exported */
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#define CLK_PLL_CORE 2
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#define CLK_PLL_AUDIO_BASE 3
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#define CLK_PLL_AUDIO 4
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#define CLK_PLL_AUDIO_2X 5
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#define CLK_PLL_AUDIO_4X 6
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#define CLK_PLL_AUDIO_8X 7
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#define CLK_PLL_VIDEO0 8
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#define CLK_PLL_VIDEO0_2X 9
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#define CLK_PLL_VE 10
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#define CLK_PLL_DDR_BASE 11
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#define CLK_PLL_DDR 12
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#define CLK_PLL_DDR_OTHER 13
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#define CLK_PLL_PERIPH_BASE 14
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#define CLK_PLL_PERIPH 15
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#define CLK_PLL_PERIPH_SATA 16
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#define CLK_PLL_VIDEO1 17
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#define CLK_PLL_VIDEO1_2X 18
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#define CLK_PLL_GPU 19
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/* The CPU clock is exported */
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#define CLK_AXI 21
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#define CLK_AXI_DRAM 22
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#define CLK_AHB 23
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#define CLK_APB0 24
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#define CLK_APB1 25
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/* AHB gates are exported (23..68) */
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/* APB0 gates are exported (69..78) */
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/* APB1 gates are exported (79..95) */
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/* IP module clocks are exported (96..128) */
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/* DRAM gates are exported (129..142)*/
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/* Media (display engine clocks & etc) are exported (143..169) */
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#define CLK_NUMBER_SUN4I (CLK_MBUS + 1)
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#define CLK_NUMBER_SUN7I (CLK_OUT_B + 1)
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#endif /* _CCU_SUN4I_A10_H_ */
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