mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-30 11:41:38 -04:00
Merge branch 'irqchip/stacked-omap' into irqchip/core
This commit is contained in:
Jason Cooper
commit
07c523f149
30 changed files with 376 additions and 278 deletions
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@ -11,11 +11,12 @@
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*/
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/irqdomain.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/slab.h>
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#include <linux/irqchip/arm-gic.h>
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#include <linux/irqchip/irq-crossbar.h>
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#include "irqchip.h"
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#define IRQ_FREE -1
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#define IRQ_RESERVED -2
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@ -24,6 +25,7 @@
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/**
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* struct crossbar_device - crossbar device description
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* @lock: spinlock serializing access to @irq_map
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* @int_max: maximum number of supported interrupts
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* @safe_map: safe default value to initialize the crossbar
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* @max_crossbar_sources: Maximum number of crossbar sources
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@ -33,6 +35,7 @@
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* @write: register write function pointer
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*/
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struct crossbar_device {
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raw_spinlock_t lock;
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uint int_max;
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uint safe_map;
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uint max_crossbar_sources;
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@ -44,72 +47,101 @@ struct crossbar_device {
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static struct crossbar_device *cb;
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static inline void crossbar_writel(int irq_no, int cb_no)
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static void crossbar_writel(int irq_no, int cb_no)
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{
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writel(cb_no, cb->crossbar_base + cb->register_offsets[irq_no]);
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}
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static inline void crossbar_writew(int irq_no, int cb_no)
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static void crossbar_writew(int irq_no, int cb_no)
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{
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writew(cb_no, cb->crossbar_base + cb->register_offsets[irq_no]);
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}
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static inline void crossbar_writeb(int irq_no, int cb_no)
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static void crossbar_writeb(int irq_no, int cb_no)
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{
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writeb(cb_no, cb->crossbar_base + cb->register_offsets[irq_no]);
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}
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static inline int get_prev_map_irq(int cb_no)
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{
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int i;
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for (i = cb->int_max - 1; i >= 0; i--)
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if (cb->irq_map[i] == cb_no)
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return i;
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return -ENODEV;
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}
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static inline int allocate_free_irq(int cb_no)
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static struct irq_chip crossbar_chip = {
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.name = "CBAR",
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.irq_eoi = irq_chip_eoi_parent,
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.irq_mask = irq_chip_mask_parent,
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.irq_unmask = irq_chip_unmask_parent,
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.irq_retrigger = irq_chip_retrigger_hierarchy,
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.irq_set_wake = irq_chip_set_wake_parent,
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#ifdef CONFIG_SMP
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.irq_set_affinity = irq_chip_set_affinity_parent,
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#endif
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};
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static int allocate_gic_irq(struct irq_domain *domain, unsigned virq,
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irq_hw_number_t hwirq)
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{
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struct of_phandle_args args;
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int i;
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int err;
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raw_spin_lock(&cb->lock);
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for (i = cb->int_max - 1; i >= 0; i--) {
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if (cb->irq_map[i] == IRQ_FREE) {
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cb->irq_map[i] = cb_no;
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return i;
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cb->irq_map[i] = hwirq;
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break;
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}
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}
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raw_spin_unlock(&cb->lock);
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return -ENODEV;
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if (i < 0)
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return -ENODEV;
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args.np = domain->parent->of_node;
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args.args_count = 3;
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args.args[0] = 0; /* SPI */
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args.args[1] = i;
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args.args[2] = IRQ_TYPE_LEVEL_HIGH;
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err = irq_domain_alloc_irqs_parent(domain, virq, 1, &args);
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if (err)
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cb->irq_map[i] = IRQ_FREE;
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else
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cb->write(i, hwirq);
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return err;
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}
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static inline bool needs_crossbar_write(irq_hw_number_t hw)
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static int crossbar_domain_alloc(struct irq_domain *d, unsigned int virq,
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unsigned int nr_irqs, void *data)
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{
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int cb_no;
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struct of_phandle_args *args = data;
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irq_hw_number_t hwirq;
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int i;
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if (hw > GIC_IRQ_START) {
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cb_no = cb->irq_map[hw - GIC_IRQ_START];
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if (cb_no != IRQ_RESERVED && cb_no != IRQ_SKIP)
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return true;
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if (args->args_count != 3)
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return -EINVAL; /* Not GIC compliant */
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if (args->args[0] != 0)
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return -EINVAL; /* No PPI should point to this domain */
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hwirq = args->args[1];
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if ((hwirq + nr_irqs) > cb->max_crossbar_sources)
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return -EINVAL; /* Can't deal with this */
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for (i = 0; i < nr_irqs; i++) {
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int err = allocate_gic_irq(d, virq + i, hwirq + i);
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if (err)
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return err;
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irq_domain_set_hwirq_and_chip(d, virq + i, hwirq + i,
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&crossbar_chip, NULL);
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}
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return false;
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}
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static int crossbar_domain_map(struct irq_domain *d, unsigned int irq,
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irq_hw_number_t hw)
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{
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if (needs_crossbar_write(hw))
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cb->write(hw - GIC_IRQ_START, cb->irq_map[hw - GIC_IRQ_START]);
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return 0;
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}
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/**
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* crossbar_domain_unmap - unmap a crossbar<->irq connection
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* @d: domain of irq to unmap
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* @irq: virq number
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* crossbar_domain_free - unmap/free a crossbar<->irq connection
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* @domain: domain of irq to unmap
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* @virq: virq number
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* @nr_irqs: number of irqs to free
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*
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* We do not maintain a use count of total number of map/unmap
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* calls for a particular irq to find out if a irq can be really
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@ -117,14 +149,20 @@ static int crossbar_domain_map(struct irq_domain *d, unsigned int irq,
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* after which irq is anyways unusable. So an explicit map has to be called
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* after that.
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*/
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static void crossbar_domain_unmap(struct irq_domain *d, unsigned int irq)
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static void crossbar_domain_free(struct irq_domain *domain, unsigned int virq,
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unsigned int nr_irqs)
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{
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irq_hw_number_t hw = irq_get_irq_data(irq)->hwirq;
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int i;
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if (needs_crossbar_write(hw)) {
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cb->irq_map[hw - GIC_IRQ_START] = IRQ_FREE;
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cb->write(hw - GIC_IRQ_START, cb->safe_map);
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raw_spin_lock(&cb->lock);
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for (i = 0; i < nr_irqs; i++) {
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struct irq_data *d = irq_domain_get_irq_data(domain, virq + i);
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irq_domain_reset_irq_data(d);
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cb->irq_map[d->hwirq] = IRQ_FREE;
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cb->write(d->hwirq, cb->safe_map);
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}
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raw_spin_unlock(&cb->lock);
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}
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static int crossbar_domain_xlate(struct irq_domain *d,
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@ -133,44 +171,22 @@ static int crossbar_domain_xlate(struct irq_domain *d,
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unsigned long *out_hwirq,
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unsigned int *out_type)
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{
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int ret;
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int req_num = intspec[1];
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int direct_map_num;
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if (d->of_node != controller)
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return -EINVAL; /* Shouldn't happen, really... */
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if (intsize != 3)
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return -EINVAL; /* Not GIC compliant */
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if (intspec[0] != 0)
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return -EINVAL; /* No PPI should point to this domain */
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if (req_num >= cb->max_crossbar_sources) {
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direct_map_num = req_num - cb->max_crossbar_sources;
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if (direct_map_num < cb->int_max) {
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ret = cb->irq_map[direct_map_num];
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if (ret == IRQ_RESERVED || ret == IRQ_SKIP) {
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/* We use the interrupt num as h/w irq num */
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ret = direct_map_num;
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goto found;
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}
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}
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pr_err("%s: requested crossbar number %d > max %d\n",
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__func__, req_num, cb->max_crossbar_sources);
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return -EINVAL;
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}
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ret = get_prev_map_irq(req_num);
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if (ret >= 0)
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goto found;
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ret = allocate_free_irq(req_num);
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if (ret < 0)
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return ret;
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found:
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*out_hwirq = ret + GIC_IRQ_START;
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*out_hwirq = intspec[1];
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*out_type = intspec[2];
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return 0;
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}
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static const struct irq_domain_ops routable_irq_domain_ops = {
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.map = crossbar_domain_map,
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.unmap = crossbar_domain_unmap,
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.xlate = crossbar_domain_xlate
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static const struct irq_domain_ops crossbar_domain_ops = {
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.alloc = crossbar_domain_alloc,
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.free = crossbar_domain_free,
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.xlate = crossbar_domain_xlate,
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};
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static int __init crossbar_of_init(struct device_node *node)
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@ -293,7 +309,8 @@ static int __init crossbar_of_init(struct device_node *node)
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cb->write(i, cb->safe_map);
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}
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register_routable_domain_ops(&routable_irq_domain_ops);
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raw_spin_lock_init(&cb->lock);
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return 0;
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err_reg_offset:
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@ -309,18 +326,37 @@ err_cb:
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return ret;
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}
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static const struct of_device_id crossbar_match[] __initconst = {
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{ .compatible = "ti,irq-crossbar" },
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{}
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};
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int __init irqcrossbar_init(void)
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static int __init irqcrossbar_init(struct device_node *node,
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struct device_node *parent)
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{
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struct device_node *np;
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np = of_find_matching_node(NULL, crossbar_match);
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if (!np)
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return -ENODEV;
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struct irq_domain *parent_domain, *domain;
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int err;
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if (!parent) {
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pr_err("%s: no parent, giving up\n", node->full_name);
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return -ENODEV;
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}
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parent_domain = irq_find_host(parent);
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if (!parent_domain) {
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pr_err("%s: unable to obtain parent domain\n", node->full_name);
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return -ENXIO;
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}
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err = crossbar_of_init(node);
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if (err)
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return err;
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domain = irq_domain_add_hierarchy(parent_domain, 0,
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cb->max_crossbar_sources,
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node, &crossbar_domain_ops,
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NULL);
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if (!domain) {
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pr_err("%s: failed to allocated domain\n", node->full_name);
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return -ENOMEM;
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}
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crossbar_of_init(np);
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return 0;
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}
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IRQCHIP_DECLARE(ti_irqcrossbar, "ti,irq-crossbar", irqcrossbar_init);
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@ -798,15 +798,12 @@ static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq,
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irq_domain_set_info(d, irq, hw, &gic_chip, d->host_data,
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handle_fasteoi_irq, NULL, NULL);
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set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
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gic_routable_irq_domain_ops->map(d, irq, hw);
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}
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return 0;
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}
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static void gic_irq_domain_unmap(struct irq_domain *d, unsigned int irq)
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{
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gic_routable_irq_domain_ops->unmap(d, irq);
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}
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static int gic_irq_domain_xlate(struct irq_domain *d,
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@ -825,16 +822,8 @@ static int gic_irq_domain_xlate(struct irq_domain *d,
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*out_hwirq = intspec[1] + 16;
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/* For SPIs, we need to add 16 more to get the GIC irq ID number */
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if (!intspec[0]) {
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ret = gic_routable_irq_domain_ops->xlate(d, controller,
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intspec,
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intsize,
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out_hwirq,
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out_type);
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if (IS_ERR_VALUE(ret))
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return ret;
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}
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if (!intspec[0])
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*out_hwirq += 16;
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*out_type = intspec[2] & IRQ_TYPE_SENSE_MASK;
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@ -891,37 +880,6 @@ static const struct irq_domain_ops gic_irq_domain_ops = {
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.xlate = gic_irq_domain_xlate,
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};
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/* Default functions for routable irq domain */
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static int gic_routable_irq_domain_map(struct irq_domain *d, unsigned int irq,
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irq_hw_number_t hw)
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{
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return 0;
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}
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static void gic_routable_irq_domain_unmap(struct irq_domain *d,
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unsigned int irq)
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{
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}
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static int gic_routable_irq_domain_xlate(struct irq_domain *d,
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struct device_node *controller,
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const u32 *intspec, unsigned int intsize,
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unsigned long *out_hwirq,
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unsigned int *out_type)
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{
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*out_hwirq += 16;
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return 0;
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}
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static const struct irq_domain_ops gic_default_routable_irq_domain_ops = {
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.map = gic_routable_irq_domain_map,
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.unmap = gic_routable_irq_domain_unmap,
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.xlate = gic_routable_irq_domain_xlate,
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};
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const struct irq_domain_ops *gic_routable_irq_domain_ops =
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&gic_default_routable_irq_domain_ops;
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void __init gic_init_bases(unsigned int gic_nr, int irq_start,
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void __iomem *dist_base, void __iomem *cpu_base,
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u32 percpu_offset, struct device_node *node)
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@ -929,7 +887,6 @@ void __init gic_init_bases(unsigned int gic_nr, int irq_start,
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irq_hw_number_t hwirq_base;
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struct gic_chip_data *gic;
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int gic_irqs, irq_base, i;
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int nr_routable_irqs;
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BUG_ON(gic_nr >= MAX_GIC_NR);
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@ -985,15 +942,9 @@ void __init gic_init_bases(unsigned int gic_nr, int irq_start,
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gic->gic_irqs = gic_irqs;
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if (node) { /* DT case */
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const struct irq_domain_ops *ops = &gic_irq_domain_hierarchy_ops;
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if (!of_property_read_u32(node, "arm,routable-irqs",
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&nr_routable_irqs)) {
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ops = &gic_irq_domain_ops;
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gic_irqs = nr_routable_irqs;
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}
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gic->domain = irq_domain_add_linear(node, gic_irqs, ops, gic);
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gic->domain = irq_domain_add_linear(node, gic_irqs,
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&gic_irq_domain_hierarchy_ops,
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gic);
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} else { /* Non-DT case */
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/*
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* For primary GICs, skip over SGIs.
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