From 07d15a5e0ccbe749d61cdfd104be7b5f241c8de4 Mon Sep 17 00:00:00 2001 From: Jigar Agrawal Date: Wed, 2 Sep 2020 17:01:49 -0700 Subject: [PATCH] ARM: dts: msm: Add camera device tree for Waipio Add device tree changes for memory, regulators, clock and interrupt information for CCI, CSIPHY, CPAS, LX7, CDM, TPG, VFE, CSID, IPE, BPS, JPEG, VFE-LITE and CSID-LITE nodes. Update SMMU Node. Add new SFE Nodes. Updated cdp and mtp dtsi files. Update to move camera pinctrl to sensor cdp and mtp files. CRs-Fixed: 2784041 Change-Id: I015a17dcea5ba82e8048138ead93281ec69ef5f5 --- waipio-camera-sensor-cdp.dtsi | 597 ++++++++ waipio-camera-sensor-mtp.dtsi | 597 ++++++++ waipio-camera.dtsi | 2719 +++++++++++++++++++++++++++++++++ 3 files changed, 3913 insertions(+) create mode 100644 waipio-camera-sensor-cdp.dtsi create mode 100644 waipio-camera-sensor-mtp.dtsi create mode 100644 waipio-camera.dtsi diff --git a/waipio-camera-sensor-cdp.dtsi b/waipio-camera-sensor-cdp.dtsi new file mode 100644 index 000000000000..0f63ffd41bb8 --- /dev/null +++ b/waipio-camera-sensor-cdp.dtsi @@ -0,0 +1,597 @@ +#include + +&soc { + led_flash_triple_rear: qcom,camera-flash@1 { + cell-index = <1>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8350c_flash0 &pm8350c_flash1>; + torch-source = <&pm8350c_torch0 &pm8350c_torch1>; + switch-source = <&pm8350c_switch2>; + status = "ok"; + }; + + led_flash_triple_rear_aux2: qcom,camera-flash@2 { + cell-index = <2>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8350c_flash0 &pm8350c_flash1>; + torch-source = <&pm8350c_torch0 &pm8350c_torch1>; + switch-source = <&pm8350c_switch2>; + status = "ok"; + }; + + led_flash_triple_rear_aux: qcom,camera-flash@3 { + cell-index = <3>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8350c_flash0 &pm8350c_flash1>; + torch-source = <&pm8350c_torch0 &pm8350c_torch1>; + switch-source = <&pm8350c_switch2>; + status = "ok"; + }; + + qcom,cam-res-mgr { + compatible = "qcom,cam-res-mgr"; + status = "ok"; + }; +}; + +&cam_cci0 { + actuator_triple_uw: qcom,actuator0 { + cell-index = <0>; + compatible = "qcom,actuator"; + cci-master = <0>; + cam_vaf-supply = <&pm8008i_l7>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2704000>; + rgltr-max-voltage = <3000000>; + rgltr-load-current = <103000>; + }; + + actuator_triple_tele: qcom,actuator1 { + cell-index = <1>; + compatible = "qcom,actuator"; + cci-master = <1>; + cam_vaf-supply = <&pm8008i_l7>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2704000>; + rgltr-max-voltage = <3000000>; + rgltr-load-current = <103000>; + }; + + eeprom_tof1: qcom,eeprom0 { + cell-index = <0>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8008j_l3>; + cam_vdig-supply = <&pm8350_s12>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&pm8008j_l6>; + cam_v_custom1-supply = <&pm8008j_l7>; + regulator-names = "cam_vio", "cam_vdig", + "cam_clk", "cam_vana", "cam_v_custom1"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1256000 0 2800000 3000000>; + rgltr-max-voltage = <1800000 1256000 0 2800000 3304000>; + rgltr-load-current = <5000 680000 0 35000 15000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 100 0>, + <&tlmm 25 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + cci-master = <0>; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + eeprom_triple_uw: qcom,eeprom1 { + cell-index = <1>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8008j_l3>; + cam_vana-supply = <&pm8008i_l6>; + cam_vdig-supply = <&pm8008i_l2>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vaf-supply = <&pm8008i_l7>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2704000 952000 0 2704000>; + rgltr-max-voltage = <1800000 2896000 1144000 0 3000000>; + rgltr-load-current = <3000 52000 257000 0 103000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rst1>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rst1>; + gpios = <&tlmm 101 0>, + <&tlmm 24 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + cci-master = <0>; + clocks = <&clock_camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + eeprom_triple_tele: qcom,eeprom3 { + cell-index = <3>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8008j_l3>; + cam_vana-supply = <&pm8008i_l4>; + cam_vdig-supply = <&pm8008i_l2>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vaf-supply = <&pm8008i_l7>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2704000 952000 0 2704000>; + rgltr-max-voltage = <1800000 2896000 1144000 0 3000000>; + rgltr-load-current = <10000 52000 140000 0 103000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_rst3>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_suspend_rst3>; + gpios = <&tlmm 103 0>, + <&tlmm 120 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3"; + cci-master = <1>; + clocks = <&clock_camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor0 { + cell-index = <7>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <0>; + eeprom-src = <&eeprom_tof1>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + cam_vio-supply = <&pm8008j_l3>; + cam_vdig-supply = <&pm8350_s12>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&pm8008j_l6>; + cam_v_custom1-supply = <&pm8008j_l7>; + regulator-names = "cam_vio", "cam_vdig", + "cam_clk", "cam_vana", "cam_v_custom1"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1256000 0 2800000 3000000>; + rgltr-max-voltage = <1800000 1256000 0 2800000 3304000>; + rgltr-load-current = <5000 680000 0 35000 15000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 100 0>, + <&tlmm 25 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + cci-master = <0>; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor1 { + cell-index = <6>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <1>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_triple_uw>; + actuator-src = <&actuator_triple_uw>; + led-flash-src = <&led_flash_triple_rear>; + cam_vio-supply = <&pm8008j_l3>; + cam_vana-supply = <&pm8008i_l6>; + cam_vdig-supply = <&pm8008i_l2>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_bob-supply = <&pm8350c_bob>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_bob"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2704000 952000 0 3008000>; + rgltr-max-voltage = <1800000 2896000 1144000 0 3960000>; + rgltr-load-current = <3000 52000 257000 0 7100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rst1>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rst1>; + gpios = <&tlmm 101 0>, + <&tlmm 24 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + cci-master = <0>; + clocks = <&clock_camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor3 { + cell-index = <5>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <3>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_triple_tele>; + actuator-src = <&actuator_triple_tele>; + led-flash-src = <&led_flash_triple_rear_aux>; + cam_vio-supply = <&pm8008j_l3>; + cam_vana-supply = <&pm8008i_l4>; + cam_vdig-supply = <&pm8008i_l2>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_bob-supply = <&pm8350c_bob>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_bob"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2704000 952000 0 3008000>; + rgltr-max-voltage = <1800000 2896000 1144000 0 3960000>; + rgltr-load-current = <10000 52000 140000 0 7100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_rst3>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_suspend_rst3>; + gpios = <&tlmm 103 0>, + <&tlmm 120 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3"; + cci-master = <1>; + clocks = <&clock_camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; +}; + +&cam_cci1 { + actuator_triple_wide: qcom,actuator2 { + cell-index = <0>; + compatible = "qcom,actuator"; + cci-master = <0>; + cam_vaf-supply = <&pm8008i_l7>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2704000>; + rgltr-max-voltage = <3000000>; + rgltr-load-current = <103000>; + }; + + eeprom_triple_wide: qcom,eeprom2 { + cell-index = <2>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8008j_l3>; + cam_vana-supply = <&pm8008i_l3>; + cam_vana1-supply = <&pm8008j_l4>; + cam_vdig-supply = <&pm8008j_l1>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vaf-supply = <&pm8008i_l7>; + regulator-names = "cam_vio", "cam_vana", "cam_vana1", + "cam_vdig", "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2704000 1704000 1000000 0 2704000>; + rgltr-max-voltage = <1800000 3000000 1896000 1200000 0 3000000>; + rgltr-load-current = <4000 96000 88000 872000 0 103000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2>; + gpios = <&tlmm 102 0>, + <&tlmm 117 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + cci-master = <0>; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + eeprom_tof2: qcom,eeprom4 { + cell-index = <4>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8008j_l3>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + regulator-names = "cam_vio", "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 0>; + rgltr-max-voltage = <1800000 0>; + rgltr-load-current = <185000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk4_active + &cam_sensor_active_rst4>; + pinctrl-1 = <&cam_sensor_mclk4_suspend + &cam_sensor_suspend_rst4>; + gpios = <&tlmm 104 0>, + <&tlmm 119 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK4", + "CAM_RESET4"; + cci-master = <0>; + clocks = <&clock_camcc CAM_CC_MCLK4_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + eeprom_front: qcom,eeprom5 { + cell-index = <5>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8008j_l3>; + cam_vana-supply = <&pm8008i_l6>; + cam_vdig-supply = <&pm8008i_l2>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2704000 952000 0>; + rgltr-max-voltage = <1800000 2896000 1144000 0>; + rgltr-load-current = <3000 52000 257000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk5_active + &cam_sensor_active_rst5>; + pinctrl-1 = <&cam_sensor_mclk5_suspend + &cam_sensor_suspend_rst5>; + gpios = <&tlmm 105 0>, + <&tlmm 118 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK5", + "CAM_RESET5"; + cci-master = <0>; + clocks = <&clock_camcc CAM_CC_MCLK5_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + eeprom_aon: qcom,eeprom6 { + cell-index = <6>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8008j_l3>; + cam_vdig-supply = <&pm8008j_l5>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&pm8008j_l2>; + regulator-names = "cam_vio", "cam_vdig","cam_clk", "cam_vana"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2704000 0 952000>; + rgltr-max-voltage = <1800000 2896000 0 1144000>; + rgltr-load-current = <1120 14700 0 23800>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk6_active + &cam_sensor_active_rst6>; + pinctrl-1 = <&cam_sensor_mclk6_suspend + &cam_sensor_suspend_rst6>; + gpios = <&tlmm 106 0>, + <&tlmm 108 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK6", + "CAM_RESET6"; + cci-master = <1>; + clocks = <&clock_camcc CAM_CC_MCLK6_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor2 { + cell-index = <4>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <2>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + actuator-src = <&actuator_triple_wide>; + eeprom-src = <&eeprom_triple_wide>; + led-flash-src = <&led_flash_triple_rear_aux2>; + cam_vio-supply = <&pm8008j_l3>; + cam_vana-supply = <&pm8008i_l3>; + cam_vana1-supply = <&pm8008j_l4>; + cam_vdig-supply = <&pm8008j_l1>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_bob-supply = <&pm8350c_bob>; + regulator-names = "cam_vio", "cam_vana", "cam_vana1", + "cam_vdig", "cam_clk", "cam_bob"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2704000 1704000 1000000 0 3008000>; + rgltr-max-voltage = <1800000 3000000 1896000 1200000 0 3960000>; + rgltr-load-current = <4000 96000 88000 872000 0 7100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2>; + gpios = <&tlmm 102 0>, + <&tlmm 117 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + cci-master = <0>; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor4 { + cell-index = <3>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <4>; + eeprom-src = <&eeprom_tof2>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + cam_vio-supply = <&pm8008j_l3>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + regulator-names = "cam_vio", "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 0>; + rgltr-max-voltage = <1800000 0>; + rgltr-load-current = <185000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk4_active + &cam_sensor_active_rst4>; + pinctrl-1 = <&cam_sensor_mclk4_suspend + &cam_sensor_suspend_rst4>; + gpios = <&tlmm 104 0>, + <&tlmm 119 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK4", + "CAM_RESET4"; + cci-master = <0>; + clocks = <&clock_camcc CAM_CC_MCLK4_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor5 { + cell-index = <2>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <5>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + eeprom-src = <&eeprom_front>; + cam_vio-supply = <&pm8008j_l3>; + cam_vana-supply = <&pm8008i_l6>; + cam_vdig-supply = <&pm8008i_l2>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_bob-supply = <&pm8350c_bob>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_bob"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2704000 952000 0 3008000>; + rgltr-max-voltage = <1800000 2896000 1144000 0 3960000>; + rgltr-load-current = <3000 52000 257000 0 7100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk5_active + &cam_sensor_active_rst5>; + pinctrl-1 = <&cam_sensor_mclk5_suspend + &cam_sensor_suspend_rst5>; + gpios = <&tlmm 105 0>, + <&tlmm 118 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK5", + "CAM_RESET5"; + cci-master = <0>; + clocks = <&clock_camcc CAM_CC_MCLK5_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor6 { + cell-index = <1>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <4>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + eeprom-src = <&eeprom_aon>; + cam_vio-supply = <&pm8008j_l3>; + cam_vdig-supply = <&pm8008j_l5>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&pm8008j_l2>; + cam_bob-supply = <&pm8350c_bob>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", "cam_vana", + "cam_bob"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2704000 0 952000 3008000>; + rgltr-max-voltage = <1800000 2896000 0 1144000 3960000>; + rgltr-load-current = <1120 14700 0 23800 7100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk6_active + &cam_sensor_active_rst6>; + pinctrl-1 = <&cam_sensor_mclk6_suspend + &cam_sensor_suspend_rst6>; + gpios = <&tlmm 106 0>, + <&tlmm 108 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK6", + "CAM_RESET6"; + cci-master = <1>; + clocks = <&clock_camcc CAM_CC_MCLK6_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; +}; diff --git a/waipio-camera-sensor-mtp.dtsi b/waipio-camera-sensor-mtp.dtsi new file mode 100644 index 000000000000..0f63ffd41bb8 --- /dev/null +++ b/waipio-camera-sensor-mtp.dtsi @@ -0,0 +1,597 @@ +#include + +&soc { + led_flash_triple_rear: qcom,camera-flash@1 { + cell-index = <1>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8350c_flash0 &pm8350c_flash1>; + torch-source = <&pm8350c_torch0 &pm8350c_torch1>; + switch-source = <&pm8350c_switch2>; + status = "ok"; + }; + + led_flash_triple_rear_aux2: qcom,camera-flash@2 { + cell-index = <2>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8350c_flash0 &pm8350c_flash1>; + torch-source = <&pm8350c_torch0 &pm8350c_torch1>; + switch-source = <&pm8350c_switch2>; + status = "ok"; + }; + + led_flash_triple_rear_aux: qcom,camera-flash@3 { + cell-index = <3>; + compatible = "qcom,camera-flash"; + flash-source = <&pm8350c_flash0 &pm8350c_flash1>; + torch-source = <&pm8350c_torch0 &pm8350c_torch1>; + switch-source = <&pm8350c_switch2>; + status = "ok"; + }; + + qcom,cam-res-mgr { + compatible = "qcom,cam-res-mgr"; + status = "ok"; + }; +}; + +&cam_cci0 { + actuator_triple_uw: qcom,actuator0 { + cell-index = <0>; + compatible = "qcom,actuator"; + cci-master = <0>; + cam_vaf-supply = <&pm8008i_l7>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2704000>; + rgltr-max-voltage = <3000000>; + rgltr-load-current = <103000>; + }; + + actuator_triple_tele: qcom,actuator1 { + cell-index = <1>; + compatible = "qcom,actuator"; + cci-master = <1>; + cam_vaf-supply = <&pm8008i_l7>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2704000>; + rgltr-max-voltage = <3000000>; + rgltr-load-current = <103000>; + }; + + eeprom_tof1: qcom,eeprom0 { + cell-index = <0>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8008j_l3>; + cam_vdig-supply = <&pm8350_s12>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&pm8008j_l6>; + cam_v_custom1-supply = <&pm8008j_l7>; + regulator-names = "cam_vio", "cam_vdig", + "cam_clk", "cam_vana", "cam_v_custom1"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1256000 0 2800000 3000000>; + rgltr-max-voltage = <1800000 1256000 0 2800000 3304000>; + rgltr-load-current = <5000 680000 0 35000 15000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 100 0>, + <&tlmm 25 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + cci-master = <0>; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + eeprom_triple_uw: qcom,eeprom1 { + cell-index = <1>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8008j_l3>; + cam_vana-supply = <&pm8008i_l6>; + cam_vdig-supply = <&pm8008i_l2>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vaf-supply = <&pm8008i_l7>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2704000 952000 0 2704000>; + rgltr-max-voltage = <1800000 2896000 1144000 0 3000000>; + rgltr-load-current = <3000 52000 257000 0 103000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rst1>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rst1>; + gpios = <&tlmm 101 0>, + <&tlmm 24 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + cci-master = <0>; + clocks = <&clock_camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + eeprom_triple_tele: qcom,eeprom3 { + cell-index = <3>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8008j_l3>; + cam_vana-supply = <&pm8008i_l4>; + cam_vdig-supply = <&pm8008i_l2>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vaf-supply = <&pm8008i_l7>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2704000 952000 0 2704000>; + rgltr-max-voltage = <1800000 2896000 1144000 0 3000000>; + rgltr-load-current = <10000 52000 140000 0 103000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_rst3>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_suspend_rst3>; + gpios = <&tlmm 103 0>, + <&tlmm 120 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3"; + cci-master = <1>; + clocks = <&clock_camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor0 { + cell-index = <7>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <0>; + eeprom-src = <&eeprom_tof1>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + cam_vio-supply = <&pm8008j_l3>; + cam_vdig-supply = <&pm8350_s12>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&pm8008j_l6>; + cam_v_custom1-supply = <&pm8008j_l7>; + regulator-names = "cam_vio", "cam_vdig", + "cam_clk", "cam_vana", "cam_v_custom1"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 1256000 0 2800000 3000000>; + rgltr-max-voltage = <1800000 1256000 0 2800000 3304000>; + rgltr-load-current = <5000 680000 0 35000 15000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk0_active + &cam_sensor_active_rst0>; + pinctrl-1 = <&cam_sensor_mclk0_suspend + &cam_sensor_suspend_rst0>; + gpios = <&tlmm 100 0>, + <&tlmm 25 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK0", + "CAM_RESET0"; + cci-master = <0>; + clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor1 { + cell-index = <6>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <1>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_triple_uw>; + actuator-src = <&actuator_triple_uw>; + led-flash-src = <&led_flash_triple_rear>; + cam_vio-supply = <&pm8008j_l3>; + cam_vana-supply = <&pm8008i_l6>; + cam_vdig-supply = <&pm8008i_l2>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_bob-supply = <&pm8350c_bob>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_bob"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2704000 952000 0 3008000>; + rgltr-max-voltage = <1800000 2896000 1144000 0 3960000>; + rgltr-load-current = <3000 52000 257000 0 7100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk1_active + &cam_sensor_active_rst1>; + pinctrl-1 = <&cam_sensor_mclk1_suspend + &cam_sensor_suspend_rst1>; + gpios = <&tlmm 101 0>, + <&tlmm 24 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK1", + "CAM_RESET1"; + cci-master = <0>; + clocks = <&clock_camcc CAM_CC_MCLK1_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor3 { + cell-index = <5>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <3>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + eeprom-src = <&eeprom_triple_tele>; + actuator-src = <&actuator_triple_tele>; + led-flash-src = <&led_flash_triple_rear_aux>; + cam_vio-supply = <&pm8008j_l3>; + cam_vana-supply = <&pm8008i_l4>; + cam_vdig-supply = <&pm8008i_l2>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_bob-supply = <&pm8350c_bob>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_bob"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2704000 952000 0 3008000>; + rgltr-max-voltage = <1800000 2896000 1144000 0 3960000>; + rgltr-load-current = <10000 52000 140000 0 7100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk3_active + &cam_sensor_active_rst3>; + pinctrl-1 = <&cam_sensor_mclk3_suspend + &cam_sensor_suspend_rst3>; + gpios = <&tlmm 103 0>, + <&tlmm 120 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK3", + "CAM_RESET3"; + cci-master = <1>; + clocks = <&clock_camcc CAM_CC_MCLK3_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; +}; + +&cam_cci1 { + actuator_triple_wide: qcom,actuator2 { + cell-index = <0>; + compatible = "qcom,actuator"; + cci-master = <0>; + cam_vaf-supply = <&pm8008i_l7>; + regulator-names = "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <2704000>; + rgltr-max-voltage = <3000000>; + rgltr-load-current = <103000>; + }; + + eeprom_triple_wide: qcom,eeprom2 { + cell-index = <2>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8008j_l3>; + cam_vana-supply = <&pm8008i_l3>; + cam_vana1-supply = <&pm8008j_l4>; + cam_vdig-supply = <&pm8008j_l1>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vaf-supply = <&pm8008i_l7>; + regulator-names = "cam_vio", "cam_vana", "cam_vana1", + "cam_vdig", "cam_clk", "cam_vaf"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2704000 1704000 1000000 0 2704000>; + rgltr-max-voltage = <1800000 3000000 1896000 1200000 0 3000000>; + rgltr-load-current = <4000 96000 88000 872000 0 103000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2>; + gpios = <&tlmm 102 0>, + <&tlmm 117 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + cci-master = <0>; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + eeprom_tof2: qcom,eeprom4 { + cell-index = <4>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8008j_l3>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + regulator-names = "cam_vio", "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 0>; + rgltr-max-voltage = <1800000 0>; + rgltr-load-current = <185000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk4_active + &cam_sensor_active_rst4>; + pinctrl-1 = <&cam_sensor_mclk4_suspend + &cam_sensor_suspend_rst4>; + gpios = <&tlmm 104 0>, + <&tlmm 119 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK4", + "CAM_RESET4"; + cci-master = <0>; + clocks = <&clock_camcc CAM_CC_MCLK4_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + eeprom_front: qcom,eeprom5 { + cell-index = <5>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8008j_l3>; + cam_vana-supply = <&pm8008i_l6>; + cam_vdig-supply = <&pm8008i_l2>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2704000 952000 0>; + rgltr-max-voltage = <1800000 2896000 1144000 0>; + rgltr-load-current = <3000 52000 257000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk5_active + &cam_sensor_active_rst5>; + pinctrl-1 = <&cam_sensor_mclk5_suspend + &cam_sensor_suspend_rst5>; + gpios = <&tlmm 105 0>, + <&tlmm 118 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK5", + "CAM_RESET5"; + cci-master = <0>; + clocks = <&clock_camcc CAM_CC_MCLK5_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + eeprom_aon: qcom,eeprom6 { + cell-index = <6>; + compatible = "qcom,eeprom"; + cam_vio-supply = <&pm8008j_l3>; + cam_vdig-supply = <&pm8008j_l5>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&pm8008j_l2>; + regulator-names = "cam_vio", "cam_vdig","cam_clk", "cam_vana"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2704000 0 952000>; + rgltr-max-voltage = <1800000 2896000 0 1144000>; + rgltr-load-current = <1120 14700 0 23800>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk6_active + &cam_sensor_active_rst6>; + pinctrl-1 = <&cam_sensor_mclk6_suspend + &cam_sensor_suspend_rst6>; + gpios = <&tlmm 106 0>, + <&tlmm 108 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK6", + "CAM_RESET6"; + cci-master = <1>; + clocks = <&clock_camcc CAM_CC_MCLK6_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor2 { + cell-index = <4>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <2>; + sensor-position-roll = <90>; + sensor-position-pitch = <0>; + sensor-position-yaw = <180>; + actuator-src = <&actuator_triple_wide>; + eeprom-src = <&eeprom_triple_wide>; + led-flash-src = <&led_flash_triple_rear_aux2>; + cam_vio-supply = <&pm8008j_l3>; + cam_vana-supply = <&pm8008i_l3>; + cam_vana1-supply = <&pm8008j_l4>; + cam_vdig-supply = <&pm8008j_l1>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_bob-supply = <&pm8350c_bob>; + regulator-names = "cam_vio", "cam_vana", "cam_vana1", + "cam_vdig", "cam_clk", "cam_bob"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2704000 1704000 1000000 0 3008000>; + rgltr-max-voltage = <1800000 3000000 1896000 1200000 0 3960000>; + rgltr-load-current = <4000 96000 88000 872000 0 7100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk2_active + &cam_sensor_active_rst2>; + pinctrl-1 = <&cam_sensor_mclk2_suspend + &cam_sensor_suspend_rst2>; + gpios = <&tlmm 102 0>, + <&tlmm 117 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK2", + "CAM_RESET2"; + cci-master = <0>; + clocks = <&clock_camcc CAM_CC_MCLK2_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor4 { + cell-index = <3>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <4>; + eeprom-src = <&eeprom_tof2>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + cam_vio-supply = <&pm8008j_l3>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + regulator-names = "cam_vio", "cam_clk"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 0>; + rgltr-max-voltage = <1800000 0>; + rgltr-load-current = <185000 0>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk4_active + &cam_sensor_active_rst4>; + pinctrl-1 = <&cam_sensor_mclk4_suspend + &cam_sensor_suspend_rst4>; + gpios = <&tlmm 104 0>, + <&tlmm 119 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK4", + "CAM_RESET4"; + cci-master = <0>; + clocks = <&clock_camcc CAM_CC_MCLK4_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor5 { + cell-index = <2>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <5>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + eeprom-src = <&eeprom_front>; + cam_vio-supply = <&pm8008j_l3>; + cam_vana-supply = <&pm8008i_l6>; + cam_vdig-supply = <&pm8008i_l2>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_bob-supply = <&pm8350c_bob>; + regulator-names = "cam_vio", "cam_vana", "cam_vdig", + "cam_clk", "cam_bob"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2704000 952000 0 3008000>; + rgltr-max-voltage = <1800000 2896000 1144000 0 3960000>; + rgltr-load-current = <3000 52000 257000 0 7100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk5_active + &cam_sensor_active_rst5>; + pinctrl-1 = <&cam_sensor_mclk5_suspend + &cam_sensor_suspend_rst5>; + gpios = <&tlmm 105 0>, + <&tlmm 118 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK5", + "CAM_RESET5"; + cci-master = <0>; + clocks = <&clock_camcc CAM_CC_MCLK5_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; + + qcom,cam-sensor6 { + cell-index = <1>; + compatible = "qcom,cam-sensor"; + csiphy-sd-index = <4>; + sensor-position-roll = <270>; + sensor-position-pitch = <0>; + sensor-position-yaw = <0>; + eeprom-src = <&eeprom_aon>; + cam_vio-supply = <&pm8008j_l3>; + cam_vdig-supply = <&pm8008j_l5>; + cam_clk-supply = <&cam_cc_titan_top_gdsc>; + cam_vana-supply = <&pm8008j_l2>; + cam_bob-supply = <&pm8350c_bob>; + regulator-names = "cam_vio", "cam_vdig", "cam_clk", "cam_vana", + "cam_bob"; + rgltr-cntrl-support; + rgltr-min-voltage = <1800000 2704000 0 952000 3008000>; + rgltr-max-voltage = <1800000 2896000 0 1144000 3960000>; + rgltr-load-current = <1120 14700 0 23800 7100000>; + gpio-no-mux = <0>; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cam_sensor_mclk6_active + &cam_sensor_active_rst6>; + pinctrl-1 = <&cam_sensor_mclk6_suspend + &cam_sensor_suspend_rst6>; + gpios = <&tlmm 106 0>, + <&tlmm 108 0>; + gpio-reset = <1>; + gpio-req-tbl-num = <0 1>; + gpio-req-tbl-flags = <1 0>; + gpio-req-tbl-label = "CAMIF_MCLK6", + "CAM_RESET6"; + cci-master = <1>; + clocks = <&clock_camcc CAM_CC_MCLK6_CLK>; + clock-names = "cam_clk"; + clock-cntl-level = "nominal"; + clock-rates = <24000000>; + status = "ok"; + }; +}; diff --git a/waipio-camera.dtsi b/waipio-camera.dtsi new file mode 100644 index 000000000000..4d7025515784 --- /dev/null +++ b/waipio-camera.dtsi @@ -0,0 +1,2719 @@ +#include + +&tlmm { + cci0_active: cci0_active { + mux { + /* CLK, DATA */ + pins = "gpio110","gpio111"; // Only 2 + function = "cci_i2c"; + }; + + config { + pins = "gpio110","gpio111"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci0_suspend: cci0_suspend { + mux { + /* CLK, DATA */ + pins = "gpio110","gpio111"; + function = "cci_i2c"; + }; + + config { + pins = "gpio110","gpio111"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci1_active: cci1_active { + mux { + /* CLK, DATA */ + pins = "gpio112","gpio113"; + function = "cci_i2c"; + }; + + config { + pins = "gpio112","gpio113"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci1_suspend: cci1_suspend { + mux { + /* CLK, DATA */ + pins = "gpio112","gpio113"; + function = "cci_i2c"; + }; + + config { + pins = "gpio112","gpio113"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci2_active: cci2_active { + mux { + /* CLK, DATA */ + pins = "gpio114","gpio115"; + function = "cci_i2c"; + }; + + config { + pins = "gpio114","gpio115"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci2_suspend: cci2_suspend { + mux { + /* CLK, DATA */ + pins = "gpio114","gpio115"; + function = "cci_i2c"; + }; + + config { + pins = "gpio114","gpio115"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci3_active: cci3_active { + mux { + /* CLK, DATA */ + pins = "gpio208","gpio209"; + function = "cci_i2c"; + }; + + config { + pins = "gpio208","gpio209"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci3_suspend: cci3_suspend { + mux { + /* CLK, DATA */ + pins = "gpio208","gpio209"; + function = "cci_i2c"; + }; + + config { + pins = "gpio208","gpio209"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + + }; + + cam_sensor_mclk0_active: cam_sensor_mclk0_active { + /* MCLK0 */ + mux { + pins = "gpio100"; + function = "cam_mclk"; + }; + + config { + pins = "gpio100"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk0_suspend: cam_sensor_mclk0_suspend { + /* MCLK0 */ + mux { + pins = "gpio100"; + function = "cam_mclk"; + }; + + config { + pins = "gpio100"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk1_active: cam_sensor_mclk1_active { + /* MCLK1 */ + mux { + pins = "gpio101"; + function = "cam_mclk"; + }; + + config { + pins = "gpio101"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk1_suspend: cam_sensor_mclk1_suspend { + /* MCLK1 */ + mux { + pins = "gpio101"; + function = "cam_mclk"; + }; + + config { + pins = "gpio101"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk2_active: cam_sensor_mclk2_active { + /* MCLK2 */ + mux { + pins = "gpio102"; + function = "cam_mclk"; + }; + + config { + pins = "gpio102"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk2_suspend: cam_sensor_mclk2_suspend { + /* MCLK2 */ + mux { + pins = "gpio102"; + function = "cam_mclk"; + }; + + config { + pins = "gpio102"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk3_active: cam_sensor_mclk3_active { + /* MCLK3 */ + mux { + pins = "gpio103"; + function = "cam_mclk"; + }; + + config { + pins = "gpio103"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk3_suspend: cam_sensor_mclk3_suspend { + /* MCLK3 */ + mux { + pins = "gpio103"; + function = "cam_mclk"; + }; + + config { + pins = "gpio103"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk4_active: cam_sensor_mclk4_active { + /* MCLK4 */ + mux { + pins = "gpio104"; + function = "cam_mclk"; + }; + + config { + pins = "gpio104"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk4_suspend: cam_sensor_mclk4_suspend { + /* MCLK4 */ + mux { + pins = "gpio104"; + function = "cam_mclk"; + }; + + config { + pins = "gpio104"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk5_active: cam_sensor_mclk5_active { + /* MCLK5 */ + mux { + pins = "gpio105"; + function = "cam_mclk"; + }; + + config { + pins = "gpio105"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk5_suspend: cam_sensor_mclk5_suspend { + /* MCLK5 */ + mux { + pins = "gpio105"; + function = "cam_mclk"; + }; + + config { + pins = "gpio105"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk6_active: cam_sensor_mclk6_active { + /* MCLK6 */ + mux { + pins = "gpio106"; + function = "cam_mclk"; + }; + + config { + pins = "gpio106"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk6_suspend: cam_sensor_mclk6_suspend { + /* MCLK6 */ + mux { + pins = "gpio106"; + function = "cam_mclk"; + }; + + config { + pins = "gpio106"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_active_rst0: cam_sensor_active_rst0 { + /* RESET REAR */ + mux { + pins = "gpio25"; + function = "gpio"; + }; + + config { + pins = "gpio25"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_rst0: cam_sensor_suspend_rst0 { + /* RESET REAR */ + mux { + pins = "gpio25"; + function = "gpio"; + }; + + config { + pins = "gpio25"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_active_rst1: cam_sensor_active_rst1 { + /* RESET REARAUX */ + mux { + pins = "gpio24"; + function = "gpio"; + }; + + config { + pins = "gpio24"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_rst1: cam_sensor_suspend_rst1 { + /* RESET REARAUX */ + mux { + pins = "gpio24"; + function = "gpio"; + }; + + config { + pins = "gpio24"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_active_rst2: cam_sensor_active_rst2 { + /* RESET 2 */ + mux { + pins = "gpio117"; + function = "gpio"; + }; + + config { + pins = "gpio117"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_rst2: cam_sensor_suspend_rst2 { + /* RESET 2 */ + mux { + pins = "gpio117"; + function = "gpio"; + }; + + config { + pins = "gpio117"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_active_rst3: cam_sensor_active_rst3 { + /* RESET 3 */ + mux { + pins = "gpio120"; + function = "gpio"; + }; + + config { + pins = "gpio120"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_rst3: cam_sensor_suspend_rst3 { + /* RESET 3 */ + mux { + pins = "gpio120"; + function = "gpio"; + }; + + config { + pins = "gpio120"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_active_rst4: cam_sensor_active_rst4 { + /* RESET 4 */ + mux { + pins = "gpio119"; + function = "gpio"; + }; + + config { + pins = "gpio119"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_rst4: cam_sensor_suspend_rst4 { + /* RESET 4 */ + mux { + pins = "gpio119"; + function = "gpio"; + }; + + config { + pins = "gpio119"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_active_rst5: cam_sensor_active_rst5 { + /* RESET 5 */ + mux { + pins = "gpio118"; + function = "gpio"; + }; + + config { + pins = "gpio118"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_rst5: cam_sensor_suspend_rst5 { + /* RESET 5 */ + mux { + pins = "gpio118"; + function = "gpio"; + }; + + config { + pins = "gpio118"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_active_rst6: cam_sensor_active_rst6 { + /* RESET 6 */ + mux { + pins = "gpio108"; + function = "gpio"; + }; + + config { + pins = "gpio108"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_suspend_rst6: cam_sensor_suspend_rst6 { + /* RESET 6 */ + mux { + pins = "gpio108"; + function = "gpio"; + }; + + config { + pins = "gpio108"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; +}; + +&soc { + qcom,cam-req-mgr { + compatible = "qcom,cam-req-mgr"; + status = "ok"; + }; + + qcom,cam-sync { + compatible = "qcom,cam-sync"; + status = "ok"; + }; + + cam_csiphy0: qcom,csiphy0@ace4000 { + cell-index = <0>; + compatible = "qcom,csiphy-v2.1.0", "qcom,csiphy"; + reg = < 0x0ace4000 0x2000>; + reg-names = "csiphy"; + reg-cam-base = <0xe4000>; + interrupt-names = "CSIPHY0"; + interrupts = ; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + csi-vdd-1p2-supply = <&L6B>; + csi-vdd-0p9-supply = <&L5B>; + rgltr-cntrl-support; + rgltr-min-voltage = <0 1200000 880000>; + rgltr-max-voltage = <0 1248000 912000>; + rgltr-load-current = <0 54700 102000>; + clock-names = "cphy_rx_clk_src", + "csiphy0_clk", + "csi0phytimer_clk_src", + "csi0phytimer_clk"; + clocks = <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&clock_camcc CAM_CC_CSIPHY0_CLK>, + <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>, + <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK>; + src-clock-name = "csi0phytimer_clk_src"; + clock-cntl-level = "nominal"; + clock-rates = + <480000000 0 400000000 0>; + status = "ok"; + }; + + cam_csiphy1: qcom,csiphy1@ace6000 { + cell-index = <1>; + compatible = "qcom,csiphy-v2.1.0", "qcom,csiphy"; + reg = <0xace6000 0x2000>; + reg-names = "csiphy"; + reg-cam-base = <0xe6000>; + interrupt-names = "CSIPHY1"; + interrupts = ; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + csi-vdd-1p2-supply = <&L6B>; + csi-vdd-0p9-supply = <&L5B>; + rgltr-cntrl-support; + rgltr-min-voltage = <0 1200000 880000>; + rgltr-max-voltage = <0 1248000 912000>; + rgltr-load-current = <0 54700 102000>; + clock-names = "cphy_rx_clk_src", + "csiphy1_clk", + "csi1phytimer_clk_src", + "csi1phytimer_clk"; + clocks = <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&clock_camcc CAM_CC_CSIPHY1_CLK>, + <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>, + <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK>; + src-clock-name = "csi1phytimer_clk_src"; + clock-cntl-level = "nominal"; + clock-rates = + <480000000 0 400000000 0>; + + status = "ok"; + }; + + cam_csiphy2: qcom,csiphy2@ace8000 { + cell-index = <2>; + compatible = "qcom,csiphy-v2.1.0", "qcom,csiphy"; + reg = <0xace8000 0x2000>; + reg-names = "csiphy"; + reg-cam-base = <0xe8000>; + interrupt-names = "CSIPHY2"; + interrupts = ; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + csi-vdd-1p2-supply = <&L6B>; + csi-vdd-0p9-supply = <&L5B>; + rgltr-cntrl-support; + rgltr-min-voltage = <0 1200000 880000>; + rgltr-max-voltage = <0 1248000 912000>; + rgltr-load-current = <0 54700 102000>; + clock-names = "cphy_rx_clk_src", + "csiphy2_clk", + "csi2phytimer_clk_src", + "csi2phytimer_clk"; + clocks = <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&clock_camcc CAM_CC_CSIPHY2_CLK>, + <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>, + <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK>; + src-clock-name = "csi2phytimer_clk_src"; + clock-cntl-level = "nominal"; + clock-rates = + <480000000 0 400000000 0>; + status = "ok"; + }; + + cam_csiphy3: qcom,csiphy3@acea000 { + cell-index = <3>; + compatible = "qcom,csiphy-v2.1.0", "qcom,csiphy"; + reg = <0xacea000 0x2000>; + reg-names = "csiphy"; + reg-cam-base = <0xea000>; + interrupt-names = "CSIPHY3"; + interrupts = ; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + csi-vdd-1p2-supply = <&L6B>; + csi-vdd-0p9-supply = <&L5B>; + rgltr-cntrl-support; + rgltr-min-voltage = <0 1200000 880000>; + rgltr-max-voltage = <0 1248000 912000>; + rgltr-load-current = <0 54700 102000>; + clock-names = "cphy_rx_clk_src", + "csiphy3_clk", + "csi3phytimer_clk_src", + "csi3phytimer_clk"; + clocks = <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&clock_camcc CAM_CC_CSIPHY3_CLK>, + <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>, + <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK>; + src-clock-name = "csi3phytimer_clk_src"; + clock-cntl-level = "nominal"; + clock-rates = + <480000000 0 400000000 0>; + status = "ok"; + }; + + cam_csiphy4: qcom,csiphy4@acec000 { + cell-index = <4>; + compatible = "qcom,csiphy-v2.1.0", "qcom,csiphy"; + reg = <0xacec000 0x2000>; + reg-names = "csiphy"; + reg-cam-base = <0xec000>; + interrupt-names = "CSIPHY4"; + interrupts = ; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + csi-vdd-1p2-supply = <&L6B>; + csi-vdd-0p9-supply = <&L5B>; + rgltr-cntrl-support; + rgltr-min-voltage = <0 1200000 880000>; + rgltr-max-voltage = <0 1248000 912000>; + rgltr-load-current = <0 54700 102000>; + clock-names = "cphy_rx_clk_src", + "csiphy4_clk", + "csi4phytimer_clk_src", + "csi4phytimer_clk"; + clocks = <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&clock_camcc CAM_CC_CSIPHY4_CLK>, + <&clock_camcc CAM_CC_CSI4PHYTIMER_CLK_SRC>, + <&clock_camcc CAM_CC_CSI4PHYTIMER_CLK>; + src-clock-name = "csi4phytimer_clk_src"; + clock-cntl-level = "nominal"; + clock-rates = + <480000000 0 400000000 0>; + status = "ok"; + }; + + cam_csiphy5: qcom,csiphy5@acee000 { + cell-index = <5>; + compatible = "qcom,csiphy-v2.1.0", "qcom,csiphy"; + reg = <0xacee000 0x2000>; + reg-names = "csiphy"; + reg-cam-base = <0xee000>; + interrupt-names = "CSIPHY5"; + interrupts = ; + regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + csi-vdd-1p2-supply = <&L6B>; + csi-vdd-0p9-supply = <&L5B>; + rgltr-cntrl-support; + rgltr-min-voltage = <0 1200000 880000>; + rgltr-max-voltage = <0 1248000 912000>; + rgltr-load-current = <0 54700 102000>; + clock-names = "cphy_rx_clk_src", + "csiphy5_clk", + "csi5phytimer_clk_src", + "csi5phytimer_clk"; + clocks = <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&clock_camcc CAM_CC_CSIPHY5_CLK>, + <&clock_camcc CAM_CC_CSI5PHYTIMER_CLK_SRC>, + <&clock_camcc CAM_CC_CSI5PHYTIMER_CLK>; + src-clock-name = "csi5phytimer_clk_src"; + clock-cntl-level = "nominal"; + clock-rates = + <480000000 0 400000000 0>; + status = "ok"; + }; + + cam_cci0: qcom,cci0@ac15000 { + cell-index = <0>; + compatible = "qcom,cci", "simple-bus"; + reg = <0xac15000 0x1000>; + reg-names = "cci"; + reg-cam-base = <0x15000>; + interrupt-names = "cci0"; + interrupts = ; + regulator-names = "gdscr"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + clock-names = "cci_0_clk_src", + "cci_0_clk"; + clocks = <&clock_camcc CAM_CC_CCI_0_CLK_SRC>, + <&clock_camcc CAM_CC_CCI_0_CLK>; + clock-rates = <37500000 0>; + clock-cntl-level = "lowsvs"; + src-clock-name = "cci_0_clk_src"; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cci0_active &cci1_active>; + pinctrl-1 = <&cci0_suspend &cci1_suspend>; + gpios = <&tlmm 110 0>, + <&tlmm 111 0>, + <&tlmm 112 0>, + <&tlmm 113 0>; + gpio-req-tbl-num = <0 1 2 3>; + gpio-req-tbl-flags = <1 1 1 1>; + gpio-req-tbl-label = "CCI_I2C_DATA0", + "CCI_I2C_CLK0", + "CCI_I2C_DATA1", + "CCI_I2C_CLK1"; + + i2c_freq_100Khz_cci0: qcom,i2c_standard_mode { + hw-thigh = <201>; + hw-tlow = <174>; + hw-tsu-sto = <204>; + hw-tsu-sta = <231>; + hw-thd-dat = <22>; + hw-thd-sta = <162>; + hw-tbuf = <227>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_400Khz_cci0: qcom,i2c_fast_mode { + hw-thigh = <38>; + hw-tlow = <56>; + hw-tsu-sto = <40>; + hw-tsu-sta = <40>; + hw-thd-dat = <22>; + hw-thd-sta = <35>; + hw-tbuf = <62>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_custom_cci0: qcom,i2c_custom_mode { + hw-thigh = <38>; + hw-tlow = <56>; + hw-tsu-sto = <40>; + hw-tsu-sta = <40>; + hw-thd-dat = <22>; + hw-thd-sta = <35>; + hw-tbuf = <62>; + hw-scl-stretch-en = <1>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_1Mhz_cci0: qcom,i2c_fast_plus_mode { + hw-thigh = <16>; + hw-tlow = <22>; + hw-tsu-sto = <17>; + hw-tsu-sta = <18>; + hw-thd-dat = <16>; + hw-thd-sta = <15>; + hw-tbuf = <24>; + hw-scl-stretch-en = <0>; + hw-trdhld = <3>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + status = "ok"; + }; + + cam_cci1: qcom,cci1@ac16000 { + cell-index = <1>; + compatible = "qcom,cci", "simple-bus"; + reg = <0xac16000 0x1000>; + reg-names = "cci"; + reg-cam-base = <0x16000>; + interrupt-names = "cci1"; + interrupts = ; + regulator-names = "gdscr"; + gdscr-supply = <&cam_cc_titan_top_gdsc>; + clock-names = "cci_1_clk_src", + "cci_1_clk"; + clocks = <&clock_camcc CAM_CC_CCI_1_CLK_SRC>, + <&clock_camcc CAM_CC_CCI_1_CLK>; + clock-rates = <37500000 0>; + clock-cntl-level = "lowsvs"; + src-clock-name = "cci_1_clk_src"; + pinctrl-names = "cam_default", "cam_suspend"; + pinctrl-0 = <&cci2_active &cci3_active>; + pinctrl-1 = <&cci2_suspend &cci3_suspend>; + gpios = <&tlmm 114 0>, + <&tlmm 115 0>, + <&tlmm 208 0>, + <&tlmm 209 0>; + gpio-req-tbl-num = <0 1 2 3>; + gpio-req-tbl-flags = <1 1 1 1>; + gpio-req-tbl-label = "CCI_I2C_DATA2", + "CCI_I2C_CLK2", + "CCI_I2C_DATA3", + "CCI_I2C_CLK3"; + + i2c_freq_100Khz_cci1: qcom,i2c_standard_mode { + hw-thigh = <201>; + hw-tlow = <174>; + hw-tsu-sto = <204>; + hw-tsu-sta = <231>; + hw-thd-dat = <22>; + hw-thd-sta = <162>; + hw-tbuf = <227>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_400Khz_cci1: qcom,i2c_fast_mode { + hw-thigh = <38>; + hw-tlow = <56>; + hw-tsu-sto = <40>; + hw-tsu-sta = <40>; + hw-thd-dat = <22>; + hw-thd-sta = <35>; + hw-tbuf = <62>; + hw-scl-stretch-en = <0>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_custom_cci1: qcom,i2c_custom_mode { + hw-thigh = <38>; + hw-tlow = <56>; + hw-tsu-sto = <40>; + hw-tsu-sta = <40>; + hw-thd-dat = <22>; + hw-thd-sta = <35>; + hw-tbuf = <62>; + hw-scl-stretch-en = <1>; + hw-trdhld = <6>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + i2c_freq_1Mhz_cci1: qcom,i2c_fast_plus_mode { + hw-thigh = <16>; + hw-tlow = <22>; + hw-tsu-sto = <17>; + hw-tsu-sta = <18>; + hw-thd-dat = <16>; + hw-thd-sta = <15>; + hw-tbuf = <24>; + hw-scl-stretch-en = <0>; + hw-trdhld = <3>; + hw-tsp = <3>; + cci-clk-src = <37500000>; + status = "ok"; + }; + + status = "ok"; + }; + + qcom,cam_smmu { + compatible = "qcom,msm-cam-smmu", "simple-bus"; + status = "ok"; + + msm_cam_smmu_ife { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x800 0x460>, + <&apps_smmu 0x820 0x460>, + <&apps_smmu 0xC00 0x460>, + <&apps_smmu 0xC20 0x460>, + <&apps_smmu 0x840 0x460>, + <&apps_smmu 0x860 0x460>, + <&apps_smmu 0xC40 0x460>, + <&apps_smmu 0xC60 0x460>; + qcom,iommu-dma-addr-pool = <0x100000 0xffe00000>; + dma-coherent-hint-cached; + cam-smmu-label = "ife", "sfe"; + multiple-client-devices; + ife_iova_mem_map: iova-mem-map { + /* IO region is approximately 4.0 GB */ + iova-mem-region-io { + iova-region-name = "io"; + /* 1 MB pad for start */ + iova-region-start = <0x100000>; + /* 1 MB pad for end */ + iova-region-len = <0xffe00000>; + iova-region-id = <0x3>; + status = "ok"; + }; + }; + }; + + msm_cam_smmu_jpeg { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x20E0 0x400>, + <&apps_smmu 0x24E0 0x400>; + cam-smmu-label = "jpeg"; + qcom,iommu-dma-addr-pool = <0x100000 0xffe00000>; + dma-coherent-hint-cached; + jpeg_iova_mem_map: iova-mem-map { + /* IO region is approximately 4.0 GB */ + iova-mem-region-io { + iova-region-name = "io"; + /* 1 MB pad for start */ + iova-region-start = <0x100000>; + /* 1 MB pad for end */ + iova-region-len = <0xffe00000>; + iova-region-id = <0x3>; + status = "ok"; + }; + }; + }; + + msm_cam_icp_fw { + compatible = "qcom,msm-cam-smmu-fw-dev"; + label="icp"; + memory-region = <&pil_camera_mem>; + }; + + msm_cam_smmu_icp { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x2020 0x420>, + <&apps_smmu 0x2000 0x420>, + <&apps_smmu 0x2420 0x420>, + <&apps_smmu 0x2400 0x420>, + <&apps_smmu 0x2040 0x420>, + <&apps_smmu 0x2060 0x420>, + <&apps_smmu 0x2440 0x420>, + <&apps_smmu 0x2460 0x420>, + <&apps_smmu 0x2101 0x400>, + <&apps_smmu 0x2501 0x400>, + <&apps_smmu 0x2080 0x400>, + <&apps_smmu 0x2480 0x400>, + <&apps_smmu 0x2120 0x420>, + <&apps_smmu 0x2520 0x420>; + cam-smmu-label = "icp"; + qcom,iommu-dma-addr-pool = <0x10c00000 0xee300000>; + iova-region-discard = <0xe0000000 0x800000>; + dma-coherent-hint-cached; + icp_iova_mem_map: iova-mem-map { + iova-mem-region-shared { + /* Shared region is 261MB long */ + iova-region-name = "shared"; + iova-region-start = <0x500000>; + iova-region-len = <0x10500000>; + iova-region-id = <0x1>; + status = "ok"; + }; + + iova-mem-region-secondary-heap { + /* Secondary heap region is 1MB long */ + iova-region-name = "secheap"; + iova-region-start = <0x10a00000>; + iova-region-len = <0x100000>; + iova-region-id = <0x4>; + status = "ok"; + }; + + iova-mem-region-io { + /* IO region is approximately 3.8 GB */ + iova-region-name = "io"; + iova-region-start = <0x10c00000>; + iova-region-len = <0xee300000>; + iova-region-id = <0x3>; + iova-region-discard = <0xe0000000 0x800000>; + status = "ok"; + }; + + iova-mem-qdss-region { + /* QDSS region is appropriate 1MB */ + iova-region-name = "qdss"; + iova-region-start = <0x10b00000>; + iova-region-len = <0x100000>; + iova-region-id = <0x5>; + qdss-phy-addr = <0x16790000>; + status = "ok"; + }; + }; + }; + + msm_cam_smmu_cpas_cdm { + compatible = "qcom,msm-cam-smmu-cb"; + iommus = <&apps_smmu 0x20C0 0x0400>, + <&apps_smmu 0x24C0 0x0400>, + <&apps_smmu 0x20A0 0x0400>, + <&apps_smmu 0x24A0 0x0400>; + cam-smmu-label = "cpas-cdm"; + qcom,iommu-dma-addr-pool = <0x100000 0xffe00000>; + dma-coherent-hint-cached; + cpas_cdm_iova_mem_map: iova-mem-map { + iova-mem-region-io { + /* IO region is approximately 4.0 GB */ + iova-region-name = "io"; + /* 1 MB pad for start */ + iova-region-start = <0x100000>; + /* 1 MB pad for end */ + iova-region-len = <0xffe00000>; + iova-region-id = <0x3>; + status = "ok"; + }; + }; + }; + + msm_cam_smmu_secure { + compatible = "qcom,msm-cam-smmu-cb"; + cam-smmu-label = "cam-secure"; + qcom,secure-cb; + }; + }; + + qcom,cam-cpas@ac13000 { + cell-index = <0>; + compatible = "qcom,cam-cpas"; + label = "cpas"; + arch-compat = "cpas_top"; + reg-names = "cam_cpas_top", "cam_camnoc", "cam_rpmh"; + reg = <0xac13000 0x1000>, + <0xac19000 0x9000>, + <0xbbf0000 0x1F00>; + reg-cam-base = <0x13000 0x19000 0x0bbf0000>; + interrupt-names = "cpas_camnoc"; + interrupts = ; + camnoc-axi-min-ib-bw = <3000000000>; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + clock-names = + "gcc_ahb_clk", + "gcc_axi_hf_clk", + "gcc_axi_sf_clk", + "cam_cc_slow_ahb_clk_src", + "cpas_ahb_clk", + "cpas_core_ahb_clk", + "cam_cc_fast_ahb_clk_src", + "cam_cc_cpas_fast_ahb_clk", + "camnoc_axi_clk_src", + "camnoc_axi_clk"; + clocks = + <&clock_gcc GCC_CAMERA_AHB_CLK>, + <&clock_gcc GCC_CAMERA_HF_AXI_CLK>, + <&clock_gcc GCC_CAMERA_SF_AXI_CLK>, + <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&clock_camcc CAM_CC_CPAS_AHB_CLK>, + <&clock_camcc CAM_CC_CORE_AHB_CLK>, + <&clock_camcc CAM_CC_FAST_AHB_CLK_SRC>, + <&clock_camcc CAM_CC_CPAS_FAST_AHB_CLK>, + <&clock_camcc CAM_CC_CAMNOC_AXI_CLK_SRC>, + <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>; + clock-rates = + <0 0 0 0 0 0 0 0 0 0>, + <0 0 0 80000000 0 0 100000000 0 300000000 0>, + <0 0 0 80000000 0 0 200000000 0 400000000 0>, + <0 0 0 80000000 0 0 300000000 0 400000000 0>, + <0 0 0 80000000 0 0 400000000 0 400000000 0>, + <0 0 0 80000000 0 0 400000000 0 400000000 0>, + <0 0 0 80000000 0 0 400000000 0 400000000 0>; + clock-cntl-level = "suspend", "lowsvs", "svs", "svs_l1", + "nominal", "nominal_l1", "turbo"; + src-clock-name = "camnoc_axi_clk_src"; + control-camnoc-axi-clk; + camnoc-bus-width = <32>; + camnoc-axi-clk-bw-margin-perc = <20>; + interconnect-names = "cam_ahb"; + interconnects =<&gem_noc MASTER_APPSS_PROC + &config_noc SLAVE_CAMERA_CFG>; + rpmh-bcm-info = <12 0x4 0x800 0 4>; + cam-ahb-num-cases = <8>; + cam-ahb-bw-KBps = + <0 0>, <0 76800>, <0 76800>, <0 150000>, <0 150000>, + <0 300000>, <0 300000>, <0 300000>; + vdd-corners = ; + vdd-corner-ahb-mapping = "suspend", "lowsvs", + "lowsvs", "svs", "svs_l1", + "nominal", "nominal", "nominal", + "turbo", "turbo"; + client-id-based; + client-names = + "csiphy0", "csiphy1", "csiphy2", "csiphy3", "csiphy4", "csiphy5", + "cci0", "cci1", "csid0", "csid1", "csid2", "csid3", "csid4", + "csid5", "csid6", "csid7", "ife0", "ife1", "ife2", "ife3", "ife4", + "ife5", "ife6", "ife7", "sfe0", "sfe1", "custom0", "custom1", + "ipe0", "cpas-cdm0", "rt-cdm0", "rt-cdm1", "rt-cdm2", + "cam-cdm-intf0", "bps0", "icp0", "jpeg-dma0", "jpeg-enc0", "tpg0", + "tpg1", "tpg2"; + + camera-bus-nodes { + level3-nodes { + level-index = <3>; + level3_rt0_rd_wr_sum: level3-rt0-rd-wr-sum { + cell-index = <0>; + node-name = "level3-rt0-rd-wr-sum"; + traffic-merge-type = + ; + ib-bw-voting-needed; + qcom,axi-port-mnoc { + interconnect-names = "cam_hf_0"; + interconnects = + <&mmss_noc MASTER_CAMNOC_HF + &mc_virt SLAVE_EBI1>; + }; + }; + + level3_nrt0_rd_wr_sum: level3-nrt0-rd-wr-sum { + cell-index = <1>; + node-name = "level3-nrt0-rd-wr-sum"; + traffic-merge-type = + ; + qcom,axi-port-mnoc { + interconnect-names = "cam_sf_0"; + interconnects = + <&mmss_noc MASTER_CAMNOC_SF + &mc_virt SLAVE_EBI1>; + }; + }; + + level3_nrt1_rd_wr_sum: level3-nrt1-rd-wr-sum { + cell-index = <2>; + node-name = "level3-nrt1-rd-wr-sum"; + traffic-merge-type = + ; + qcom,axi-port-mnoc { + interconnect-names = + "cam_sf_icp"; + interconnects = + <&mmss_noc MASTER_CAMNOC_ICP + &mc_virt SLAVE_EBI1>; + }; + }; + }; + + level2-nodes { + level-index = <2>; + camnoc-max-needed; + level2_rt0_wr: level2-rt0-wr { + cell-index = <3>; + node-name = "level2-rt0-wr"; + parent-node = <&level3_rt0_rd_wr_sum>; + traffic-merge-type = + ; + }; + + level2_rt0_rd: level2-rt0-rd { + cell-index = <4>; + node-name = "level2-rt0-rd"; + parent-node = <&level3_rt0_rd_wr_sum>; + traffic-merge-type = + ; + }; + + level2_nrt0_wr: level2-nrt0-wr { + cell-index = <5>; + node-name = "level2-nrt0-wr"; + parent-node = <&level3_nrt0_rd_wr_sum>; + traffic-merge-type = + ; + }; + + level2_nrt0_rd: level2-nrt0-rd { + cell-index = <6>; + node-name = "level2-nrt0-rd"; + parent-node = <&level3_nrt0_rd_wr_sum>; + traffic-merge-type = + ; + }; + + level2_nrt1_rd: level2-nrt1-rd { + cell-index = <7>; + node-name = "level2-nrt1-rd"; + parent-node = <&level3_nrt1_rd_wr_sum>; + traffic-merge-type = + ; + bus-width-factor = <4>; + }; + }; + + level1-nodes { + level-index = <1>; + camnoc-max-needed; + level1_rt0_wr0: level1-rt0-wr0 { + cell-index = <8>; + node-name = "level1-rt0-wr0"; + parent-node = <&level2_rt0_wr>; + traffic-merge-type = + ; + }; + + level1_rt0_wr1: level1-rt0-wr1 { + cell-index = <9>; + node-name = "level1-rt0-wr1"; + parent-node = <&level2_rt0_wr>; + traffic-merge-type = + ; + }; + + level1_rt0_wr2: level1-rt0-wr2 { + cell-index = <10>; + node-name = "level1-rt0-wr2"; + parent-node = <&level2_rt0_wr>; + traffic-merge-type = + ; + }; + + level1_rt0_wr3: level1-rt0-wr3 { + cell-index = <11>; + node-name = "level1-rt0-wr3"; + parent-node = <&level2_rt0_wr>; + traffic-merge-type = + ; + }; + + level1_rt0_wr4: level1-rt0-wr4 { + cell-index = <12>; + node-name = "level1-rt0-wr4"; + parent-node = <&level2_rt0_wr>; + traffic-merge-type = + ; + }; + + level1_rt0_rd0: level1-rt0-rd0 { + cell-index = <13>; + node-name = "level1-rt0-rd0"; + parent-node = <&level2_rt0_rd>; + traffic-merge-type = + ; + }; + + level1_nrt0_wr0: level1-nrt0-wr0 { + cell-index = <14>; + node-name = "level1-nrt0-wr0"; + parent-node = <&level2_nrt0_wr>; + traffic-merge-type = + ; + }; + + level1_nrt0_rd0: level1-nrt0-rd0 { + cell-index = <15>; + node-name = "level1-nrt0-rd0"; + parent-node = <&level2_nrt0_rd>; + traffic-merge-type = + ; + }; + + level1_nrt0_rd1: level1-nrt0-rd1 { + cell-index = <16>; + node-name = "level1-nrt0-rd1"; + parent-node = <&level2_nrt0_rd>; + traffic-merge-type = + ; + }; + }; + + level0-nodes { + level-index = <0>; + ife0_ubwc_wr: ife0-ubwc-wr { + cell-index = <17>; + node-name = "ife0-ubwc-wr"; + client-name = "ife0"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr0>; + }; + + ife1_ubwc_wr: ife1-ubwc-wr { + cell-index = <18>; + node-name = "ife1-ubwc-wr"; + client-name = "ife1"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr0>; + }; + + ife2_ubwc_wr: ife2-ubwc-wr { + cell-index = <19>; + node-name = "ife2-ubwc-wr"; + client-name = "ife2"; + traffic-data = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr0>; + }; + + ife0_rdi_pixel_raw_wr: ife0-rdi-pixel-raw-wr { + cell-index = <20>; + node-name = "ife0-rdi-pixel-raw-wr"; + client-name = "ife0"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr1>; + }; + + ife1_rdi_pixel_raw_wr: ife1-rdi-pixel-raw-wr { + cell-index = <21>; + node-name = "ife1-rdi-pixel-raw-wr"; + client-name = "ife1"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr1>; + }; + + ife2_rdi_pixel_raw_wr: ife2-rdi-pixel-raw-wr { + cell-index = <22>; + node-name = "ife2-rdi-pixel-raw-wr"; + client-name = "ife2"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr1>; + }; + + sfe0_rdi_stats_nrdi_wr: sfe0-rdi-stats-nrdi-wr { + cell-index = <23>; + node-name = "sfe0-rdi-stats-nrdi-wr"; + client-name = "sfe0"; + traffic-data = ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr1>; + }; + + sfe1_rdi_stats_nrdi_wr: sfe1-rdi-stats-nrdi-wr { + cell-index = <24>; + node-name = "sfe1-rdi-stats-nrdi-wr"; + client-name = "sfe1"; + traffic-data = ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr1>; + }; + + custom0_wr: custom0-wr { + cell-index = <25>; + node-name = "custom0-wr"; + client-name = "custom0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_rt0_wr1>; + }; + + ife0_pdaf_wr: ife0-pdaf-wr { + cell-index = <26>; + node-name = "ife0-pdaf-wr"; + client-name = "ife0"; + traffic-data = + ; + traffic-transaction-type = + ; + parent-node = <&level1_rt0_wr2>; + }; + + ife1_pdaf_wr: ife1-pdaf-wr { + cell-index = <27>; + node-name = "ife1-pdaf-wr"; + client-name = "ife1"; + traffic-data = + ; + traffic-transaction-type = + ; + parent-node = <&level1_rt0_wr2>; + }; + + ife2_pdaf_wr: ife2-pdaf-wr { + cell-index = <28>; + node-name = "ife2-pdaf-wr"; + client-name = "ife2"; + traffic-data = + ; + traffic-transaction-type = + ; + parent-node = <&level1_rt0_wr2>; + }; + + ife0_linear_stats_wr: ife0-linear-stats-wr { + cell-index = <29>; + node-name = "ife0-linear-stats-wr"; + client-name = "ife0"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr3>; + }; + + ife1_linear_stats_wr: ife1-linear-stats-wr { + cell-index = <30>; + node-name = "ife1-linear-stats-wr"; + client-name = "ife1"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr3>; + }; + + ife2_linear_stats_wr: ife2-linear-stats-wr { + cell-index = <31>; + node-name = "ife2-linear-stats-wr"; + client-name = "ife2"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level2_rt0_wr>; + }; + + custom1_wr: custom1-wr { + cell-index = <32>; + node-name = "custom1-wr"; + client-name = "custom1"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_rt0_wr4>; + }; + + ife7_rdi_stats_pixel_raw_wr: ife7-rdi-stats-pixel-raw-wr { + cell-index = <33>; + node-name = "ife7-rdi-stats-pixel-raw-wr"; + client-name = "ife7"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr4>; + }; + + ife6_rdi_stats_pixel_raw_wr: ife6-rdi-stats-pixel-raw-wr { + cell-index = <34>; + node-name = "ife6-rdi-stats-pixel-raw-wr"; + client-name = "ife6"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr4>; + }; + + ife5_rdi_stats_pixel_raw_wr: ife5-rdi-stats-pixel-raw-wr { + cell-index = <35>; + node-name = "ife5-rdi-stats-pixel-raw-wr"; + client-name = "ife5"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr4>; + }; + + ife4_rdi_stats_pixel_raw_wr: ife4-rdi-stats-pixel-raw-wr { + cell-index = <36>; + node-name = "ife4-rdi-stats-pixel-raw-wr"; + client-name = "ife4"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr4>; + }; + + ife3_rdi_stats_pixel_raw_wr: ife3-rdi-stats-pixel-raw-wr { + cell-index = <37>; + node-name = "ife3-rdi-stats-pixel-raw-wr"; + client-name = "ife3"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_wr4>; + }; + + sfe0_all_rd: sfe0-all-rd { + cell-index = <38>; + node-name = "sfe0-all-rd"; + client-name = "sfe0"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_rd0>; + }; + + sfe1_all_rd: sfe1-all-rd { + cell-index = <39>; + node-name = "sfe1-all-rd"; + client-name = "sfe1"; + traffic-data = + ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level1_rt0_rd0>; + }; + + custom0_rd: custom0-rd { + cell-index = <40>; + node-name = "custom0-rd"; + client-name = "custom0"; + traffic-data = + ; + traffic-transaction-type = + ; + parent-node = <&level1_rt0_rd0>; + }; + + custom1_rd: custom1-rd { + cell-index = <41>; + node-name = "custom1-rd"; + client-name = "custom1"; + traffic-data = + ; + traffic-transaction-type = + ; + parent-node = <&level1_rt0_rd0>; + }; + + ipe0_all_wr: ipe0-all-wr { + cell-index = <42>; + node-name = "ipe0-all-wr"; + client-name = "ipe0"; + traffic-data = ; + traffic-transaction-type = + ; + constituent-paths = + ; + parent-node = <&level2_nrt0_wr>; + }; + + bps0_all_wr: bps0-all-wr { + cell-index = <43>; + node-name = "bps0-all-wr"; + client-name = "bps0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level2_nrt0_wr>; + }; + + bps0_all_rd: bps0-all-rd { + cell-index = <44>; + node-name = "bps0-all-rd"; + client-name = "bps0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level2_nrt0_rd>; + }; + + jpeg_enc0_all_rd: jpeg-enc0-all-rd { + cell-index = <45>; + node-name = "jpeg-enc0-all-rd"; + client-name = "jpeg-enc0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt0_rd0>; + }; + + jpeg_dma0_all_rd: jpeg-dma0-all-rd { + cell-index = <46>; + node-name = "jpeg-dma0-all-rd"; + client-name = "jpeg-dma0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt0_rd0>; + }; + + jpeg_enc0_all_wr: jpeg-enc0-all-wr { + cell-index = <47>; + node-name = "jpeg-enc0-all-wr"; + client-name = "jpeg-enc0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt0_wr0>; + }; + + jpeg_dma0_all_wr: jpeg-dma0-all-wr { + cell-index = <48>; + node-name = "jpeg-dma0-all-wr"; + client-name = "jpeg-dma0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt0_wr0>; + }; + + ipe0_ref_rd: ipe0-ref-rd { + cell-index = <49>; + node-name = "ipe0-ref-rd"; + client-name = "ipe0"; + traffic-data = + ; + traffic-transaction-type = + ; + parent-node = <&level2_nrt0_rd>; + }; + + ipe0_in_rd: ipe0-in-rd { + cell-index = <50>; + node-name = "ipe0-in-rd"; + client-name = "ipe0"; + traffic-data = + ; + traffic-transaction-type = + ; + parent-node = <&level2_nrt0_rd>; + }; + + rt_cdm0_all_rd: rt-cdm0-all-rd { + cell-index = <51>; + node-name = "rt-cdm0-all-rd"; + client-name = "rt-cdm0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt0_rd1>; + }; + + rt_cdm1_all_rd: rt-cdm1-all-rd { + cell-index = <52>; + node-name = "rt-cdm1-all-rd"; + client-name = "rt-cdm1"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt0_rd1>; + }; + + rt_cdm2_all_rd: rt-cdm2-all-rd { + cell-index = <53>; + node-name = "rt-cdm2-all-rd"; + client-name = "rt-cdm2"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt0_rd1>; + }; + + cpas_cdm0_all_rd: cpas-cdm0-all-rd { + cell-index = <54>; + node-name = "cpas-cdm0-all-rd"; + client-name = "cpas-cdm0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt0_rd1>; + }; + + ipe0_cdm_all_rd: ipe0-cdm-all-rd { + cell-index = <55>; + node-name = "ipe0-cdm-all-rd"; + client-name = "ipe0-cdm"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt0_rd1>; + }; + + bps0_cdm_all_rd: bps0-cdm-all-rd { + cell-index = <56>; + node-name = "bps0-cdm-all-rd"; + client-name = "bps0-cdm"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level1_nrt0_rd1>; + }; + + icp0_all_rd: icp0-all-rd { + cell-index = <57>; + node-name = "icp0-all-rd"; + client-name = "icp0"; + traffic-data = ; + traffic-transaction-type = + ; + parent-node = <&level2_nrt1_rd>; + }; + }; + }; + + status = "ok"; + }; + + qcom,cam-cdm-intf { + compatible = "qcom,cam-cdm-intf"; + cell-index = <0>; + label = "cam-cdm-intf"; + num-hw-cdm = <1>; + cdm-client-names = "vfe", + "jpegdma", + "jpegenc"; + status = "ok"; + }; + + qcom,cpas-cdm0@ac24000 { + cell-index = <0>; + compatible = "qcom,cam-cpas-cdm2_1"; + label = "cpas-cdm"; + reg = <0xac24000 0x400>; + reg-names = "cpas-cdm"; + reg-cam-base = <0x24000>; + interrupt-names = "cpas-cdm"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + clock-names = "cam_cc_slow_ahb_clk_src", + "cam_cc_cpas_ahb_clk"; + clocks = <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&clock_camcc CAM_CC_CPAS_AHB_CLK>; + clock-rates = <80000000 0>; + clock-cntl-level = "svs"; + cdm-client-names = "ife3", "ife4", "ife5", "ife6", "ife7"; + config-fifo; + fifo-depths = <64 0 0 0>; + single-context-cdm; + status = "ok"; + }; + + qcom,rt-cdm0@ac25000 { + cell-index = <0>; + compatible = "qcom,cam-rt-cdm2_1"; + label = "rt-cdm"; + reg = <0xac25000 0x400>; + reg-names = "rt-cdm0"; + reg-cam-base = <0x25000>; + interrupt-names = "rt-cdm0"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + clock-names = + "cam_cc_slow_ahb_clk_src", + "cam_cc_cpas_ahb_clk"; + clocks = + <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&clock_camcc CAM_CC_CPAS_AHB_CLK>; + clock-rates = + <80000000 0>, + <80000000 0>, + <80000000 0>, + <80000000 0>, + <80000000 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; + cdm-client-names = "ife0", "dualife0"; + config-fifo; + fifo-depths = <64 0 0 0>; + single-context-cdm; + status = "ok"; + }; + + qcom,rt-cdm1@ac26000 { + cell-index = <1>; + compatible = "qcom,cam-rt-cdm2_1"; + label = "rt-cdm"; + reg = <0xac26000 0x400>; + reg-names = "rt-cdm1"; + reg-cam-base = <0x26000>; + interrupt-names = "rt-cdm1"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + clock-names = + "cam_cc_slow_ahb_clk_src", + "cam_cc_cpas_ahb_clk"; + clocks = + <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&clock_camcc CAM_CC_CPAS_AHB_CLK>; + clock-rates = + <80000000 0>, + <80000000 0>, + <80000000 0>, + <80000000 0>, + <80000000 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; + cdm-client-names = "ife1", "dualife1"; + config-fifo; + fifo-depths = <64 0 0 0>; + single-context-cdm; + status = "ok"; + }; + + qcom,rt-cdm2@ac27000 { + cell-index = <2>; + compatible = "qcom,cam-rt-cdm2_1"; + label = "rt-cdm"; + reg = <0xac27000 0x400>; + reg-names = "rt-cdm2"; + reg-cam-base = <0x27000>; + interrupt-names = "rt-cdm2"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + clock-names = + "cam_cc_slow_ahb_clk_src", + "cam_cc_cpas_ahb_clk"; + clocks = + <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&clock_camcc CAM_CC_CPAS_AHB_CLK>; + clock-rates = + <80000000 0>, + <80000000 0>, + <80000000 0>, + <80000000 0>, + <80000000 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", "turbo"; + cdm-client-names = "ife2", "dualife2"; + config-fifo; + fifo-depths = <64 0 0 0>; + single-context-cdm; + status = "ok"; + }; + + qcom,cam-isp { + compatible = "qcom,cam-isp"; + arch-compat = "ife"; + status = "ok"; + }; + + cam_sfe0: qcom,sfe0@ac9e000 { + cell-index = <0>; + compatible = "qcom,sfe680"; + reg-names = "sfe0", "rt_wrapper"; + reg = <0xac9e000 0x8000>, + <0xac62000 0x64000>; + reg-cam-base = <0x9e000 0x62000>; + interrupt-names = "sfe"; + interrupts = ; + regulator-names = "gdsc", "sfe0"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + sfe0-supply = <&cam_cc_sfe_0_gdsc>; + clock-names = + "cam_cc_fast_ahb_clk_src", + "sfe_0_fast_ahb", + "sfe_0_clk_src", + "sfe_0_clk", + "cam_cc_cpas_sfe_0_clk"; + clocks = + <&clock_camcc CAM_CC_FAST_AHB_CLK_SRC>, + <&clock_camcc CAM_CC_SFE_0_FAST_AHB_CLK>, + <&clock_camcc CAM_CC_SFE_0_CLK_SRC>, + <&clock_camcc CAM_CC_SFE_0_CLK>, + <&clock_camcc CAM_CC_CPAS_SFE_0_CLK>; + clock-rates = + <100000000 0 432000000 0 0>, + <200000000 0 594000000 0 0>, + <300000000 0 675000000 0 0>, + <400000000 0 785000000 0 0>, + <400000000 0 785000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + src-clock-name = "sfe_0_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_sfe1: qcom,sfe1@aca6000 { + cell-index = <1>; + compatible = "qcom,sfe680"; + reg-names = "sfe1", "rt_wrapper"; + reg = <0xaca6000 0x8000>, + <0xac62000 0x64000>; + reg-cam-base = <0xa6000 0x62000>; + interrupt-names = "sfe"; + interrupts = ; + regulator-names = "gdsc", "sfe1"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + sfe1-supply = <&cam_cc_sfe_1_gdsc>; + clock-names = + "cam_cc_fast_ahb_clk_src", + "sfe_1_fast_ahb", + "sfe_1_clk_src", + "sfe_1_clk", + "cam_cc_cpas_sfe_1_clk"; + clocks = + <&clock_camcc CAM_CC_FAST_AHB_CLK_SRC>, + <&clock_camcc CAM_CC_SFE_1_FAST_AHB_CLK>, + <&clock_camcc CAM_CC_SFE_1_CLK_SRC>, + <&clock_camcc CAM_CC_SFE_1_CLK>, + <&clock_camcc CAM_CC_CPAS_SFE_1_CLK>; + clock-rates = + <100000000 0 432000000 0 0>, + <200000000 0 594000000 0 0>, + <300000000 0 675000000 0 0>, + <400000000 0 785000000 0 0>, + <400000000 0 785000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + src-clock-name = "sfe_1_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_csid0: qcom,csid0@acb7000 { + cell-index = <0>; + compatible = "qcom,csid680"; + reg-names = "csid", "csid_top", "rt_wrapper"; + reg = <0xacb7000 0xd00>, + <0xacb6000 0x1000>, + <0xac62000 0x64000>; + reg-cam-base = <0xb7000 0xb6000 0x62000>; + interrupt-names = "csid"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + clock-names = + "csid_clk_src", + "csid_clk", + "cphy_rx_clk_src", + "csiphy_rx_clk", + "cam_cc_fast_ahb_clk_src", + "cpas_fast_ahb"; + clocks = + <&clock_camcc CAM_CC_CSID_CLK_SRC>, + <&clock_camcc CAM_CC_CSID_CLK>, + <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&clock_camcc CAM_CC_CSID_CSIPHY_RX_CLK>; + clock-rates = + <400000000 0 400000000 0>, + <480000000 0 480000000 0>, + <480000000 0 480000000 0>, + <480000000 0 480000000 0>, + <480000000 0 480000000 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + src-clock-name = "csid_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_vfe0: qcom,ife0@ac62000 { + cell-index = <0>; + compatible = "qcom,vfe680"; + reg-names = "ife", "cam_camnoc", "rt_wrapper"; + reg = <0xac62000 0xf000>, + <0xac19000 0x9000>, + <0xac62000 0x64000>; + reg-cam-base = <0x62000 0x19000 0x62000>; + interrupt-names = "ife"; + interrupts = ; + regulator-names = "gdsc", "ife0"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + ife0-supply = <&cam_cc_ife_0_gdsc>; + clock-names = + "cam_cc_fast_ahb_clk_src", + "ife_0_fast_ahb", + "ife_0_clk_src", + "ife_0_clk", + "cam_cc_cpas_ife_0_clk"; + clocks = + <&clock_camcc CAM_CC_FAST_AHB_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_0_FAST_AHB_CLK>, + <&clock_camcc CAM_CC_IFE_0_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_0_CLK>, + <&clock_camcc CAM_CC_CPAS_IFE_0_CLK>; + clock-rates = + <100000000 0 432000000 0 0>, + <200000000 0 594000000 0 0>, + <300000000 0 675000000 0 0>, + <400000000 0 785000000 0 0>, + <400000000 0 785000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + src-clock-name = "ife_0_clk_src"; + clock-control-debugfs = "true"; + clock-names-option = "ife_dsp_clk"; + clocks-option = <&clock_camcc CAM_CC_IFE_0_DSP_CLK>; + clock-rates-option = <594000000>; + ubwc-static-cfg = <0x1026 0x1036>; + cam_hw_pid = <16 28 20 8>; + status = "ok"; + }; + + cam_csid1: qcom,csid1@acb9000 { + cell-index = <1>; + compatible = "qcom,csid680"; + reg-names = "csid", "csid_top", "rt_wrapper"; + reg = <0xacb9000 0xd00>, + <0xacb6000 0x1000>, + <0xac62000 0x64000>; + reg-cam-base = <0xb9000 0xb6000 0x62000>; + interrupt-names = "csid"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + clock-names = + "csid_clk_src", + "csid_clk", + "cphy_rx_clk_src", + "csiphy_rx_clk"; + clocks = + <&clock_camcc CAM_CC_CSID_CLK_SRC>, + <&clock_camcc CAM_CC_CSID_CLK>, + <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&clock_camcc CAM_CC_CSID_CSIPHY_RX_CLK>; + clock-rates = + <400000000 0 400000000 0>, + <480000000 0 480000000 0>, + <480000000 0 480000000 0>, + <480000000 0 480000000 0>, + <480000000 0 480000000 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + src-clock-name = "csid_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_vfe1: qcom,ife1@ac71000 { + cell-index = <1>; + compatible = "qcom,vfe680"; + reg-names = "ife", "cam_camnoc", "rt_wrapper"; + reg = <0xac71000 0xf000>, + <0xac19000 0x9000>, + <0xac62000 0x64000>; + reg-cam-base = <0x71000 0x19000 0x62000>; + interrupt-names = "ife"; + interrupts = ; + regulator-names = "gdsc", "ife1"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + ife1-supply = <&cam_cc_ife_1_gdsc>; + clock-names = + "cam_cc_fast_ahb_clk_src", + "ife_1_fast_ahb", + "ife_1_clk_src", + "ife_1_clk", + "cam_cc_cpas_ife_1_clk"; + clocks = + <&clock_camcc CAM_CC_FAST_AHB_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_1_FAST_AHB_CLK>, + <&clock_camcc CAM_CC_IFE_1_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_1_CLK>, + <&clock_camcc CAM_CC_CPAS_IFE_1_CLK>; + clock-rates = + <100000000 0 432000000 0 0>, + <200000000 0 594000000 0 0>, + <300000000 0 675000000 0 0>, + <400000000 0 785000000 0 0>, + <400000000 0 785000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + src-clock-name = "ife_1_clk_src"; + clock-control-debugfs = "true"; + clock-names-option = "ife_dsp_clk"; + clocks-option = <&clock_camcc CAM_CC_IFE_1_DSP_CLK>; + clock-rates-option = <594000000>; + ubwc-static-cfg = <0x1026 0x1036>; + cam_hw_pid = <17 29 21 9>; + status = "ok"; + }; + + cam_csid2: qcom,csid2@acbb000 { + cell-index = <2>; + compatible = "qcom,csid680"; + reg-names = "csid", "csid_top", "rt_wrapper"; + reg = <0xacbb000 0xd00>, + <0xacb6000 0x1000>, + <0xac62000 0x64000>; + reg-cam-base = <0xbb000 0xb6000 0x62000>; + interrupt-names = "csid"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + clock-names = + "csid_clk_src", + "csid_clk", + "cphy_rx_clk_src", + "csiphy_rx_clk"; + clocks = + <&clock_camcc CAM_CC_CSID_CLK_SRC>, + <&clock_camcc CAM_CC_CSID_CLK>, + <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&clock_camcc CAM_CC_CSID_CSIPHY_RX_CLK>; + clock-rates = + <400000000 0 400000000 0>, + <480000000 0 480000000 0>, + <480000000 0 480000000 0>, + <480000000 0 480000000 0>, + <480000000 0 480000000 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + src-clock-name = "csid_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_vfe2: qcom,ife2@ac80000 { + cell-index = <2>; + compatible = "qcom,vfe680"; + reg-names = "ife", "cam_camnoc", "rt_wrapper"; + reg = <0xac80000 0xf000>, + <0xac19000 0x9000>, + <0xac62000 0x64000>; + reg-cam-base = <0x80000 0x19000 0x62000>; + interrupt-names = "ife"; + interrupts = ; + regulator-names = "gdsc", "ife2"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + ife2-supply = <&cam_cc_ife_2_gdsc>; + clock-names = + "cam_cc_fast_ahb_clk_src", + "ife_2_fast_ahb", + "ife_2_clk_src", + "ife_2_clk", + "cam_cc_cpas_ife_2_clk"; + clocks = + <&clock_camcc CAM_CC_FAST_AHB_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_2_FAST_AHB_CLK>, + <&clock_camcc CAM_CC_IFE_2_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_2_CLK>, + <&clock_camcc CAM_CC_CPAS_IFE_2_CLK>; + clock-rates = + <100000000 432000000 0 0>, + <200000000 594000000 0 0>, + <300000000 675000000 0 0>, + <400000000 785000000 0 0>, + <400000000 785000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + src-clock-name = "ife_2_clk_src"; + clock-control-debugfs = "true"; + clock-names-option = "ife_dsp_clk"; + clocks-option = <&clock_camcc CAM_CC_IFE_2_DSP_CLK>; + clock-rates-option = <594000000>; + ubwc-static-cfg = <0x1026 0x1036>; + cam_hw_pid = <18 30 22 10>; + status = "ok"; + }; + + cam_csid_lite0: qcom,csid-lite0@acc6000 { + cell-index = <3>; + compatible = "qcom,csid-lite680"; + reg-names = "csid-lite"; + reg = <0xacc6000 0xa00>; + reg-cam-base = <0xc6000>; + interrupt-names = "csid-lite"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + clock-names = + "cam_cc_slow_ahb_clk_src", + "ife_lite_ahb", + "ife_lite_csid_clk_src", + "ife_lite_csid_clk", + "ife_lite_cphy_rx_clk_src", + "ife_lite_cphy_rx_clk", + "ife_lite_clk_src", + "ife_lite_clk", + "cam_cc_cpas_ife_lite_clk"; + clocks = + <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK>, + <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&clock_camcc CAM_CC_IFE_LITE_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_LITE_CLK>, + <&clock_camcc CAM_CC_CPAS_IFE_LITE_CLK>; + clock-rates = + <80000000 0 400000000 0 400000000 0 400000000 0 0>, + <80000000 0 480000000 0 480000000 0 480000000 0 0>, + <80000000 0 480000000 0 480000000 0 480000000 0 0>, + <80000000 0 480000000 0 480000000 0 480000000 0 0>, + <80000000 0 480000000 0 480000000 0 480000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + src-clock-name = "ife_lite_csid_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_vfe_lite0: qcom,ife-lite0@acc6000 { + cell-index = <3>; + compatible = "qcom,vfe-lite680"; + reg-names = "ife-lite"; + reg = <0xacc6000 0x2800>; + reg-cam-base = <0xc6000>; + interrupt-names = "ife-lite"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + clock-names = + "cam_cc_slow_ahb_clk_src", + "ife_lite_ahb", + "ife_lite_csid_clk_src", + "ife_lite_csid_clk", + "ife_lite_cphy_rx_clk_src", + "ife_lite_cphy_rx_clk", + "ife_lite_clk_src", + "ife_lite_clk", + "cam_cc_cpas_ife_lite_clk"; + clocks = + <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK>, + <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&clock_camcc CAM_CC_IFE_LITE_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_LITE_CLK>, + <&clock_camcc CAM_CC_CPAS_IFE_LITE_CLK>; + clock-rates = + <80000000 0 400000000 0 400000000 0 400000000 0 0>, + <80000000 0 480000000 0 480000000 0 480000000 0 0>, + <80000000 0 480000000 0 480000000 0 480000000 0 0>, + <80000000 0 480000000 0 480000000 0 480000000 0 0>, + <80000000 0 480000000 0 480000000 0 480000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + src-clock-name = "ife_lite_clk_src"; + clock-control-debugfs = "true"; + cam_hw_pid = <0>; + status = "ok"; + }; + + cam_csid_lite1: qcom,csid-lite1@acca000 { + cell-index = <4>; + compatible = "qcom,csid-lite680"; + reg-names = "csid-lite"; + reg = <0xacca000 0xa00>; + reg-cam-base = <0xca000>; + interrupt-names = "csid-lite"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + clock-names = + "cam_cc_slow_ahb_clk_src", + "ife_lite_ahb", + "ife_lite_csid_clk_src", + "ife_lite_csid_clk", + "ife_lite_cphy_rx_clk_src", + "ife_lite_cphy_rx_clk", + "ife_lite_clk_src", + "ife_lite_clk", + "cam_cc_cpas_ife_lite_clk"; + clocks = + <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK>, + <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&clock_camcc CAM_CC_IFE_LITE_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_LITE_CLK>, + <&clock_camcc CAM_CC_CPAS_IFE_LITE_CLK>; + clock-rates = + <80000000 0 400000000 0 400000000 0 400000000 0 0>, + <80000000 0 480000000 0 480000000 0 480000000 0 0>, + <80000000 0 480000000 0 480000000 0 480000000 0 0>, + <80000000 0 480000000 0 480000000 0 480000000 0 0>, + <80000000 0 480000000 0 480000000 0 480000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + src-clock-name = "ife_lite_csid_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_vfe_lite1: qcom,ife-lite1@acca000 { + cell-index = <4>; + compatible = "qcom,vfe-lite680"; + reg-names = "ife-lite"; + reg = <0xacca000 0x2800>; + reg-cam-base = <0xca000>; + interrupt-names = "ife-lite"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + clock-names = + "cam_cc_slow_ahb_clk_src", + "ife_lite_ahb", + "ife_lite_csid_clk_src", + "ife_lite_csid_clk", + "ife_lite_cphy_rx_clk_src", + "ife_lite_cphy_rx_clk", + "ife_lite_clk_src", + "ife_lite_clk", + "cam_cc_cpas_ife_lite_clk"; + clocks = + <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_LITE_CSID_CLK>, + <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&clock_camcc CAM_CC_IFE_LITE_CLK_SRC>, + <&clock_camcc CAM_CC_IFE_LITE_CLK>, + <&clock_camcc CAM_CC_CPAS_IFE_LITE_CLK>; + clock-rates = + <80000000 0 400000000 0 400000000 0 400000000 0 0>, + <80000000 0 480000000 0 480000000 0 480000000 0 0>, + <80000000 0 480000000 0 480000000 0 480000000 0 0>, + <80000000 0 480000000 0 480000000 0 480000000 0 0>, + <80000000 0 480000000 0 480000000 0 480000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + src-clock-name = "ife_lite_clk_src"; + clock-control-debugfs = "true"; + cam_hw_pid = <1>; + status = "ok"; + }; + + cam_csiphy_tpg0: qcom,tpg0@acf6000 { + cell-index = <0>; + compatible = "qcom,tpg103"; + reg-names = "tpg0", "cam_cpas_top"; + reg = <0xacf6000 0x400>, + <0xac13000 0x1000>; + reg-cam-base = <0xf6000 0x13000>; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + interrupt-names = "tpg0"; + interrupts = ; + clock-names = + "cphy_rx_clk_src", + "csid_csiphy_rx_clk"; + clocks = + <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&clock_camcc CAM_CC_CSID_CSIPHY_RX_CLK>; + clock-rates = + <480000000 0>; + clock-cntl-level = "nominal"; + src-clock-name = "cphy_rx_clk_src"; + status = "ok"; + }; + + cam_csiphy_tpg1: qcom,tpg1@acf7000 { + cell-index = <1>; + compatible = "qcom,tpg103"; + reg-names = "tpg1", "cam_cpas_top"; + reg = <0xacf7000 0x400>, + <0xac13000 0x1000>; + reg-cam-base = <0xf7000 0x13000>; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + interrupt-names = "tpg1"; + interrupts = ; + clock-names = + "cphy_rx_clk_src", + "csid_csiphy_rx_clk"; + clocks = + <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&clock_camcc CAM_CC_CSID_CSIPHY_RX_CLK>; + clock-rates = + <480000000 0>; + clock-cntl-level = "nominal"; + src-clock-name = "cphy_rx_clk_src"; + status = "ok"; + }; + + cam_csiphy_tpg2: qcom,tpg2@acf8000 { + cell-index = <2>; + compatible = "qcom,tpg103"; + reg-names = "tpg2", "cam_cpas_top"; + reg = <0xacf8000 0x400>, + <0xac13000 0x1000>; + reg-cam-base = <0xf8000 0x13000>; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + interrupt-names = "tpg2"; + interrupts = ; + clock-names = + "cphy_rx_clk_src", + "csid_csiphy_rx_clk"; + clocks = + <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>, + <&clock_camcc CAM_CC_CSID_CSIPHY_RX_CLK>; + clock-rates = + <480000000 0>; + clock-cntl-level = "nominal"; + src-clock-name = "cphy_rx_clk_src"; + status = "ok"; + }; + + qcom,cam-icp { + compatible = "qcom,cam-icp"; + compat-hw-name = "qcom,lx7", + "qcom,ipe0", + "qcom,bps"; + num-lx7 = <1>; + num-ipe = <1>; + num-bps = <1>; + status = "ok"; + icp_pc_en; + ipe_bps_pc_en; + }; + + cam_lx7: qcom,lx7 { + cell-index = <0>; + compatible = "qcom,cam-lx7"; + reg = <0xac01000 0x400>, + <0xac01800 0x400>; + reg-names = "lx7_csr", "lx7_cirq"; + reg-cam-base = <0x1000 0x1800>; + interrupt-names = "lx7"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + clock-names = + "icp_clk_src", + "icp_clk"; + clocks = + <&clock_camcc CAM_CC_ICP_CLK_SRC>, + <&clock_camcc CAM_CC_ICP_CLK>; + clock-rates = + <400000000 0>, + <480000000 0>, + <600000000 0>, + <600000000 0>, + <600000000 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + src-clock-name = "icp_clk_src"; + fw_name = "CAMERA_ICP.elf"; + ubwc-ipe-fetch-cfg = <0x707b 0x7083>; + /* TO-DO write cfg redundant for BUS 2.0 architecture*/ + ubwc-ipe-write-cfg = <0x161ef 0x1620f>; + ubwc-bps-fetch-cfg = <0x707b 0x7083>; + /* TO-DO write cfg redundant for BUS 2.0 architecture*/ + ubwc-bps-write-cfg = <0x161ef 0x1620f>; + status = "ok"; + }; + + cam_ipe0: qcom,ipe0@ac42000 { + cell-index = <0>; + compatible = "qcom,cam-ipe"; + reg = <0xac42000 0x16000>; + reg-names = "ipe0_top"; + reg-cam-base = <0x42000>; + regulator-names = "gdsc", "ipe0-vdd"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + ipe0-vdd-supply = <&cam_cc_ipe_0_gdsc>; + clock-names = + "cam_cc_slow_ahb_clk_src", + "ipe_nps_ahb_clk", + "cam_cc_fast_ahb_clk_src", + "ipe_nps_fast_ahb_clk", + "ipe_pps_fast_ahb_clk", + "ipe_nps_clk_src", + "ipe_nps_clk"; + "ipe_pps_clk", + "cam_cc_cpas_ipe_nps_clk"; + clocks = + <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&clock_camcc CAM_CC_IPE_NPS_AHB_CLK>, + <&clock_camcc CAM_CC_FAST_AHB_CLK_SRC>, + <&clock_camcc CAM_CC_IPE_NPS_FAST_AHB_CLK>, + <&clock_camcc CAM_CC_IPE_PPS_FAST_AHB_CLK>, + <&clock_camcc CAM_CC_IPE_NPS_CLK_SRC>, + <&clock_camcc CAM_CC_IPE_NPS_CLK>, + <&clock_camcc CAM_CC_IPE_PPS_CLK>, + <&clock_camcc CAM_CC_CPAS_IPE_NPS_CLK>; + + clock-rates = + <80000000 0 100000000 0 0 364000000 0 0 0>, + <80000000 0 200000000 0 0 500000000 0 0 0>, + <80000000 0 300000000 0 0 600000000 0 0 0>, + <80000000 0 400000000 0 0 700000000 0 0 0>, + <80000000 0 400000000 0 0 700000000 0 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + src-clock-name = "ipe_nps_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; + + cam_bps: qcom,bps@ac2c000 { + cell-index = <0>; + compatible = "qcom,cam-bps"; + reg = <0xac2c000 0x7800>; + reg-names = "bps_top"; + reg-cam-base = <0x2c000>; + regulator-names = "gdsc", "bps-vdd"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + bps-vdd-supply = <&cam_cc_bps_gdsc>; + clock-names = + "cam_cc_slow_ahb_clk_src", + "bps_ahb_clk", + "cam_cc_fast_ahb_clk_src", + "bps_fast_ahb_clk", + "bps_clk_src", + "bps_clk", + "cam_cc_cpas_bps_clk"; + clocks = + <&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>, + <&clock_camcc CAM_CC_BPS_AHB_CLK>, + <&clock_camcc CAM_CC_FAST_AHB_CLK_SRC>, + <&clock_camcc CAM_CC_BPS_FAST_AHB_CLK>, + <&clock_camcc CAM_CC_BPS_CLK_SRC>, + <&clock_camcc CAM_CC_BPS_CLK>, + <&clock_camcc CAM_CC_CPAS_BPS_CLK>; + + clock-rates = + <80000000 0 100000000 0 200000000 0 0>, + <80000000 0 200000000 0 400000000 0 0>, + <80000000 0 300000000 0 480000000 0 0>, + <80000000 0 400000000 0 600000000 0 0>, + <80000000 0 400000000 0 600000000 0 0>; + clock-cntl-level = "lowsvs", "svs", "svs_l1", "nominal", + "turbo"; + src-clock-name = "bps_clk_src"; + clock-control-debugfs = "true"; + status = "ok"; + }; + + qcom,cam-jpeg { + compatible = "qcom,cam-jpeg"; + compat-hw-name = "qcom,jpegenc", + "qcom,jpegdma"; + num-jpeg-enc = <1>; + num-jpeg-dma = <1>; + status = "ok"; + }; + + cam_jpeg_enc: qcom,jpegenc@ac2a000 { + cell-index = <0>; + compatible = "qcom,cam_jpeg_enc"; + reg-names = "jpege_hw"; + reg = <0xac2a000 0x1000>; + reg-cam-base = <0x2a000>; + interrupt-names = "jpeg"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + clock-names = + "jpegenc_clk_src", + "jpegenc_clk"; + clocks = + <&clock_camcc CAM_CC_JPEG_CLK_SRC>, + <&clock_camcc CAM_CC_JPEG_CLK>; + clock-rates = <600000000 0>; + src-clock-name = "jpegenc_clk_src"; + clock-cntl-level = "nominal"; + status = "ok"; + }; + + cam_jpeg_dma: qcom,jpegdma@ac2b000 { + cell-index = <0>; + compatible = "qcom,cam_jpeg_dma"; + reg-names = "jpegdma_hw"; + reg = <0xac2b000 0x1000>; + reg-cam-base = <0x2b000>; + interrupt-names = "jpegdma"; + interrupts = ; + regulator-names = "gdsc"; + gdsc-supply = <&cam_cc_titan_top_gdsc>; + clock-names = + "jpegdma_clk_src", + "jpegdma_clk"; + clocks = + <&clock_camcc CAM_CC_JPEG_CLK_SRC>, + <&clock_camcc CAM_CC_JPEG_CLK>; + clock-rates = <600000000 0>; + src-clock-name = "jpegdma_clk_src"; + clock-cntl-level = "nominal"; + status = "ok"; + }; +};