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ARM: dts: qcom: Update A660 v2 supported power levels

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Include new power levels for A660 v2 and add the corresponding ddr votes.
Also include ACD control register configurations for ACD enabled levels.

Change-Id: I77278651a33917b521216d29f549a5ce86c943e8
This commit is contained in:
Mohammed Mirza Mandayappurath Manzoor 2020-08-17 11:11:11 -07:00
commit 07f670b043
1 changed files with 79 additions and 11 deletions
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90
qcom/lahaina-v2-gpu.dtsi
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@ -1,7 +1,7 @@
&msm_gpu {
qcom,chipid = <0x06060001>;
qcom,initial-pwrlevel = <5>;
qcom,initial-pwrlevel = <9>;
/* Power levels */
qcom,gpu-pwrlevels {
@ -12,6 +12,38 @@
qcom,gpu-pwrlevel@0 {
reg = <0>;
qcom,gpu-freq = <840000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
qcom,bus-freq-ddr7 = <11>;
qcom,bus-min-ddr7 = <11>;
qcom,bus-max-ddr7 = <11>;
qcom,bus-freq-ddr8 = <11>;
qcom,bus-min-ddr8 = <11>;
qcom,bus-max-ddr8 = <11>;
qcom,acd-level = <0x882c5ffd>;
};
qcom,gpu-pwrlevel@1 {
reg = <1>;
qcom,gpu-freq = <778000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
qcom,bus-freq-ddr7 = <11>;
qcom,bus-min-ddr7 = <11>;
qcom,bus-max-ddr7 = <11>;
qcom,bus-freq-ddr8 = <11>;
qcom,bus-min-ddr8 = <11>;
qcom,bus-max-ddr8 = <11>;
qcom,acd-level = <0xa82d5ffd>;
};
qcom,gpu-pwrlevel@2 {
reg = <2>;
qcom,gpu-freq = <738000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
@ -22,10 +54,12 @@
qcom,bus-freq-ddr8 = <11>;
qcom,bus-min-ddr8 = <11>;
qcom,bus-max-ddr8 = <11>;
qcom,acd-level = <0xa82d5ffd>;
};
qcom,gpu-pwrlevel@1 {
reg = <1>;
qcom,gpu-pwrlevel@3 {
reg = <3>;
qcom,gpu-freq = <676000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
@ -36,10 +70,12 @@
qcom,bus-freq-ddr8 = <10>;
qcom,bus-min-ddr8 = <10>;
qcom,bus-max-ddr8 = <11>;
qcom,acd-level = <0xa82c5ffd>;
};
qcom,gpu-pwrlevel@2 {
reg = <2>;
qcom,gpu-pwrlevel@4 {
reg = <4>;
qcom,gpu-freq = <608000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
@ -50,10 +86,12 @@
qcom,bus-freq-ddr8 = <7>;
qcom,bus-min-ddr8 = <7>;
qcom,bus-max-ddr8 = <11>;
qcom,acd-level = <0x882d5ffd>;
};
qcom,gpu-pwrlevel@3 {
reg = <3>;
qcom,gpu-pwrlevel@5 {
reg = <5>;
qcom,gpu-freq = <540000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
@ -64,10 +102,26 @@
qcom,bus-freq-ddr8 = <7>;
qcom,bus-min-ddr8 = <7>;
qcom,bus-max-ddr8 = <9>;
qcom,acd-level = <0xa82d5ffd>;
};
qcom,gpu-pwrlevel@4 {
reg = <4>;
qcom,gpu-pwrlevel@6 {
reg = <6>;
qcom,gpu-freq = <491000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
qcom,bus-freq-ddr7 = <8>;
qcom,bus-min-ddr7 = <6>;
qcom,bus-max-ddr7 = <10>;
qcom,bus-freq-ddr8 = <7>;
qcom,bus-min-ddr8 = <5>;
qcom,bus-max-ddr8 = <7>;
};
qcom,gpu-pwrlevel@7 {
reg = <7>;
qcom,gpu-freq = <443000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
@ -80,8 +134,22 @@
qcom,bus-max-ddr8 = <7>;
};
qcom,gpu-pwrlevel@5 {
reg = <5>;
qcom,gpu-pwrlevel@8 {
reg = <8>;
qcom,gpu-freq = <379000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
qcom,bus-freq-ddr7 = <8>;
qcom,bus-min-ddr7 = <6>;
qcom,bus-max-ddr7 = <10>;
qcom,bus-freq-ddr8 = <6>;
qcom,bus-min-ddr8 = <5>;
qcom,bus-max-ddr8 = <7>;
};
qcom,gpu-pwrlevel@9 {
reg = <9>;
qcom,gpu-freq = <315000000>;
qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;