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Merge branch 'master' into for-next

Browse source 
Fast-forwarded to current state of Linus' tree as there are patches to be
applied for files that didn't exist on the old branch.
This commit is contained in:
Jiri Kosina 2011-04-26 10:22:15 +02:00
commit 07f9479a40
6039 changed files with 191389 additions and 81783 deletions
Download patch file Download diff file Expand all files Collapse all files

6
arch/xtensa/Kconfig
View file

@ -7,6 +7,8 @@ config ZONE_DMA
config XTENSA
def_bool y
select HAVE_IDE
select HAVE_GENERIC_HARDIRQS
select GENERIC_IRQ_SHOW
help
Xtensa processors are 32-bit RISC machines designed by Tensilica
primarily for embedded systems. These processors are both
@ -21,10 +23,10 @@ config RWSEM_XCHGADD_ALGORITHM
config GENERIC_FIND_NEXT_BIT
def_bool y
config GENERIC_HWEIGHT
config GENERIC_FIND_BIT_LE
def_bool y
config GENERIC_HARDIRQS
config GENERIC_HWEIGHT
def_bool y
config GENERIC_GPIO

2
arch/xtensa/boot/Makefile
View file

@ -14,7 +14,7 @@ HOSTFLAGS += -Iarch/$(ARCH)/boot/include
BIG_ENDIAN := $(shell echo -e __XTENSA_EB__ | $(CC) -E - | grep -v "\#")
export EXTRA_CFLAGS
export ccflags-y
export BIG_ENDIAN
subdir-y := lib

2
arch/xtensa/boot/lib/Makefile
View file

@ -6,7 +6,7 @@ zlib := inffast.c inflate.c inftrees.c
lib-y += $(zlib:.c=.o) zmem.o
EXTRA_CFLAGS += -Ilib/zlib_inflate
ccflags-y := -Ilib/zlib_inflate
quiet_cmd_copy_zlib = COPY $@
cmd_copy_zlib = cat $< > $@

3
arch/xtensa/include/asm/bitops.h
View file

@ -106,7 +106,7 @@ static inline unsigned long __fls(unsigned long word)
#include <asm-generic/bitops/fls64.h>
#include <asm-generic/bitops/find.h>
#include <asm-generic/bitops/ext2-non-atomic.h>
#include <asm-generic/bitops/le.h>
#ifdef __XTENSA_EL__
# define ext2_set_bit_atomic(lock,nr,addr) \
@ -125,7 +125,6 @@ static inline unsigned long __fls(unsigned long word)
#include <asm-generic/bitops/hweight.h>
#include <asm-generic/bitops/lock.h>
#include <asm-generic/bitops/sched.h>
#include <asm-generic/bitops/minix.h>
#endif /* __KERNEL__ */

2
arch/xtensa/include/asm/dma.h
View file

@ -37,7 +37,7 @@
* the size of the statically mapped kernel segment
* (XCHAL_KSEG_{CACHED,BYPASS}_SIZE), ie. 128 MB.
*
* NOTE: When the entire KSEG area is DMA capable, we substract
* NOTE: When the entire KSEG area is DMA capable, we subtract
* one from the max address so that the virt_to_phys() macro
* works correctly on the address (otherwise the address
* enters another area, and virt_to_phys() may not return

4
arch/xtensa/include/asm/types.h
View file

@ -32,10 +32,6 @@ typedef unsigned short umode_t;
#define BITS_PER_LONG 32
/* Dma addresses are 32-bits wide. */
typedef u32 dma_addr_t;
#endif /* __KERNEL__ */
#endif

2
arch/xtensa/kernel/entry.S
View file

@ -1026,7 +1026,7 @@ ENTRY(fast_syscall_unrecoverable)
* TRY adds an entry to the __ex_table fixup table for the immediately
* following instruction.
*
* CATCH catches any exception that occurred at one of the preceeding TRY
* CATCH catches any exception that occurred at one of the preceding TRY
* statements and continues from there
*
* Usage TRY l32i a0, a1, 0

100
arch/xtensa/kernel/irq.c
View file

@ -35,7 +35,6 @@ atomic_t irq_err_count;
asmlinkage void do_IRQ(int irq, struct pt_regs *regs)
{
struct pt_regs *old_regs = set_irq_regs(regs);
struct irq_desc *desc = irq_desc + irq;
if (irq >= NR_IRQS) {
printk(KERN_EMERG "%s: cannot handle IRQ %d\n",
@ -57,104 +56,63 @@ asmlinkage void do_IRQ(int irq, struct pt_regs *regs)
sp - sizeof(struct thread_info));
}
#endif
desc->handle_irq(irq, desc);
generic_handle_irq(irq);
irq_exit();
set_irq_regs(old_regs);
}
/*
* Generic, controller-independent functions:
*/
int show_interrupts(struct seq_file *p, void *v)
int arch_show_interrupts(struct seq_file *p, int prec)
{
int i = *(loff_t *) v, j;
struct irqaction * action;
unsigned long flags;
if (i == 0) {
seq_printf(p, " ");
for_each_online_cpu(j)
seq_printf(p, "CPU%d ",j);
seq_putc(p, '\n');
}
if (i < NR_IRQS) {
raw_spin_lock_irqsave(&irq_desc[i].lock, flags);
action = irq_desc[i].action;
if (!action)
goto skip;
seq_printf(p, "%3d: ",i);
#ifndef CONFIG_SMP
seq_printf(p, "%10u ", kstat_irqs(i));
#else
for_each_online_cpu(j)
seq_printf(p, "%10u ", kstat_irqs_cpu(i, j));
#endif
seq_printf(p, " %14s", irq_desc[i].chip->name);
seq_printf(p, " %s", action->name);
for (action=action->next; action; action = action->next)
seq_printf(p, ", %s", action->name);
seq_putc(p, '\n');
skip:
raw_spin_unlock_irqrestore(&irq_desc[i].lock, flags);
} else if (i == NR_IRQS) {
seq_printf(p, "NMI: ");
for_each_online_cpu(j)
seq_printf(p, "%10u ", nmi_count(j));
seq_putc(p, '\n');
seq_printf(p, "ERR: %10u\n", atomic_read(&irq_err_count));
}
seq_printf(p, "%*s: ", prec, "ERR");
seq_printf(p, "%10u\n", atomic_read(&irq_err_count));
return 0;
}
static void xtensa_irq_mask(unsigned int irq)
static void xtensa_irq_mask(struct irq_data *d)
{
cached_irq_mask &= ~(1 << irq);
cached_irq_mask &= ~(1 << d->irq);
set_sr (cached_irq_mask, INTENABLE);
}
static void xtensa_irq_unmask(unsigned int irq)
static void xtensa_irq_unmask(struct irq_data *d)
{
cached_irq_mask |= 1 << irq;
cached_irq_mask |= 1 << d->irq;
set_sr (cached_irq_mask, INTENABLE);
}
static void xtensa_irq_enable(unsigned int irq)
static void xtensa_irq_enable(struct irq_data *d)
{
variant_irq_enable(irq);
xtensa_irq_unmask(irq);
variant_irq_enable(d->irq);
xtensa_irq_unmask(d->irq);
}
static void xtensa_irq_disable(unsigned int irq)
static void xtensa_irq_disable(struct irq_data *d)
{
xtensa_irq_mask(irq);
variant_irq_disable(irq);
xtensa_irq_mask(d->irq);
variant_irq_disable(d->irq);
}
static void xtensa_irq_ack(unsigned int irq)
static void xtensa_irq_ack(struct irq_data *d)
{
set_sr(1 << irq, INTCLEAR);
set_sr(1 << d->irq, INTCLEAR);
}
static int xtensa_irq_retrigger(unsigned int irq)
static int xtensa_irq_retrigger(struct irq_data *d)
{
set_sr (1 << irq, INTSET);
set_sr (1 << d->irq, INTSET);
return 1;
}
static struct irq_chip xtensa_irq_chip = {
.name = "xtensa",
.enable = xtensa_irq_enable,
.disable = xtensa_irq_disable,
.mask = xtensa_irq_mask,
.unmask = xtensa_irq_unmask,
.ack = xtensa_irq_ack,
.retrigger = xtensa_irq_retrigger,
.irq_enable = xtensa_irq_enable,
.irq_disable = xtensa_irq_disable,
.irq_mask = xtensa_irq_mask,
.irq_unmask = xtensa_irq_unmask,
.irq_ack = xtensa_irq_ack,
.irq_retrigger = xtensa_irq_retrigger,
};
void __init init_IRQ(void)
@ -165,25 +123,25 @@ void __init init_IRQ(void)
int mask = 1 << index;
if (mask & XCHAL_INTTYPE_MASK_SOFTWARE)
set_irq_chip_and_handler(index, &xtensa_irq_chip,
irq_set_chip_and_handler(index, &xtensa_irq_chip,
handle_simple_irq);
else if (mask & XCHAL_INTTYPE_MASK_EXTERN_EDGE)
set_irq_chip_and_handler(index, &xtensa_irq_chip,
irq_set_chip_and_handler(index, &xtensa_irq_chip,
handle_edge_irq);
else if (mask & XCHAL_INTTYPE_MASK_EXTERN_LEVEL)
set_irq_chip_and_handler(index, &xtensa_irq_chip,
irq_set_chip_and_handler(index, &xtensa_irq_chip,
handle_level_irq);
else if (mask & XCHAL_INTTYPE_MASK_TIMER)
set_irq_chip_and_handler(index, &xtensa_irq_chip,
irq_set_chip_and_handler(index, &xtensa_irq_chip,
handle_edge_irq);
else /* XCHAL_INTTYPE_MASK_WRITE_ERROR */
/* XCHAL_INTTYPE_MASK_NMI */
set_irq_chip_and_handler(index, &xtensa_irq_chip,
irq_set_chip_and_handler(index, &xtensa_irq_chip,
handle_level_irq);
}

2
arch/xtensa/platforms/s6105/device.c
View file

@ -120,7 +120,7 @@ static int __init prepare_phy_irq(int pin)
irq = gpio_to_irq(pin);
if (irq < 0)
goto free;
if (set_irq_type(irq, IRQ_TYPE_LEVEL_LOW) < 0)
if (irq_set_irq_type(irq, IRQ_TYPE_LEVEL_LOW) < 0)
goto free;
return irq;
free:

45
arch/xtensa/variants/s6000/gpio.c
View file

@ -85,30 +85,29 @@ int s6_gpio_init(u32 afsel)
return gpiochip_add(&gpiochip);
}
static void ack(unsigned int irq)
static void ack(struct irq_data *d)
{
writeb(1 << (irq - IRQ_BASE), S6_REG_GPIO + S6_GPIO_IC);
writeb(1 << (d->irq - IRQ_BASE), S6_REG_GPIO + S6_GPIO_IC);
}
static void mask(unsigned int irq)
static void mask(struct irq_data *d)
{
u8 r = readb(S6_REG_GPIO + S6_GPIO_IE);
r &= ~(1 << (irq - IRQ_BASE));
r &= ~(1 << (d->irq - IRQ_BASE));
writeb(r, S6_REG_GPIO + S6_GPIO_IE);
}
static void unmask(unsigned int irq)
static void unmask(struct irq_data *d)
{
u8 m = readb(S6_REG_GPIO + S6_GPIO_IE);
m |= 1 << (irq - IRQ_BASE);
m |= 1 << (d->irq - IRQ_BASE);
writeb(m, S6_REG_GPIO + S6_GPIO_IE);
}
static int set_type(unsigned int irq, unsigned int type)
static int set_type(struct irq_data *d, unsigned int type)
{
const u8 m = 1 << (irq - IRQ_BASE);
const u8 m = 1 << (d->irq - IRQ_BASE);
irq_flow_handler_t handler;
struct irq_desc *desc;
u8 reg;
if (type == IRQ_TYPE_PROBE) {
@ -129,8 +128,7 @@ static int set_type(unsigned int irq, unsigned int type)
handler = handle_edge_irq;
}
writeb(reg, S6_REG_GPIO + S6_GPIO_BANK(0) + S6_GPIO_IS);
desc = irq_to_desc(irq);
desc->handle_irq = handler;
__irq_set_handler_locked(irq, handler);
reg = readb(S6_REG_GPIO + S6_GPIO_BANK(0) + S6_GPIO_IEV);
if (type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_EDGE_RISING))
@ -150,22 +148,23 @@ static int set_type(unsigned int irq, unsigned int type)
static struct irq_chip gpioirqs = {
.name = "GPIO",
.ack = ack,
.mask = mask,
.unmask = unmask,
.set_type = set_type,
.irq_ack = ack,
.irq_mask = mask,
.irq_unmask = unmask,
.irq_set_type = set_type,
};
static u8 demux_masks[4];
static void demux_irqs(unsigned int irq, struct irq_desc *desc)
{
u8 *mask = get_irq_desc_data(desc);
struct irq_chip *chip = irq_desc_get_chip(desc);
u8 *mask = irq_desc_get_handler_data(desc);
u8 pending;
int cirq;
desc->chip->mask(irq);
desc->chip->ack(irq);
chip->irq_mask(&desc->irq_data);
chip->irq_ack(&desc->irq_data));
pending = readb(S6_REG_GPIO + S6_GPIO_BANK(0) + S6_GPIO_MIS) & *mask;
cirq = IRQ_BASE - 1;
while (pending) {
@ -174,7 +173,7 @@ static void demux_irqs(unsigned int irq, struct irq_desc *desc)
pending >>= n;
generic_handle_irq(cirq);
}
desc->chip->unmask(irq);
chip->irq_unmask(&desc->irq_data));
}
extern const signed char *platform_irq_mappings[XTENSA_NR_IRQS];
@ -219,11 +218,11 @@ void __init variant_init_irq(void)
i = ffs(mask);
cirq += i;
mask >>= i;
set_irq_chip(cirq, &gpioirqs);
set_irq_type(irq, IRQ_TYPE_LEVEL_LOW);
irq_set_chip(cirq, &gpioirqs);
irq_set_irq_type(irq, IRQ_TYPE_LEVEL_LOW);
} while (mask);
set_irq_data(irq, demux_masks + n);
set_irq_chained_handler(irq, demux_irqs);
irq_set_handler_data(irq, demux_masks + n);
irq_set_chained_handler(irq, demux_irqs);
if (++n == ARRAY_SIZE(demux_masks))
break;
}