mirror of
https://github.com/BobTheBlinker/android_kernel_motorola_sm6375.git
synced 2026-10-08 21:22:09 -04:00
fw-api: kiwi_v2: Hardware files required for TxMon
Hardware files required to support TxMon. Change-Id: I7af4347cf90d590a0ac5467bd142d3a49ef712cb CRs-Fixed: 2262693
This commit is contained in:
Srinivas Girigowda
Madan Koyyalamudi
parent
d5a1751a4f
commit
08105d291d
99 changed files with 24371 additions and 0 deletions
68
hw/kiwi/v2/ack_report.h
Normal file
68
hw/kiwi/v2/ack_report.h
Normal file
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@ -0,0 +1,68 @@
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/*
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* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
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||||
*
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||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef _ACK_REPORT_H_
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#define _ACK_REPORT_H_
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#if !defined(__ASSEMBLER__)
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#endif
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#define NUM_OF_DWORDS_ACK_REPORT 1
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struct ack_report {
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#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
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uint32_t selfgen_response_reason : 4,
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ax_trigger_type : 4,
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sr_ppdu : 1,
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reserved : 7,
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frame_control : 16;
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#else
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uint32_t frame_control : 16,
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reserved : 7,
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sr_ppdu : 1,
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ax_trigger_type : 4,
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selfgen_response_reason : 4;
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#endif
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};
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#define ACK_REPORT_SELFGEN_RESPONSE_REASON_OFFSET 0x00000000
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#define ACK_REPORT_SELFGEN_RESPONSE_REASON_LSB 0
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#define ACK_REPORT_SELFGEN_RESPONSE_REASON_MSB 3
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#define ACK_REPORT_SELFGEN_RESPONSE_REASON_MASK 0x0000000f
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#define ACK_REPORT_AX_TRIGGER_TYPE_OFFSET 0x00000000
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#define ACK_REPORT_AX_TRIGGER_TYPE_LSB 4
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#define ACK_REPORT_AX_TRIGGER_TYPE_MSB 7
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#define ACK_REPORT_AX_TRIGGER_TYPE_MASK 0x000000f0
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#define ACK_REPORT_SR_PPDU_OFFSET 0x00000000
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#define ACK_REPORT_SR_PPDU_LSB 8
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#define ACK_REPORT_SR_PPDU_MSB 8
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#define ACK_REPORT_SR_PPDU_MASK 0x00000100
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#define ACK_REPORT_RESERVED_OFFSET 0x00000000
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#define ACK_REPORT_RESERVED_LSB 9
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#define ACK_REPORT_RESERVED_MSB 15
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#define ACK_REPORT_RESERVED_MASK 0x0000fe00
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#define ACK_REPORT_FRAME_CONTROL_OFFSET 0x00000000
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#define ACK_REPORT_FRAME_CONTROL_LSB 16
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#define ACK_REPORT_FRAME_CONTROL_MSB 31
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#define ACK_REPORT_FRAME_CONTROL_MASK 0xffff0000
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#endif
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147
hw/kiwi/v2/coex_rx_status.h
Normal file
147
hw/kiwi/v2/coex_rx_status.h
Normal file
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@ -0,0 +1,147 @@
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/*
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* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
|
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* copyright notice and this permission notice appear in all copies.
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||||
*
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||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef _COEX_RX_STATUS_H_
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#define _COEX_RX_STATUS_H_
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#if !defined(__ASSEMBLER__)
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#endif
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#define NUM_OF_DWORDS_COEX_RX_STATUS 2
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#define NUM_OF_QWORDS_COEX_RX_STATUS 1
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struct coex_rx_status {
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#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
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uint32_t rx_mac_frame_status : 2,
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rx_with_tx_response : 1,
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rx_rate : 5,
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rx_bw : 3,
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single_mpdu : 1,
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filter_status : 1,
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ampdu : 1,
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directed : 1,
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reserved_0 : 1,
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rx_nss : 3,
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rx_rssi : 8,
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rx_type : 3,
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retry_bit_setting : 1,
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more_data_bit_setting : 1;
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uint32_t remain_rx_packet_time : 16,
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rx_remaining_fes_time : 16;
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#else
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uint32_t more_data_bit_setting : 1,
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retry_bit_setting : 1,
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rx_type : 3,
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rx_rssi : 8,
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rx_nss : 3,
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reserved_0 : 1,
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directed : 1,
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ampdu : 1,
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filter_status : 1,
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single_mpdu : 1,
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rx_bw : 3,
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rx_rate : 5,
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rx_with_tx_response : 1,
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rx_mac_frame_status : 2;
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uint32_t rx_remaining_fes_time : 16,
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remain_rx_packet_time : 16;
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#endif
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};
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#define COEX_RX_STATUS_RX_MAC_FRAME_STATUS_OFFSET 0x0000000000000000
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#define COEX_RX_STATUS_RX_MAC_FRAME_STATUS_LSB 0
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#define COEX_RX_STATUS_RX_MAC_FRAME_STATUS_MSB 1
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#define COEX_RX_STATUS_RX_MAC_FRAME_STATUS_MASK 0x0000000000000003
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#define COEX_RX_STATUS_RX_WITH_TX_RESPONSE_OFFSET 0x0000000000000000
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#define COEX_RX_STATUS_RX_WITH_TX_RESPONSE_LSB 2
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#define COEX_RX_STATUS_RX_WITH_TX_RESPONSE_MSB 2
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#define COEX_RX_STATUS_RX_WITH_TX_RESPONSE_MASK 0x0000000000000004
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#define COEX_RX_STATUS_RX_RATE_OFFSET 0x0000000000000000
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#define COEX_RX_STATUS_RX_RATE_LSB 3
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#define COEX_RX_STATUS_RX_RATE_MSB 7
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#define COEX_RX_STATUS_RX_RATE_MASK 0x00000000000000f8
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#define COEX_RX_STATUS_RX_BW_OFFSET 0x0000000000000000
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#define COEX_RX_STATUS_RX_BW_LSB 8
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#define COEX_RX_STATUS_RX_BW_MSB 10
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#define COEX_RX_STATUS_RX_BW_MASK 0x0000000000000700
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#define COEX_RX_STATUS_SINGLE_MPDU_OFFSET 0x0000000000000000
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#define COEX_RX_STATUS_SINGLE_MPDU_LSB 11
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#define COEX_RX_STATUS_SINGLE_MPDU_MSB 11
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#define COEX_RX_STATUS_SINGLE_MPDU_MASK 0x0000000000000800
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#define COEX_RX_STATUS_FILTER_STATUS_OFFSET 0x0000000000000000
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#define COEX_RX_STATUS_FILTER_STATUS_LSB 12
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#define COEX_RX_STATUS_FILTER_STATUS_MSB 12
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#define COEX_RX_STATUS_FILTER_STATUS_MASK 0x0000000000001000
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#define COEX_RX_STATUS_AMPDU_OFFSET 0x0000000000000000
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#define COEX_RX_STATUS_AMPDU_LSB 13
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#define COEX_RX_STATUS_AMPDU_MSB 13
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#define COEX_RX_STATUS_AMPDU_MASK 0x0000000000002000
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#define COEX_RX_STATUS_DIRECTED_OFFSET 0x0000000000000000
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#define COEX_RX_STATUS_DIRECTED_LSB 14
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#define COEX_RX_STATUS_DIRECTED_MSB 14
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#define COEX_RX_STATUS_DIRECTED_MASK 0x0000000000004000
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#define COEX_RX_STATUS_RESERVED_0_OFFSET 0x0000000000000000
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#define COEX_RX_STATUS_RESERVED_0_LSB 15
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#define COEX_RX_STATUS_RESERVED_0_MSB 15
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#define COEX_RX_STATUS_RESERVED_0_MASK 0x0000000000008000
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#define COEX_RX_STATUS_RX_NSS_OFFSET 0x0000000000000000
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#define COEX_RX_STATUS_RX_NSS_LSB 16
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#define COEX_RX_STATUS_RX_NSS_MSB 18
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#define COEX_RX_STATUS_RX_NSS_MASK 0x0000000000070000
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#define COEX_RX_STATUS_RX_RSSI_OFFSET 0x0000000000000000
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#define COEX_RX_STATUS_RX_RSSI_LSB 19
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#define COEX_RX_STATUS_RX_RSSI_MSB 26
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#define COEX_RX_STATUS_RX_RSSI_MASK 0x0000000007f80000
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#define COEX_RX_STATUS_RX_TYPE_OFFSET 0x0000000000000000
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#define COEX_RX_STATUS_RX_TYPE_LSB 27
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#define COEX_RX_STATUS_RX_TYPE_MSB 29
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#define COEX_RX_STATUS_RX_TYPE_MASK 0x0000000038000000
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#define COEX_RX_STATUS_RETRY_BIT_SETTING_OFFSET 0x0000000000000000
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#define COEX_RX_STATUS_RETRY_BIT_SETTING_LSB 30
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#define COEX_RX_STATUS_RETRY_BIT_SETTING_MSB 30
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#define COEX_RX_STATUS_RETRY_BIT_SETTING_MASK 0x0000000040000000
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#define COEX_RX_STATUS_MORE_DATA_BIT_SETTING_OFFSET 0x0000000000000000
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#define COEX_RX_STATUS_MORE_DATA_BIT_SETTING_LSB 31
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#define COEX_RX_STATUS_MORE_DATA_BIT_SETTING_MSB 31
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#define COEX_RX_STATUS_MORE_DATA_BIT_SETTING_MASK 0x0000000080000000
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#define COEX_RX_STATUS_REMAIN_RX_PACKET_TIME_OFFSET 0x0000000000000000
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#define COEX_RX_STATUS_REMAIN_RX_PACKET_TIME_LSB 32
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#define COEX_RX_STATUS_REMAIN_RX_PACKET_TIME_MSB 47
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#define COEX_RX_STATUS_REMAIN_RX_PACKET_TIME_MASK 0x0000ffff00000000
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#define COEX_RX_STATUS_RX_REMAINING_FES_TIME_OFFSET 0x0000000000000000
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#define COEX_RX_STATUS_RX_REMAINING_FES_TIME_LSB 48
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#define COEX_RX_STATUS_RX_REMAINING_FES_TIME_MSB 63
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#define COEX_RX_STATUS_RX_REMAINING_FES_TIME_MASK 0xffff000000000000
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#endif
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196
hw/kiwi/v2/coex_tx_req.h
Normal file
196
hw/kiwi/v2/coex_tx_req.h
Normal file
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@ -0,0 +1,196 @@
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/*
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* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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||||
*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef _COEX_TX_REQ_H_
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#define _COEX_TX_REQ_H_
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#if !defined(__ASSEMBLER__)
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#endif
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#define NUM_OF_DWORDS_COEX_TX_REQ 4
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#define NUM_OF_QWORDS_COEX_TX_REQ 2
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struct coex_tx_req {
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#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
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uint32_t tx_pwr : 8,
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min_tx_pwr : 8,
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nss : 3,
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tx_chain_mask : 8,
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bw : 3,
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reserved_0 : 2;
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uint32_t alt_tx_pwr : 8,
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alt_min_tx_pwr : 8,
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alt_nss : 3,
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alt_tx_chain_mask : 8,
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alt_bw : 3,
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reserved_1 : 2;
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uint32_t tx_pwr_1 : 8,
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alt_tx_pwr_1 : 8,
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wlan_request_duration : 16;
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uint32_t wlan_pkt_type : 4,
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coex_tx_reason : 2,
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response_frame_type : 5,
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wlan_low_priority_slicing_allowed : 1,
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wlan_high_priority_slicing_allowed : 1,
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sch_tx_burst_ongoing : 1,
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coex_tx_priority : 4,
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reserved_3a : 14;
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#else
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uint32_t reserved_0 : 2,
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bw : 3,
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tx_chain_mask : 8,
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nss : 3,
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min_tx_pwr : 8,
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tx_pwr : 8;
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uint32_t reserved_1 : 2,
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alt_bw : 3,
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alt_tx_chain_mask : 8,
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alt_nss : 3,
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alt_min_tx_pwr : 8,
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alt_tx_pwr : 8;
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uint32_t wlan_request_duration : 16,
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alt_tx_pwr_1 : 8,
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tx_pwr_1 : 8;
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uint32_t reserved_3a : 14,
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coex_tx_priority : 4,
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sch_tx_burst_ongoing : 1,
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wlan_high_priority_slicing_allowed : 1,
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wlan_low_priority_slicing_allowed : 1,
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response_frame_type : 5,
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coex_tx_reason : 2,
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wlan_pkt_type : 4;
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#endif
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};
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#define COEX_TX_REQ_TX_PWR_OFFSET 0x0000000000000000
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#define COEX_TX_REQ_TX_PWR_LSB 0
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#define COEX_TX_REQ_TX_PWR_MSB 7
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#define COEX_TX_REQ_TX_PWR_MASK 0x00000000000000ff
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#define COEX_TX_REQ_MIN_TX_PWR_OFFSET 0x0000000000000000
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#define COEX_TX_REQ_MIN_TX_PWR_LSB 8
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#define COEX_TX_REQ_MIN_TX_PWR_MSB 15
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#define COEX_TX_REQ_MIN_TX_PWR_MASK 0x000000000000ff00
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#define COEX_TX_REQ_NSS_OFFSET 0x0000000000000000
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#define COEX_TX_REQ_NSS_LSB 16
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#define COEX_TX_REQ_NSS_MSB 18
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#define COEX_TX_REQ_NSS_MASK 0x0000000000070000
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#define COEX_TX_REQ_TX_CHAIN_MASK_OFFSET 0x0000000000000000
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#define COEX_TX_REQ_TX_CHAIN_MASK_LSB 19
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#define COEX_TX_REQ_TX_CHAIN_MASK_MSB 26
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#define COEX_TX_REQ_TX_CHAIN_MASK_MASK 0x0000000007f80000
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#define COEX_TX_REQ_BW_OFFSET 0x0000000000000000
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#define COEX_TX_REQ_BW_LSB 27
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#define COEX_TX_REQ_BW_MSB 29
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#define COEX_TX_REQ_BW_MASK 0x0000000038000000
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#define COEX_TX_REQ_RESERVED_0_OFFSET 0x0000000000000000
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#define COEX_TX_REQ_RESERVED_0_LSB 30
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#define COEX_TX_REQ_RESERVED_0_MSB 31
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#define COEX_TX_REQ_RESERVED_0_MASK 0x00000000c0000000
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#define COEX_TX_REQ_ALT_TX_PWR_OFFSET 0x0000000000000000
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#define COEX_TX_REQ_ALT_TX_PWR_LSB 32
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#define COEX_TX_REQ_ALT_TX_PWR_MSB 39
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#define COEX_TX_REQ_ALT_TX_PWR_MASK 0x000000ff00000000
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#define COEX_TX_REQ_ALT_MIN_TX_PWR_OFFSET 0x0000000000000000
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#define COEX_TX_REQ_ALT_MIN_TX_PWR_LSB 40
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#define COEX_TX_REQ_ALT_MIN_TX_PWR_MSB 47
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#define COEX_TX_REQ_ALT_MIN_TX_PWR_MASK 0x0000ff0000000000
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#define COEX_TX_REQ_ALT_NSS_OFFSET 0x0000000000000000
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#define COEX_TX_REQ_ALT_NSS_LSB 48
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#define COEX_TX_REQ_ALT_NSS_MSB 50
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#define COEX_TX_REQ_ALT_NSS_MASK 0x0007000000000000
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#define COEX_TX_REQ_ALT_TX_CHAIN_MASK_OFFSET 0x0000000000000000
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#define COEX_TX_REQ_ALT_TX_CHAIN_MASK_LSB 51
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#define COEX_TX_REQ_ALT_TX_CHAIN_MASK_MSB 58
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#define COEX_TX_REQ_ALT_TX_CHAIN_MASK_MASK 0x07f8000000000000
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#define COEX_TX_REQ_ALT_BW_OFFSET 0x0000000000000000
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#define COEX_TX_REQ_ALT_BW_LSB 59
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#define COEX_TX_REQ_ALT_BW_MSB 61
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#define COEX_TX_REQ_ALT_BW_MASK 0x3800000000000000
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#define COEX_TX_REQ_RESERVED_1_OFFSET 0x0000000000000000
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#define COEX_TX_REQ_RESERVED_1_LSB 62
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#define COEX_TX_REQ_RESERVED_1_MSB 63
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#define COEX_TX_REQ_RESERVED_1_MASK 0xc000000000000000
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#define COEX_TX_REQ_TX_PWR_1_OFFSET 0x0000000000000008
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#define COEX_TX_REQ_TX_PWR_1_LSB 0
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#define COEX_TX_REQ_TX_PWR_1_MSB 7
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#define COEX_TX_REQ_TX_PWR_1_MASK 0x00000000000000ff
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#define COEX_TX_REQ_ALT_TX_PWR_1_OFFSET 0x0000000000000008
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#define COEX_TX_REQ_ALT_TX_PWR_1_LSB 8
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#define COEX_TX_REQ_ALT_TX_PWR_1_MSB 15
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#define COEX_TX_REQ_ALT_TX_PWR_1_MASK 0x000000000000ff00
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#define COEX_TX_REQ_WLAN_REQUEST_DURATION_OFFSET 0x0000000000000008
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#define COEX_TX_REQ_WLAN_REQUEST_DURATION_LSB 16
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#define COEX_TX_REQ_WLAN_REQUEST_DURATION_MSB 31
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#define COEX_TX_REQ_WLAN_REQUEST_DURATION_MASK 0x00000000ffff0000
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#define COEX_TX_REQ_WLAN_PKT_TYPE_OFFSET 0x0000000000000008
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#define COEX_TX_REQ_WLAN_PKT_TYPE_LSB 32
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#define COEX_TX_REQ_WLAN_PKT_TYPE_MSB 35
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#define COEX_TX_REQ_WLAN_PKT_TYPE_MASK 0x0000000f00000000
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#define COEX_TX_REQ_COEX_TX_REASON_OFFSET 0x0000000000000008
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#define COEX_TX_REQ_COEX_TX_REASON_LSB 36
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#define COEX_TX_REQ_COEX_TX_REASON_MSB 37
|
||||
#define COEX_TX_REQ_COEX_TX_REASON_MASK 0x0000003000000000
|
||||
|
||||
#define COEX_TX_REQ_RESPONSE_FRAME_TYPE_OFFSET 0x0000000000000008
|
||||
#define COEX_TX_REQ_RESPONSE_FRAME_TYPE_LSB 38
|
||||
#define COEX_TX_REQ_RESPONSE_FRAME_TYPE_MSB 42
|
||||
#define COEX_TX_REQ_RESPONSE_FRAME_TYPE_MASK 0x000007c000000000
|
||||
|
||||
#define COEX_TX_REQ_WLAN_LOW_PRIORITY_SLICING_ALLOWED_OFFSET 0x0000000000000008
|
||||
#define COEX_TX_REQ_WLAN_LOW_PRIORITY_SLICING_ALLOWED_LSB 43
|
||||
#define COEX_TX_REQ_WLAN_LOW_PRIORITY_SLICING_ALLOWED_MSB 43
|
||||
#define COEX_TX_REQ_WLAN_LOW_PRIORITY_SLICING_ALLOWED_MASK 0x0000080000000000
|
||||
|
||||
#define COEX_TX_REQ_WLAN_HIGH_PRIORITY_SLICING_ALLOWED_OFFSET 0x0000000000000008
|
||||
#define COEX_TX_REQ_WLAN_HIGH_PRIORITY_SLICING_ALLOWED_LSB 44
|
||||
#define COEX_TX_REQ_WLAN_HIGH_PRIORITY_SLICING_ALLOWED_MSB 44
|
||||
#define COEX_TX_REQ_WLAN_HIGH_PRIORITY_SLICING_ALLOWED_MASK 0x0000100000000000
|
||||
|
||||
#define COEX_TX_REQ_SCH_TX_BURST_ONGOING_OFFSET 0x0000000000000008
|
||||
#define COEX_TX_REQ_SCH_TX_BURST_ONGOING_LSB 45
|
||||
#define COEX_TX_REQ_SCH_TX_BURST_ONGOING_MSB 45
|
||||
#define COEX_TX_REQ_SCH_TX_BURST_ONGOING_MASK 0x0000200000000000
|
||||
|
||||
#define COEX_TX_REQ_COEX_TX_PRIORITY_OFFSET 0x0000000000000008
|
||||
#define COEX_TX_REQ_COEX_TX_PRIORITY_LSB 46
|
||||
#define COEX_TX_REQ_COEX_TX_PRIORITY_MSB 49
|
||||
#define COEX_TX_REQ_COEX_TX_PRIORITY_MASK 0x0003c00000000000
|
||||
|
||||
#define COEX_TX_REQ_RESERVED_3A_OFFSET 0x0000000000000008
|
||||
#define COEX_TX_REQ_RESERVED_3A_LSB 50
|
||||
#define COEX_TX_REQ_RESERVED_3A_MSB 63
|
||||
#define COEX_TX_REQ_RESERVED_3A_MASK 0xfffc000000000000
|
||||
|
||||
#endif
|
||||
133
hw/kiwi/v2/coex_tx_status.h
Normal file
133
hw/kiwi/v2/coex_tx_status.h
Normal file
|
|
@ -0,0 +1,133 @@
|
|||
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
#ifndef _COEX_TX_STATUS_H_
|
||||
#define _COEX_TX_STATUS_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#define NUM_OF_DWORDS_COEX_TX_STATUS 4
|
||||
|
||||
#define NUM_OF_QWORDS_COEX_TX_STATUS 2
|
||||
|
||||
struct coex_tx_status {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t reserved_0a : 7,
|
||||
tx_bw : 3,
|
||||
tx_status_reason : 3,
|
||||
tx_wait_ack : 1,
|
||||
fes_tx_is_gen_frame : 1,
|
||||
sch_tx_burst_ongoing : 1,
|
||||
current_tx_duration : 16;
|
||||
uint32_t next_rx_active_time : 16,
|
||||
remaining_fes_time : 16;
|
||||
uint32_t tx_antenna_mask : 8,
|
||||
shared_ant_tx_pwr : 8,
|
||||
other_ant_tx_pwr : 8,
|
||||
reserved_2 : 8;
|
||||
uint32_t tlv64_padding : 32;
|
||||
#else
|
||||
uint32_t current_tx_duration : 16,
|
||||
sch_tx_burst_ongoing : 1,
|
||||
fes_tx_is_gen_frame : 1,
|
||||
tx_wait_ack : 1,
|
||||
tx_status_reason : 3,
|
||||
tx_bw : 3,
|
||||
reserved_0a : 7;
|
||||
uint32_t remaining_fes_time : 16,
|
||||
next_rx_active_time : 16;
|
||||
uint32_t reserved_2 : 8,
|
||||
other_ant_tx_pwr : 8,
|
||||
shared_ant_tx_pwr : 8,
|
||||
tx_antenna_mask : 8;
|
||||
uint32_t tlv64_padding : 32;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define COEX_TX_STATUS_RESERVED_0A_OFFSET 0x0000000000000000
|
||||
#define COEX_TX_STATUS_RESERVED_0A_LSB 0
|
||||
#define COEX_TX_STATUS_RESERVED_0A_MSB 6
|
||||
#define COEX_TX_STATUS_RESERVED_0A_MASK 0x000000000000007f
|
||||
|
||||
#define COEX_TX_STATUS_TX_BW_OFFSET 0x0000000000000000
|
||||
#define COEX_TX_STATUS_TX_BW_LSB 7
|
||||
#define COEX_TX_STATUS_TX_BW_MSB 9
|
||||
#define COEX_TX_STATUS_TX_BW_MASK 0x0000000000000380
|
||||
|
||||
#define COEX_TX_STATUS_TX_STATUS_REASON_OFFSET 0x0000000000000000
|
||||
#define COEX_TX_STATUS_TX_STATUS_REASON_LSB 10
|
||||
#define COEX_TX_STATUS_TX_STATUS_REASON_MSB 12
|
||||
#define COEX_TX_STATUS_TX_STATUS_REASON_MASK 0x0000000000001c00
|
||||
|
||||
#define COEX_TX_STATUS_TX_WAIT_ACK_OFFSET 0x0000000000000000
|
||||
#define COEX_TX_STATUS_TX_WAIT_ACK_LSB 13
|
||||
#define COEX_TX_STATUS_TX_WAIT_ACK_MSB 13
|
||||
#define COEX_TX_STATUS_TX_WAIT_ACK_MASK 0x0000000000002000
|
||||
|
||||
#define COEX_TX_STATUS_FES_TX_IS_GEN_FRAME_OFFSET 0x0000000000000000
|
||||
#define COEX_TX_STATUS_FES_TX_IS_GEN_FRAME_LSB 14
|
||||
#define COEX_TX_STATUS_FES_TX_IS_GEN_FRAME_MSB 14
|
||||
#define COEX_TX_STATUS_FES_TX_IS_GEN_FRAME_MASK 0x0000000000004000
|
||||
|
||||
#define COEX_TX_STATUS_SCH_TX_BURST_ONGOING_OFFSET 0x0000000000000000
|
||||
#define COEX_TX_STATUS_SCH_TX_BURST_ONGOING_LSB 15
|
||||
#define COEX_TX_STATUS_SCH_TX_BURST_ONGOING_MSB 15
|
||||
#define COEX_TX_STATUS_SCH_TX_BURST_ONGOING_MASK 0x0000000000008000
|
||||
|
||||
#define COEX_TX_STATUS_CURRENT_TX_DURATION_OFFSET 0x0000000000000000
|
||||
#define COEX_TX_STATUS_CURRENT_TX_DURATION_LSB 16
|
||||
#define COEX_TX_STATUS_CURRENT_TX_DURATION_MSB 31
|
||||
#define COEX_TX_STATUS_CURRENT_TX_DURATION_MASK 0x00000000ffff0000
|
||||
|
||||
#define COEX_TX_STATUS_NEXT_RX_ACTIVE_TIME_OFFSET 0x0000000000000000
|
||||
#define COEX_TX_STATUS_NEXT_RX_ACTIVE_TIME_LSB 32
|
||||
#define COEX_TX_STATUS_NEXT_RX_ACTIVE_TIME_MSB 47
|
||||
#define COEX_TX_STATUS_NEXT_RX_ACTIVE_TIME_MASK 0x0000ffff00000000
|
||||
|
||||
#define COEX_TX_STATUS_REMAINING_FES_TIME_OFFSET 0x0000000000000000
|
||||
#define COEX_TX_STATUS_REMAINING_FES_TIME_LSB 48
|
||||
#define COEX_TX_STATUS_REMAINING_FES_TIME_MSB 63
|
||||
#define COEX_TX_STATUS_REMAINING_FES_TIME_MASK 0xffff000000000000
|
||||
|
||||
#define COEX_TX_STATUS_TX_ANTENNA_MASK_OFFSET 0x0000000000000008
|
||||
#define COEX_TX_STATUS_TX_ANTENNA_MASK_LSB 0
|
||||
#define COEX_TX_STATUS_TX_ANTENNA_MASK_MSB 7
|
||||
#define COEX_TX_STATUS_TX_ANTENNA_MASK_MASK 0x00000000000000ff
|
||||
|
||||
#define COEX_TX_STATUS_SHARED_ANT_TX_PWR_OFFSET 0x0000000000000008
|
||||
#define COEX_TX_STATUS_SHARED_ANT_TX_PWR_LSB 8
|
||||
#define COEX_TX_STATUS_SHARED_ANT_TX_PWR_MSB 15
|
||||
#define COEX_TX_STATUS_SHARED_ANT_TX_PWR_MASK 0x000000000000ff00
|
||||
|
||||
#define COEX_TX_STATUS_OTHER_ANT_TX_PWR_OFFSET 0x0000000000000008
|
||||
#define COEX_TX_STATUS_OTHER_ANT_TX_PWR_LSB 16
|
||||
#define COEX_TX_STATUS_OTHER_ANT_TX_PWR_MSB 23
|
||||
#define COEX_TX_STATUS_OTHER_ANT_TX_PWR_MASK 0x0000000000ff0000
|
||||
|
||||
#define COEX_TX_STATUS_RESERVED_2_OFFSET 0x0000000000000008
|
||||
#define COEX_TX_STATUS_RESERVED_2_LSB 24
|
||||
#define COEX_TX_STATUS_RESERVED_2_MSB 31
|
||||
#define COEX_TX_STATUS_RESERVED_2_MASK 0x00000000ff000000
|
||||
|
||||
#define COEX_TX_STATUS_TLV64_PADDING_OFFSET 0x0000000000000008
|
||||
#define COEX_TX_STATUS_TLV64_PADDING_LSB 32
|
||||
#define COEX_TX_STATUS_TLV64_PADDING_MSB 63
|
||||
#define COEX_TX_STATUS_TLV64_PADDING_MASK 0xffffffff00000000
|
||||
|
||||
#endif
|
||||
110
hw/kiwi/v2/eht_sig_usr_mu_mimo_info.h
Normal file
110
hw/kiwi/v2/eht_sig_usr_mu_mimo_info.h
Normal file
|
|
@ -0,0 +1,110 @@
|
|||
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
#ifndef _EHT_SIG_USR_MU_MIMO_INFO_H_
|
||||
#define _EHT_SIG_USR_MU_MIMO_INFO_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#define NUM_OF_DWORDS_EHT_SIG_USR_MU_MIMO_INFO 2
|
||||
|
||||
struct eht_sig_usr_mu_mimo_info {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t sta_id : 11,
|
||||
sta_mcs : 4,
|
||||
sta_coding : 1,
|
||||
sta_spatial_config : 6,
|
||||
reserved_0a : 1,
|
||||
rx_integrity_check_passed : 1,
|
||||
subband80_cc_mask : 8;
|
||||
uint32_t user_order_subband80_0 : 8,
|
||||
user_order_subband80_1 : 8,
|
||||
user_order_subband80_2 : 8,
|
||||
user_order_subband80_3 : 8;
|
||||
#else
|
||||
uint32_t subband80_cc_mask : 8,
|
||||
rx_integrity_check_passed : 1,
|
||||
reserved_0a : 1,
|
||||
sta_spatial_config : 6,
|
||||
sta_coding : 1,
|
||||
sta_mcs : 4,
|
||||
sta_id : 11;
|
||||
uint32_t user_order_subband80_3 : 8,
|
||||
user_order_subband80_2 : 8,
|
||||
user_order_subband80_1 : 8,
|
||||
user_order_subband80_0 : 8;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_STA_ID_OFFSET 0x00000000
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_STA_ID_LSB 0
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_STA_ID_MSB 10
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_STA_ID_MASK 0x000007ff
|
||||
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_STA_MCS_OFFSET 0x00000000
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_STA_MCS_LSB 11
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_STA_MCS_MSB 14
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_STA_MCS_MASK 0x00007800
|
||||
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_STA_CODING_OFFSET 0x00000000
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_STA_CODING_LSB 15
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_STA_CODING_MSB 15
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_STA_CODING_MASK 0x00008000
|
||||
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_STA_SPATIAL_CONFIG_OFFSET 0x00000000
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_STA_SPATIAL_CONFIG_LSB 16
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_STA_SPATIAL_CONFIG_MSB 21
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_STA_SPATIAL_CONFIG_MASK 0x003f0000
|
||||
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_RESERVED_0A_OFFSET 0x00000000
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_RESERVED_0A_LSB 22
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_RESERVED_0A_MSB 22
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_RESERVED_0A_MASK 0x00400000
|
||||
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 23
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 23
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x00800000
|
||||
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_SUBBAND80_CC_MASK_OFFSET 0x00000000
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_SUBBAND80_CC_MASK_LSB 24
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_SUBBAND80_CC_MASK_MSB 31
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_SUBBAND80_CC_MASK_MASK 0xff000000
|
||||
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_0_OFFSET 0x00000004
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_0_LSB 0
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_0_MSB 7
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_0_MASK 0x000000ff
|
||||
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_1_OFFSET 0x00000004
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_1_LSB 8
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_1_MSB 15
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_1_MASK 0x0000ff00
|
||||
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_2_OFFSET 0x00000004
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_2_LSB 16
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_2_MSB 23
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_2_MASK 0x00ff0000
|
||||
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_3_OFFSET 0x00000004
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_3_LSB 24
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_3_MSB 31
|
||||
#define EHT_SIG_USR_MU_MIMO_INFO_USER_ORDER_SUBBAND80_3_MASK 0xff000000
|
||||
|
||||
#endif
|
||||
124
hw/kiwi/v2/eht_sig_usr_ofdma_info.h
Normal file
124
hw/kiwi/v2/eht_sig_usr_ofdma_info.h
Normal file
|
|
@ -0,0 +1,124 @@
|
|||
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
#ifndef _EHT_SIG_USR_OFDMA_INFO_H_
|
||||
#define _EHT_SIG_USR_OFDMA_INFO_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#define NUM_OF_DWORDS_EHT_SIG_USR_OFDMA_INFO 2
|
||||
|
||||
struct eht_sig_usr_ofdma_info {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t sta_id : 11,
|
||||
sta_mcs : 4,
|
||||
validate_0a : 1,
|
||||
nss : 4,
|
||||
txbf : 1,
|
||||
sta_coding : 1,
|
||||
reserved_0b : 1,
|
||||
rx_integrity_check_passed : 1,
|
||||
subband80_cc_mask : 8;
|
||||
uint32_t user_order_subband80_0 : 8,
|
||||
user_order_subband80_1 : 8,
|
||||
user_order_subband80_2 : 8,
|
||||
user_order_subband80_3 : 8;
|
||||
#else
|
||||
uint32_t subband80_cc_mask : 8,
|
||||
rx_integrity_check_passed : 1,
|
||||
reserved_0b : 1,
|
||||
sta_coding : 1,
|
||||
txbf : 1,
|
||||
nss : 4,
|
||||
validate_0a : 1,
|
||||
sta_mcs : 4,
|
||||
sta_id : 11;
|
||||
uint32_t user_order_subband80_3 : 8,
|
||||
user_order_subband80_2 : 8,
|
||||
user_order_subband80_1 : 8,
|
||||
user_order_subband80_0 : 8;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define EHT_SIG_USR_OFDMA_INFO_STA_ID_OFFSET 0x00000000
|
||||
#define EHT_SIG_USR_OFDMA_INFO_STA_ID_LSB 0
|
||||
#define EHT_SIG_USR_OFDMA_INFO_STA_ID_MSB 10
|
||||
#define EHT_SIG_USR_OFDMA_INFO_STA_ID_MASK 0x000007ff
|
||||
|
||||
#define EHT_SIG_USR_OFDMA_INFO_STA_MCS_OFFSET 0x00000000
|
||||
#define EHT_SIG_USR_OFDMA_INFO_STA_MCS_LSB 11
|
||||
#define EHT_SIG_USR_OFDMA_INFO_STA_MCS_MSB 14
|
||||
#define EHT_SIG_USR_OFDMA_INFO_STA_MCS_MASK 0x00007800
|
||||
|
||||
#define EHT_SIG_USR_OFDMA_INFO_VALIDATE_0A_OFFSET 0x00000000
|
||||
#define EHT_SIG_USR_OFDMA_INFO_VALIDATE_0A_LSB 15
|
||||
#define EHT_SIG_USR_OFDMA_INFO_VALIDATE_0A_MSB 15
|
||||
#define EHT_SIG_USR_OFDMA_INFO_VALIDATE_0A_MASK 0x00008000
|
||||
|
||||
#define EHT_SIG_USR_OFDMA_INFO_NSS_OFFSET 0x00000000
|
||||
#define EHT_SIG_USR_OFDMA_INFO_NSS_LSB 16
|
||||
#define EHT_SIG_USR_OFDMA_INFO_NSS_MSB 19
|
||||
#define EHT_SIG_USR_OFDMA_INFO_NSS_MASK 0x000f0000
|
||||
|
||||
#define EHT_SIG_USR_OFDMA_INFO_TXBF_OFFSET 0x00000000
|
||||
#define EHT_SIG_USR_OFDMA_INFO_TXBF_LSB 20
|
||||
#define EHT_SIG_USR_OFDMA_INFO_TXBF_MSB 20
|
||||
#define EHT_SIG_USR_OFDMA_INFO_TXBF_MASK 0x00100000
|
||||
|
||||
#define EHT_SIG_USR_OFDMA_INFO_STA_CODING_OFFSET 0x00000000
|
||||
#define EHT_SIG_USR_OFDMA_INFO_STA_CODING_LSB 21
|
||||
#define EHT_SIG_USR_OFDMA_INFO_STA_CODING_MSB 21
|
||||
#define EHT_SIG_USR_OFDMA_INFO_STA_CODING_MASK 0x00200000
|
||||
|
||||
#define EHT_SIG_USR_OFDMA_INFO_RESERVED_0B_OFFSET 0x00000000
|
||||
#define EHT_SIG_USR_OFDMA_INFO_RESERVED_0B_LSB 22
|
||||
#define EHT_SIG_USR_OFDMA_INFO_RESERVED_0B_MSB 22
|
||||
#define EHT_SIG_USR_OFDMA_INFO_RESERVED_0B_MASK 0x00400000
|
||||
|
||||
#define EHT_SIG_USR_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000
|
||||
#define EHT_SIG_USR_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 23
|
||||
#define EHT_SIG_USR_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 23
|
||||
#define EHT_SIG_USR_OFDMA_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x00800000
|
||||
|
||||
#define EHT_SIG_USR_OFDMA_INFO_SUBBAND80_CC_MASK_OFFSET 0x00000000
|
||||
#define EHT_SIG_USR_OFDMA_INFO_SUBBAND80_CC_MASK_LSB 24
|
||||
#define EHT_SIG_USR_OFDMA_INFO_SUBBAND80_CC_MASK_MSB 31
|
||||
#define EHT_SIG_USR_OFDMA_INFO_SUBBAND80_CC_MASK_MASK 0xff000000
|
||||
|
||||
#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_0_OFFSET 0x00000004
|
||||
#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_0_LSB 0
|
||||
#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_0_MSB 7
|
||||
#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_0_MASK 0x000000ff
|
||||
|
||||
#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_1_OFFSET 0x00000004
|
||||
#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_1_LSB 8
|
||||
#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_1_MSB 15
|
||||
#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_1_MASK 0x0000ff00
|
||||
|
||||
#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_2_OFFSET 0x00000004
|
||||
#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_2_LSB 16
|
||||
#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_2_MSB 23
|
||||
#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_2_MASK 0x00ff0000
|
||||
|
||||
#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_3_OFFSET 0x00000004
|
||||
#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_3_LSB 24
|
||||
#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_3_MSB 31
|
||||
#define EHT_SIG_USR_OFDMA_INFO_USER_ORDER_SUBBAND80_3_MASK 0xff000000
|
||||
|
||||
#endif
|
||||
89
hw/kiwi/v2/eht_sig_usr_su_info.h
Normal file
89
hw/kiwi/v2/eht_sig_usr_su_info.h
Normal file
|
|
@ -0,0 +1,89 @@
|
|||
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
#ifndef _EHT_SIG_USR_SU_INFO_H_
|
||||
#define _EHT_SIG_USR_SU_INFO_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#define NUM_OF_DWORDS_EHT_SIG_USR_SU_INFO 1
|
||||
|
||||
struct eht_sig_usr_su_info {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t sta_id : 11,
|
||||
sta_mcs : 4,
|
||||
validate_0a : 1,
|
||||
nss : 4,
|
||||
txbf : 1,
|
||||
sta_coding : 1,
|
||||
reserved_0b : 9,
|
||||
rx_integrity_check_passed : 1;
|
||||
#else
|
||||
uint32_t rx_integrity_check_passed : 1,
|
||||
reserved_0b : 9,
|
||||
sta_coding : 1,
|
||||
txbf : 1,
|
||||
nss : 4,
|
||||
validate_0a : 1,
|
||||
sta_mcs : 4,
|
||||
sta_id : 11;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define EHT_SIG_USR_SU_INFO_STA_ID_OFFSET 0x00000000
|
||||
#define EHT_SIG_USR_SU_INFO_STA_ID_LSB 0
|
||||
#define EHT_SIG_USR_SU_INFO_STA_ID_MSB 10
|
||||
#define EHT_SIG_USR_SU_INFO_STA_ID_MASK 0x000007ff
|
||||
|
||||
#define EHT_SIG_USR_SU_INFO_STA_MCS_OFFSET 0x00000000
|
||||
#define EHT_SIG_USR_SU_INFO_STA_MCS_LSB 11
|
||||
#define EHT_SIG_USR_SU_INFO_STA_MCS_MSB 14
|
||||
#define EHT_SIG_USR_SU_INFO_STA_MCS_MASK 0x00007800
|
||||
|
||||
#define EHT_SIG_USR_SU_INFO_VALIDATE_0A_OFFSET 0x00000000
|
||||
#define EHT_SIG_USR_SU_INFO_VALIDATE_0A_LSB 15
|
||||
#define EHT_SIG_USR_SU_INFO_VALIDATE_0A_MSB 15
|
||||
#define EHT_SIG_USR_SU_INFO_VALIDATE_0A_MASK 0x00008000
|
||||
|
||||
#define EHT_SIG_USR_SU_INFO_NSS_OFFSET 0x00000000
|
||||
#define EHT_SIG_USR_SU_INFO_NSS_LSB 16
|
||||
#define EHT_SIG_USR_SU_INFO_NSS_MSB 19
|
||||
#define EHT_SIG_USR_SU_INFO_NSS_MASK 0x000f0000
|
||||
|
||||
#define EHT_SIG_USR_SU_INFO_TXBF_OFFSET 0x00000000
|
||||
#define EHT_SIG_USR_SU_INFO_TXBF_LSB 20
|
||||
#define EHT_SIG_USR_SU_INFO_TXBF_MSB 20
|
||||
#define EHT_SIG_USR_SU_INFO_TXBF_MASK 0x00100000
|
||||
|
||||
#define EHT_SIG_USR_SU_INFO_STA_CODING_OFFSET 0x00000000
|
||||
#define EHT_SIG_USR_SU_INFO_STA_CODING_LSB 21
|
||||
#define EHT_SIG_USR_SU_INFO_STA_CODING_MSB 21
|
||||
#define EHT_SIG_USR_SU_INFO_STA_CODING_MASK 0x00200000
|
||||
|
||||
#define EHT_SIG_USR_SU_INFO_RESERVED_0B_OFFSET 0x00000000
|
||||
#define EHT_SIG_USR_SU_INFO_RESERVED_0B_LSB 22
|
||||
#define EHT_SIG_USR_SU_INFO_RESERVED_0B_MSB 30
|
||||
#define EHT_SIG_USR_SU_INFO_RESERVED_0B_MASK 0x7fc00000
|
||||
|
||||
#define EHT_SIG_USR_SU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000000
|
||||
#define EHT_SIG_USR_SU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31
|
||||
#define EHT_SIG_USR_SU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31
|
||||
#define EHT_SIG_USR_SU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
|
||||
|
||||
#endif
|
||||
217
hw/kiwi/v2/expected_response.h
Normal file
217
hw/kiwi/v2/expected_response.h
Normal file
|
|
@ -0,0 +1,217 @@
|
|||
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
#ifndef _EXPECTED_RESPONSE_H_
|
||||
#define _EXPECTED_RESPONSE_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#define NUM_OF_DWORDS_EXPECTED_RESPONSE 6
|
||||
|
||||
#define NUM_OF_QWORDS_EXPECTED_RESPONSE 3
|
||||
|
||||
struct expected_response {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t tx_ad2_31_0 : 32;
|
||||
uint32_t tx_ad2_47_32 : 16,
|
||||
expected_response_type : 5,
|
||||
response_to_response : 3,
|
||||
su_ba_user_number : 1,
|
||||
response_info_part2_required : 1,
|
||||
transmitted_bssid_check_en : 1,
|
||||
reserved_1 : 5;
|
||||
uint32_t ndp_sta_partial_aid_2_8_0 : 11,
|
||||
reserved_2 : 10,
|
||||
ndp_sta_partial_aid1_8_0 : 11;
|
||||
uint32_t ast_index : 16,
|
||||
capture_ack_ba_sounding : 1,
|
||||
capture_sounding_1str_20mhz : 1,
|
||||
capture_sounding_1str_40mhz : 1,
|
||||
capture_sounding_1str_80mhz : 1,
|
||||
capture_sounding_1str_160mhz : 1,
|
||||
capture_sounding_1str_240mhz : 1,
|
||||
capture_sounding_1str_320mhz : 1,
|
||||
reserved_3a : 9;
|
||||
uint32_t fcs : 9,
|
||||
reserved_4a : 1,
|
||||
crc : 4,
|
||||
scrambler_seed : 7,
|
||||
reserved_4b : 11;
|
||||
uint32_t tlv64_padding : 32;
|
||||
#else
|
||||
uint32_t tx_ad2_31_0 : 32;
|
||||
uint32_t reserved_1 : 5,
|
||||
transmitted_bssid_check_en : 1,
|
||||
response_info_part2_required : 1,
|
||||
su_ba_user_number : 1,
|
||||
response_to_response : 3,
|
||||
expected_response_type : 5,
|
||||
tx_ad2_47_32 : 16;
|
||||
uint32_t ndp_sta_partial_aid1_8_0 : 11,
|
||||
reserved_2 : 10,
|
||||
ndp_sta_partial_aid_2_8_0 : 11;
|
||||
uint32_t reserved_3a : 9,
|
||||
capture_sounding_1str_320mhz : 1,
|
||||
capture_sounding_1str_240mhz : 1,
|
||||
capture_sounding_1str_160mhz : 1,
|
||||
capture_sounding_1str_80mhz : 1,
|
||||
capture_sounding_1str_40mhz : 1,
|
||||
capture_sounding_1str_20mhz : 1,
|
||||
capture_ack_ba_sounding : 1,
|
||||
ast_index : 16;
|
||||
uint32_t reserved_4b : 11,
|
||||
scrambler_seed : 7,
|
||||
crc : 4,
|
||||
reserved_4a : 1,
|
||||
fcs : 9;
|
||||
uint32_t tlv64_padding : 32;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define EXPECTED_RESPONSE_TX_AD2_31_0_OFFSET 0x0000000000000000
|
||||
#define EXPECTED_RESPONSE_TX_AD2_31_0_LSB 0
|
||||
#define EXPECTED_RESPONSE_TX_AD2_31_0_MSB 31
|
||||
#define EXPECTED_RESPONSE_TX_AD2_31_0_MASK 0x00000000ffffffff
|
||||
|
||||
#define EXPECTED_RESPONSE_TX_AD2_47_32_OFFSET 0x0000000000000000
|
||||
#define EXPECTED_RESPONSE_TX_AD2_47_32_LSB 32
|
||||
#define EXPECTED_RESPONSE_TX_AD2_47_32_MSB 47
|
||||
#define EXPECTED_RESPONSE_TX_AD2_47_32_MASK 0x0000ffff00000000
|
||||
|
||||
#define EXPECTED_RESPONSE_EXPECTED_RESPONSE_TYPE_OFFSET 0x0000000000000000
|
||||
#define EXPECTED_RESPONSE_EXPECTED_RESPONSE_TYPE_LSB 48
|
||||
#define EXPECTED_RESPONSE_EXPECTED_RESPONSE_TYPE_MSB 52
|
||||
#define EXPECTED_RESPONSE_EXPECTED_RESPONSE_TYPE_MASK 0x001f000000000000
|
||||
|
||||
#define EXPECTED_RESPONSE_RESPONSE_TO_RESPONSE_OFFSET 0x0000000000000000
|
||||
#define EXPECTED_RESPONSE_RESPONSE_TO_RESPONSE_LSB 53
|
||||
#define EXPECTED_RESPONSE_RESPONSE_TO_RESPONSE_MSB 55
|
||||
#define EXPECTED_RESPONSE_RESPONSE_TO_RESPONSE_MASK 0x00e0000000000000
|
||||
|
||||
#define EXPECTED_RESPONSE_SU_BA_USER_NUMBER_OFFSET 0x0000000000000000
|
||||
#define EXPECTED_RESPONSE_SU_BA_USER_NUMBER_LSB 56
|
||||
#define EXPECTED_RESPONSE_SU_BA_USER_NUMBER_MSB 56
|
||||
#define EXPECTED_RESPONSE_SU_BA_USER_NUMBER_MASK 0x0100000000000000
|
||||
|
||||
#define EXPECTED_RESPONSE_RESPONSE_INFO_PART2_REQUIRED_OFFSET 0x0000000000000000
|
||||
#define EXPECTED_RESPONSE_RESPONSE_INFO_PART2_REQUIRED_LSB 57
|
||||
#define EXPECTED_RESPONSE_RESPONSE_INFO_PART2_REQUIRED_MSB 57
|
||||
#define EXPECTED_RESPONSE_RESPONSE_INFO_PART2_REQUIRED_MASK 0x0200000000000000
|
||||
|
||||
#define EXPECTED_RESPONSE_TRANSMITTED_BSSID_CHECK_EN_OFFSET 0x0000000000000000
|
||||
#define EXPECTED_RESPONSE_TRANSMITTED_BSSID_CHECK_EN_LSB 58
|
||||
#define EXPECTED_RESPONSE_TRANSMITTED_BSSID_CHECK_EN_MSB 58
|
||||
#define EXPECTED_RESPONSE_TRANSMITTED_BSSID_CHECK_EN_MASK 0x0400000000000000
|
||||
|
||||
#define EXPECTED_RESPONSE_RESERVED_1_OFFSET 0x0000000000000000
|
||||
#define EXPECTED_RESPONSE_RESERVED_1_LSB 59
|
||||
#define EXPECTED_RESPONSE_RESERVED_1_MSB 63
|
||||
#define EXPECTED_RESPONSE_RESERVED_1_MASK 0xf800000000000000
|
||||
|
||||
#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID_2_8_0_OFFSET 0x0000000000000008
|
||||
#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID_2_8_0_LSB 0
|
||||
#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID_2_8_0_MSB 10
|
||||
#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID_2_8_0_MASK 0x00000000000007ff
|
||||
|
||||
#define EXPECTED_RESPONSE_RESERVED_2_OFFSET 0x0000000000000008
|
||||
#define EXPECTED_RESPONSE_RESERVED_2_LSB 11
|
||||
#define EXPECTED_RESPONSE_RESERVED_2_MSB 20
|
||||
#define EXPECTED_RESPONSE_RESERVED_2_MASK 0x00000000001ff800
|
||||
|
||||
#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID1_8_0_OFFSET 0x0000000000000008
|
||||
#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID1_8_0_LSB 21
|
||||
#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID1_8_0_MSB 31
|
||||
#define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID1_8_0_MASK 0x00000000ffe00000
|
||||
|
||||
#define EXPECTED_RESPONSE_AST_INDEX_OFFSET 0x0000000000000008
|
||||
#define EXPECTED_RESPONSE_AST_INDEX_LSB 32
|
||||
#define EXPECTED_RESPONSE_AST_INDEX_MSB 47
|
||||
#define EXPECTED_RESPONSE_AST_INDEX_MASK 0x0000ffff00000000
|
||||
|
||||
#define EXPECTED_RESPONSE_CAPTURE_ACK_BA_SOUNDING_OFFSET 0x0000000000000008
|
||||
#define EXPECTED_RESPONSE_CAPTURE_ACK_BA_SOUNDING_LSB 48
|
||||
#define EXPECTED_RESPONSE_CAPTURE_ACK_BA_SOUNDING_MSB 48
|
||||
#define EXPECTED_RESPONSE_CAPTURE_ACK_BA_SOUNDING_MASK 0x0001000000000000
|
||||
|
||||
#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_20MHZ_OFFSET 0x0000000000000008
|
||||
#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_20MHZ_LSB 49
|
||||
#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_20MHZ_MSB 49
|
||||
#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_20MHZ_MASK 0x0002000000000000
|
||||
|
||||
#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_40MHZ_OFFSET 0x0000000000000008
|
||||
#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_40MHZ_LSB 50
|
||||
#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_40MHZ_MSB 50
|
||||
#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_40MHZ_MASK 0x0004000000000000
|
||||
|
||||
#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_80MHZ_OFFSET 0x0000000000000008
|
||||
#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_80MHZ_LSB 51
|
||||
#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_80MHZ_MSB 51
|
||||
#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_80MHZ_MASK 0x0008000000000000
|
||||
|
||||
#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_160MHZ_OFFSET 0x0000000000000008
|
||||
#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_160MHZ_LSB 52
|
||||
#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_160MHZ_MSB 52
|
||||
#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_160MHZ_MASK 0x0010000000000000
|
||||
|
||||
#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_240MHZ_OFFSET 0x0000000000000008
|
||||
#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_240MHZ_LSB 53
|
||||
#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_240MHZ_MSB 53
|
||||
#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_240MHZ_MASK 0x0020000000000000
|
||||
|
||||
#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_320MHZ_OFFSET 0x0000000000000008
|
||||
#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_320MHZ_LSB 54
|
||||
#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_320MHZ_MSB 54
|
||||
#define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_320MHZ_MASK 0x0040000000000000
|
||||
|
||||
#define EXPECTED_RESPONSE_RESERVED_3A_OFFSET 0x0000000000000008
|
||||
#define EXPECTED_RESPONSE_RESERVED_3A_LSB 55
|
||||
#define EXPECTED_RESPONSE_RESERVED_3A_MSB 63
|
||||
#define EXPECTED_RESPONSE_RESERVED_3A_MASK 0xff80000000000000
|
||||
|
||||
#define EXPECTED_RESPONSE_FCS_OFFSET 0x0000000000000010
|
||||
#define EXPECTED_RESPONSE_FCS_LSB 0
|
||||
#define EXPECTED_RESPONSE_FCS_MSB 8
|
||||
#define EXPECTED_RESPONSE_FCS_MASK 0x00000000000001ff
|
||||
|
||||
#define EXPECTED_RESPONSE_RESERVED_4A_OFFSET 0x0000000000000010
|
||||
#define EXPECTED_RESPONSE_RESERVED_4A_LSB 9
|
||||
#define EXPECTED_RESPONSE_RESERVED_4A_MSB 9
|
||||
#define EXPECTED_RESPONSE_RESERVED_4A_MASK 0x0000000000000200
|
||||
|
||||
#define EXPECTED_RESPONSE_CRC_OFFSET 0x0000000000000010
|
||||
#define EXPECTED_RESPONSE_CRC_LSB 10
|
||||
#define EXPECTED_RESPONSE_CRC_MSB 13
|
||||
#define EXPECTED_RESPONSE_CRC_MASK 0x0000000000003c00
|
||||
|
||||
#define EXPECTED_RESPONSE_SCRAMBLER_SEED_OFFSET 0x0000000000000010
|
||||
#define EXPECTED_RESPONSE_SCRAMBLER_SEED_LSB 14
|
||||
#define EXPECTED_RESPONSE_SCRAMBLER_SEED_MSB 20
|
||||
#define EXPECTED_RESPONSE_SCRAMBLER_SEED_MASK 0x00000000001fc000
|
||||
|
||||
#define EXPECTED_RESPONSE_RESERVED_4B_OFFSET 0x0000000000000010
|
||||
#define EXPECTED_RESPONSE_RESERVED_4B_LSB 21
|
||||
#define EXPECTED_RESPONSE_RESERVED_4B_MSB 31
|
||||
#define EXPECTED_RESPONSE_RESERVED_4B_MASK 0x00000000ffe00000
|
||||
|
||||
#define EXPECTED_RESPONSE_TLV64_PADDING_OFFSET 0x0000000000000010
|
||||
#define EXPECTED_RESPONSE_TLV64_PADDING_LSB 32
|
||||
#define EXPECTED_RESPONSE_TLV64_PADDING_MSB 63
|
||||
#define EXPECTED_RESPONSE_TLV64_PADDING_MASK 0xffffffff00000000
|
||||
|
||||
#endif
|
||||
93
hw/kiwi/v2/mactx_eht_sig_usr_mu_mimo.h
Normal file
93
hw/kiwi/v2/mactx_eht_sig_usr_mu_mimo.h
Normal file
|
|
@ -0,0 +1,93 @@
|
|||
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
#ifndef _MACTX_EHT_SIG_USR_MU_MIMO_H_
|
||||
#define _MACTX_EHT_SIG_USR_MU_MIMO_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#include "eht_sig_usr_mu_mimo_info.h"
|
||||
#define NUM_OF_DWORDS_MACTX_EHT_SIG_USR_MU_MIMO 2
|
||||
|
||||
#define NUM_OF_QWORDS_MACTX_EHT_SIG_USR_MU_MIMO 1
|
||||
|
||||
struct mactx_eht_sig_usr_mu_mimo {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
struct eht_sig_usr_mu_mimo_info mactx_eht_sig_usr_mu_mimo_info_details;
|
||||
#else
|
||||
struct eht_sig_usr_mu_mimo_info mactx_eht_sig_usr_mu_mimo_info_details;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_ID_OFFSET 0x0000000000000000
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_ID_LSB 0
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_ID_MSB 10
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_ID_MASK 0x00000000000007ff
|
||||
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_MCS_OFFSET 0x0000000000000000
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_MCS_LSB 11
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_MCS_MSB 14
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_MCS_MASK 0x0000000000007800
|
||||
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_CODING_OFFSET 0x0000000000000000
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_CODING_LSB 15
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_CODING_MSB 15
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_CODING_MASK 0x0000000000008000
|
||||
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_SPATIAL_CONFIG_OFFSET 0x0000000000000000
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_SPATIAL_CONFIG_LSB 16
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_SPATIAL_CONFIG_MSB 21
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_STA_SPATIAL_CONFIG_MASK 0x00000000003f0000
|
||||
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RESERVED_0A_LSB 22
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RESERVED_0A_MSB 22
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RESERVED_0A_MASK 0x0000000000400000
|
||||
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 23
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 23
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000000800000
|
||||
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_SUBBAND80_CC_MASK_OFFSET 0x0000000000000000
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_SUBBAND80_CC_MASK_LSB 24
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_SUBBAND80_CC_MASK_MSB 31
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_SUBBAND80_CC_MASK_MASK 0x00000000ff000000
|
||||
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_0_OFFSET 0x0000000000000000
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_0_LSB 32
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_0_MSB 39
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_0_MASK 0x000000ff00000000
|
||||
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_1_OFFSET 0x0000000000000000
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_1_LSB 40
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_1_MSB 47
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_1_MASK 0x0000ff0000000000
|
||||
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_2_OFFSET 0x0000000000000000
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_2_LSB 48
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_2_MSB 55
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_2_MASK 0x00ff000000000000
|
||||
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_3_OFFSET 0x0000000000000000
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_3_LSB 56
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_3_MSB 63
|
||||
#define MACTX_EHT_SIG_USR_MU_MIMO_MACTX_EHT_SIG_USR_MU_MIMO_INFO_DETAILS_USER_ORDER_SUBBAND80_3_MASK 0xff00000000000000
|
||||
|
||||
#endif
|
||||
103
hw/kiwi/v2/mactx_eht_sig_usr_ofdma.h
Normal file
103
hw/kiwi/v2/mactx_eht_sig_usr_ofdma.h
Normal file
|
|
@ -0,0 +1,103 @@
|
|||
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
#ifndef _MACTX_EHT_SIG_USR_OFDMA_H_
|
||||
#define _MACTX_EHT_SIG_USR_OFDMA_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#include "eht_sig_usr_ofdma_info.h"
|
||||
#define NUM_OF_DWORDS_MACTX_EHT_SIG_USR_OFDMA 2
|
||||
|
||||
#define NUM_OF_QWORDS_MACTX_EHT_SIG_USR_OFDMA 1
|
||||
|
||||
struct mactx_eht_sig_usr_ofdma {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
struct eht_sig_usr_ofdma_info mactx_eht_sig_usr_ofdma_info_details;
|
||||
#else
|
||||
struct eht_sig_usr_ofdma_info mactx_eht_sig_usr_ofdma_info_details;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_ID_OFFSET 0x0000000000000000
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_ID_LSB 0
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_ID_MSB 10
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_ID_MASK 0x00000000000007ff
|
||||
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_MCS_OFFSET 0x0000000000000000
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_MCS_LSB 11
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_MCS_MSB 14
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_MCS_MASK 0x0000000000007800
|
||||
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_VALIDATE_0A_OFFSET 0x0000000000000000
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_VALIDATE_0A_LSB 15
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_VALIDATE_0A_MSB 15
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_VALIDATE_0A_MASK 0x0000000000008000
|
||||
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_NSS_OFFSET 0x0000000000000000
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_NSS_LSB 16
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_NSS_MSB 19
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_NSS_MASK 0x00000000000f0000
|
||||
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_TXBF_OFFSET 0x0000000000000000
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_TXBF_LSB 20
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_TXBF_MSB 20
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_TXBF_MASK 0x0000000000100000
|
||||
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_CODING_OFFSET 0x0000000000000000
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_CODING_LSB 21
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_CODING_MSB 21
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_STA_CODING_MASK 0x0000000000200000
|
||||
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RESERVED_0B_LSB 22
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RESERVED_0B_MSB 22
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RESERVED_0B_MASK 0x0000000000400000
|
||||
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 23
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 23
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000000800000
|
||||
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_SUBBAND80_CC_MASK_OFFSET 0x0000000000000000
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_SUBBAND80_CC_MASK_LSB 24
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_SUBBAND80_CC_MASK_MSB 31
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_SUBBAND80_CC_MASK_MASK 0x00000000ff000000
|
||||
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_0_OFFSET 0x0000000000000000
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_0_LSB 32
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_0_MSB 39
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_0_MASK 0x000000ff00000000
|
||||
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_1_OFFSET 0x0000000000000000
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_1_LSB 40
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_1_MSB 47
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_1_MASK 0x0000ff0000000000
|
||||
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_2_OFFSET 0x0000000000000000
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_2_LSB 48
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_2_MSB 55
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_2_MASK 0x00ff000000000000
|
||||
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_3_OFFSET 0x0000000000000000
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_3_LSB 56
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_3_MSB 63
|
||||
#define MACTX_EHT_SIG_USR_OFDMA_MACTX_EHT_SIG_USR_OFDMA_INFO_DETAILS_USER_ORDER_SUBBAND80_3_MASK 0xff00000000000000
|
||||
|
||||
#endif
|
||||
85
hw/kiwi/v2/mactx_eht_sig_usr_su.h
Normal file
85
hw/kiwi/v2/mactx_eht_sig_usr_su.h
Normal file
|
|
@ -0,0 +1,85 @@
|
|||
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
#ifndef _MACTX_EHT_SIG_USR_SU_H_
|
||||
#define _MACTX_EHT_SIG_USR_SU_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#include "eht_sig_usr_su_info.h"
|
||||
#define NUM_OF_DWORDS_MACTX_EHT_SIG_USR_SU 2
|
||||
|
||||
#define NUM_OF_QWORDS_MACTX_EHT_SIG_USR_SU 1
|
||||
|
||||
struct mactx_eht_sig_usr_su {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
struct eht_sig_usr_su_info mactx_eht_sig_usr_su_info_details;
|
||||
uint32_t tlv64_padding : 32;
|
||||
#else
|
||||
struct eht_sig_usr_su_info mactx_eht_sig_usr_su_info_details;
|
||||
uint32_t tlv64_padding : 32;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_ID_OFFSET 0x0000000000000000
|
||||
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_ID_LSB 0
|
||||
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_ID_MSB 10
|
||||
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_ID_MASK 0x00000000000007ff
|
||||
|
||||
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_MCS_OFFSET 0x0000000000000000
|
||||
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_MCS_LSB 11
|
||||
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_MCS_MSB 14
|
||||
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_MCS_MASK 0x0000000000007800
|
||||
|
||||
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_VALIDATE_0A_OFFSET 0x0000000000000000
|
||||
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_VALIDATE_0A_LSB 15
|
||||
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_VALIDATE_0A_MSB 15
|
||||
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_VALIDATE_0A_MASK 0x0000000000008000
|
||||
|
||||
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_NSS_OFFSET 0x0000000000000000
|
||||
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_NSS_LSB 16
|
||||
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_NSS_MSB 19
|
||||
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_NSS_MASK 0x00000000000f0000
|
||||
|
||||
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_TXBF_OFFSET 0x0000000000000000
|
||||
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_TXBF_LSB 20
|
||||
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_TXBF_MSB 20
|
||||
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_TXBF_MASK 0x0000000000100000
|
||||
|
||||
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_CODING_OFFSET 0x0000000000000000
|
||||
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_CODING_LSB 21
|
||||
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_CODING_MSB 21
|
||||
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_STA_CODING_MASK 0x0000000000200000
|
||||
|
||||
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000
|
||||
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RESERVED_0B_LSB 22
|
||||
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RESERVED_0B_MSB 30
|
||||
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RESERVED_0B_MASK 0x000000007fc00000
|
||||
|
||||
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
|
||||
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
|
||||
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
|
||||
#define MACTX_EHT_SIG_USR_SU_MACTX_EHT_SIG_USR_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000
|
||||
|
||||
#define MACTX_EHT_SIG_USR_SU_TLV64_PADDING_OFFSET 0x0000000000000000
|
||||
#define MACTX_EHT_SIG_USR_SU_TLV64_PADDING_LSB 32
|
||||
#define MACTX_EHT_SIG_USR_SU_TLV64_PADDING_MSB 63
|
||||
#define MACTX_EHT_SIG_USR_SU_TLV64_PADDING_MASK 0xffffffff00000000
|
||||
|
||||
#endif
|
||||
148
hw/kiwi/v2/mactx_he_sig_a_mu_dl.h
Normal file
148
hw/kiwi/v2/mactx_he_sig_a_mu_dl.h
Normal file
|
|
@ -0,0 +1,148 @@
|
|||
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
#ifndef _MACTX_HE_SIG_A_MU_DL_H_
|
||||
#define _MACTX_HE_SIG_A_MU_DL_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#include "he_sig_a_mu_dl_info.h"
|
||||
#define NUM_OF_DWORDS_MACTX_HE_SIG_A_MU_DL 2
|
||||
|
||||
#define NUM_OF_QWORDS_MACTX_HE_SIG_A_MU_DL 1
|
||||
|
||||
struct mactx_he_sig_a_mu_dl {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
struct he_sig_a_mu_dl_info mactx_he_sig_a_mu_dl_info_details;
|
||||
#else
|
||||
struct he_sig_a_mu_dl_info mactx_he_sig_a_mu_dl_info_details;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_LSB 0
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_MSB 0
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_MASK 0x0000000000000001
|
||||
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_LSB 1
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_MSB 3
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_MCS_OF_SIG_B_MASK 0x000000000000000e
|
||||
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_LSB 4
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_MSB 4
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DCM_OF_SIG_B_MASK 0x0000000000000010
|
||||
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_LSB 5
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_MSB 10
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_BSS_COLOR_ID_MASK 0x00000000000007e0
|
||||
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_LSB 11
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_MSB 14
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_SPATIAL_REUSE_MASK 0x0000000000007800
|
||||
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_LSB 15
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_MSB 17
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TRANSMIT_BW_MASK 0x0000000000038000
|
||||
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_LSB 18
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_MSB 21
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_SIG_B_SYMBOLS_MASK 0x00000000003c0000
|
||||
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_LSB 22
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_MSB 22
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_COMP_MODE_SIG_B_MASK 0x0000000000400000
|
||||
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_LSB 23
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_MSB 24
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CP_LTF_SIZE_MASK 0x0000000001800000
|
||||
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_LSB 25
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_MSB 25
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_DOPPLER_INDICATION_MASK 0x0000000002000000
|
||||
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_LSB 26
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_MSB 31
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_0A_MASK 0x00000000fc000000
|
||||
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_LSB 32
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_MSB 38
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f00000000
|
||||
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_LSB 39
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_MSB 39
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1A_MASK 0x0000008000000000
|
||||
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_LSB 40
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_MSB 42
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_NUM_LTF_SYMBOLS_MASK 0x0000070000000000
|
||||
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 43
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 43
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x0000080000000000
|
||||
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_LSB 44
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_MSB 44
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_STBC_MASK 0x0000100000000000
|
||||
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 45
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MSB 46
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x0000600000000000
|
||||
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 47
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 47
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x0000800000000000
|
||||
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_LSB 48
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_MSB 51
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_CRC_MASK 0x000f000000000000
|
||||
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_LSB 52
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_MSB 57
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_TAIL_MASK 0x03f0000000000000
|
||||
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_LSB 58
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_MSB 62
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RESERVED_1B_MASK 0x7c00000000000000
|
||||
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63
|
||||
#define MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000
|
||||
|
||||
#endif
|
||||
98
hw/kiwi/v2/mactx_he_sig_a_mu_ul.h
Normal file
98
hw/kiwi/v2/mactx_he_sig_a_mu_ul.h
Normal file
|
|
@ -0,0 +1,98 @@
|
|||
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
#ifndef _MACTX_HE_SIG_A_MU_UL_H_
|
||||
#define _MACTX_HE_SIG_A_MU_UL_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#include "he_sig_a_mu_ul_info.h"
|
||||
#define NUM_OF_DWORDS_MACTX_HE_SIG_A_MU_UL 2
|
||||
|
||||
#define NUM_OF_QWORDS_MACTX_HE_SIG_A_MU_UL 1
|
||||
|
||||
struct mactx_he_sig_a_mu_ul {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
struct he_sig_a_mu_ul_info mactx_he_sig_a_mu_ul_info_details;
|
||||
#else
|
||||
struct he_sig_a_mu_ul_info mactx_he_sig_a_mu_ul_info_details;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_LSB 0
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_MSB 0
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_FORMAT_INDICATION_MASK 0x0000000000000001
|
||||
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_LSB 1
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_MSB 6
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_BSS_COLOR_ID_MASK 0x000000000000007e
|
||||
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_LSB 7
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_MSB 22
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_SPATIAL_REUSE_MASK 0x00000000007fff80
|
||||
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_LSB 23
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_MSB 23
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0A_MASK 0x0000000000800000
|
||||
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_LSB 24
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_MSB 25
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TRANSMIT_BW_MASK 0x0000000003000000
|
||||
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_LSB 26
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_MSB 31
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_0B_MASK 0x00000000fc000000
|
||||
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_LSB 32
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_MSB 38
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f00000000
|
||||
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_LSB 39
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_MSB 47
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1A_MASK 0x0000ff8000000000
|
||||
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_LSB 48
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_MSB 51
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_CRC_MASK 0x000f000000000000
|
||||
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_LSB 52
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_MSB 57
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_TAIL_MASK 0x03f0000000000000
|
||||
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_LSB 58
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_MSB 62
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RESERVED_1B_MASK 0x7c00000000000000
|
||||
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63
|
||||
#define MACTX_HE_SIG_A_MU_UL_MACTX_HE_SIG_A_MU_UL_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000
|
||||
|
||||
#endif
|
||||
173
hw/kiwi/v2/mactx_he_sig_a_su.h
Normal file
173
hw/kiwi/v2/mactx_he_sig_a_su.h
Normal file
|
|
@ -0,0 +1,173 @@
|
|||
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
#ifndef _MACTX_HE_SIG_A_SU_H_
|
||||
#define _MACTX_HE_SIG_A_SU_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#include "he_sig_a_su_info.h"
|
||||
#define NUM_OF_DWORDS_MACTX_HE_SIG_A_SU 2
|
||||
|
||||
#define NUM_OF_QWORDS_MACTX_HE_SIG_A_SU 1
|
||||
|
||||
struct mactx_he_sig_a_su {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
struct he_sig_a_su_info mactx_he_sig_a_su_info_details;
|
||||
#else
|
||||
struct he_sig_a_su_info mactx_he_sig_a_su_info_details;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_LSB 0
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_MSB 0
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_MASK 0x0000000000000001
|
||||
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_LSB 1
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_MSB 1
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BEAM_CHANGE_MASK 0x0000000000000002
|
||||
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_LSB 2
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_MSB 2
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DL_UL_FLAG_MASK 0x0000000000000004
|
||||
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_LSB 3
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_MSB 6
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_MCS_MASK 0x0000000000000078
|
||||
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DCM_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DCM_LSB 7
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DCM_MSB 7
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DCM_MASK 0x0000000000000080
|
||||
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_LSB 8
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_MSB 13
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_BSS_COLOR_ID_MASK 0x0000000000003f00
|
||||
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_LSB 14
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_MSB 14
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0A_MASK 0x0000000000004000
|
||||
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_LSB 15
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_MSB 18
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_SPATIAL_REUSE_MASK 0x0000000000078000
|
||||
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_LSB 19
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_MSB 20
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TRANSMIT_BW_MASK 0x0000000000180000
|
||||
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_LSB 21
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_MSB 22
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CP_LTF_SIZE_MASK 0x0000000000600000
|
||||
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_NSTS_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_NSTS_LSB 23
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_NSTS_MSB 25
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_NSTS_MASK 0x0000000003800000
|
||||
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_LSB 26
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_MSB 31
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_0B_MASK 0x00000000fc000000
|
||||
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_LSB 32
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_MSB 38
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXOP_DURATION_MASK 0x0000007f00000000
|
||||
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CODING_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CODING_LSB 39
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CODING_MSB 39
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CODING_MASK 0x0000008000000000
|
||||
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 40
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 40
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x0000010000000000
|
||||
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_STBC_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_STBC_LSB 41
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_STBC_MSB 41
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_STBC_MASK 0x0000020000000000
|
||||
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXBF_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXBF_LSB 42
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXBF_MSB 42
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TXBF_MASK 0x0000040000000000
|
||||
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 43
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MSB 44
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x0000180000000000
|
||||
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 45
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 45
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x0000200000000000
|
||||
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_LSB 46
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_MSB 46
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RESERVED_1A_MASK 0x0000400000000000
|
||||
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_LSB 47
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_MSB 47
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOPPLER_INDICATION_MASK 0x0000800000000000
|
||||
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CRC_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CRC_LSB 48
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CRC_MSB 51
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_CRC_MASK 0x000f000000000000
|
||||
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TAIL_LSB 52
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TAIL_MSB 57
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_TAIL_MASK 0x03f0000000000000
|
||||
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_LSB 58
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MSB 58
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MASK 0x0400000000000000
|
||||
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_LSB 59
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_MSB 61
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_DOT11AX_EXT_RU_SIZE_MASK 0x3800000000000000
|
||||
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_LSB 62
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_MSB 62
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_NDP_MASK 0x4000000000000000
|
||||
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63
|
||||
#define MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000
|
||||
|
||||
#endif
|
||||
60
hw/kiwi/v2/mactx_he_sig_b1_mu.h
Normal file
60
hw/kiwi/v2/mactx_he_sig_b1_mu.h
Normal file
|
|
@ -0,0 +1,60 @@
|
|||
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
#ifndef _MACTX_HE_SIG_B1_MU_H_
|
||||
#define _MACTX_HE_SIG_B1_MU_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#include "he_sig_b1_mu_info.h"
|
||||
#define NUM_OF_DWORDS_MACTX_HE_SIG_B1_MU 2
|
||||
|
||||
#define NUM_OF_QWORDS_MACTX_HE_SIG_B1_MU 1
|
||||
|
||||
struct mactx_he_sig_b1_mu {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
struct he_sig_b1_mu_info mactx_he_sig_b1_mu_info_details;
|
||||
uint32_t tlv64_padding : 32;
|
||||
#else
|
||||
struct he_sig_b1_mu_info mactx_he_sig_b1_mu_info_details;
|
||||
uint32_t tlv64_padding : 32;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_LSB 0
|
||||
#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_MSB 7
|
||||
#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_MASK 0x00000000000000ff
|
||||
|
||||
#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_LSB 8
|
||||
#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_MSB 30
|
||||
#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RESERVED_0_MASK 0x000000007fffff00
|
||||
|
||||
#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
|
||||
#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
|
||||
#define MACTX_HE_SIG_B1_MU_MACTX_HE_SIG_B1_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000
|
||||
|
||||
#define MACTX_HE_SIG_B1_MU_TLV64_PADDING_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_B1_MU_TLV64_PADDING_LSB 32
|
||||
#define MACTX_HE_SIG_B1_MU_TLV64_PADDING_MSB 63
|
||||
#define MACTX_HE_SIG_B1_MU_TLV64_PADDING_MASK 0xffffffff00000000
|
||||
|
||||
#endif
|
||||
93
hw/kiwi/v2/mactx_he_sig_b2_mu.h
Normal file
93
hw/kiwi/v2/mactx_he_sig_b2_mu.h
Normal file
|
|
@ -0,0 +1,93 @@
|
|||
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
#ifndef _MACTX_HE_SIG_B2_MU_H_
|
||||
#define _MACTX_HE_SIG_B2_MU_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#include "he_sig_b2_mu_info.h"
|
||||
#define NUM_OF_DWORDS_MACTX_HE_SIG_B2_MU 2
|
||||
|
||||
#define NUM_OF_QWORDS_MACTX_HE_SIG_B2_MU 1
|
||||
|
||||
struct mactx_he_sig_b2_mu {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
struct he_sig_b2_mu_info mactx_he_sig_b2_mu_info_details;
|
||||
#else
|
||||
struct he_sig_b2_mu_info mactx_he_sig_b2_mu_info_details;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_LSB 0
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_MSB 10
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_MASK 0x00000000000007ff
|
||||
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_LSB 11
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_MSB 14
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_SPATIAL_CONFIG_MASK 0x0000000000007800
|
||||
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_LSB 15
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_MSB 18
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_MCS_MASK 0x0000000000078000
|
||||
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_LSB 19
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_MSB 19
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_SET_TO_1_MASK 0x0000000000080000
|
||||
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_LSB 20
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_MSB 20
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_STA_CODING_MASK 0x0000000000100000
|
||||
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_LSB 21
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_MSB 27
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_0A_MASK 0x000000000fe00000
|
||||
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_LSB 28
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_MSB 30
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_NSTS_MASK 0x0000000070000000
|
||||
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000
|
||||
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_LSB 32
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_MSB 39
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_USER_ORDER_MASK 0x000000ff00000000
|
||||
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_LSB 40
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_MSB 47
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_CC_MASK_MASK 0x0000ff0000000000
|
||||
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_LSB 48
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_MSB 63
|
||||
#define MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS_RESERVED_1A_MASK 0xffff000000000000
|
||||
|
||||
#endif
|
||||
93
hw/kiwi/v2/mactx_he_sig_b2_ofdma.h
Normal file
93
hw/kiwi/v2/mactx_he_sig_b2_ofdma.h
Normal file
|
|
@ -0,0 +1,93 @@
|
|||
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
#ifndef _MACTX_HE_SIG_B2_OFDMA_H_
|
||||
#define _MACTX_HE_SIG_B2_OFDMA_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#include "he_sig_b2_ofdma_info.h"
|
||||
#define NUM_OF_DWORDS_MACTX_HE_SIG_B2_OFDMA 2
|
||||
|
||||
#define NUM_OF_QWORDS_MACTX_HE_SIG_B2_OFDMA 1
|
||||
|
||||
struct mactx_he_sig_b2_ofdma {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
struct he_sig_b2_ofdma_info mactx_he_sig_b2_ofdma_info_details;
|
||||
#else
|
||||
struct he_sig_b2_ofdma_info mactx_he_sig_b2_ofdma_info_details;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_LSB 0
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_MSB 10
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_MASK 0x00000000000007ff
|
||||
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_LSB 11
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_MSB 13
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_NSTS_MASK 0x0000000000003800
|
||||
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_LSB 14
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_MSB 14
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_TXBF_MASK 0x0000000000004000
|
||||
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_LSB 15
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_MSB 18
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_MCS_MASK 0x0000000000078000
|
||||
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_LSB 19
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_MSB 19
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_DCM_MASK 0x0000000000080000
|
||||
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_LSB 20
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_MSB 20
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_CODING_MASK 0x0000000000100000
|
||||
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_LSB 21
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_MSB 30
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_0_MASK 0x000000007fe00000
|
||||
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000
|
||||
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_LSB 32
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_MSB 39
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_USER_ORDER_MASK 0x000000ff00000000
|
||||
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_LSB 40
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_MSB 47
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_CC_MASK_MASK 0x0000ff0000000000
|
||||
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_LSB 48
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_MSB 63
|
||||
#define MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS_RESERVED_1A_MASK 0xffff000000000000
|
||||
|
||||
#endif
|
||||
118
hw/kiwi/v2/mactx_ht_sig.h
Normal file
118
hw/kiwi/v2/mactx_ht_sig.h
Normal file
|
|
@ -0,0 +1,118 @@
|
|||
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
#ifndef _MACTX_HT_SIG_H_
|
||||
#define _MACTX_HT_SIG_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#include "ht_sig_info.h"
|
||||
#define NUM_OF_DWORDS_MACTX_HT_SIG 2
|
||||
|
||||
#define NUM_OF_QWORDS_MACTX_HT_SIG 1
|
||||
|
||||
struct mactx_ht_sig {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
struct ht_sig_info mactx_ht_sig_info_details;
|
||||
#else
|
||||
struct ht_sig_info mactx_ht_sig_info_details;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_MCS_OFFSET 0x0000000000000000
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_MCS_LSB 0
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_MCS_MSB 6
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_MCS_MASK 0x000000000000007f
|
||||
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CBW_OFFSET 0x0000000000000000
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CBW_LSB 7
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CBW_MSB 7
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CBW_MASK 0x0000000000000080
|
||||
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_LENGTH_LSB 8
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_LENGTH_MSB 23
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_LENGTH_MASK 0x0000000000ffff00
|
||||
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_0_LSB 24
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_0_MSB 31
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_0_MASK 0x00000000ff000000
|
||||
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SMOOTHING_OFFSET 0x0000000000000000
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SMOOTHING_LSB 32
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SMOOTHING_MSB 32
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SMOOTHING_MASK 0x0000000100000000
|
||||
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_OFFSET 0x0000000000000000
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_LSB 33
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_MSB 33
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NOT_SOUNDING_MASK 0x0000000200000000
|
||||
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_HT_RESERVED_OFFSET 0x0000000000000000
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_HT_RESERVED_LSB 34
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_HT_RESERVED_MSB 34
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_HT_RESERVED_MASK 0x0000000400000000
|
||||
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_AGGREGATION_OFFSET 0x0000000000000000
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_AGGREGATION_LSB 35
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_AGGREGATION_MSB 35
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_AGGREGATION_MASK 0x0000000800000000
|
||||
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_STBC_OFFSET 0x0000000000000000
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_STBC_LSB 36
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_STBC_MSB 37
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_STBC_MASK 0x0000003000000000
|
||||
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_FEC_CODING_OFFSET 0x0000000000000000
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_FEC_CODING_LSB 38
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_FEC_CODING_MSB 38
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_FEC_CODING_MASK 0x0000004000000000
|
||||
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SHORT_GI_OFFSET 0x0000000000000000
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SHORT_GI_LSB 39
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SHORT_GI_MSB 39
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SHORT_GI_MASK 0x0000008000000000
|
||||
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_OFFSET 0x0000000000000000
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_LSB 40
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_MSB 41
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_NUM_EXT_SP_STR_MASK 0x0000030000000000
|
||||
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CRC_OFFSET 0x0000000000000000
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CRC_LSB 42
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CRC_MSB 49
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_CRC_MASK 0x0003fc0000000000
|
||||
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_OFFSET 0x0000000000000000
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_LSB 50
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_MSB 55
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_SIGNAL_TAIL_MASK 0x00fc000000000000
|
||||
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_1_LSB 56
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_1_MSB 62
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RESERVED_1_MASK 0x7f00000000000000
|
||||
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63
|
||||
#define MACTX_HT_SIG_MACTX_HT_SIG_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000
|
||||
|
||||
#endif
|
||||
90
hw/kiwi/v2/mactx_l_sig_a.h
Normal file
90
hw/kiwi/v2/mactx_l_sig_a.h
Normal file
|
|
@ -0,0 +1,90 @@
|
|||
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
#ifndef _MACTX_L_SIG_A_H_
|
||||
#define _MACTX_L_SIG_A_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#include "l_sig_a_info.h"
|
||||
#define NUM_OF_DWORDS_MACTX_L_SIG_A 2
|
||||
|
||||
#define NUM_OF_QWORDS_MACTX_L_SIG_A 1
|
||||
|
||||
struct mactx_l_sig_a {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
struct l_sig_a_info mactx_l_sig_a_info_details;
|
||||
uint32_t tlv64_padding : 32;
|
||||
#else
|
||||
struct l_sig_a_info mactx_l_sig_a_info_details;
|
||||
uint32_t tlv64_padding : 32;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RATE_OFFSET 0x0000000000000000
|
||||
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RATE_LSB 0
|
||||
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RATE_MSB 3
|
||||
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RATE_MASK 0x000000000000000f
|
||||
|
||||
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_OFFSET 0x0000000000000000
|
||||
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_LSB 4
|
||||
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_MSB 4
|
||||
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LSIG_RESERVED_MASK 0x0000000000000010
|
||||
|
||||
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000
|
||||
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LENGTH_LSB 5
|
||||
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LENGTH_MSB 16
|
||||
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_LENGTH_MASK 0x000000000001ffe0
|
||||
|
||||
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PARITY_OFFSET 0x0000000000000000
|
||||
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PARITY_LSB 17
|
||||
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PARITY_MSB 17
|
||||
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PARITY_MASK 0x0000000000020000
|
||||
|
||||
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000
|
||||
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_TAIL_LSB 18
|
||||
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_TAIL_MSB 23
|
||||
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_TAIL_MASK 0x0000000000fc0000
|
||||
|
||||
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PKT_TYPE_OFFSET 0x0000000000000000
|
||||
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PKT_TYPE_LSB 24
|
||||
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PKT_TYPE_MSB 27
|
||||
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_PKT_TYPE_MASK 0x000000000f000000
|
||||
|
||||
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_OFFSET 0x0000000000000000
|
||||
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_LSB 28
|
||||
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_MSB 28
|
||||
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_CAPTURED_IMPLICIT_SOUNDING_MASK 0x0000000010000000
|
||||
|
||||
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000
|
||||
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RESERVED_LSB 29
|
||||
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RESERVED_MSB 30
|
||||
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RESERVED_MASK 0x0000000060000000
|
||||
|
||||
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
|
||||
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
|
||||
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
|
||||
#define MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000
|
||||
|
||||
#define MACTX_L_SIG_A_TLV64_PADDING_OFFSET 0x0000000000000000
|
||||
#define MACTX_L_SIG_A_TLV64_PADDING_LSB 32
|
||||
#define MACTX_L_SIG_A_TLV64_PADDING_MSB 63
|
||||
#define MACTX_L_SIG_A_TLV64_PADDING_MASK 0xffffffff00000000
|
||||
|
||||
#endif
|
||||
65
hw/kiwi/v2/mactx_l_sig_b.h
Normal file
65
hw/kiwi/v2/mactx_l_sig_b.h
Normal file
|
|
@ -0,0 +1,65 @@
|
|||
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
#ifndef _MACTX_L_SIG_B_H_
|
||||
#define _MACTX_L_SIG_B_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#include "l_sig_b_info.h"
|
||||
#define NUM_OF_DWORDS_MACTX_L_SIG_B 2
|
||||
|
||||
#define NUM_OF_QWORDS_MACTX_L_SIG_B 1
|
||||
|
||||
struct mactx_l_sig_b {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
struct l_sig_b_info mactx_l_sig_b_info_details;
|
||||
uint32_t tlv64_padding : 32;
|
||||
#else
|
||||
struct l_sig_b_info mactx_l_sig_b_info_details;
|
||||
uint32_t tlv64_padding : 32;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RATE_OFFSET 0x0000000000000000
|
||||
#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RATE_LSB 0
|
||||
#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RATE_MSB 3
|
||||
#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RATE_MASK 0x000000000000000f
|
||||
|
||||
#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000
|
||||
#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_LENGTH_LSB 4
|
||||
#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_LENGTH_MSB 15
|
||||
#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_LENGTH_MASK 0x000000000000fff0
|
||||
|
||||
#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000
|
||||
#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RESERVED_LSB 16
|
||||
#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RESERVED_MSB 30
|
||||
#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RESERVED_MASK 0x000000007fff0000
|
||||
|
||||
#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
|
||||
#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 31
|
||||
#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 31
|
||||
#define MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x0000000080000000
|
||||
|
||||
#define MACTX_L_SIG_B_TLV64_PADDING_OFFSET 0x0000000000000000
|
||||
#define MACTX_L_SIG_B_TLV64_PADDING_LSB 32
|
||||
#define MACTX_L_SIG_B_TLV64_PADDING_MSB 63
|
||||
#define MACTX_L_SIG_B_TLV64_PADDING_MASK 0xffffffff00000000
|
||||
|
||||
#endif
|
||||
371
hw/kiwi/v2/mactx_phy_desc.h
Normal file
371
hw/kiwi/v2/mactx_phy_desc.h
Normal file
|
|
@ -0,0 +1,371 @@
|
|||
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
#ifndef _MACTX_PHY_DESC_H_
|
||||
#define _MACTX_PHY_DESC_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#define NUM_OF_DWORDS_MACTX_PHY_DESC 4
|
||||
|
||||
#define NUM_OF_QWORDS_MACTX_PHY_DESC 2
|
||||
|
||||
struct mactx_phy_desc {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t reserved_0a : 16,
|
||||
bf_type : 2,
|
||||
wait_sifs : 2,
|
||||
dot11b_preamble_type : 1,
|
||||
pkt_type : 4,
|
||||
su_or_mu : 2,
|
||||
mu_type : 1,
|
||||
bandwidth : 3,
|
||||
channel_capture : 1;
|
||||
uint32_t mcs : 4,
|
||||
global_ofdma_mimo_enable : 1,
|
||||
reserved_1a : 1,
|
||||
stbc : 1,
|
||||
dot11ax_su_extended : 1,
|
||||
dot11ax_trigger_frame_embedded : 1,
|
||||
tx_pwr_shared : 8,
|
||||
tx_pwr_unshared : 8,
|
||||
measure_power : 1,
|
||||
tpc_glut_self_cal : 1,
|
||||
back_to_back_transmission_expected : 1,
|
||||
heavy_clip_nss : 3,
|
||||
txbf_per_packet_no_csd_no_walsh : 1;
|
||||
uint32_t ndp : 2,
|
||||
ul_flag : 1,
|
||||
triggered : 1,
|
||||
ap_pkt_bw : 3,
|
||||
ru_position_start : 8,
|
||||
pcu_ppdu_setup_start_reason : 3,
|
||||
tlv_source : 1,
|
||||
reserved_2a : 2,
|
||||
nss : 3,
|
||||
stream_offset : 3,
|
||||
reserved_2b : 2,
|
||||
clpc_enable : 1,
|
||||
mu_ndp : 1,
|
||||
response_expected : 1;
|
||||
uint32_t rx_chain_mask : 8,
|
||||
rx_chain_mask_valid : 1,
|
||||
ant_sel_valid : 1,
|
||||
ant_sel : 1,
|
||||
cp_setting : 2,
|
||||
he_ppdu_subtype : 2,
|
||||
active_channel : 3,
|
||||
generate_phyrx_tx_start_timing : 1,
|
||||
ltf_size : 2,
|
||||
ru_size_updated_v2 : 4,
|
||||
reserved_3c : 1,
|
||||
u_sig_puncture_pattern_encoding : 6;
|
||||
#else
|
||||
uint32_t channel_capture : 1,
|
||||
bandwidth : 3,
|
||||
mu_type : 1,
|
||||
su_or_mu : 2,
|
||||
pkt_type : 4,
|
||||
dot11b_preamble_type : 1,
|
||||
wait_sifs : 2,
|
||||
bf_type : 2,
|
||||
reserved_0a : 16;
|
||||
uint32_t txbf_per_packet_no_csd_no_walsh : 1,
|
||||
heavy_clip_nss : 3,
|
||||
back_to_back_transmission_expected : 1,
|
||||
tpc_glut_self_cal : 1,
|
||||
measure_power : 1,
|
||||
tx_pwr_unshared : 8,
|
||||
tx_pwr_shared : 8,
|
||||
dot11ax_trigger_frame_embedded : 1,
|
||||
dot11ax_su_extended : 1,
|
||||
stbc : 1,
|
||||
reserved_1a : 1,
|
||||
global_ofdma_mimo_enable : 1,
|
||||
mcs : 4;
|
||||
uint32_t response_expected : 1,
|
||||
mu_ndp : 1,
|
||||
clpc_enable : 1,
|
||||
reserved_2b : 2,
|
||||
stream_offset : 3,
|
||||
nss : 3,
|
||||
reserved_2a : 2,
|
||||
tlv_source : 1,
|
||||
pcu_ppdu_setup_start_reason : 3,
|
||||
ru_position_start : 8,
|
||||
ap_pkt_bw : 3,
|
||||
triggered : 1,
|
||||
ul_flag : 1,
|
||||
ndp : 2;
|
||||
uint32_t u_sig_puncture_pattern_encoding : 6,
|
||||
reserved_3c : 1,
|
||||
ru_size_updated_v2 : 4,
|
||||
ltf_size : 2,
|
||||
generate_phyrx_tx_start_timing : 1,
|
||||
active_channel : 3,
|
||||
he_ppdu_subtype : 2,
|
||||
cp_setting : 2,
|
||||
ant_sel : 1,
|
||||
ant_sel_valid : 1,
|
||||
rx_chain_mask_valid : 1,
|
||||
rx_chain_mask : 8;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define MACTX_PHY_DESC_RESERVED_0A_OFFSET 0x0000000000000000
|
||||
#define MACTX_PHY_DESC_RESERVED_0A_LSB 0
|
||||
#define MACTX_PHY_DESC_RESERVED_0A_MSB 15
|
||||
#define MACTX_PHY_DESC_RESERVED_0A_MASK 0x000000000000ffff
|
||||
|
||||
#define MACTX_PHY_DESC_BF_TYPE_OFFSET 0x0000000000000000
|
||||
#define MACTX_PHY_DESC_BF_TYPE_LSB 16
|
||||
#define MACTX_PHY_DESC_BF_TYPE_MSB 17
|
||||
#define MACTX_PHY_DESC_BF_TYPE_MASK 0x0000000000030000
|
||||
|
||||
#define MACTX_PHY_DESC_WAIT_SIFS_OFFSET 0x0000000000000000
|
||||
#define MACTX_PHY_DESC_WAIT_SIFS_LSB 18
|
||||
#define MACTX_PHY_DESC_WAIT_SIFS_MSB 19
|
||||
#define MACTX_PHY_DESC_WAIT_SIFS_MASK 0x00000000000c0000
|
||||
|
||||
#define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_OFFSET 0x0000000000000000
|
||||
#define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_LSB 20
|
||||
#define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_MSB 20
|
||||
#define MACTX_PHY_DESC_DOT11B_PREAMBLE_TYPE_MASK 0x0000000000100000
|
||||
|
||||
#define MACTX_PHY_DESC_PKT_TYPE_OFFSET 0x0000000000000000
|
||||
#define MACTX_PHY_DESC_PKT_TYPE_LSB 21
|
||||
#define MACTX_PHY_DESC_PKT_TYPE_MSB 24
|
||||
#define MACTX_PHY_DESC_PKT_TYPE_MASK 0x0000000001e00000
|
||||
|
||||
#define MACTX_PHY_DESC_SU_OR_MU_OFFSET 0x0000000000000000
|
||||
#define MACTX_PHY_DESC_SU_OR_MU_LSB 25
|
||||
#define MACTX_PHY_DESC_SU_OR_MU_MSB 26
|
||||
#define MACTX_PHY_DESC_SU_OR_MU_MASK 0x0000000006000000
|
||||
|
||||
#define MACTX_PHY_DESC_MU_TYPE_OFFSET 0x0000000000000000
|
||||
#define MACTX_PHY_DESC_MU_TYPE_LSB 27
|
||||
#define MACTX_PHY_DESC_MU_TYPE_MSB 27
|
||||
#define MACTX_PHY_DESC_MU_TYPE_MASK 0x0000000008000000
|
||||
|
||||
#define MACTX_PHY_DESC_BANDWIDTH_OFFSET 0x0000000000000000
|
||||
#define MACTX_PHY_DESC_BANDWIDTH_LSB 28
|
||||
#define MACTX_PHY_DESC_BANDWIDTH_MSB 30
|
||||
#define MACTX_PHY_DESC_BANDWIDTH_MASK 0x0000000070000000
|
||||
|
||||
#define MACTX_PHY_DESC_CHANNEL_CAPTURE_OFFSET 0x0000000000000000
|
||||
#define MACTX_PHY_DESC_CHANNEL_CAPTURE_LSB 31
|
||||
#define MACTX_PHY_DESC_CHANNEL_CAPTURE_MSB 31
|
||||
#define MACTX_PHY_DESC_CHANNEL_CAPTURE_MASK 0x0000000080000000
|
||||
|
||||
#define MACTX_PHY_DESC_MCS_OFFSET 0x0000000000000000
|
||||
#define MACTX_PHY_DESC_MCS_LSB 32
|
||||
#define MACTX_PHY_DESC_MCS_MSB 35
|
||||
#define MACTX_PHY_DESC_MCS_MASK 0x0000000f00000000
|
||||
|
||||
#define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_OFFSET 0x0000000000000000
|
||||
#define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_LSB 36
|
||||
#define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_MSB 36
|
||||
#define MACTX_PHY_DESC_GLOBAL_OFDMA_MIMO_ENABLE_MASK 0x0000001000000000
|
||||
|
||||
#define MACTX_PHY_DESC_RESERVED_1A_OFFSET 0x0000000000000000
|
||||
#define MACTX_PHY_DESC_RESERVED_1A_LSB 37
|
||||
#define MACTX_PHY_DESC_RESERVED_1A_MSB 37
|
||||
#define MACTX_PHY_DESC_RESERVED_1A_MASK 0x0000002000000000
|
||||
|
||||
#define MACTX_PHY_DESC_STBC_OFFSET 0x0000000000000000
|
||||
#define MACTX_PHY_DESC_STBC_LSB 38
|
||||
#define MACTX_PHY_DESC_STBC_MSB 38
|
||||
#define MACTX_PHY_DESC_STBC_MASK 0x0000004000000000
|
||||
|
||||
#define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000000
|
||||
#define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_LSB 39
|
||||
#define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_MSB 39
|
||||
#define MACTX_PHY_DESC_DOT11AX_SU_EXTENDED_MASK 0x0000008000000000
|
||||
|
||||
#define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_OFFSET 0x0000000000000000
|
||||
#define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_LSB 40
|
||||
#define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_MSB 40
|
||||
#define MACTX_PHY_DESC_DOT11AX_TRIGGER_FRAME_EMBEDDED_MASK 0x0000010000000000
|
||||
|
||||
#define MACTX_PHY_DESC_TX_PWR_SHARED_OFFSET 0x0000000000000000
|
||||
#define MACTX_PHY_DESC_TX_PWR_SHARED_LSB 41
|
||||
#define MACTX_PHY_DESC_TX_PWR_SHARED_MSB 48
|
||||
#define MACTX_PHY_DESC_TX_PWR_SHARED_MASK 0x0001fe0000000000
|
||||
|
||||
#define MACTX_PHY_DESC_TX_PWR_UNSHARED_OFFSET 0x0000000000000000
|
||||
#define MACTX_PHY_DESC_TX_PWR_UNSHARED_LSB 49
|
||||
#define MACTX_PHY_DESC_TX_PWR_UNSHARED_MSB 56
|
||||
#define MACTX_PHY_DESC_TX_PWR_UNSHARED_MASK 0x01fe000000000000
|
||||
|
||||
#define MACTX_PHY_DESC_MEASURE_POWER_OFFSET 0x0000000000000000
|
||||
#define MACTX_PHY_DESC_MEASURE_POWER_LSB 57
|
||||
#define MACTX_PHY_DESC_MEASURE_POWER_MSB 57
|
||||
#define MACTX_PHY_DESC_MEASURE_POWER_MASK 0x0200000000000000
|
||||
|
||||
#define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_OFFSET 0x0000000000000000
|
||||
#define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_LSB 58
|
||||
#define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_MSB 58
|
||||
#define MACTX_PHY_DESC_TPC_GLUT_SELF_CAL_MASK 0x0400000000000000
|
||||
|
||||
#define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_OFFSET 0x0000000000000000
|
||||
#define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_LSB 59
|
||||
#define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_MSB 59
|
||||
#define MACTX_PHY_DESC_BACK_TO_BACK_TRANSMISSION_EXPECTED_MASK 0x0800000000000000
|
||||
|
||||
#define MACTX_PHY_DESC_HEAVY_CLIP_NSS_OFFSET 0x0000000000000000
|
||||
#define MACTX_PHY_DESC_HEAVY_CLIP_NSS_LSB 60
|
||||
#define MACTX_PHY_DESC_HEAVY_CLIP_NSS_MSB 62
|
||||
#define MACTX_PHY_DESC_HEAVY_CLIP_NSS_MASK 0x7000000000000000
|
||||
|
||||
#define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_OFFSET 0x0000000000000000
|
||||
#define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_LSB 63
|
||||
#define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_MSB 63
|
||||
#define MACTX_PHY_DESC_TXBF_PER_PACKET_NO_CSD_NO_WALSH_MASK 0x8000000000000000
|
||||
|
||||
#define MACTX_PHY_DESC_NDP_OFFSET 0x0000000000000008
|
||||
#define MACTX_PHY_DESC_NDP_LSB 0
|
||||
#define MACTX_PHY_DESC_NDP_MSB 1
|
||||
#define MACTX_PHY_DESC_NDP_MASK 0x0000000000000003
|
||||
|
||||
#define MACTX_PHY_DESC_UL_FLAG_OFFSET 0x0000000000000008
|
||||
#define MACTX_PHY_DESC_UL_FLAG_LSB 2
|
||||
#define MACTX_PHY_DESC_UL_FLAG_MSB 2
|
||||
#define MACTX_PHY_DESC_UL_FLAG_MASK 0x0000000000000004
|
||||
|
||||
#define MACTX_PHY_DESC_TRIGGERED_OFFSET 0x0000000000000008
|
||||
#define MACTX_PHY_DESC_TRIGGERED_LSB 3
|
||||
#define MACTX_PHY_DESC_TRIGGERED_MSB 3
|
||||
#define MACTX_PHY_DESC_TRIGGERED_MASK 0x0000000000000008
|
||||
|
||||
#define MACTX_PHY_DESC_AP_PKT_BW_OFFSET 0x0000000000000008
|
||||
#define MACTX_PHY_DESC_AP_PKT_BW_LSB 4
|
||||
#define MACTX_PHY_DESC_AP_PKT_BW_MSB 6
|
||||
#define MACTX_PHY_DESC_AP_PKT_BW_MASK 0x0000000000000070
|
||||
|
||||
#define MACTX_PHY_DESC_RU_POSITION_START_OFFSET 0x0000000000000008
|
||||
#define MACTX_PHY_DESC_RU_POSITION_START_LSB 7
|
||||
#define MACTX_PHY_DESC_RU_POSITION_START_MSB 14
|
||||
#define MACTX_PHY_DESC_RU_POSITION_START_MASK 0x0000000000007f80
|
||||
|
||||
#define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_OFFSET 0x0000000000000008
|
||||
#define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_LSB 15
|
||||
#define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_MSB 17
|
||||
#define MACTX_PHY_DESC_PCU_PPDU_SETUP_START_REASON_MASK 0x0000000000038000
|
||||
|
||||
#define MACTX_PHY_DESC_TLV_SOURCE_OFFSET 0x0000000000000008
|
||||
#define MACTX_PHY_DESC_TLV_SOURCE_LSB 18
|
||||
#define MACTX_PHY_DESC_TLV_SOURCE_MSB 18
|
||||
#define MACTX_PHY_DESC_TLV_SOURCE_MASK 0x0000000000040000
|
||||
|
||||
#define MACTX_PHY_DESC_RESERVED_2A_OFFSET 0x0000000000000008
|
||||
#define MACTX_PHY_DESC_RESERVED_2A_LSB 19
|
||||
#define MACTX_PHY_DESC_RESERVED_2A_MSB 20
|
||||
#define MACTX_PHY_DESC_RESERVED_2A_MASK 0x0000000000180000
|
||||
|
||||
#define MACTX_PHY_DESC_NSS_OFFSET 0x0000000000000008
|
||||
#define MACTX_PHY_DESC_NSS_LSB 21
|
||||
#define MACTX_PHY_DESC_NSS_MSB 23
|
||||
#define MACTX_PHY_DESC_NSS_MASK 0x0000000000e00000
|
||||
|
||||
#define MACTX_PHY_DESC_STREAM_OFFSET_OFFSET 0x0000000000000008
|
||||
#define MACTX_PHY_DESC_STREAM_OFFSET_LSB 24
|
||||
#define MACTX_PHY_DESC_STREAM_OFFSET_MSB 26
|
||||
#define MACTX_PHY_DESC_STREAM_OFFSET_MASK 0x0000000007000000
|
||||
|
||||
#define MACTX_PHY_DESC_RESERVED_2B_OFFSET 0x0000000000000008
|
||||
#define MACTX_PHY_DESC_RESERVED_2B_LSB 27
|
||||
#define MACTX_PHY_DESC_RESERVED_2B_MSB 28
|
||||
#define MACTX_PHY_DESC_RESERVED_2B_MASK 0x0000000018000000
|
||||
|
||||
#define MACTX_PHY_DESC_CLPC_ENABLE_OFFSET 0x0000000000000008
|
||||
#define MACTX_PHY_DESC_CLPC_ENABLE_LSB 29
|
||||
#define MACTX_PHY_DESC_CLPC_ENABLE_MSB 29
|
||||
#define MACTX_PHY_DESC_CLPC_ENABLE_MASK 0x0000000020000000
|
||||
|
||||
#define MACTX_PHY_DESC_MU_NDP_OFFSET 0x0000000000000008
|
||||
#define MACTX_PHY_DESC_MU_NDP_LSB 30
|
||||
#define MACTX_PHY_DESC_MU_NDP_MSB 30
|
||||
#define MACTX_PHY_DESC_MU_NDP_MASK 0x0000000040000000
|
||||
|
||||
#define MACTX_PHY_DESC_RESPONSE_EXPECTED_OFFSET 0x0000000000000008
|
||||
#define MACTX_PHY_DESC_RESPONSE_EXPECTED_LSB 31
|
||||
#define MACTX_PHY_DESC_RESPONSE_EXPECTED_MSB 31
|
||||
#define MACTX_PHY_DESC_RESPONSE_EXPECTED_MASK 0x0000000080000000
|
||||
|
||||
#define MACTX_PHY_DESC_RX_CHAIN_MASK_OFFSET 0x0000000000000008
|
||||
#define MACTX_PHY_DESC_RX_CHAIN_MASK_LSB 32
|
||||
#define MACTX_PHY_DESC_RX_CHAIN_MASK_MSB 39
|
||||
#define MACTX_PHY_DESC_RX_CHAIN_MASK_MASK 0x000000ff00000000
|
||||
|
||||
#define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_OFFSET 0x0000000000000008
|
||||
#define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_LSB 40
|
||||
#define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_MSB 40
|
||||
#define MACTX_PHY_DESC_RX_CHAIN_MASK_VALID_MASK 0x0000010000000000
|
||||
|
||||
#define MACTX_PHY_DESC_ANT_SEL_VALID_OFFSET 0x0000000000000008
|
||||
#define MACTX_PHY_DESC_ANT_SEL_VALID_LSB 41
|
||||
#define MACTX_PHY_DESC_ANT_SEL_VALID_MSB 41
|
||||
#define MACTX_PHY_DESC_ANT_SEL_VALID_MASK 0x0000020000000000
|
||||
|
||||
#define MACTX_PHY_DESC_ANT_SEL_OFFSET 0x0000000000000008
|
||||
#define MACTX_PHY_DESC_ANT_SEL_LSB 42
|
||||
#define MACTX_PHY_DESC_ANT_SEL_MSB 42
|
||||
#define MACTX_PHY_DESC_ANT_SEL_MASK 0x0000040000000000
|
||||
|
||||
#define MACTX_PHY_DESC_CP_SETTING_OFFSET 0x0000000000000008
|
||||
#define MACTX_PHY_DESC_CP_SETTING_LSB 43
|
||||
#define MACTX_PHY_DESC_CP_SETTING_MSB 44
|
||||
#define MACTX_PHY_DESC_CP_SETTING_MASK 0x0000180000000000
|
||||
|
||||
#define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_OFFSET 0x0000000000000008
|
||||
#define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_LSB 45
|
||||
#define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_MSB 46
|
||||
#define MACTX_PHY_DESC_HE_PPDU_SUBTYPE_MASK 0x0000600000000000
|
||||
|
||||
#define MACTX_PHY_DESC_ACTIVE_CHANNEL_OFFSET 0x0000000000000008
|
||||
#define MACTX_PHY_DESC_ACTIVE_CHANNEL_LSB 47
|
||||
#define MACTX_PHY_DESC_ACTIVE_CHANNEL_MSB 49
|
||||
#define MACTX_PHY_DESC_ACTIVE_CHANNEL_MASK 0x0003800000000000
|
||||
|
||||
#define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_OFFSET 0x0000000000000008
|
||||
#define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_LSB 50
|
||||
#define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_MSB 50
|
||||
#define MACTX_PHY_DESC_GENERATE_PHYRX_TX_START_TIMING_MASK 0x0004000000000000
|
||||
|
||||
#define MACTX_PHY_DESC_LTF_SIZE_OFFSET 0x0000000000000008
|
||||
#define MACTX_PHY_DESC_LTF_SIZE_LSB 51
|
||||
#define MACTX_PHY_DESC_LTF_SIZE_MSB 52
|
||||
#define MACTX_PHY_DESC_LTF_SIZE_MASK 0x0018000000000000
|
||||
|
||||
#define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_OFFSET 0x0000000000000008
|
||||
#define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_LSB 53
|
||||
#define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_MSB 56
|
||||
#define MACTX_PHY_DESC_RU_SIZE_UPDATED_V2_MASK 0x01e0000000000000
|
||||
|
||||
#define MACTX_PHY_DESC_RESERVED_3C_OFFSET 0x0000000000000008
|
||||
#define MACTX_PHY_DESC_RESERVED_3C_LSB 57
|
||||
#define MACTX_PHY_DESC_RESERVED_3C_MSB 57
|
||||
#define MACTX_PHY_DESC_RESERVED_3C_MASK 0x0200000000000000
|
||||
|
||||
#define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000008
|
||||
#define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 58
|
||||
#define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 63
|
||||
#define MACTX_PHY_DESC_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc00000000000000
|
||||
|
||||
#endif
|
||||
138
hw/kiwi/v2/mactx_u_sig_eht_su_mu.h
Normal file
138
hw/kiwi/v2/mactx_u_sig_eht_su_mu.h
Normal file
|
|
@ -0,0 +1,138 @@
|
|||
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
#ifndef _MACTX_U_SIG_EHT_SU_MU_H_
|
||||
#define _MACTX_U_SIG_EHT_SU_MU_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#include "u_sig_eht_su_mu_info.h"
|
||||
#define NUM_OF_DWORDS_MACTX_U_SIG_EHT_SU_MU 2
|
||||
|
||||
#define NUM_OF_QWORDS_MACTX_U_SIG_EHT_SU_MU 1
|
||||
|
||||
struct mactx_u_sig_eht_su_mu {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
struct u_sig_eht_su_mu_info mactx_u_sig_eht_su_mu_info_details;
|
||||
#else
|
||||
struct u_sig_eht_su_mu_info mactx_u_sig_eht_su_mu_info_details;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PHY_VERSION_OFFSET 0x0000000000000000
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PHY_VERSION_LSB 0
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PHY_VERSION_MSB 2
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PHY_VERSION_MASK 0x0000000000000007
|
||||
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x0000000000000000
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TRANSMIT_BW_LSB 3
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TRANSMIT_BW_MSB 5
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TRANSMIT_BW_MASK 0x0000000000000038
|
||||
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x0000000000000000
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DL_UL_FLAG_LSB 6
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DL_UL_FLAG_MSB 6
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DL_UL_FLAG_MASK 0x0000000000000040
|
||||
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x0000000000000000
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_BSS_COLOR_ID_LSB 7
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_BSS_COLOR_ID_MSB 12
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_BSS_COLOR_ID_MASK 0x0000000000001f80
|
||||
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TXOP_DURATION_LSB 13
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TXOP_DURATION_MSB 19
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TXOP_DURATION_MASK 0x00000000000fe000
|
||||
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DISREGARD_0A_OFFSET 0x0000000000000000
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DISREGARD_0A_LSB 20
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DISREGARD_0A_MSB 24
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DISREGARD_0A_MASK 0x0000000001f00000
|
||||
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_0B_OFFSET 0x0000000000000000
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_0B_LSB 25
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_0B_MSB 25
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_0B_MASK 0x0000000002000000
|
||||
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_0C_OFFSET 0x0000000000000000
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_0C_LSB 26
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_0C_MSB 31
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_0C_MASK 0x00000000fc000000
|
||||
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_OFFSET 0x0000000000000000
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_LSB 32
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_MSB 33
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_MASK 0x0000000300000000
|
||||
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1A_OFFSET 0x0000000000000000
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1A_LSB 34
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1A_MSB 34
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1A_MASK 0x0000000400000000
|
||||
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PUNCTURED_CHANNEL_INFORMATION_OFFSET 0x0000000000000000
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PUNCTURED_CHANNEL_INFORMATION_LSB 35
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PUNCTURED_CHANNEL_INFORMATION_MSB 39
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_PUNCTURED_CHANNEL_INFORMATION_MASK 0x000000f800000000
|
||||
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1B_OFFSET 0x0000000000000000
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1B_LSB 40
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1B_MSB 40
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_VALIDATE_1B_MASK 0x0000010000000000
|
||||
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_MCS_OF_EHT_SIG_OFFSET 0x0000000000000000
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_MCS_OF_EHT_SIG_LSB 41
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_MCS_OF_EHT_SIG_MSB 42
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_MCS_OF_EHT_SIG_MASK 0x0000060000000000
|
||||
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_NUM_EHT_SIG_SYMBOLS_OFFSET 0x0000000000000000
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_NUM_EHT_SIG_SYMBOLS_LSB 43
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_NUM_EHT_SIG_SYMBOLS_MSB 47
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_NUM_EHT_SIG_SYMBOLS_MASK 0x0000f80000000000
|
||||
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_CRC_OFFSET 0x0000000000000000
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_CRC_LSB 48
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_CRC_MSB 51
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_CRC_MASK 0x000f000000000000
|
||||
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TAIL_LSB 52
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TAIL_MSB 57
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_TAIL_MASK 0x03f0000000000000
|
||||
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000000
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DOT11AX_SU_EXTENDED_LSB 58
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MSB 58
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_DOT11AX_SU_EXTENDED_MASK 0x0400000000000000
|
||||
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_1D_OFFSET 0x0000000000000000
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_1D_LSB 59
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_1D_MSB 61
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RESERVED_1D_MASK 0x3800000000000000
|
||||
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_NDP_OFFSET 0x0000000000000000
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_NDP_LSB 62
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_NDP_MSB 62
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_NDP_MASK 0x4000000000000000
|
||||
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63
|
||||
#define MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000
|
||||
|
||||
#endif
|
||||
113
hw/kiwi/v2/mactx_u_sig_eht_tb.h
Normal file
113
hw/kiwi/v2/mactx_u_sig_eht_tb.h
Normal file
|
|
@ -0,0 +1,113 @@
|
|||
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
#ifndef _MACTX_U_SIG_EHT_TB_H_
|
||||
#define _MACTX_U_SIG_EHT_TB_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#include "u_sig_eht_tb_info.h"
|
||||
#define NUM_OF_DWORDS_MACTX_U_SIG_EHT_TB 2
|
||||
|
||||
#define NUM_OF_QWORDS_MACTX_U_SIG_EHT_TB 1
|
||||
|
||||
struct mactx_u_sig_eht_tb {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
struct u_sig_eht_tb_info mactx_u_sig_eht_tb_info_details;
|
||||
#else
|
||||
struct u_sig_eht_tb_info mactx_u_sig_eht_tb_info_details;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_PHY_VERSION_OFFSET 0x0000000000000000
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_PHY_VERSION_LSB 0
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_PHY_VERSION_MSB 2
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_PHY_VERSION_MASK 0x0000000000000007
|
||||
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TRANSMIT_BW_OFFSET 0x0000000000000000
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TRANSMIT_BW_LSB 3
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TRANSMIT_BW_MSB 5
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TRANSMIT_BW_MASK 0x0000000000000038
|
||||
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DL_UL_FLAG_OFFSET 0x0000000000000000
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DL_UL_FLAG_LSB 6
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DL_UL_FLAG_MSB 6
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DL_UL_FLAG_MASK 0x0000000000000040
|
||||
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_BSS_COLOR_ID_OFFSET 0x0000000000000000
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_BSS_COLOR_ID_LSB 7
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_BSS_COLOR_ID_MSB 12
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_BSS_COLOR_ID_MASK 0x0000000000001f80
|
||||
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TXOP_DURATION_OFFSET 0x0000000000000000
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TXOP_DURATION_LSB 13
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TXOP_DURATION_MSB 19
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TXOP_DURATION_MASK 0x00000000000fe000
|
||||
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_0A_OFFSET 0x0000000000000000
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_0A_LSB 20
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_0A_MSB 25
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_0A_MASK 0x0000000003f00000
|
||||
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_0C_OFFSET 0x0000000000000000
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_0C_LSB 26
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_0C_MSB 31
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_0C_MASK 0x00000000fc000000
|
||||
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_OFFSET 0x0000000000000000
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_LSB 32
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_MSB 33
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_EHT_PPDU_SIG_CMN_TYPE_MASK 0x0000000300000000
|
||||
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_VALIDATE_1A_OFFSET 0x0000000000000000
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_VALIDATE_1A_LSB 34
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_VALIDATE_1A_MSB 34
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_VALIDATE_1A_MASK 0x0000000400000000
|
||||
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000000
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_SPATIAL_REUSE_LSB 35
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_SPATIAL_REUSE_MSB 42
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_SPATIAL_REUSE_MASK 0x000007f800000000
|
||||
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_1B_OFFSET 0x0000000000000000
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_1B_LSB 43
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_1B_MSB 47
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_DISREGARD_1B_MASK 0x0000f80000000000
|
||||
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_CRC_OFFSET 0x0000000000000000
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_CRC_LSB 48
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_CRC_MSB 51
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_CRC_MASK 0x000f000000000000
|
||||
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TAIL_LSB 52
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TAIL_MSB 57
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_TAIL_MASK 0x03f0000000000000
|
||||
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_1C_OFFSET 0x0000000000000000
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_1C_LSB 58
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_1C_MSB 62
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RESERVED_1C_MASK 0x7c00000000000000
|
||||
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63
|
||||
#define MACTX_U_SIG_EHT_TB_MACTX_U_SIG_EHT_TB_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000
|
||||
|
||||
#endif
|
||||
484
hw/kiwi/v2/mactx_user_desc_common.h
Normal file
484
hw/kiwi/v2/mactx_user_desc_common.h
Normal file
|
|
@ -0,0 +1,484 @@
|
|||
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
#ifndef _MACTX_USER_DESC_COMMON_H_
|
||||
#define _MACTX_USER_DESC_COMMON_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#include "unallocated_ru_160_info.h"
|
||||
#include "ru_allocation_160_info.h"
|
||||
#define NUM_OF_DWORDS_MACTX_USER_DESC_COMMON 16
|
||||
|
||||
#define NUM_OF_QWORDS_MACTX_USER_DESC_COMMON 8
|
||||
|
||||
struct mactx_user_desc_common {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t num_users : 6,
|
||||
reserved_0b : 5,
|
||||
ltf_size : 2,
|
||||
reserved_0c : 3,
|
||||
he_stf_long : 1,
|
||||
reserved_0d : 7,
|
||||
num_users_he_sigb_band0 : 8;
|
||||
uint32_t num_ltf_symbols : 3,
|
||||
reserved_1a : 5,
|
||||
num_users_he_sigb_band1 : 8,
|
||||
reserved_1b : 16;
|
||||
uint32_t packet_extension_a_factor : 2,
|
||||
packet_extension_pe_disambiguity : 1,
|
||||
packet_extension : 3,
|
||||
reserved : 2,
|
||||
he_sigb_dcm : 1,
|
||||
reserved_2b : 7,
|
||||
he_sigb_compression : 1,
|
||||
reserved_2c : 15;
|
||||
uint32_t he_sigb_0_mcs : 3,
|
||||
reserved_3a : 13,
|
||||
num_he_sigb_sym : 5,
|
||||
center_ru_0 : 1,
|
||||
center_ru_1 : 1,
|
||||
reserved_3b : 1,
|
||||
ftm_en : 1,
|
||||
pe_nss : 3,
|
||||
pe_ltf_size : 2,
|
||||
pe_content : 1,
|
||||
pe_chain_csd_en : 1;
|
||||
struct ru_allocation_160_info ru_allocation_0123_details;
|
||||
struct ru_allocation_160_info ru_allocation_4567_details;
|
||||
struct unallocated_ru_160_info ru_allocation_160_0_details;
|
||||
struct unallocated_ru_160_info ru_allocation_160_1_details;
|
||||
uint32_t num_data_symbols : 16,
|
||||
ndp_ru_tone_set_index : 7,
|
||||
ndp_feedback_status : 1,
|
||||
doppler_indication : 1,
|
||||
reserved_14a : 7;
|
||||
uint32_t spatial_reuse : 16,
|
||||
reserved_15a : 16;
|
||||
#else
|
||||
uint32_t num_users_he_sigb_band0 : 8,
|
||||
reserved_0d : 7,
|
||||
he_stf_long : 1,
|
||||
reserved_0c : 3,
|
||||
ltf_size : 2,
|
||||
reserved_0b : 5,
|
||||
num_users : 6;
|
||||
uint32_t reserved_1b : 16,
|
||||
num_users_he_sigb_band1 : 8,
|
||||
reserved_1a : 5,
|
||||
num_ltf_symbols : 3;
|
||||
uint32_t reserved_2c : 15,
|
||||
he_sigb_compression : 1,
|
||||
reserved_2b : 7,
|
||||
he_sigb_dcm : 1,
|
||||
reserved : 2,
|
||||
packet_extension : 3,
|
||||
packet_extension_pe_disambiguity : 1,
|
||||
packet_extension_a_factor : 2;
|
||||
uint32_t pe_chain_csd_en : 1,
|
||||
pe_content : 1,
|
||||
pe_ltf_size : 2,
|
||||
pe_nss : 3,
|
||||
ftm_en : 1,
|
||||
reserved_3b : 1,
|
||||
center_ru_1 : 1,
|
||||
center_ru_0 : 1,
|
||||
num_he_sigb_sym : 5,
|
||||
reserved_3a : 13,
|
||||
he_sigb_0_mcs : 3;
|
||||
struct ru_allocation_160_info ru_allocation_0123_details;
|
||||
struct ru_allocation_160_info ru_allocation_4567_details;
|
||||
struct unallocated_ru_160_info ru_allocation_160_0_details;
|
||||
struct unallocated_ru_160_info ru_allocation_160_1_details;
|
||||
uint32_t reserved_14a : 7,
|
||||
doppler_indication : 1,
|
||||
ndp_feedback_status : 1,
|
||||
ndp_ru_tone_set_index : 7,
|
||||
num_data_symbols : 16;
|
||||
uint32_t reserved_15a : 16,
|
||||
spatial_reuse : 16;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_NUM_USERS_OFFSET 0x0000000000000000
|
||||
#define MACTX_USER_DESC_COMMON_NUM_USERS_LSB 0
|
||||
#define MACTX_USER_DESC_COMMON_NUM_USERS_MSB 5
|
||||
#define MACTX_USER_DESC_COMMON_NUM_USERS_MASK 0x000000000000003f
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_RESERVED_0B_OFFSET 0x0000000000000000
|
||||
#define MACTX_USER_DESC_COMMON_RESERVED_0B_LSB 6
|
||||
#define MACTX_USER_DESC_COMMON_RESERVED_0B_MSB 10
|
||||
#define MACTX_USER_DESC_COMMON_RESERVED_0B_MASK 0x00000000000007c0
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_LTF_SIZE_OFFSET 0x0000000000000000
|
||||
#define MACTX_USER_DESC_COMMON_LTF_SIZE_LSB 11
|
||||
#define MACTX_USER_DESC_COMMON_LTF_SIZE_MSB 12
|
||||
#define MACTX_USER_DESC_COMMON_LTF_SIZE_MASK 0x0000000000001800
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_RESERVED_0C_OFFSET 0x0000000000000000
|
||||
#define MACTX_USER_DESC_COMMON_RESERVED_0C_LSB 13
|
||||
#define MACTX_USER_DESC_COMMON_RESERVED_0C_MSB 15
|
||||
#define MACTX_USER_DESC_COMMON_RESERVED_0C_MASK 0x000000000000e000
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_HE_STF_LONG_OFFSET 0x0000000000000000
|
||||
#define MACTX_USER_DESC_COMMON_HE_STF_LONG_LSB 16
|
||||
#define MACTX_USER_DESC_COMMON_HE_STF_LONG_MSB 16
|
||||
#define MACTX_USER_DESC_COMMON_HE_STF_LONG_MASK 0x0000000000010000
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_RESERVED_0D_OFFSET 0x0000000000000000
|
||||
#define MACTX_USER_DESC_COMMON_RESERVED_0D_LSB 17
|
||||
#define MACTX_USER_DESC_COMMON_RESERVED_0D_MSB 23
|
||||
#define MACTX_USER_DESC_COMMON_RESERVED_0D_MASK 0x0000000000fe0000
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND0_OFFSET 0x0000000000000000
|
||||
#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND0_LSB 24
|
||||
#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND0_MSB 31
|
||||
#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND0_MASK 0x00000000ff000000
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_NUM_LTF_SYMBOLS_OFFSET 0x0000000000000000
|
||||
#define MACTX_USER_DESC_COMMON_NUM_LTF_SYMBOLS_LSB 32
|
||||
#define MACTX_USER_DESC_COMMON_NUM_LTF_SYMBOLS_MSB 34
|
||||
#define MACTX_USER_DESC_COMMON_NUM_LTF_SYMBOLS_MASK 0x0000000700000000
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_RESERVED_1A_OFFSET 0x0000000000000000
|
||||
#define MACTX_USER_DESC_COMMON_RESERVED_1A_LSB 35
|
||||
#define MACTX_USER_DESC_COMMON_RESERVED_1A_MSB 39
|
||||
#define MACTX_USER_DESC_COMMON_RESERVED_1A_MASK 0x000000f800000000
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND1_OFFSET 0x0000000000000000
|
||||
#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND1_LSB 40
|
||||
#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND1_MSB 47
|
||||
#define MACTX_USER_DESC_COMMON_NUM_USERS_HE_SIGB_BAND1_MASK 0x0000ff0000000000
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_RESERVED_1B_OFFSET 0x0000000000000000
|
||||
#define MACTX_USER_DESC_COMMON_RESERVED_1B_LSB 48
|
||||
#define MACTX_USER_DESC_COMMON_RESERVED_1B_MSB 63
|
||||
#define MACTX_USER_DESC_COMMON_RESERVED_1B_MASK 0xffff000000000000
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000000000000008
|
||||
#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_A_FACTOR_LSB 0
|
||||
#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_A_FACTOR_MSB 1
|
||||
#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_A_FACTOR_MASK 0x0000000000000003
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000000000000008
|
||||
#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 2
|
||||
#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 2
|
||||
#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x0000000000000004
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_OFFSET 0x0000000000000008
|
||||
#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_LSB 3
|
||||
#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_MSB 5
|
||||
#define MACTX_USER_DESC_COMMON_PACKET_EXTENSION_MASK 0x0000000000000038
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_RESERVED_OFFSET 0x0000000000000008
|
||||
#define MACTX_USER_DESC_COMMON_RESERVED_LSB 6
|
||||
#define MACTX_USER_DESC_COMMON_RESERVED_MSB 7
|
||||
#define MACTX_USER_DESC_COMMON_RESERVED_MASK 0x00000000000000c0
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_HE_SIGB_DCM_OFFSET 0x0000000000000008
|
||||
#define MACTX_USER_DESC_COMMON_HE_SIGB_DCM_LSB 8
|
||||
#define MACTX_USER_DESC_COMMON_HE_SIGB_DCM_MSB 8
|
||||
#define MACTX_USER_DESC_COMMON_HE_SIGB_DCM_MASK 0x0000000000000100
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_RESERVED_2B_OFFSET 0x0000000000000008
|
||||
#define MACTX_USER_DESC_COMMON_RESERVED_2B_LSB 9
|
||||
#define MACTX_USER_DESC_COMMON_RESERVED_2B_MSB 15
|
||||
#define MACTX_USER_DESC_COMMON_RESERVED_2B_MASK 0x000000000000fe00
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_HE_SIGB_COMPRESSION_OFFSET 0x0000000000000008
|
||||
#define MACTX_USER_DESC_COMMON_HE_SIGB_COMPRESSION_LSB 16
|
||||
#define MACTX_USER_DESC_COMMON_HE_SIGB_COMPRESSION_MSB 16
|
||||
#define MACTX_USER_DESC_COMMON_HE_SIGB_COMPRESSION_MASK 0x0000000000010000
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_RESERVED_2C_OFFSET 0x0000000000000008
|
||||
#define MACTX_USER_DESC_COMMON_RESERVED_2C_LSB 17
|
||||
#define MACTX_USER_DESC_COMMON_RESERVED_2C_MSB 31
|
||||
#define MACTX_USER_DESC_COMMON_RESERVED_2C_MASK 0x00000000fffe0000
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_HE_SIGB_0_MCS_OFFSET 0x0000000000000008
|
||||
#define MACTX_USER_DESC_COMMON_HE_SIGB_0_MCS_LSB 32
|
||||
#define MACTX_USER_DESC_COMMON_HE_SIGB_0_MCS_MSB 34
|
||||
#define MACTX_USER_DESC_COMMON_HE_SIGB_0_MCS_MASK 0x0000000700000000
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_RESERVED_3A_OFFSET 0x0000000000000008
|
||||
#define MACTX_USER_DESC_COMMON_RESERVED_3A_LSB 35
|
||||
#define MACTX_USER_DESC_COMMON_RESERVED_3A_MSB 47
|
||||
#define MACTX_USER_DESC_COMMON_RESERVED_3A_MASK 0x0000fff800000000
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_NUM_HE_SIGB_SYM_OFFSET 0x0000000000000008
|
||||
#define MACTX_USER_DESC_COMMON_NUM_HE_SIGB_SYM_LSB 48
|
||||
#define MACTX_USER_DESC_COMMON_NUM_HE_SIGB_SYM_MSB 52
|
||||
#define MACTX_USER_DESC_COMMON_NUM_HE_SIGB_SYM_MASK 0x001f000000000000
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_CENTER_RU_0_OFFSET 0x0000000000000008
|
||||
#define MACTX_USER_DESC_COMMON_CENTER_RU_0_LSB 53
|
||||
#define MACTX_USER_DESC_COMMON_CENTER_RU_0_MSB 53
|
||||
#define MACTX_USER_DESC_COMMON_CENTER_RU_0_MASK 0x0020000000000000
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_CENTER_RU_1_OFFSET 0x0000000000000008
|
||||
#define MACTX_USER_DESC_COMMON_CENTER_RU_1_LSB 54
|
||||
#define MACTX_USER_DESC_COMMON_CENTER_RU_1_MSB 54
|
||||
#define MACTX_USER_DESC_COMMON_CENTER_RU_1_MASK 0x0040000000000000
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_RESERVED_3B_OFFSET 0x0000000000000008
|
||||
#define MACTX_USER_DESC_COMMON_RESERVED_3B_LSB 55
|
||||
#define MACTX_USER_DESC_COMMON_RESERVED_3B_MSB 55
|
||||
#define MACTX_USER_DESC_COMMON_RESERVED_3B_MASK 0x0080000000000000
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_FTM_EN_OFFSET 0x0000000000000008
|
||||
#define MACTX_USER_DESC_COMMON_FTM_EN_LSB 56
|
||||
#define MACTX_USER_DESC_COMMON_FTM_EN_MSB 56
|
||||
#define MACTX_USER_DESC_COMMON_FTM_EN_MASK 0x0100000000000000
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_PE_NSS_OFFSET 0x0000000000000008
|
||||
#define MACTX_USER_DESC_COMMON_PE_NSS_LSB 57
|
||||
#define MACTX_USER_DESC_COMMON_PE_NSS_MSB 59
|
||||
#define MACTX_USER_DESC_COMMON_PE_NSS_MASK 0x0e00000000000000
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_PE_LTF_SIZE_OFFSET 0x0000000000000008
|
||||
#define MACTX_USER_DESC_COMMON_PE_LTF_SIZE_LSB 60
|
||||
#define MACTX_USER_DESC_COMMON_PE_LTF_SIZE_MSB 61
|
||||
#define MACTX_USER_DESC_COMMON_PE_LTF_SIZE_MASK 0x3000000000000000
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_PE_CONTENT_OFFSET 0x0000000000000008
|
||||
#define MACTX_USER_DESC_COMMON_PE_CONTENT_LSB 62
|
||||
#define MACTX_USER_DESC_COMMON_PE_CONTENT_MSB 62
|
||||
#define MACTX_USER_DESC_COMMON_PE_CONTENT_MASK 0x4000000000000000
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_PE_CHAIN_CSD_EN_OFFSET 0x0000000000000008
|
||||
#define MACTX_USER_DESC_COMMON_PE_CHAIN_CSD_EN_LSB 63
|
||||
#define MACTX_USER_DESC_COMMON_PE_CHAIN_CSD_EN_MSB 63
|
||||
#define MACTX_USER_DESC_COMMON_PE_CHAIN_CSD_EN_MASK 0x8000000000000000
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_0_OFFSET 0x0000000000000010
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_0_LSB 0
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_0_MSB 8
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_0_MASK 0x00000000000001ff
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_1_OFFSET 0x0000000000000010
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_1_LSB 9
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_1_MSB 17
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_1_MASK 0x000000000003fe00
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_0A_OFFSET 0x0000000000000010
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_0A_LSB 18
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_0A_MSB 23
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_0A_MASK 0x0000000000fc0000
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_OFFSET 0x0000000000000010
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_LSB 24
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_MSB 27
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_MASK 0x000000000f000000
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_OFFSET 0x0000000000000010
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_LSB 28
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_MSB 31
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_MASK 0x00000000f0000000
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_2_OFFSET 0x0000000000000010
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_2_LSB 32
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_2_MSB 40
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_2_MASK 0x000001ff00000000
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_3_OFFSET 0x0000000000000010
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_3_LSB 41
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_3_MSB 49
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_3_MASK 0x0003fe0000000000
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_1A_OFFSET 0x0000000000000010
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_1A_LSB 50
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_1A_MSB 63
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_1A_MASK 0xfffc000000000000
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_0_OFFSET 0x0000000000000018
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_0_LSB 0
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_0_MSB 8
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_0_MASK 0x00000000000001ff
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_1_OFFSET 0x0000000000000018
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_1_LSB 9
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_1_MSB 17
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_1_MASK 0x000000000003fe00
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_2A_OFFSET 0x0000000000000018
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_2A_LSB 18
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_2A_MSB 31
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_2A_MASK 0x00000000fffc0000
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_2_OFFSET 0x0000000000000018
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_2_LSB 32
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_2_MSB 40
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_2_MASK 0x000001ff00000000
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_3_OFFSET 0x0000000000000018
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_3_LSB 41
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_3_MSB 49
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_3_MASK 0x0003fe0000000000
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_3A_OFFSET 0x0000000000000018
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_3A_LSB 50
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_3A_MSB 63
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_0123_DETAILS_RESERVED_3A_MASK 0xfffc000000000000
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_0_OFFSET 0x0000000000000020
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_0_LSB 0
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_0_MSB 8
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_0_MASK 0x00000000000001ff
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_1_OFFSET 0x0000000000000020
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_1_LSB 9
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_1_MSB 17
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_1_MASK 0x000000000003fe00
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_0A_OFFSET 0x0000000000000020
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_0A_LSB 18
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_0A_MSB 23
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_0A_MASK 0x0000000000fc0000
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_OFFSET 0x0000000000000020
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_LSB 24
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_MSB 27
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_01_SUBBAND80_MASK_MASK 0x000000000f000000
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_OFFSET 0x0000000000000020
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_LSB 28
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_MSB 31
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATIONS_23_SUBBAND80_MASK_MASK 0x00000000f0000000
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_2_OFFSET 0x0000000000000020
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_2_LSB 32
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_2_MSB 40
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_2_MASK 0x000001ff00000000
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_3_OFFSET 0x0000000000000020
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_3_LSB 41
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_3_MSB 49
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_3_MASK 0x0003fe0000000000
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_1A_OFFSET 0x0000000000000020
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_1A_LSB 50
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_1A_MSB 63
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_1A_MASK 0xfffc000000000000
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_0_OFFSET 0x0000000000000028
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_0_LSB 0
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_0_MSB 8
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_0_MASK 0x00000000000001ff
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_1_OFFSET 0x0000000000000028
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_1_LSB 9
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_1_MSB 17
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_1_MASK 0x000000000003fe00
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_2A_OFFSET 0x0000000000000028
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_2A_LSB 18
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_2A_MSB 31
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_2A_MASK 0x00000000fffc0000
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_2_OFFSET 0x0000000000000028
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_2_LSB 32
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_2_MSB 40
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_2_MASK 0x000001ff00000000
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_3_OFFSET 0x0000000000000028
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_3_LSB 41
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_3_MSB 49
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_3_MASK 0x0003fe0000000000
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_3A_OFFSET 0x0000000000000028
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_3A_LSB 50
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_3A_MSB 63
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_4567_DETAILS_RESERVED_3A_MASK 0xfffc000000000000
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC0_OFFSET 0x0000000000000030
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC0_LSB 0
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC0_MSB 7
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC0_MASK 0x00000000000000ff
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC1_OFFSET 0x0000000000000030
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC1_LSB 8
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC1_MSB 15
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_0_CC1_MASK 0x000000000000ff00
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC0_OFFSET 0x0000000000000030
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC0_LSB 16
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC0_MSB 23
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC0_MASK 0x0000000000ff0000
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC1_OFFSET 0x0000000000000030
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC1_LSB 24
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC1_MSB 31
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_0_DETAILS_SUBBAND80_1_CC1_MASK 0x00000000ff000000
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC0_OFFSET 0x0000000000000030
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC0_LSB 32
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC0_MSB 39
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC0_MASK 0x000000ff00000000
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC1_OFFSET 0x0000000000000030
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC1_LSB 40
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC1_MSB 47
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_0_CC1_MASK 0x0000ff0000000000
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC0_OFFSET 0x0000000000000030
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC0_LSB 48
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC0_MSB 55
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC0_MASK 0x00ff000000000000
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC1_OFFSET 0x0000000000000030
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC1_LSB 56
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC1_MSB 63
|
||||
#define MACTX_USER_DESC_COMMON_RU_ALLOCATION_160_1_DETAILS_SUBBAND80_1_CC1_MASK 0xff00000000000000
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_NUM_DATA_SYMBOLS_OFFSET 0x0000000000000038
|
||||
#define MACTX_USER_DESC_COMMON_NUM_DATA_SYMBOLS_LSB 0
|
||||
#define MACTX_USER_DESC_COMMON_NUM_DATA_SYMBOLS_MSB 15
|
||||
#define MACTX_USER_DESC_COMMON_NUM_DATA_SYMBOLS_MASK 0x000000000000ffff
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_NDP_RU_TONE_SET_INDEX_OFFSET 0x0000000000000038
|
||||
#define MACTX_USER_DESC_COMMON_NDP_RU_TONE_SET_INDEX_LSB 16
|
||||
#define MACTX_USER_DESC_COMMON_NDP_RU_TONE_SET_INDEX_MSB 22
|
||||
#define MACTX_USER_DESC_COMMON_NDP_RU_TONE_SET_INDEX_MASK 0x00000000007f0000
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_NDP_FEEDBACK_STATUS_OFFSET 0x0000000000000038
|
||||
#define MACTX_USER_DESC_COMMON_NDP_FEEDBACK_STATUS_LSB 23
|
||||
#define MACTX_USER_DESC_COMMON_NDP_FEEDBACK_STATUS_MSB 23
|
||||
#define MACTX_USER_DESC_COMMON_NDP_FEEDBACK_STATUS_MASK 0x0000000000800000
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_DOPPLER_INDICATION_OFFSET 0x0000000000000038
|
||||
#define MACTX_USER_DESC_COMMON_DOPPLER_INDICATION_LSB 24
|
||||
#define MACTX_USER_DESC_COMMON_DOPPLER_INDICATION_MSB 24
|
||||
#define MACTX_USER_DESC_COMMON_DOPPLER_INDICATION_MASK 0x0000000001000000
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_RESERVED_14A_OFFSET 0x0000000000000038
|
||||
#define MACTX_USER_DESC_COMMON_RESERVED_14A_LSB 25
|
||||
#define MACTX_USER_DESC_COMMON_RESERVED_14A_MSB 31
|
||||
#define MACTX_USER_DESC_COMMON_RESERVED_14A_MASK 0x00000000fe000000
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_SPATIAL_REUSE_OFFSET 0x0000000000000038
|
||||
#define MACTX_USER_DESC_COMMON_SPATIAL_REUSE_LSB 32
|
||||
#define MACTX_USER_DESC_COMMON_SPATIAL_REUSE_MSB 47
|
||||
#define MACTX_USER_DESC_COMMON_SPATIAL_REUSE_MASK 0x0000ffff00000000
|
||||
|
||||
#define MACTX_USER_DESC_COMMON_RESERVED_15A_OFFSET 0x0000000000000038
|
||||
#define MACTX_USER_DESC_COMMON_RESERVED_15A_LSB 48
|
||||
#define MACTX_USER_DESC_COMMON_RESERVED_15A_MSB 63
|
||||
#define MACTX_USER_DESC_COMMON_RESERVED_15A_MASK 0xffff000000000000
|
||||
|
||||
#endif
|
||||
196
hw/kiwi/v2/mactx_user_desc_per_user.h
Normal file
196
hw/kiwi/v2/mactx_user_desc_per_user.h
Normal file
|
|
@ -0,0 +1,196 @@
|
|||
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
#ifndef _MACTX_USER_DESC_PER_USER_H_
|
||||
#define _MACTX_USER_DESC_PER_USER_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#define NUM_OF_DWORDS_MACTX_USER_DESC_PER_USER 4
|
||||
|
||||
#define NUM_OF_QWORDS_MACTX_USER_DESC_PER_USER 2
|
||||
|
||||
struct mactx_user_desc_per_user {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t psdu_length : 24,
|
||||
reserved_0a : 8;
|
||||
uint32_t ru_start_index : 8,
|
||||
ru_size : 4,
|
||||
reserved_1b : 4,
|
||||
ofdma_mu_mimo_enabled : 1,
|
||||
nss : 3,
|
||||
stream_offset : 3,
|
||||
reserved_1c : 1,
|
||||
mcs : 4,
|
||||
dcm : 1,
|
||||
reserved_1d : 3;
|
||||
uint32_t fec_type : 1,
|
||||
reserved_2a : 7,
|
||||
user_bf_type : 2,
|
||||
reserved_2b : 6,
|
||||
drop_user_cbf : 1,
|
||||
reserved_2c : 7,
|
||||
ldpc_extra_symbol : 1,
|
||||
force_extra_symbol : 1,
|
||||
reserved_2d : 6;
|
||||
uint32_t sw_peer_id : 16,
|
||||
per_user_subband_mask : 16;
|
||||
#else
|
||||
uint32_t reserved_0a : 8,
|
||||
psdu_length : 24;
|
||||
uint32_t reserved_1d : 3,
|
||||
dcm : 1,
|
||||
mcs : 4,
|
||||
reserved_1c : 1,
|
||||
stream_offset : 3,
|
||||
nss : 3,
|
||||
ofdma_mu_mimo_enabled : 1,
|
||||
reserved_1b : 4,
|
||||
ru_size : 4,
|
||||
ru_start_index : 8;
|
||||
uint32_t reserved_2d : 6,
|
||||
force_extra_symbol : 1,
|
||||
ldpc_extra_symbol : 1,
|
||||
reserved_2c : 7,
|
||||
drop_user_cbf : 1,
|
||||
reserved_2b : 6,
|
||||
user_bf_type : 2,
|
||||
reserved_2a : 7,
|
||||
fec_type : 1;
|
||||
uint32_t per_user_subband_mask : 16,
|
||||
sw_peer_id : 16;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define MACTX_USER_DESC_PER_USER_PSDU_LENGTH_OFFSET 0x0000000000000000
|
||||
#define MACTX_USER_DESC_PER_USER_PSDU_LENGTH_LSB 0
|
||||
#define MACTX_USER_DESC_PER_USER_PSDU_LENGTH_MSB 23
|
||||
#define MACTX_USER_DESC_PER_USER_PSDU_LENGTH_MASK 0x0000000000ffffff
|
||||
|
||||
#define MACTX_USER_DESC_PER_USER_RESERVED_0A_OFFSET 0x0000000000000000
|
||||
#define MACTX_USER_DESC_PER_USER_RESERVED_0A_LSB 24
|
||||
#define MACTX_USER_DESC_PER_USER_RESERVED_0A_MSB 31
|
||||
#define MACTX_USER_DESC_PER_USER_RESERVED_0A_MASK 0x00000000ff000000
|
||||
|
||||
#define MACTX_USER_DESC_PER_USER_RU_START_INDEX_OFFSET 0x0000000000000000
|
||||
#define MACTX_USER_DESC_PER_USER_RU_START_INDEX_LSB 32
|
||||
#define MACTX_USER_DESC_PER_USER_RU_START_INDEX_MSB 39
|
||||
#define MACTX_USER_DESC_PER_USER_RU_START_INDEX_MASK 0x000000ff00000000
|
||||
|
||||
#define MACTX_USER_DESC_PER_USER_RU_SIZE_OFFSET 0x0000000000000000
|
||||
#define MACTX_USER_DESC_PER_USER_RU_SIZE_LSB 40
|
||||
#define MACTX_USER_DESC_PER_USER_RU_SIZE_MSB 43
|
||||
#define MACTX_USER_DESC_PER_USER_RU_SIZE_MASK 0x00000f0000000000
|
||||
|
||||
#define MACTX_USER_DESC_PER_USER_RESERVED_1B_OFFSET 0x0000000000000000
|
||||
#define MACTX_USER_DESC_PER_USER_RESERVED_1B_LSB 44
|
||||
#define MACTX_USER_DESC_PER_USER_RESERVED_1B_MSB 47
|
||||
#define MACTX_USER_DESC_PER_USER_RESERVED_1B_MASK 0x0000f00000000000
|
||||
|
||||
#define MACTX_USER_DESC_PER_USER_OFDMA_MU_MIMO_ENABLED_OFFSET 0x0000000000000000
|
||||
#define MACTX_USER_DESC_PER_USER_OFDMA_MU_MIMO_ENABLED_LSB 48
|
||||
#define MACTX_USER_DESC_PER_USER_OFDMA_MU_MIMO_ENABLED_MSB 48
|
||||
#define MACTX_USER_DESC_PER_USER_OFDMA_MU_MIMO_ENABLED_MASK 0x0001000000000000
|
||||
|
||||
#define MACTX_USER_DESC_PER_USER_NSS_OFFSET 0x0000000000000000
|
||||
#define MACTX_USER_DESC_PER_USER_NSS_LSB 49
|
||||
#define MACTX_USER_DESC_PER_USER_NSS_MSB 51
|
||||
#define MACTX_USER_DESC_PER_USER_NSS_MASK 0x000e000000000000
|
||||
|
||||
#define MACTX_USER_DESC_PER_USER_STREAM_OFFSET_OFFSET 0x0000000000000000
|
||||
#define MACTX_USER_DESC_PER_USER_STREAM_OFFSET_LSB 52
|
||||
#define MACTX_USER_DESC_PER_USER_STREAM_OFFSET_MSB 54
|
||||
#define MACTX_USER_DESC_PER_USER_STREAM_OFFSET_MASK 0x0070000000000000
|
||||
|
||||
#define MACTX_USER_DESC_PER_USER_RESERVED_1C_OFFSET 0x0000000000000000
|
||||
#define MACTX_USER_DESC_PER_USER_RESERVED_1C_LSB 55
|
||||
#define MACTX_USER_DESC_PER_USER_RESERVED_1C_MSB 55
|
||||
#define MACTX_USER_DESC_PER_USER_RESERVED_1C_MASK 0x0080000000000000
|
||||
|
||||
#define MACTX_USER_DESC_PER_USER_MCS_OFFSET 0x0000000000000000
|
||||
#define MACTX_USER_DESC_PER_USER_MCS_LSB 56
|
||||
#define MACTX_USER_DESC_PER_USER_MCS_MSB 59
|
||||
#define MACTX_USER_DESC_PER_USER_MCS_MASK 0x0f00000000000000
|
||||
|
||||
#define MACTX_USER_DESC_PER_USER_DCM_OFFSET 0x0000000000000000
|
||||
#define MACTX_USER_DESC_PER_USER_DCM_LSB 60
|
||||
#define MACTX_USER_DESC_PER_USER_DCM_MSB 60
|
||||
#define MACTX_USER_DESC_PER_USER_DCM_MASK 0x1000000000000000
|
||||
|
||||
#define MACTX_USER_DESC_PER_USER_RESERVED_1D_OFFSET 0x0000000000000000
|
||||
#define MACTX_USER_DESC_PER_USER_RESERVED_1D_LSB 61
|
||||
#define MACTX_USER_DESC_PER_USER_RESERVED_1D_MSB 63
|
||||
#define MACTX_USER_DESC_PER_USER_RESERVED_1D_MASK 0xe000000000000000
|
||||
|
||||
#define MACTX_USER_DESC_PER_USER_FEC_TYPE_OFFSET 0x0000000000000008
|
||||
#define MACTX_USER_DESC_PER_USER_FEC_TYPE_LSB 0
|
||||
#define MACTX_USER_DESC_PER_USER_FEC_TYPE_MSB 0
|
||||
#define MACTX_USER_DESC_PER_USER_FEC_TYPE_MASK 0x0000000000000001
|
||||
|
||||
#define MACTX_USER_DESC_PER_USER_RESERVED_2A_OFFSET 0x0000000000000008
|
||||
#define MACTX_USER_DESC_PER_USER_RESERVED_2A_LSB 1
|
||||
#define MACTX_USER_DESC_PER_USER_RESERVED_2A_MSB 7
|
||||
#define MACTX_USER_DESC_PER_USER_RESERVED_2A_MASK 0x00000000000000fe
|
||||
|
||||
#define MACTX_USER_DESC_PER_USER_USER_BF_TYPE_OFFSET 0x0000000000000008
|
||||
#define MACTX_USER_DESC_PER_USER_USER_BF_TYPE_LSB 8
|
||||
#define MACTX_USER_DESC_PER_USER_USER_BF_TYPE_MSB 9
|
||||
#define MACTX_USER_DESC_PER_USER_USER_BF_TYPE_MASK 0x0000000000000300
|
||||
|
||||
#define MACTX_USER_DESC_PER_USER_RESERVED_2B_OFFSET 0x0000000000000008
|
||||
#define MACTX_USER_DESC_PER_USER_RESERVED_2B_LSB 10
|
||||
#define MACTX_USER_DESC_PER_USER_RESERVED_2B_MSB 15
|
||||
#define MACTX_USER_DESC_PER_USER_RESERVED_2B_MASK 0x000000000000fc00
|
||||
|
||||
#define MACTX_USER_DESC_PER_USER_DROP_USER_CBF_OFFSET 0x0000000000000008
|
||||
#define MACTX_USER_DESC_PER_USER_DROP_USER_CBF_LSB 16
|
||||
#define MACTX_USER_DESC_PER_USER_DROP_USER_CBF_MSB 16
|
||||
#define MACTX_USER_DESC_PER_USER_DROP_USER_CBF_MASK 0x0000000000010000
|
||||
|
||||
#define MACTX_USER_DESC_PER_USER_RESERVED_2C_OFFSET 0x0000000000000008
|
||||
#define MACTX_USER_DESC_PER_USER_RESERVED_2C_LSB 17
|
||||
#define MACTX_USER_DESC_PER_USER_RESERVED_2C_MSB 23
|
||||
#define MACTX_USER_DESC_PER_USER_RESERVED_2C_MASK 0x0000000000fe0000
|
||||
|
||||
#define MACTX_USER_DESC_PER_USER_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000008
|
||||
#define MACTX_USER_DESC_PER_USER_LDPC_EXTRA_SYMBOL_LSB 24
|
||||
#define MACTX_USER_DESC_PER_USER_LDPC_EXTRA_SYMBOL_MSB 24
|
||||
#define MACTX_USER_DESC_PER_USER_LDPC_EXTRA_SYMBOL_MASK 0x0000000001000000
|
||||
|
||||
#define MACTX_USER_DESC_PER_USER_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000008
|
||||
#define MACTX_USER_DESC_PER_USER_FORCE_EXTRA_SYMBOL_LSB 25
|
||||
#define MACTX_USER_DESC_PER_USER_FORCE_EXTRA_SYMBOL_MSB 25
|
||||
#define MACTX_USER_DESC_PER_USER_FORCE_EXTRA_SYMBOL_MASK 0x0000000002000000
|
||||
|
||||
#define MACTX_USER_DESC_PER_USER_RESERVED_2D_OFFSET 0x0000000000000008
|
||||
#define MACTX_USER_DESC_PER_USER_RESERVED_2D_LSB 26
|
||||
#define MACTX_USER_DESC_PER_USER_RESERVED_2D_MSB 31
|
||||
#define MACTX_USER_DESC_PER_USER_RESERVED_2D_MASK 0x00000000fc000000
|
||||
|
||||
#define MACTX_USER_DESC_PER_USER_SW_PEER_ID_OFFSET 0x0000000000000008
|
||||
#define MACTX_USER_DESC_PER_USER_SW_PEER_ID_LSB 32
|
||||
#define MACTX_USER_DESC_PER_USER_SW_PEER_ID_MSB 47
|
||||
#define MACTX_USER_DESC_PER_USER_SW_PEER_ID_MASK 0x0000ffff00000000
|
||||
|
||||
#define MACTX_USER_DESC_PER_USER_PER_USER_SUBBAND_MASK_OFFSET 0x0000000000000008
|
||||
#define MACTX_USER_DESC_PER_USER_PER_USER_SUBBAND_MASK_LSB 48
|
||||
#define MACTX_USER_DESC_PER_USER_PER_USER_SUBBAND_MASK_MSB 63
|
||||
#define MACTX_USER_DESC_PER_USER_PER_USER_SUBBAND_MASK_MASK 0xffff000000000000
|
||||
|
||||
#endif
|
||||
128
hw/kiwi/v2/mactx_vht_sig_a.h
Normal file
128
hw/kiwi/v2/mactx_vht_sig_a.h
Normal file
|
|
@ -0,0 +1,128 @@
|
|||
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
#ifndef _MACTX_VHT_SIG_A_H_
|
||||
#define _MACTX_VHT_SIG_A_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#include "vht_sig_a_info.h"
|
||||
#define NUM_OF_DWORDS_MACTX_VHT_SIG_A 2
|
||||
|
||||
#define NUM_OF_QWORDS_MACTX_VHT_SIG_A 1
|
||||
|
||||
struct mactx_vht_sig_a {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
struct vht_sig_a_info mactx_vht_sig_a_info_details;
|
||||
#else
|
||||
struct vht_sig_a_info mactx_vht_sig_a_info_details;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_LSB 0
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_MSB 1
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_MASK 0x0000000000000003
|
||||
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_LSB 2
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_MSB 2
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0_MASK 0x0000000000000004
|
||||
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_STBC_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_STBC_LSB 3
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_STBC_MSB 3
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_STBC_MASK 0x0000000000000008
|
||||
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_LSB 4
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_MSB 9
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GROUP_ID_MASK 0x00000000000003f0
|
||||
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_N_STS_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_N_STS_LSB 10
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_N_STS_MSB 21
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_N_STS_MASK 0x00000000003ffc00
|
||||
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_LSB 22
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_MSB 22
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TXOP_PS_NOT_ALLOWED_MASK 0x0000000000400000
|
||||
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_LSB 23
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_MSB 23
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_0B_MASK 0x0000000000800000
|
||||
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_LSB 24
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_MSB 31
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_0_MASK 0x00000000ff000000
|
||||
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_LSB 32
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_MSB 33
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_GI_SETTING_MASK 0x0000000300000000
|
||||
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_LSB 34
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_MSB 34
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_SU_MU_CODING_MASK 0x0000000400000000
|
||||
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_LSB 35
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MSB 35
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x0000000800000000
|
||||
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_MCS_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_MCS_LSB 36
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_MCS_MSB 39
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_MCS_MASK 0x000000f000000000
|
||||
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_LSB 40
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_MSB 40
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_BEAMFORMED_MASK 0x0000010000000000
|
||||
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_LSB 41
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_MSB 41
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_VHTA_RESERVED_1_MASK 0x0000020000000000
|
||||
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_CRC_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_CRC_LSB 42
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_CRC_MSB 49
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_CRC_MASK 0x0003fc0000000000
|
||||
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TAIL_LSB 50
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TAIL_MSB 55
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_TAIL_MASK 0x00fc000000000000
|
||||
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_LSB 56
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_MSB 62
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RESERVED_1_MASK 0x7f00000000000000
|
||||
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_LSB 63
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MSB 63
|
||||
#define MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS_RX_INTEGRITY_CHECK_PASSED_MASK 0x8000000000000000
|
||||
|
||||
#endif
|
||||
198
hw/kiwi/v2/mactx_vht_sig_b_mu160.h
Normal file
198
hw/kiwi/v2/mactx_vht_sig_b_mu160.h
Normal file
|
|
@ -0,0 +1,198 @@
|
|||
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
#ifndef _MACTX_VHT_SIG_B_MU160_H_
|
||||
#define _MACTX_VHT_SIG_B_MU160_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#include "vht_sig_b_mu160_info.h"
|
||||
#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_MU160 8
|
||||
|
||||
#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_MU160 4
|
||||
|
||||
struct mactx_vht_sig_b_mu160 {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
struct vht_sig_b_mu160_info mactx_vht_sig_b_mu160_info_details;
|
||||
#else
|
||||
struct vht_sig_b_mu160_info mactx_vht_sig_b_mu160_info_details;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_LSB 0
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_MSB 18
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_MASK 0x000000000007ffff
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_LSB 19
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_MSB 22
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_MASK 0x0000000000780000
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_LSB 23
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_MSB 28
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_MASK 0x000000001f800000
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_0_LSB 29
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_0_MSB 31
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_0_MASK 0x00000000e0000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_A_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_A_LSB 32
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_A_MSB 50
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_A_MASK 0x0007ffff00000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_A_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_A_LSB 51
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_A_MSB 54
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_A_MASK 0x0078000000000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_A_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_A_LSB 55
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_A_MSB 60
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_A_MASK 0x1f80000000000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_1_LSB 61
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_1_MSB 63
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_1_MASK 0xe000000000000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_B_OFFSET 0x0000000000000008
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_B_LSB 0
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_B_MSB 18
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_B_MASK 0x000000000007ffff
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_B_OFFSET 0x0000000000000008
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_B_LSB 19
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_B_MSB 22
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_B_MASK 0x0000000000780000
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_B_OFFSET 0x0000000000000008
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_B_LSB 23
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_B_MSB 28
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_B_MASK 0x000000001f800000
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_2_OFFSET 0x0000000000000008
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_2_LSB 29
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_2_MSB 31
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_2_MASK 0x00000000e0000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_C_OFFSET 0x0000000000000008
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_C_LSB 32
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_C_MSB 50
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_C_MASK 0x0007ffff00000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_C_OFFSET 0x0000000000000008
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_C_LSB 51
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_C_MSB 54
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_C_MASK 0x0078000000000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_C_OFFSET 0x0000000000000008
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_C_LSB 55
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_C_MSB 60
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_C_MASK 0x1f80000000000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_3_OFFSET 0x0000000000000008
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_3_LSB 61
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_3_MSB 63
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_3_MASK 0xe000000000000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_D_OFFSET 0x0000000000000010
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_D_LSB 0
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_D_MSB 18
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_D_MASK 0x000000000007ffff
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_D_OFFSET 0x0000000000000010
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_D_LSB 19
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_D_MSB 22
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_D_MASK 0x0000000000780000
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_D_OFFSET 0x0000000000000010
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_D_LSB 23
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_D_MSB 28
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_D_MASK 0x000000001f800000
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_4_OFFSET 0x0000000000000010
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_4_LSB 29
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_4_MSB 31
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_4_MASK 0x00000000e0000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_E_OFFSET 0x0000000000000010
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_E_LSB 32
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_E_MSB 50
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_E_MASK 0x0007ffff00000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_E_OFFSET 0x0000000000000010
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_E_LSB 51
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_E_MSB 54
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_E_MASK 0x0078000000000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_E_OFFSET 0x0000000000000010
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_E_LSB 55
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_E_MSB 60
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_E_MASK 0x1f80000000000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_5_OFFSET 0x0000000000000010
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_5_LSB 61
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_5_MSB 63
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_5_MASK 0xe000000000000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_F_OFFSET 0x0000000000000018
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_F_LSB 0
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_F_MSB 18
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_F_MASK 0x000000000007ffff
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_F_OFFSET 0x0000000000000018
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_F_LSB 19
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_F_MSB 22
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_F_MASK 0x0000000000780000
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_F_OFFSET 0x0000000000000018
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_F_LSB 23
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_F_MSB 28
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_F_MASK 0x000000001f800000
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MU_USER_NUMBER_OFFSET 0x0000000000000018
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MU_USER_NUMBER_LSB 29
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MU_USER_NUMBER_MSB 31
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MU_USER_NUMBER_MASK 0x00000000e0000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_G_OFFSET 0x0000000000000018
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_G_LSB 32
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_G_MSB 50
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_LENGTH_COPY_G_MASK 0x0007ffff00000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_G_OFFSET 0x0000000000000018
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_G_LSB 51
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_G_MSB 54
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_MCS_COPY_G_MASK 0x0078000000000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_G_OFFSET 0x0000000000000018
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_G_LSB 55
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_G_MSB 60
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_TAIL_COPY_G_MASK 0x1f80000000000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_7_OFFSET 0x0000000000000018
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_7_LSB 61
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_7_MSB 63
|
||||
#define MACTX_VHT_SIG_B_MU160_MACTX_VHT_SIG_B_MU160_INFO_DETAILS_RESERVED_7_MASK 0xe000000000000000
|
||||
|
||||
#endif
|
||||
70
hw/kiwi/v2/mactx_vht_sig_b_mu20.h
Normal file
70
hw/kiwi/v2/mactx_vht_sig_b_mu20.h
Normal file
|
|
@ -0,0 +1,70 @@
|
|||
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
#ifndef _MACTX_VHT_SIG_B_MU20_H_
|
||||
#define _MACTX_VHT_SIG_B_MU20_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#include "vht_sig_b_mu20_info.h"
|
||||
#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_MU20 2
|
||||
|
||||
#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_MU20 1
|
||||
|
||||
struct mactx_vht_sig_b_mu20 {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
struct vht_sig_b_mu20_info mactx_vht_sig_b_mu20_info_details;
|
||||
uint32_t tlv64_padding : 32;
|
||||
#else
|
||||
struct vht_sig_b_mu20_info mactx_vht_sig_b_mu20_info_details;
|
||||
uint32_t tlv64_padding : 32;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_LENGTH_LSB 0
|
||||
#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_LENGTH_MSB 15
|
||||
#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_LENGTH_MASK 0x000000000000ffff
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MCS_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MCS_LSB 16
|
||||
#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MCS_MSB 19
|
||||
#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MCS_MASK 0x00000000000f0000
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_TAIL_LSB 20
|
||||
#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_TAIL_MSB 25
|
||||
#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_TAIL_MASK 0x0000000003f00000
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MU_USER_NUMBER_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MU_USER_NUMBER_LSB 26
|
||||
#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MU_USER_NUMBER_MSB 28
|
||||
#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_MU_USER_NUMBER_MASK 0x000000001c000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_RESERVED_0_LSB 29
|
||||
#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_RESERVED_0_MSB 31
|
||||
#define MACTX_VHT_SIG_B_MU20_MACTX_VHT_SIG_B_MU20_INFO_DETAILS_RESERVED_0_MASK 0x00000000e0000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU20_TLV64_PADDING_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_MU20_TLV64_PADDING_LSB 32
|
||||
#define MACTX_VHT_SIG_B_MU20_TLV64_PADDING_MSB 63
|
||||
#define MACTX_VHT_SIG_B_MU20_TLV64_PADDING_MASK 0xffffffff00000000
|
||||
|
||||
#endif
|
||||
83
hw/kiwi/v2/mactx_vht_sig_b_mu40.h
Normal file
83
hw/kiwi/v2/mactx_vht_sig_b_mu40.h
Normal file
|
|
@ -0,0 +1,83 @@
|
|||
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
#ifndef _MACTX_VHT_SIG_B_MU40_H_
|
||||
#define _MACTX_VHT_SIG_B_MU40_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#include "vht_sig_b_mu40_info.h"
|
||||
#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_MU40 2
|
||||
|
||||
#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_MU40 1
|
||||
|
||||
struct mactx_vht_sig_b_mu40 {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
struct vht_sig_b_mu40_info mactx_vht_sig_b_mu40_info_details;
|
||||
#else
|
||||
struct vht_sig_b_mu40_info mactx_vht_sig_b_mu40_info_details;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_LSB 0
|
||||
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_MSB 16
|
||||
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_MASK 0x000000000001ffff
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_LSB 17
|
||||
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_MSB 20
|
||||
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_MASK 0x00000000001e0000
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_LSB 21
|
||||
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_MSB 26
|
||||
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_MASK 0x0000000007e00000
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_0_LSB 27
|
||||
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_0_MSB 28
|
||||
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_0_MASK 0x0000000018000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MU_USER_NUMBER_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MU_USER_NUMBER_LSB 29
|
||||
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MU_USER_NUMBER_MSB 31
|
||||
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MU_USER_NUMBER_MASK 0x00000000e0000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_COPY_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_COPY_LSB 32
|
||||
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_COPY_MSB 48
|
||||
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_LENGTH_COPY_MASK 0x0001ffff00000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_COPY_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_COPY_LSB 49
|
||||
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_COPY_MSB 52
|
||||
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_MCS_COPY_MASK 0x001e000000000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_COPY_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_COPY_LSB 53
|
||||
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_COPY_MSB 58
|
||||
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_TAIL_COPY_MASK 0x07e0000000000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_1_LSB 59
|
||||
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_1_MSB 63
|
||||
#define MACTX_VHT_SIG_B_MU40_MACTX_VHT_SIG_B_MU40_INFO_DETAILS_RESERVED_1_MASK 0xf800000000000000
|
||||
|
||||
#endif
|
||||
118
hw/kiwi/v2/mactx_vht_sig_b_mu80.h
Normal file
118
hw/kiwi/v2/mactx_vht_sig_b_mu80.h
Normal file
|
|
@ -0,0 +1,118 @@
|
|||
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
#ifndef _MACTX_VHT_SIG_B_MU80_H_
|
||||
#define _MACTX_VHT_SIG_B_MU80_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#include "vht_sig_b_mu80_info.h"
|
||||
#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_MU80 4
|
||||
|
||||
#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_MU80 2
|
||||
|
||||
struct mactx_vht_sig_b_mu80 {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
struct vht_sig_b_mu80_info mactx_vht_sig_b_mu80_info_details;
|
||||
#else
|
||||
struct vht_sig_b_mu80_info mactx_vht_sig_b_mu80_info_details;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_LSB 0
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_MSB 18
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_MASK 0x000000000007ffff
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_LSB 19
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_MSB 22
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_MASK 0x0000000000780000
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_LSB 23
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_MSB 28
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_MASK 0x000000001f800000
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_0_LSB 29
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_0_MSB 31
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_0_MASK 0x00000000e0000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_A_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_A_LSB 32
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_A_MSB 50
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_A_MASK 0x0007ffff00000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_A_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_A_LSB 51
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_A_MSB 54
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_A_MASK 0x0078000000000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_A_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_A_LSB 55
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_A_MSB 60
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_A_MASK 0x1f80000000000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_1_LSB 61
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_1_MSB 63
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_1_MASK 0xe000000000000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_B_OFFSET 0x0000000000000008
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_B_LSB 0
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_B_MSB 18
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_B_MASK 0x000000000007ffff
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_B_OFFSET 0x0000000000000008
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_B_LSB 19
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_B_MSB 22
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_B_MASK 0x0000000000780000
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_B_OFFSET 0x0000000000000008
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_B_LSB 23
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_B_MSB 28
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_B_MASK 0x000000001f800000
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MU_USER_NUMBER_OFFSET 0x0000000000000008
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MU_USER_NUMBER_LSB 29
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MU_USER_NUMBER_MSB 31
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MU_USER_NUMBER_MASK 0x00000000e0000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_C_OFFSET 0x0000000000000008
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_C_LSB 32
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_C_MSB 50
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_LENGTH_COPY_C_MASK 0x0007ffff00000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_C_OFFSET 0x0000000000000008
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_C_LSB 51
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_C_MSB 54
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_MCS_COPY_C_MASK 0x0078000000000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_C_OFFSET 0x0000000000000008
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_C_LSB 55
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_C_MSB 60
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_TAIL_COPY_C_MASK 0x1f80000000000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_3_OFFSET 0x0000000000000008
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_3_LSB 61
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_3_MSB 63
|
||||
#define MACTX_VHT_SIG_B_MU80_MACTX_VHT_SIG_B_MU80_INFO_DETAILS_RESERVED_3_MASK 0xe000000000000000
|
||||
|
||||
#endif
|
||||
238
hw/kiwi/v2/mactx_vht_sig_b_su160.h
Normal file
238
hw/kiwi/v2/mactx_vht_sig_b_su160.h
Normal file
|
|
@ -0,0 +1,238 @@
|
|||
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
#ifndef _MACTX_VHT_SIG_B_SU160_H_
|
||||
#define _MACTX_VHT_SIG_B_SU160_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#include "vht_sig_b_su160_info.h"
|
||||
#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_SU160 8
|
||||
|
||||
#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_SU160 4
|
||||
|
||||
struct mactx_vht_sig_b_su160 {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
struct vht_sig_b_su160_info mactx_vht_sig_b_su160_info_details;
|
||||
#else
|
||||
struct vht_sig_b_su160_info mactx_vht_sig_b_su160_info_details;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_LSB 0
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_MSB 20
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_MASK 0x00000000001fffff
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_LSB 21
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_MSB 22
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_MASK 0x0000000000600000
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_LSB 23
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_MSB 28
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_MASK 0x000000001f800000
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_0_LSB 29
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_0_MSB 30
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_0_MASK 0x0000000060000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_LSB 31
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_MSB 31
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_MASK 0x0000000080000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_A_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_A_LSB 32
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_A_MSB 52
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_A_MASK 0x001fffff00000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_A_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_A_LSB 53
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_A_MSB 54
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_A_MASK 0x0060000000000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_A_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_A_LSB 55
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_A_MSB 60
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_A_MASK 0x1f80000000000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_1_LSB 61
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_1_MSB 62
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_1_MASK 0x6000000000000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_A_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_A_LSB 63
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_A_MSB 63
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_A_MASK 0x8000000000000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_B_OFFSET 0x0000000000000008
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_B_LSB 0
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_B_MSB 20
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_B_MASK 0x00000000001fffff
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_B_OFFSET 0x0000000000000008
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_B_LSB 21
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_B_MSB 22
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_B_MASK 0x0000000000600000
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_B_OFFSET 0x0000000000000008
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_B_LSB 23
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_B_MSB 28
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_B_MASK 0x000000001f800000
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_2_OFFSET 0x0000000000000008
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_2_LSB 29
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_2_MSB 30
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_2_MASK 0x0000000060000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_B_OFFSET 0x0000000000000008
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_B_LSB 31
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_B_MSB 31
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_B_MASK 0x0000000080000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_C_OFFSET 0x0000000000000008
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_C_LSB 32
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_C_MSB 52
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_C_MASK 0x001fffff00000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_C_OFFSET 0x0000000000000008
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_C_LSB 53
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_C_MSB 54
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_C_MASK 0x0060000000000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_C_OFFSET 0x0000000000000008
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_C_LSB 55
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_C_MSB 60
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_C_MASK 0x1f80000000000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_3_OFFSET 0x0000000000000008
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_3_LSB 61
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_3_MSB 62
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_3_MASK 0x6000000000000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_C_OFFSET 0x0000000000000008
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_C_LSB 63
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_C_MSB 63
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_C_MASK 0x8000000000000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_D_OFFSET 0x0000000000000010
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_D_LSB 0
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_D_MSB 20
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_D_MASK 0x00000000001fffff
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_D_OFFSET 0x0000000000000010
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_D_LSB 21
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_D_MSB 22
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_D_MASK 0x0000000000600000
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_D_OFFSET 0x0000000000000010
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_D_LSB 23
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_D_MSB 28
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_D_MASK 0x000000001f800000
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_4_OFFSET 0x0000000000000010
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_4_LSB 29
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_4_MSB 30
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_4_MASK 0x0000000060000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_D_OFFSET 0x0000000000000010
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_D_LSB 31
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_D_MSB 31
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_D_MASK 0x0000000080000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_E_OFFSET 0x0000000000000010
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_E_LSB 32
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_E_MSB 52
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_E_MASK 0x001fffff00000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_E_OFFSET 0x0000000000000010
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_E_LSB 53
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_E_MSB 54
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_E_MASK 0x0060000000000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_E_OFFSET 0x0000000000000010
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_E_LSB 55
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_E_MSB 60
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_E_MASK 0x1f80000000000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_5_OFFSET 0x0000000000000010
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_5_LSB 61
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_5_MSB 62
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_5_MASK 0x6000000000000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_E_OFFSET 0x0000000000000010
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_E_LSB 63
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_E_MSB 63
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_E_MASK 0x8000000000000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_F_OFFSET 0x0000000000000018
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_F_LSB 0
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_F_MSB 20
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_F_MASK 0x00000000001fffff
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_F_OFFSET 0x0000000000000018
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_F_LSB 21
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_F_MSB 22
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_F_MASK 0x0000000000600000
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_F_OFFSET 0x0000000000000018
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_F_LSB 23
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_F_MSB 28
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_F_MASK 0x000000001f800000
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_6_OFFSET 0x0000000000000018
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_6_LSB 29
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_6_MSB 30
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_6_MASK 0x0000000060000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_F_OFFSET 0x0000000000000018
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_F_LSB 31
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_F_MSB 31
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_F_MASK 0x0000000080000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_G_OFFSET 0x0000000000000018
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_G_LSB 32
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_G_MSB 52
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_LENGTH_COPY_G_MASK 0x001fffff00000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_G_OFFSET 0x0000000000000018
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_G_LSB 53
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_G_MSB 54
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_VHTB_RESERVED_COPY_G_MASK 0x0060000000000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_G_OFFSET 0x0000000000000018
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_G_LSB 55
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_G_MSB 60
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_TAIL_COPY_G_MASK 0x1f80000000000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_7_OFFSET 0x0000000000000018
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_7_LSB 61
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_7_MSB 62
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RESERVED_7_MASK 0x6000000000000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_G_OFFSET 0x0000000000000018
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_G_LSB 63
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_G_MSB 63
|
||||
#define MACTX_VHT_SIG_B_SU160_MACTX_VHT_SIG_B_SU160_INFO_DETAILS_RX_NDP_COPY_G_MASK 0x8000000000000000
|
||||
|
||||
#endif
|
||||
70
hw/kiwi/v2/mactx_vht_sig_b_su20.h
Normal file
70
hw/kiwi/v2/mactx_vht_sig_b_su20.h
Normal file
|
|
@ -0,0 +1,70 @@
|
|||
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
#ifndef _MACTX_VHT_SIG_B_SU20_H_
|
||||
#define _MACTX_VHT_SIG_B_SU20_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#include "vht_sig_b_su20_info.h"
|
||||
#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_SU20 2
|
||||
|
||||
#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_SU20 1
|
||||
|
||||
struct mactx_vht_sig_b_su20 {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
struct vht_sig_b_su20_info mactx_vht_sig_b_su20_info_details;
|
||||
uint32_t tlv64_padding : 32;
|
||||
#else
|
||||
struct vht_sig_b_su20_info mactx_vht_sig_b_su20_info_details;
|
||||
uint32_t tlv64_padding : 32;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_LENGTH_LSB 0
|
||||
#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_LENGTH_MSB 16
|
||||
#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_LENGTH_MASK 0x000000000001ffff
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_VHTB_RESERVED_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_VHTB_RESERVED_LSB 17
|
||||
#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_VHTB_RESERVED_MSB 19
|
||||
#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_VHTB_RESERVED_MASK 0x00000000000e0000
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_TAIL_LSB 20
|
||||
#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_TAIL_MSB 25
|
||||
#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_TAIL_MASK 0x0000000003f00000
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RESERVED_LSB 26
|
||||
#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RESERVED_MSB 30
|
||||
#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RESERVED_MASK 0x000000007c000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RX_NDP_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RX_NDP_LSB 31
|
||||
#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RX_NDP_MSB 31
|
||||
#define MACTX_VHT_SIG_B_SU20_MACTX_VHT_SIG_B_SU20_INFO_DETAILS_RX_NDP_MASK 0x0000000080000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU20_TLV64_PADDING_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_SU20_TLV64_PADDING_LSB 32
|
||||
#define MACTX_VHT_SIG_B_SU20_TLV64_PADDING_MSB 63
|
||||
#define MACTX_VHT_SIG_B_SU20_TLV64_PADDING_MASK 0xffffffff00000000
|
||||
|
||||
#endif
|
||||
88
hw/kiwi/v2/mactx_vht_sig_b_su40.h
Normal file
88
hw/kiwi/v2/mactx_vht_sig_b_su40.h
Normal file
|
|
@ -0,0 +1,88 @@
|
|||
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
#ifndef _MACTX_VHT_SIG_B_SU40_H_
|
||||
#define _MACTX_VHT_SIG_B_SU40_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#include "vht_sig_b_su40_info.h"
|
||||
#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_SU40 2
|
||||
|
||||
#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_SU40 1
|
||||
|
||||
struct mactx_vht_sig_b_su40 {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
struct vht_sig_b_su40_info mactx_vht_sig_b_su40_info_details;
|
||||
#else
|
||||
struct vht_sig_b_su40_info mactx_vht_sig_b_su40_info_details;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_LSB 0
|
||||
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_MSB 18
|
||||
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_MASK 0x000000000007ffff
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_LSB 19
|
||||
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_MSB 20
|
||||
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_MASK 0x0000000000180000
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_LSB 21
|
||||
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_MSB 26
|
||||
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_MASK 0x0000000007e00000
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_LSB 27
|
||||
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_MSB 30
|
||||
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_MASK 0x0000000078000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_LSB 31
|
||||
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_MSB 31
|
||||
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_MASK 0x0000000080000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_COPY_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_COPY_LSB 32
|
||||
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_COPY_MSB 50
|
||||
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_LENGTH_COPY_MASK 0x0007ffff00000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_COPY_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_COPY_LSB 51
|
||||
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_COPY_MSB 52
|
||||
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_VHTB_RESERVED_COPY_MASK 0x0018000000000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_COPY_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_COPY_LSB 53
|
||||
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_COPY_MSB 58
|
||||
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_TAIL_COPY_MASK 0x07e0000000000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_COPY_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_COPY_LSB 59
|
||||
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_COPY_MSB 62
|
||||
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RESERVED_COPY_MASK 0x7800000000000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_COPY_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_COPY_LSB 63
|
||||
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_COPY_MSB 63
|
||||
#define MACTX_VHT_SIG_B_SU40_MACTX_VHT_SIG_B_SU40_INFO_DETAILS_RX_NDP_COPY_MASK 0x8000000000000000
|
||||
|
||||
#endif
|
||||
138
hw/kiwi/v2/mactx_vht_sig_b_su80.h
Normal file
138
hw/kiwi/v2/mactx_vht_sig_b_su80.h
Normal file
|
|
@ -0,0 +1,138 @@
|
|||
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
#ifndef _MACTX_VHT_SIG_B_SU80_H_
|
||||
#define _MACTX_VHT_SIG_B_SU80_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#include "vht_sig_b_su80_info.h"
|
||||
#define NUM_OF_DWORDS_MACTX_VHT_SIG_B_SU80 4
|
||||
|
||||
#define NUM_OF_QWORDS_MACTX_VHT_SIG_B_SU80 2
|
||||
|
||||
struct mactx_vht_sig_b_su80 {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
struct vht_sig_b_su80_info mactx_vht_sig_b_su80_info_details;
|
||||
#else
|
||||
struct vht_sig_b_su80_info mactx_vht_sig_b_su80_info_details;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_LSB 0
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_MSB 20
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_MASK 0x00000000001fffff
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_LSB 21
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_MSB 22
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_MASK 0x0000000000600000
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_LSB 23
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_MSB 28
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_MASK 0x000000001f800000
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_0_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_0_LSB 29
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_0_MSB 30
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_0_MASK 0x0000000060000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_LSB 31
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_MSB 31
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_MASK 0x0000000080000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_A_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_A_LSB 32
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_A_MSB 52
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_A_MASK 0x001fffff00000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_A_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_A_LSB 53
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_A_MSB 54
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_A_MASK 0x0060000000000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_A_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_A_LSB 55
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_A_MSB 60
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_A_MASK 0x1f80000000000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_1_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_1_LSB 61
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_1_MSB 62
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_1_MASK 0x6000000000000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_A_OFFSET 0x0000000000000000
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_A_LSB 63
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_A_MSB 63
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_A_MASK 0x8000000000000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_B_OFFSET 0x0000000000000008
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_B_LSB 0
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_B_MSB 20
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_B_MASK 0x00000000001fffff
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_B_OFFSET 0x0000000000000008
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_B_LSB 21
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_B_MSB 22
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_B_MASK 0x0000000000600000
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_B_OFFSET 0x0000000000000008
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_B_LSB 23
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_B_MSB 28
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_B_MASK 0x000000001f800000
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_2_OFFSET 0x0000000000000008
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_2_LSB 29
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_2_MSB 30
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_2_MASK 0x0000000060000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_B_OFFSET 0x0000000000000008
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_B_LSB 31
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_B_MSB 31
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_B_MASK 0x0000000080000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_C_OFFSET 0x0000000000000008
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_C_LSB 32
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_C_MSB 52
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_LENGTH_COPY_C_MASK 0x001fffff00000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_C_OFFSET 0x0000000000000008
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_C_LSB 53
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_C_MSB 54
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_VHTB_RESERVED_COPY_C_MASK 0x0060000000000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_C_OFFSET 0x0000000000000008
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_C_LSB 55
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_C_MSB 60
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_TAIL_COPY_C_MASK 0x1f80000000000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_3_OFFSET 0x0000000000000008
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_3_LSB 61
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_3_MSB 62
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RESERVED_3_MASK 0x6000000000000000
|
||||
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_C_OFFSET 0x0000000000000008
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_C_LSB 63
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_C_MSB 63
|
||||
#define MACTX_VHT_SIG_B_SU80_MACTX_VHT_SIG_B_SU80_INFO_DETAILS_RX_NDP_COPY_C_MASK 0x8000000000000000
|
||||
|
||||
#endif
|
||||
68
hw/kiwi/v2/mlo_sta_id_details.h
Normal file
68
hw/kiwi/v2/mlo_sta_id_details.h
Normal file
|
|
@ -0,0 +1,68 @@
|
|||
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
#ifndef _MLO_STA_ID_DETAILS_H_
|
||||
#define _MLO_STA_ID_DETAILS_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#define NUM_OF_WORDS_MLO_STA_ID_DETAILS 1
|
||||
|
||||
struct mlo_sta_id_details {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint16_t nstr_mlo_sta_id : 10,
|
||||
block_self_ml_sync : 1,
|
||||
block_partner_ml_sync : 1,
|
||||
nstr_mlo_sta_id_valid : 1,
|
||||
reserved_0a : 3;
|
||||
#else
|
||||
uint16_t reserved_0a : 3,
|
||||
nstr_mlo_sta_id_valid : 1,
|
||||
block_partner_ml_sync : 1,
|
||||
block_self_ml_sync : 1,
|
||||
nstr_mlo_sta_id : 10;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_OFFSET 0x00000000
|
||||
#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_LSB 0
|
||||
#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_MSB 9
|
||||
#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_MASK 0x000003ff
|
||||
|
||||
#define MLO_STA_ID_DETAILS_BLOCK_SELF_ML_SYNC_OFFSET 0x00000000
|
||||
#define MLO_STA_ID_DETAILS_BLOCK_SELF_ML_SYNC_LSB 10
|
||||
#define MLO_STA_ID_DETAILS_BLOCK_SELF_ML_SYNC_MSB 10
|
||||
#define MLO_STA_ID_DETAILS_BLOCK_SELF_ML_SYNC_MASK 0x00000400
|
||||
|
||||
#define MLO_STA_ID_DETAILS_BLOCK_PARTNER_ML_SYNC_OFFSET 0x00000000
|
||||
#define MLO_STA_ID_DETAILS_BLOCK_PARTNER_ML_SYNC_LSB 11
|
||||
#define MLO_STA_ID_DETAILS_BLOCK_PARTNER_ML_SYNC_MSB 11
|
||||
#define MLO_STA_ID_DETAILS_BLOCK_PARTNER_ML_SYNC_MASK 0x00000800
|
||||
|
||||
#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_VALID_OFFSET 0x00000000
|
||||
#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_VALID_LSB 12
|
||||
#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_VALID_MSB 12
|
||||
#define MLO_STA_ID_DETAILS_NSTR_MLO_STA_ID_VALID_MASK 0x00001000
|
||||
|
||||
#define MLO_STA_ID_DETAILS_RESERVED_0A_OFFSET 0x00000000
|
||||
#define MLO_STA_ID_DETAILS_RESERVED_0A_LSB 13
|
||||
#define MLO_STA_ID_DETAILS_RESERVED_0A_MSB 15
|
||||
#define MLO_STA_ID_DETAILS_RESERVED_0A_MASK 0x0000e000
|
||||
|
||||
#endif
|
||||
91
hw/kiwi/v2/mon_buffer_addr.h
Normal file
91
hw/kiwi/v2/mon_buffer_addr.h
Normal file
|
|
@ -0,0 +1,91 @@
|
|||
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
#ifndef _MON_BUFFER_ADDR_H_
|
||||
#define _MON_BUFFER_ADDR_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#define NUM_OF_DWORDS_MON_BUFFER_ADDR 4
|
||||
|
||||
#define NUM_OF_QWORDS_MON_BUFFER_ADDR 2
|
||||
|
||||
struct mon_buffer_addr {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t buffer_virt_addr_31_0 : 32;
|
||||
uint32_t buffer_virt_addr_63_32 : 32;
|
||||
uint32_t dma_length : 12,
|
||||
reserved_2a : 4,
|
||||
msdu_continuation : 1,
|
||||
truncated : 1,
|
||||
reserved_2b : 14;
|
||||
uint32_t tlv64_padding : 32;
|
||||
#else
|
||||
uint32_t buffer_virt_addr_31_0 : 32;
|
||||
uint32_t buffer_virt_addr_63_32 : 32;
|
||||
uint32_t reserved_2b : 14,
|
||||
truncated : 1,
|
||||
msdu_continuation : 1,
|
||||
reserved_2a : 4,
|
||||
dma_length : 12;
|
||||
uint32_t tlv64_padding : 32;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_31_0_OFFSET 0x0000000000000000
|
||||
#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_31_0_LSB 0
|
||||
#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_31_0_MSB 31
|
||||
#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_31_0_MASK 0x00000000ffffffff
|
||||
|
||||
#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_63_32_OFFSET 0x0000000000000000
|
||||
#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_63_32_LSB 32
|
||||
#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_63_32_MSB 63
|
||||
#define MON_BUFFER_ADDR_BUFFER_VIRT_ADDR_63_32_MASK 0xffffffff00000000
|
||||
|
||||
#define MON_BUFFER_ADDR_DMA_LENGTH_OFFSET 0x0000000000000008
|
||||
#define MON_BUFFER_ADDR_DMA_LENGTH_LSB 0
|
||||
#define MON_BUFFER_ADDR_DMA_LENGTH_MSB 11
|
||||
#define MON_BUFFER_ADDR_DMA_LENGTH_MASK 0x0000000000000fff
|
||||
|
||||
#define MON_BUFFER_ADDR_RESERVED_2A_OFFSET 0x0000000000000008
|
||||
#define MON_BUFFER_ADDR_RESERVED_2A_LSB 12
|
||||
#define MON_BUFFER_ADDR_RESERVED_2A_MSB 15
|
||||
#define MON_BUFFER_ADDR_RESERVED_2A_MASK 0x000000000000f000
|
||||
|
||||
#define MON_BUFFER_ADDR_MSDU_CONTINUATION_OFFSET 0x0000000000000008
|
||||
#define MON_BUFFER_ADDR_MSDU_CONTINUATION_LSB 16
|
||||
#define MON_BUFFER_ADDR_MSDU_CONTINUATION_MSB 16
|
||||
#define MON_BUFFER_ADDR_MSDU_CONTINUATION_MASK 0x0000000000010000
|
||||
|
||||
#define MON_BUFFER_ADDR_TRUNCATED_OFFSET 0x0000000000000008
|
||||
#define MON_BUFFER_ADDR_TRUNCATED_LSB 17
|
||||
#define MON_BUFFER_ADDR_TRUNCATED_MSB 17
|
||||
#define MON_BUFFER_ADDR_TRUNCATED_MASK 0x0000000000020000
|
||||
|
||||
#define MON_BUFFER_ADDR_RESERVED_2B_OFFSET 0x0000000000000008
|
||||
#define MON_BUFFER_ADDR_RESERVED_2B_LSB 18
|
||||
#define MON_BUFFER_ADDR_RESERVED_2B_MSB 31
|
||||
#define MON_BUFFER_ADDR_RESERVED_2B_MASK 0x00000000fffc0000
|
||||
|
||||
#define MON_BUFFER_ADDR_TLV64_PADDING_OFFSET 0x0000000000000008
|
||||
#define MON_BUFFER_ADDR_TLV64_PADDING_LSB 32
|
||||
#define MON_BUFFER_ADDR_TLV64_PADDING_MSB 63
|
||||
#define MON_BUFFER_ADDR_TLV64_PADDING_MASK 0xffffffff00000000
|
||||
|
||||
#endif
|
||||
103
hw/kiwi/v2/mon_destination_ring.h
Normal file
103
hw/kiwi/v2/mon_destination_ring.h
Normal file
|
|
@ -0,0 +1,103 @@
|
|||
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
#ifndef _MON_DESTINATION_RING_H_
|
||||
#define _MON_DESTINATION_RING_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#define NUM_OF_DWORDS_MON_DESTINATION_RING 4
|
||||
|
||||
struct mon_destination_ring {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t stat_buf_virt_addr_31_0 : 32;
|
||||
uint32_t stat_buf_virt_addr_63_32 : 32;
|
||||
uint32_t ppdu_id : 32;
|
||||
uint32_t end_offset : 12,
|
||||
reserved_3a : 4,
|
||||
end_reason : 2,
|
||||
initiator : 1,
|
||||
empty_descriptor : 1,
|
||||
ring_id : 8,
|
||||
looping_count : 4;
|
||||
#else
|
||||
uint32_t stat_buf_virt_addr_31_0 : 32;
|
||||
uint32_t stat_buf_virt_addr_63_32 : 32;
|
||||
uint32_t ppdu_id : 32;
|
||||
uint32_t looping_count : 4,
|
||||
ring_id : 8,
|
||||
empty_descriptor : 1,
|
||||
initiator : 1,
|
||||
end_reason : 2,
|
||||
reserved_3a : 4,
|
||||
end_offset : 12;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_31_0_OFFSET 0x00000000
|
||||
#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_31_0_LSB 0
|
||||
#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_31_0_MSB 31
|
||||
#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_31_0_MASK 0xffffffff
|
||||
|
||||
#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_63_32_OFFSET 0x00000004
|
||||
#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_63_32_LSB 0
|
||||
#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_63_32_MSB 31
|
||||
#define MON_DESTINATION_RING_STAT_BUF_VIRT_ADDR_63_32_MASK 0xffffffff
|
||||
|
||||
#define MON_DESTINATION_RING_PPDU_ID_OFFSET 0x00000008
|
||||
#define MON_DESTINATION_RING_PPDU_ID_LSB 0
|
||||
#define MON_DESTINATION_RING_PPDU_ID_MSB 31
|
||||
#define MON_DESTINATION_RING_PPDU_ID_MASK 0xffffffff
|
||||
|
||||
#define MON_DESTINATION_RING_END_OFFSET_OFFSET 0x0000000c
|
||||
#define MON_DESTINATION_RING_END_OFFSET_LSB 0
|
||||
#define MON_DESTINATION_RING_END_OFFSET_MSB 11
|
||||
#define MON_DESTINATION_RING_END_OFFSET_MASK 0x00000fff
|
||||
|
||||
#define MON_DESTINATION_RING_RESERVED_3A_OFFSET 0x0000000c
|
||||
#define MON_DESTINATION_RING_RESERVED_3A_LSB 12
|
||||
#define MON_DESTINATION_RING_RESERVED_3A_MSB 15
|
||||
#define MON_DESTINATION_RING_RESERVED_3A_MASK 0x0000f000
|
||||
|
||||
#define MON_DESTINATION_RING_END_REASON_OFFSET 0x0000000c
|
||||
#define MON_DESTINATION_RING_END_REASON_LSB 16
|
||||
#define MON_DESTINATION_RING_END_REASON_MSB 17
|
||||
#define MON_DESTINATION_RING_END_REASON_MASK 0x00030000
|
||||
|
||||
#define MON_DESTINATION_RING_INITIATOR_OFFSET 0x0000000c
|
||||
#define MON_DESTINATION_RING_INITIATOR_LSB 18
|
||||
#define MON_DESTINATION_RING_INITIATOR_MSB 18
|
||||
#define MON_DESTINATION_RING_INITIATOR_MASK 0x00040000
|
||||
|
||||
#define MON_DESTINATION_RING_EMPTY_DESCRIPTOR_OFFSET 0x0000000c
|
||||
#define MON_DESTINATION_RING_EMPTY_DESCRIPTOR_LSB 19
|
||||
#define MON_DESTINATION_RING_EMPTY_DESCRIPTOR_MSB 19
|
||||
#define MON_DESTINATION_RING_EMPTY_DESCRIPTOR_MASK 0x00080000
|
||||
|
||||
#define MON_DESTINATION_RING_RING_ID_OFFSET 0x0000000c
|
||||
#define MON_DESTINATION_RING_RING_ID_LSB 20
|
||||
#define MON_DESTINATION_RING_RING_ID_MSB 27
|
||||
#define MON_DESTINATION_RING_RING_ID_MASK 0x0ff00000
|
||||
|
||||
#define MON_DESTINATION_RING_LOOPING_COUNT_OFFSET 0x0000000c
|
||||
#define MON_DESTINATION_RING_LOOPING_COUNT_LSB 28
|
||||
#define MON_DESTINATION_RING_LOOPING_COUNT_MSB 31
|
||||
#define MON_DESTINATION_RING_LOOPING_COUNT_MASK 0xf0000000
|
||||
|
||||
#endif
|
||||
77
hw/kiwi/v2/mon_drop.h
Normal file
77
hw/kiwi/v2/mon_drop.h
Normal file
|
|
@ -0,0 +1,77 @@
|
|||
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
#ifndef _MON_DROP_H_
|
||||
#define _MON_DROP_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#define NUM_OF_DWORDS_MON_DROP 2
|
||||
|
||||
#define NUM_OF_QWORDS_MON_DROP 1
|
||||
|
||||
struct mon_drop {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t ppdu_id : 32;
|
||||
uint32_t ppdu_drop_cnt : 10,
|
||||
mpdu_drop_cnt : 10,
|
||||
tlv_drop_cnt : 10,
|
||||
end_of_ppdu_seen : 1,
|
||||
reserved_1a : 1;
|
||||
#else
|
||||
uint32_t ppdu_id : 32;
|
||||
uint32_t reserved_1a : 1,
|
||||
end_of_ppdu_seen : 1,
|
||||
tlv_drop_cnt : 10,
|
||||
mpdu_drop_cnt : 10,
|
||||
ppdu_drop_cnt : 10;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define MON_DROP_PPDU_ID_OFFSET 0x0000000000000000
|
||||
#define MON_DROP_PPDU_ID_LSB 0
|
||||
#define MON_DROP_PPDU_ID_MSB 31
|
||||
#define MON_DROP_PPDU_ID_MASK 0x00000000ffffffff
|
||||
|
||||
#define MON_DROP_PPDU_DROP_CNT_OFFSET 0x0000000000000000
|
||||
#define MON_DROP_PPDU_DROP_CNT_LSB 32
|
||||
#define MON_DROP_PPDU_DROP_CNT_MSB 41
|
||||
#define MON_DROP_PPDU_DROP_CNT_MASK 0x000003ff00000000
|
||||
|
||||
#define MON_DROP_MPDU_DROP_CNT_OFFSET 0x0000000000000000
|
||||
#define MON_DROP_MPDU_DROP_CNT_LSB 42
|
||||
#define MON_DROP_MPDU_DROP_CNT_MSB 51
|
||||
#define MON_DROP_MPDU_DROP_CNT_MASK 0x000ffc0000000000
|
||||
|
||||
#define MON_DROP_TLV_DROP_CNT_OFFSET 0x0000000000000000
|
||||
#define MON_DROP_TLV_DROP_CNT_LSB 52
|
||||
#define MON_DROP_TLV_DROP_CNT_MSB 61
|
||||
#define MON_DROP_TLV_DROP_CNT_MASK 0x3ff0000000000000
|
||||
|
||||
#define MON_DROP_END_OF_PPDU_SEEN_OFFSET 0x0000000000000000
|
||||
#define MON_DROP_END_OF_PPDU_SEEN_LSB 62
|
||||
#define MON_DROP_END_OF_PPDU_SEEN_MSB 62
|
||||
#define MON_DROP_END_OF_PPDU_SEEN_MASK 0x4000000000000000
|
||||
|
||||
#define MON_DROP_RESERVED_1A_OFFSET 0x0000000000000000
|
||||
#define MON_DROP_RESERVED_1A_LSB 63
|
||||
#define MON_DROP_RESERVED_1A_MSB 63
|
||||
#define MON_DROP_RESERVED_1A_MASK 0x8000000000000000
|
||||
|
||||
#endif
|
||||
70
hw/kiwi/v2/mon_ingress_ring.h
Normal file
70
hw/kiwi/v2/mon_ingress_ring.h
Normal file
|
|
@ -0,0 +1,70 @@
|
|||
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
#ifndef _MON_INGRESS_RING_H_
|
||||
#define _MON_INGRESS_RING_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#include "buffer_addr_info.h"
|
||||
#define NUM_OF_DWORDS_MON_INGRESS_RING 4
|
||||
|
||||
struct mon_ingress_ring {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
struct buffer_addr_info buffer_addr_info_details;
|
||||
uint32_t buffer_virt_addr_31_0 : 32;
|
||||
uint32_t buffer_virt_addr_63_32 : 32;
|
||||
#else
|
||||
struct buffer_addr_info buffer_addr_info_details;
|
||||
uint32_t buffer_virt_addr_31_0 : 32;
|
||||
uint32_t buffer_virt_addr_63_32 : 32;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 0x00000000
|
||||
#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_LSB 0
|
||||
#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MSB 31
|
||||
#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_MASK 0xffffffff
|
||||
|
||||
#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_OFFSET 0x00000004
|
||||
#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_LSB 0
|
||||
#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MSB 7
|
||||
#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_39_32_MASK 0x000000ff
|
||||
|
||||
#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_OFFSET 0x00000004
|
||||
#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_LSB 8
|
||||
#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MSB 11
|
||||
#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_RETURN_BUFFER_MANAGER_MASK 0x00000f00
|
||||
|
||||
#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_OFFSET 0x00000004
|
||||
#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_LSB 12
|
||||
#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MSB 31
|
||||
#define MON_INGRESS_RING_BUFFER_ADDR_INFO_DETAILS_SW_BUFFER_COOKIE_MASK 0xfffff000
|
||||
|
||||
#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_OFFSET 0x00000008
|
||||
#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_LSB 0
|
||||
#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_MSB 31
|
||||
#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_MASK 0xffffffff
|
||||
|
||||
#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_OFFSET 0x0000000c
|
||||
#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_LSB 0
|
||||
#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_MSB 31
|
||||
#define MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_MASK 0xffffffff
|
||||
|
||||
#endif
|
||||
124
hw/kiwi/v2/no_ack_report.h
Normal file
124
hw/kiwi/v2/no_ack_report.h
Normal file
|
|
@ -0,0 +1,124 @@
|
|||
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
#ifndef _NO_ACK_REPORT_H_
|
||||
#define _NO_ACK_REPORT_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#define NUM_OF_DWORDS_NO_ACK_REPORT 4
|
||||
|
||||
struct no_ack_report {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t no_ack_transmit_reason : 4,
|
||||
macrx_abort_reason : 4,
|
||||
phyrx_abort_reason : 8,
|
||||
frame_control : 16;
|
||||
uint32_t rx_ppdu_duration : 24,
|
||||
sr_ppdu_during_obss : 1,
|
||||
selfgen_response_reason_to_sr_ppdu : 4,
|
||||
reserved_1 : 3;
|
||||
uint32_t pre_bt_broadcast_status_details : 12,
|
||||
first_bt_broadcast_status_details : 12,
|
||||
reserved_2 : 8;
|
||||
uint32_t second_bt_broadcast_status_details : 12,
|
||||
reserved_3 : 20;
|
||||
#else
|
||||
uint32_t frame_control : 16,
|
||||
phyrx_abort_reason : 8,
|
||||
macrx_abort_reason : 4,
|
||||
no_ack_transmit_reason : 4;
|
||||
uint32_t reserved_1 : 3,
|
||||
selfgen_response_reason_to_sr_ppdu : 4,
|
||||
sr_ppdu_during_obss : 1,
|
||||
rx_ppdu_duration : 24;
|
||||
uint32_t reserved_2 : 8,
|
||||
first_bt_broadcast_status_details : 12,
|
||||
pre_bt_broadcast_status_details : 12;
|
||||
uint32_t reserved_3 : 20,
|
||||
second_bt_broadcast_status_details : 12;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define NO_ACK_REPORT_NO_ACK_TRANSMIT_REASON_OFFSET 0x00000000
|
||||
#define NO_ACK_REPORT_NO_ACK_TRANSMIT_REASON_LSB 0
|
||||
#define NO_ACK_REPORT_NO_ACK_TRANSMIT_REASON_MSB 3
|
||||
#define NO_ACK_REPORT_NO_ACK_TRANSMIT_REASON_MASK 0x0000000f
|
||||
|
||||
#define NO_ACK_REPORT_MACRX_ABORT_REASON_OFFSET 0x00000000
|
||||
#define NO_ACK_REPORT_MACRX_ABORT_REASON_LSB 4
|
||||
#define NO_ACK_REPORT_MACRX_ABORT_REASON_MSB 7
|
||||
#define NO_ACK_REPORT_MACRX_ABORT_REASON_MASK 0x000000f0
|
||||
|
||||
#define NO_ACK_REPORT_PHYRX_ABORT_REASON_OFFSET 0x00000000
|
||||
#define NO_ACK_REPORT_PHYRX_ABORT_REASON_LSB 8
|
||||
#define NO_ACK_REPORT_PHYRX_ABORT_REASON_MSB 15
|
||||
#define NO_ACK_REPORT_PHYRX_ABORT_REASON_MASK 0x0000ff00
|
||||
|
||||
#define NO_ACK_REPORT_FRAME_CONTROL_OFFSET 0x00000000
|
||||
#define NO_ACK_REPORT_FRAME_CONTROL_LSB 16
|
||||
#define NO_ACK_REPORT_FRAME_CONTROL_MSB 31
|
||||
#define NO_ACK_REPORT_FRAME_CONTROL_MASK 0xffff0000
|
||||
|
||||
#define NO_ACK_REPORT_RX_PPDU_DURATION_OFFSET 0x00000004
|
||||
#define NO_ACK_REPORT_RX_PPDU_DURATION_LSB 0
|
||||
#define NO_ACK_REPORT_RX_PPDU_DURATION_MSB 23
|
||||
#define NO_ACK_REPORT_RX_PPDU_DURATION_MASK 0x00ffffff
|
||||
|
||||
#define NO_ACK_REPORT_SR_PPDU_DURING_OBSS_OFFSET 0x00000004
|
||||
#define NO_ACK_REPORT_SR_PPDU_DURING_OBSS_LSB 24
|
||||
#define NO_ACK_REPORT_SR_PPDU_DURING_OBSS_MSB 24
|
||||
#define NO_ACK_REPORT_SR_PPDU_DURING_OBSS_MASK 0x01000000
|
||||
|
||||
#define NO_ACK_REPORT_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_OFFSET 0x00000004
|
||||
#define NO_ACK_REPORT_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_LSB 25
|
||||
#define NO_ACK_REPORT_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_MSB 28
|
||||
#define NO_ACK_REPORT_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_MASK 0x1e000000
|
||||
|
||||
#define NO_ACK_REPORT_RESERVED_1_OFFSET 0x00000004
|
||||
#define NO_ACK_REPORT_RESERVED_1_LSB 29
|
||||
#define NO_ACK_REPORT_RESERVED_1_MSB 31
|
||||
#define NO_ACK_REPORT_RESERVED_1_MASK 0xe0000000
|
||||
|
||||
#define NO_ACK_REPORT_PRE_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x00000008
|
||||
#define NO_ACK_REPORT_PRE_BT_BROADCAST_STATUS_DETAILS_LSB 0
|
||||
#define NO_ACK_REPORT_PRE_BT_BROADCAST_STATUS_DETAILS_MSB 11
|
||||
#define NO_ACK_REPORT_PRE_BT_BROADCAST_STATUS_DETAILS_MASK 0x00000fff
|
||||
|
||||
#define NO_ACK_REPORT_FIRST_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x00000008
|
||||
#define NO_ACK_REPORT_FIRST_BT_BROADCAST_STATUS_DETAILS_LSB 12
|
||||
#define NO_ACK_REPORT_FIRST_BT_BROADCAST_STATUS_DETAILS_MSB 23
|
||||
#define NO_ACK_REPORT_FIRST_BT_BROADCAST_STATUS_DETAILS_MASK 0x00fff000
|
||||
|
||||
#define NO_ACK_REPORT_RESERVED_2_OFFSET 0x00000008
|
||||
#define NO_ACK_REPORT_RESERVED_2_LSB 24
|
||||
#define NO_ACK_REPORT_RESERVED_2_MSB 31
|
||||
#define NO_ACK_REPORT_RESERVED_2_MASK 0xff000000
|
||||
|
||||
#define NO_ACK_REPORT_SECOND_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x0000000c
|
||||
#define NO_ACK_REPORT_SECOND_BT_BROADCAST_STATUS_DETAILS_LSB 0
|
||||
#define NO_ACK_REPORT_SECOND_BT_BROADCAST_STATUS_DETAILS_MSB 11
|
||||
#define NO_ACK_REPORT_SECOND_BT_BROADCAST_STATUS_DETAILS_MASK 0x00000fff
|
||||
|
||||
#define NO_ACK_REPORT_RESERVED_3_OFFSET 0x0000000c
|
||||
#define NO_ACK_REPORT_RESERVED_3_LSB 12
|
||||
#define NO_ACK_REPORT_RESERVED_3_MSB 31
|
||||
#define NO_ACK_REPORT_RESERVED_3_MASK 0xfffff000
|
||||
|
||||
#endif
|
||||
840
hw/kiwi/v2/ofdma_trigger_details.h
Normal file
840
hw/kiwi/v2/ofdma_trigger_details.h
Normal file
|
|
@ -0,0 +1,840 @@
|
|||
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
#ifndef _OFDMA_TRIGGER_DETAILS_H_
|
||||
#define _OFDMA_TRIGGER_DETAILS_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#include "mlo_sta_id_details.h"
|
||||
#define NUM_OF_DWORDS_OFDMA_TRIGGER_DETAILS 22
|
||||
|
||||
#define NUM_OF_QWORDS_OFDMA_TRIGGER_DETAILS 11
|
||||
|
||||
struct ofdma_trigger_details {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t ax_trigger_source : 1,
|
||||
rx_trigger_frame_user_source : 2,
|
||||
received_bandwidth : 3,
|
||||
txop_duration_all_ones : 1,
|
||||
eht_trigger_response : 1,
|
||||
pre_rssi_comb : 8,
|
||||
rssi_comb : 8,
|
||||
rxpcu_pcie_l0_req_duration : 8;
|
||||
uint32_t he_trigger_ul_ppdu_length : 5,
|
||||
he_trigger_ru_allocation : 8,
|
||||
he_trigger_dl_tx_power : 5,
|
||||
he_trigger_ul_target_rssi : 5,
|
||||
he_trigger_ul_mcs : 2,
|
||||
he_trigger_reserved : 1,
|
||||
bss_color : 6;
|
||||
uint32_t trigger_type : 4,
|
||||
lsig_response_length : 12,
|
||||
cascade_indication : 1,
|
||||
carrier_sense : 1,
|
||||
bandwidth : 2,
|
||||
cp_ltf_size : 2,
|
||||
mu_mimo_ltf_mode : 1,
|
||||
number_of_ltfs : 3,
|
||||
stbc : 1,
|
||||
ldpc_extra_symbol : 1,
|
||||
ap_tx_power_lsb_part : 4;
|
||||
uint32_t ap_tx_power_msb_part : 2,
|
||||
packet_extension_a_factor : 2,
|
||||
packet_extension_pe_disambiguity : 1,
|
||||
spatial_reuse : 16,
|
||||
doppler : 1,
|
||||
he_siga_reserved : 9,
|
||||
reserved_3b : 1;
|
||||
uint32_t aid12 : 12,
|
||||
ru_allocation : 9,
|
||||
mcs : 4,
|
||||
dcm : 1,
|
||||
start_spatial_stream : 3,
|
||||
number_of_spatial_stream : 3;
|
||||
uint32_t target_rssi : 7,
|
||||
coding_type : 1,
|
||||
mpdu_mu_spacing_factor : 2,
|
||||
tid_aggregation_limit : 3,
|
||||
reserved_5b : 1,
|
||||
prefered_ac : 2,
|
||||
bar_control_ack_policy : 1,
|
||||
bar_control_multi_tid : 1,
|
||||
bar_control_compressed_bitmap : 1,
|
||||
bar_control_reserved : 9,
|
||||
bar_control_tid_info : 4;
|
||||
uint32_t nr0_per_tid_info_reserved : 12,
|
||||
nr0_per_tid_info_tid_value : 4,
|
||||
nr0_start_seq_ctrl_frag_number : 4,
|
||||
nr0_start_seq_ctrl_start_seq_number : 12;
|
||||
uint32_t nr1_per_tid_info_reserved : 12,
|
||||
nr1_per_tid_info_tid_value : 4,
|
||||
nr1_start_seq_ctrl_frag_number : 4,
|
||||
nr1_start_seq_ctrl_start_seq_number : 12;
|
||||
uint32_t nr2_per_tid_info_reserved : 12,
|
||||
nr2_per_tid_info_tid_value : 4,
|
||||
nr2_start_seq_ctrl_frag_number : 4,
|
||||
nr2_start_seq_ctrl_start_seq_number : 12;
|
||||
uint32_t nr3_per_tid_info_reserved : 12,
|
||||
nr3_per_tid_info_tid_value : 4,
|
||||
nr3_start_seq_ctrl_frag_number : 4,
|
||||
nr3_start_seq_ctrl_start_seq_number : 12;
|
||||
uint32_t nr4_per_tid_info_reserved : 12,
|
||||
nr4_per_tid_info_tid_value : 4,
|
||||
nr4_start_seq_ctrl_frag_number : 4,
|
||||
nr4_start_seq_ctrl_start_seq_number : 12;
|
||||
uint32_t nr5_per_tid_info_reserved : 12,
|
||||
nr5_per_tid_info_tid_value : 4,
|
||||
nr5_start_seq_ctrl_frag_number : 4,
|
||||
nr5_start_seq_ctrl_start_seq_number : 12;
|
||||
uint32_t nr6_per_tid_info_reserved : 12,
|
||||
nr6_per_tid_info_tid_value : 4,
|
||||
nr6_start_seq_ctrl_frag_number : 4,
|
||||
nr6_start_seq_ctrl_start_seq_number : 12;
|
||||
uint32_t nr7_per_tid_info_reserved : 12,
|
||||
nr7_per_tid_info_tid_value : 4,
|
||||
nr7_start_seq_ctrl_frag_number : 4,
|
||||
nr7_start_seq_ctrl_start_seq_number : 12;
|
||||
uint32_t fb_segment_retransmission_bitmap : 8,
|
||||
reserved_14a : 2,
|
||||
u_sig_puncture_pattern_encoding : 6,
|
||||
dot11be_puncture_bitmap : 16;
|
||||
uint32_t rx_chain_mask : 8,
|
||||
rx_duration_field : 16,
|
||||
scrambler_seed : 7,
|
||||
rx_chain_mask_type : 1;
|
||||
struct mlo_sta_id_details mlo_sta_id_details_rx;
|
||||
uint16_t normalized_pre_rssi_comb : 8,
|
||||
normalized_rssi_comb : 8;
|
||||
uint32_t sw_peer_id : 16,
|
||||
response_tx_duration : 16;
|
||||
uint32_t __reserved_g_0005_trigger_subtype : 4,
|
||||
tbr_trigger_common_info_79_68 : 12,
|
||||
tbr_trigger_sound_reserved_20_12 : 9,
|
||||
i2r_rep : 3,
|
||||
tbr_trigger_sound_reserved_25_24 : 2,
|
||||
reserved_18a : 1,
|
||||
qos_null_only_response_tx : 1;
|
||||
uint32_t tbr_trigger_sound_sac : 16,
|
||||
reserved_19a : 8,
|
||||
u_sig_reserved2 : 5,
|
||||
reserved_19b : 3;
|
||||
uint32_t eht_special_aid12 : 12,
|
||||
phy_version : 3,
|
||||
bandwidth_ext : 2,
|
||||
eht_spatial_reuse : 8,
|
||||
u_sig_reserved1 : 7;
|
||||
uint32_t eht_trigger_special_user_info_71_40 : 32;
|
||||
#else
|
||||
uint32_t rxpcu_pcie_l0_req_duration : 8,
|
||||
rssi_comb : 8,
|
||||
pre_rssi_comb : 8,
|
||||
eht_trigger_response : 1,
|
||||
txop_duration_all_ones : 1,
|
||||
received_bandwidth : 3,
|
||||
rx_trigger_frame_user_source : 2,
|
||||
ax_trigger_source : 1;
|
||||
uint32_t bss_color : 6,
|
||||
he_trigger_reserved : 1,
|
||||
he_trigger_ul_mcs : 2,
|
||||
he_trigger_ul_target_rssi : 5,
|
||||
he_trigger_dl_tx_power : 5,
|
||||
he_trigger_ru_allocation : 8,
|
||||
he_trigger_ul_ppdu_length : 5;
|
||||
uint32_t ap_tx_power_lsb_part : 4,
|
||||
ldpc_extra_symbol : 1,
|
||||
stbc : 1,
|
||||
number_of_ltfs : 3,
|
||||
mu_mimo_ltf_mode : 1,
|
||||
cp_ltf_size : 2,
|
||||
bandwidth : 2,
|
||||
carrier_sense : 1,
|
||||
cascade_indication : 1,
|
||||
lsig_response_length : 12,
|
||||
trigger_type : 4;
|
||||
uint32_t reserved_3b : 1,
|
||||
he_siga_reserved : 9,
|
||||
doppler : 1,
|
||||
spatial_reuse : 16,
|
||||
packet_extension_pe_disambiguity : 1,
|
||||
packet_extension_a_factor : 2,
|
||||
ap_tx_power_msb_part : 2;
|
||||
uint32_t number_of_spatial_stream : 3,
|
||||
start_spatial_stream : 3,
|
||||
dcm : 1,
|
||||
mcs : 4,
|
||||
ru_allocation : 9,
|
||||
aid12 : 12;
|
||||
uint32_t bar_control_tid_info : 4,
|
||||
bar_control_reserved : 9,
|
||||
bar_control_compressed_bitmap : 1,
|
||||
bar_control_multi_tid : 1,
|
||||
bar_control_ack_policy : 1,
|
||||
prefered_ac : 2,
|
||||
reserved_5b : 1,
|
||||
tid_aggregation_limit : 3,
|
||||
mpdu_mu_spacing_factor : 2,
|
||||
coding_type : 1,
|
||||
target_rssi : 7;
|
||||
uint32_t nr0_start_seq_ctrl_start_seq_number : 12,
|
||||
nr0_start_seq_ctrl_frag_number : 4,
|
||||
nr0_per_tid_info_tid_value : 4,
|
||||
nr0_per_tid_info_reserved : 12;
|
||||
uint32_t nr1_start_seq_ctrl_start_seq_number : 12,
|
||||
nr1_start_seq_ctrl_frag_number : 4,
|
||||
nr1_per_tid_info_tid_value : 4,
|
||||
nr1_per_tid_info_reserved : 12;
|
||||
uint32_t nr2_start_seq_ctrl_start_seq_number : 12,
|
||||
nr2_start_seq_ctrl_frag_number : 4,
|
||||
nr2_per_tid_info_tid_value : 4,
|
||||
nr2_per_tid_info_reserved : 12;
|
||||
uint32_t nr3_start_seq_ctrl_start_seq_number : 12,
|
||||
nr3_start_seq_ctrl_frag_number : 4,
|
||||
nr3_per_tid_info_tid_value : 4,
|
||||
nr3_per_tid_info_reserved : 12;
|
||||
uint32_t nr4_start_seq_ctrl_start_seq_number : 12,
|
||||
nr4_start_seq_ctrl_frag_number : 4,
|
||||
nr4_per_tid_info_tid_value : 4,
|
||||
nr4_per_tid_info_reserved : 12;
|
||||
uint32_t nr5_start_seq_ctrl_start_seq_number : 12,
|
||||
nr5_start_seq_ctrl_frag_number : 4,
|
||||
nr5_per_tid_info_tid_value : 4,
|
||||
nr5_per_tid_info_reserved : 12;
|
||||
uint32_t nr6_start_seq_ctrl_start_seq_number : 12,
|
||||
nr6_start_seq_ctrl_frag_number : 4,
|
||||
nr6_per_tid_info_tid_value : 4,
|
||||
nr6_per_tid_info_reserved : 12;
|
||||
uint32_t nr7_start_seq_ctrl_start_seq_number : 12,
|
||||
nr7_start_seq_ctrl_frag_number : 4,
|
||||
nr7_per_tid_info_tid_value : 4,
|
||||
nr7_per_tid_info_reserved : 12;
|
||||
uint32_t dot11be_puncture_bitmap : 16,
|
||||
u_sig_puncture_pattern_encoding : 6,
|
||||
reserved_14a : 2,
|
||||
fb_segment_retransmission_bitmap : 8;
|
||||
uint32_t rx_chain_mask_type : 1,
|
||||
scrambler_seed : 7,
|
||||
rx_duration_field : 16,
|
||||
rx_chain_mask : 8;
|
||||
uint32_t normalized_rssi_comb : 8,
|
||||
normalized_pre_rssi_comb : 8;
|
||||
struct mlo_sta_id_details mlo_sta_id_details_rx;
|
||||
uint32_t response_tx_duration : 16,
|
||||
sw_peer_id : 16;
|
||||
uint32_t qos_null_only_response_tx : 1,
|
||||
reserved_18a : 1,
|
||||
tbr_trigger_sound_reserved_25_24 : 2,
|
||||
i2r_rep : 3,
|
||||
tbr_trigger_sound_reserved_20_12 : 9,
|
||||
tbr_trigger_common_info_79_68 : 12,
|
||||
__reserved_g_0005_trigger_subtype : 4;
|
||||
uint32_t reserved_19b : 3,
|
||||
u_sig_reserved2 : 5,
|
||||
reserved_19a : 8,
|
||||
tbr_trigger_sound_sac : 16;
|
||||
uint32_t u_sig_reserved1 : 7,
|
||||
eht_spatial_reuse : 8,
|
||||
bandwidth_ext : 2,
|
||||
phy_version : 3,
|
||||
eht_special_aid12 : 12;
|
||||
uint32_t eht_trigger_special_user_info_71_40 : 32;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_OFFSET 0x0000000000000000
|
||||
#define OFDMA_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_LSB 0
|
||||
#define OFDMA_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_MSB 0
|
||||
#define OFDMA_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_MASK 0x0000000000000001
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_RX_TRIGGER_FRAME_USER_SOURCE_OFFSET 0x0000000000000000
|
||||
#define OFDMA_TRIGGER_DETAILS_RX_TRIGGER_FRAME_USER_SOURCE_LSB 1
|
||||
#define OFDMA_TRIGGER_DETAILS_RX_TRIGGER_FRAME_USER_SOURCE_MSB 2
|
||||
#define OFDMA_TRIGGER_DETAILS_RX_TRIGGER_FRAME_USER_SOURCE_MASK 0x0000000000000006
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_RECEIVED_BANDWIDTH_OFFSET 0x0000000000000000
|
||||
#define OFDMA_TRIGGER_DETAILS_RECEIVED_BANDWIDTH_LSB 3
|
||||
#define OFDMA_TRIGGER_DETAILS_RECEIVED_BANDWIDTH_MSB 5
|
||||
#define OFDMA_TRIGGER_DETAILS_RECEIVED_BANDWIDTH_MASK 0x0000000000000038
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_TXOP_DURATION_ALL_ONES_OFFSET 0x0000000000000000
|
||||
#define OFDMA_TRIGGER_DETAILS_TXOP_DURATION_ALL_ONES_LSB 6
|
||||
#define OFDMA_TRIGGER_DETAILS_TXOP_DURATION_ALL_ONES_MSB 6
|
||||
#define OFDMA_TRIGGER_DETAILS_TXOP_DURATION_ALL_ONES_MASK 0x0000000000000040
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_RESPONSE_OFFSET 0x0000000000000000
|
||||
#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_RESPONSE_LSB 7
|
||||
#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_RESPONSE_MSB 7
|
||||
#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_RESPONSE_MASK 0x0000000000000080
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_PRE_RSSI_COMB_OFFSET 0x0000000000000000
|
||||
#define OFDMA_TRIGGER_DETAILS_PRE_RSSI_COMB_LSB 8
|
||||
#define OFDMA_TRIGGER_DETAILS_PRE_RSSI_COMB_MSB 15
|
||||
#define OFDMA_TRIGGER_DETAILS_PRE_RSSI_COMB_MASK 0x000000000000ff00
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_RSSI_COMB_OFFSET 0x0000000000000000
|
||||
#define OFDMA_TRIGGER_DETAILS_RSSI_COMB_LSB 16
|
||||
#define OFDMA_TRIGGER_DETAILS_RSSI_COMB_MSB 23
|
||||
#define OFDMA_TRIGGER_DETAILS_RSSI_COMB_MASK 0x0000000000ff0000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_RXPCU_PCIE_L0_REQ_DURATION_OFFSET 0x0000000000000000
|
||||
#define OFDMA_TRIGGER_DETAILS_RXPCU_PCIE_L0_REQ_DURATION_LSB 24
|
||||
#define OFDMA_TRIGGER_DETAILS_RXPCU_PCIE_L0_REQ_DURATION_MSB 31
|
||||
#define OFDMA_TRIGGER_DETAILS_RXPCU_PCIE_L0_REQ_DURATION_MASK 0x00000000ff000000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_PPDU_LENGTH_OFFSET 0x0000000000000000
|
||||
#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_PPDU_LENGTH_LSB 32
|
||||
#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_PPDU_LENGTH_MSB 36
|
||||
#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_PPDU_LENGTH_MASK 0x0000001f00000000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RU_ALLOCATION_OFFSET 0x0000000000000000
|
||||
#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RU_ALLOCATION_LSB 37
|
||||
#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RU_ALLOCATION_MSB 44
|
||||
#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RU_ALLOCATION_MASK 0x00001fe000000000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_DL_TX_POWER_OFFSET 0x0000000000000000
|
||||
#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_DL_TX_POWER_LSB 45
|
||||
#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_DL_TX_POWER_MSB 49
|
||||
#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_DL_TX_POWER_MASK 0x0003e00000000000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_TARGET_RSSI_OFFSET 0x0000000000000000
|
||||
#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_TARGET_RSSI_LSB 50
|
||||
#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_TARGET_RSSI_MSB 54
|
||||
#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_TARGET_RSSI_MASK 0x007c000000000000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_MCS_OFFSET 0x0000000000000000
|
||||
#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_MCS_LSB 55
|
||||
#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_MCS_MSB 56
|
||||
#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_UL_MCS_MASK 0x0180000000000000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RESERVED_OFFSET 0x0000000000000000
|
||||
#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RESERVED_LSB 57
|
||||
#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RESERVED_MSB 57
|
||||
#define OFDMA_TRIGGER_DETAILS_HE_TRIGGER_RESERVED_MASK 0x0200000000000000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_BSS_COLOR_OFFSET 0x0000000000000000
|
||||
#define OFDMA_TRIGGER_DETAILS_BSS_COLOR_LSB 58
|
||||
#define OFDMA_TRIGGER_DETAILS_BSS_COLOR_MSB 63
|
||||
#define OFDMA_TRIGGER_DETAILS_BSS_COLOR_MASK 0xfc00000000000000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_TRIGGER_TYPE_OFFSET 0x0000000000000008
|
||||
#define OFDMA_TRIGGER_DETAILS_TRIGGER_TYPE_LSB 0
|
||||
#define OFDMA_TRIGGER_DETAILS_TRIGGER_TYPE_MSB 3
|
||||
#define OFDMA_TRIGGER_DETAILS_TRIGGER_TYPE_MASK 0x000000000000000f
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_OFFSET 0x0000000000000008
|
||||
#define OFDMA_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_LSB 4
|
||||
#define OFDMA_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_MSB 15
|
||||
#define OFDMA_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_MASK 0x000000000000fff0
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_CASCADE_INDICATION_OFFSET 0x0000000000000008
|
||||
#define OFDMA_TRIGGER_DETAILS_CASCADE_INDICATION_LSB 16
|
||||
#define OFDMA_TRIGGER_DETAILS_CASCADE_INDICATION_MSB 16
|
||||
#define OFDMA_TRIGGER_DETAILS_CASCADE_INDICATION_MASK 0x0000000000010000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_CARRIER_SENSE_OFFSET 0x0000000000000008
|
||||
#define OFDMA_TRIGGER_DETAILS_CARRIER_SENSE_LSB 17
|
||||
#define OFDMA_TRIGGER_DETAILS_CARRIER_SENSE_MSB 17
|
||||
#define OFDMA_TRIGGER_DETAILS_CARRIER_SENSE_MASK 0x0000000000020000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_OFFSET 0x0000000000000008
|
||||
#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_LSB 18
|
||||
#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_MSB 19
|
||||
#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_MASK 0x00000000000c0000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_CP_LTF_SIZE_OFFSET 0x0000000000000008
|
||||
#define OFDMA_TRIGGER_DETAILS_CP_LTF_SIZE_LSB 20
|
||||
#define OFDMA_TRIGGER_DETAILS_CP_LTF_SIZE_MSB 21
|
||||
#define OFDMA_TRIGGER_DETAILS_CP_LTF_SIZE_MASK 0x0000000000300000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_MU_MIMO_LTF_MODE_OFFSET 0x0000000000000008
|
||||
#define OFDMA_TRIGGER_DETAILS_MU_MIMO_LTF_MODE_LSB 22
|
||||
#define OFDMA_TRIGGER_DETAILS_MU_MIMO_LTF_MODE_MSB 22
|
||||
#define OFDMA_TRIGGER_DETAILS_MU_MIMO_LTF_MODE_MASK 0x0000000000400000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_LTFS_OFFSET 0x0000000000000008
|
||||
#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_LTFS_LSB 23
|
||||
#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_LTFS_MSB 25
|
||||
#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_LTFS_MASK 0x0000000003800000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_STBC_OFFSET 0x0000000000000008
|
||||
#define OFDMA_TRIGGER_DETAILS_STBC_LSB 26
|
||||
#define OFDMA_TRIGGER_DETAILS_STBC_MSB 26
|
||||
#define OFDMA_TRIGGER_DETAILS_STBC_MASK 0x0000000004000000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000008
|
||||
#define OFDMA_TRIGGER_DETAILS_LDPC_EXTRA_SYMBOL_LSB 27
|
||||
#define OFDMA_TRIGGER_DETAILS_LDPC_EXTRA_SYMBOL_MSB 27
|
||||
#define OFDMA_TRIGGER_DETAILS_LDPC_EXTRA_SYMBOL_MASK 0x0000000008000000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_LSB_PART_OFFSET 0x0000000000000008
|
||||
#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_LSB_PART_LSB 28
|
||||
#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_LSB_PART_MSB 31
|
||||
#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_LSB_PART_MASK 0x00000000f0000000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_MSB_PART_OFFSET 0x0000000000000008
|
||||
#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_MSB_PART_LSB 32
|
||||
#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_MSB_PART_MSB 33
|
||||
#define OFDMA_TRIGGER_DETAILS_AP_TX_POWER_MSB_PART_MASK 0x0000000300000000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000000000000008
|
||||
#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_A_FACTOR_LSB 34
|
||||
#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_A_FACTOR_MSB 35
|
||||
#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_A_FACTOR_MASK 0x0000000c00000000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000000000000008
|
||||
#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 36
|
||||
#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 36
|
||||
#define OFDMA_TRIGGER_DETAILS_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x0000001000000000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_SPATIAL_REUSE_OFFSET 0x0000000000000008
|
||||
#define OFDMA_TRIGGER_DETAILS_SPATIAL_REUSE_LSB 37
|
||||
#define OFDMA_TRIGGER_DETAILS_SPATIAL_REUSE_MSB 52
|
||||
#define OFDMA_TRIGGER_DETAILS_SPATIAL_REUSE_MASK 0x001fffe000000000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_DOPPLER_OFFSET 0x0000000000000008
|
||||
#define OFDMA_TRIGGER_DETAILS_DOPPLER_LSB 53
|
||||
#define OFDMA_TRIGGER_DETAILS_DOPPLER_MSB 53
|
||||
#define OFDMA_TRIGGER_DETAILS_DOPPLER_MASK 0x0020000000000000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_HE_SIGA_RESERVED_OFFSET 0x0000000000000008
|
||||
#define OFDMA_TRIGGER_DETAILS_HE_SIGA_RESERVED_LSB 54
|
||||
#define OFDMA_TRIGGER_DETAILS_HE_SIGA_RESERVED_MSB 62
|
||||
#define OFDMA_TRIGGER_DETAILS_HE_SIGA_RESERVED_MASK 0x7fc0000000000000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_RESERVED_3B_OFFSET 0x0000000000000008
|
||||
#define OFDMA_TRIGGER_DETAILS_RESERVED_3B_LSB 63
|
||||
#define OFDMA_TRIGGER_DETAILS_RESERVED_3B_MSB 63
|
||||
#define OFDMA_TRIGGER_DETAILS_RESERVED_3B_MASK 0x8000000000000000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_AID12_OFFSET 0x0000000000000010
|
||||
#define OFDMA_TRIGGER_DETAILS_AID12_LSB 0
|
||||
#define OFDMA_TRIGGER_DETAILS_AID12_MSB 11
|
||||
#define OFDMA_TRIGGER_DETAILS_AID12_MASK 0x0000000000000fff
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_RU_ALLOCATION_OFFSET 0x0000000000000010
|
||||
#define OFDMA_TRIGGER_DETAILS_RU_ALLOCATION_LSB 12
|
||||
#define OFDMA_TRIGGER_DETAILS_RU_ALLOCATION_MSB 20
|
||||
#define OFDMA_TRIGGER_DETAILS_RU_ALLOCATION_MASK 0x00000000001ff000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_MCS_OFFSET 0x0000000000000010
|
||||
#define OFDMA_TRIGGER_DETAILS_MCS_LSB 21
|
||||
#define OFDMA_TRIGGER_DETAILS_MCS_MSB 24
|
||||
#define OFDMA_TRIGGER_DETAILS_MCS_MASK 0x0000000001e00000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_DCM_OFFSET 0x0000000000000010
|
||||
#define OFDMA_TRIGGER_DETAILS_DCM_LSB 25
|
||||
#define OFDMA_TRIGGER_DETAILS_DCM_MSB 25
|
||||
#define OFDMA_TRIGGER_DETAILS_DCM_MASK 0x0000000002000000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_START_SPATIAL_STREAM_OFFSET 0x0000000000000010
|
||||
#define OFDMA_TRIGGER_DETAILS_START_SPATIAL_STREAM_LSB 26
|
||||
#define OFDMA_TRIGGER_DETAILS_START_SPATIAL_STREAM_MSB 28
|
||||
#define OFDMA_TRIGGER_DETAILS_START_SPATIAL_STREAM_MASK 0x000000001c000000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_SPATIAL_STREAM_OFFSET 0x0000000000000010
|
||||
#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_SPATIAL_STREAM_LSB 29
|
||||
#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_SPATIAL_STREAM_MSB 31
|
||||
#define OFDMA_TRIGGER_DETAILS_NUMBER_OF_SPATIAL_STREAM_MASK 0x00000000e0000000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_TARGET_RSSI_OFFSET 0x0000000000000010
|
||||
#define OFDMA_TRIGGER_DETAILS_TARGET_RSSI_LSB 32
|
||||
#define OFDMA_TRIGGER_DETAILS_TARGET_RSSI_MSB 38
|
||||
#define OFDMA_TRIGGER_DETAILS_TARGET_RSSI_MASK 0x0000007f00000000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_OFFSET 0x0000000000000010
|
||||
#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_LSB 39
|
||||
#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_MSB 39
|
||||
#define OFDMA_TRIGGER_DETAILS_CODING_TYPE_MASK 0x0000008000000000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_MPDU_MU_SPACING_FACTOR_OFFSET 0x0000000000000010
|
||||
#define OFDMA_TRIGGER_DETAILS_MPDU_MU_SPACING_FACTOR_LSB 40
|
||||
#define OFDMA_TRIGGER_DETAILS_MPDU_MU_SPACING_FACTOR_MSB 41
|
||||
#define OFDMA_TRIGGER_DETAILS_MPDU_MU_SPACING_FACTOR_MASK 0x0000030000000000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_OFFSET 0x0000000000000010
|
||||
#define OFDMA_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_LSB 42
|
||||
#define OFDMA_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_MSB 44
|
||||
#define OFDMA_TRIGGER_DETAILS_TID_AGGREGATION_LIMIT_MASK 0x00001c0000000000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_RESERVED_5B_OFFSET 0x0000000000000010
|
||||
#define OFDMA_TRIGGER_DETAILS_RESERVED_5B_LSB 45
|
||||
#define OFDMA_TRIGGER_DETAILS_RESERVED_5B_MSB 45
|
||||
#define OFDMA_TRIGGER_DETAILS_RESERVED_5B_MASK 0x0000200000000000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_PREFERED_AC_OFFSET 0x0000000000000010
|
||||
#define OFDMA_TRIGGER_DETAILS_PREFERED_AC_LSB 46
|
||||
#define OFDMA_TRIGGER_DETAILS_PREFERED_AC_MSB 47
|
||||
#define OFDMA_TRIGGER_DETAILS_PREFERED_AC_MASK 0x0000c00000000000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_ACK_POLICY_OFFSET 0x0000000000000010
|
||||
#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_ACK_POLICY_LSB 48
|
||||
#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_ACK_POLICY_MSB 48
|
||||
#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_ACK_POLICY_MASK 0x0001000000000000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_MULTI_TID_OFFSET 0x0000000000000010
|
||||
#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_MULTI_TID_LSB 49
|
||||
#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_MULTI_TID_MSB 49
|
||||
#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_MULTI_TID_MASK 0x0002000000000000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_COMPRESSED_BITMAP_OFFSET 0x0000000000000010
|
||||
#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_COMPRESSED_BITMAP_LSB 50
|
||||
#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_COMPRESSED_BITMAP_MSB 50
|
||||
#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_COMPRESSED_BITMAP_MASK 0x0004000000000000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_RESERVED_OFFSET 0x0000000000000010
|
||||
#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_RESERVED_LSB 51
|
||||
#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_RESERVED_MSB 59
|
||||
#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_RESERVED_MASK 0x0ff8000000000000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_TID_INFO_OFFSET 0x0000000000000010
|
||||
#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_TID_INFO_LSB 60
|
||||
#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_TID_INFO_MSB 63
|
||||
#define OFDMA_TRIGGER_DETAILS_BAR_CONTROL_TID_INFO_MASK 0xf000000000000000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_RESERVED_OFFSET 0x0000000000000018
|
||||
#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_RESERVED_LSB 0
|
||||
#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_RESERVED_MSB 11
|
||||
#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_RESERVED_MASK 0x0000000000000fff
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_TID_VALUE_OFFSET 0x0000000000000018
|
||||
#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_TID_VALUE_LSB 12
|
||||
#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_TID_VALUE_MSB 15
|
||||
#define OFDMA_TRIGGER_DETAILS_NR0_PER_TID_INFO_TID_VALUE_MASK 0x000000000000f000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000000000000018
|
||||
#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_FRAG_NUMBER_LSB 16
|
||||
#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_FRAG_NUMBER_MSB 19
|
||||
#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x00000000000f0000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000000000000018
|
||||
#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 20
|
||||
#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 31
|
||||
#define OFDMA_TRIGGER_DETAILS_NR0_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0x00000000fff00000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_RESERVED_OFFSET 0x0000000000000018
|
||||
#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_RESERVED_LSB 32
|
||||
#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_RESERVED_MSB 43
|
||||
#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_RESERVED_MASK 0x00000fff00000000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_TID_VALUE_OFFSET 0x0000000000000018
|
||||
#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_TID_VALUE_LSB 44
|
||||
#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_TID_VALUE_MSB 47
|
||||
#define OFDMA_TRIGGER_DETAILS_NR1_PER_TID_INFO_TID_VALUE_MASK 0x0000f00000000000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000000000000018
|
||||
#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_FRAG_NUMBER_LSB 48
|
||||
#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_FRAG_NUMBER_MSB 51
|
||||
#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x000f000000000000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000000000000018
|
||||
#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 52
|
||||
#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 63
|
||||
#define OFDMA_TRIGGER_DETAILS_NR1_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0xfff0000000000000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_RESERVED_OFFSET 0x0000000000000020
|
||||
#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_RESERVED_LSB 0
|
||||
#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_RESERVED_MSB 11
|
||||
#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_RESERVED_MASK 0x0000000000000fff
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_TID_VALUE_OFFSET 0x0000000000000020
|
||||
#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_TID_VALUE_LSB 12
|
||||
#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_TID_VALUE_MSB 15
|
||||
#define OFDMA_TRIGGER_DETAILS_NR2_PER_TID_INFO_TID_VALUE_MASK 0x000000000000f000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000000000000020
|
||||
#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_FRAG_NUMBER_LSB 16
|
||||
#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_FRAG_NUMBER_MSB 19
|
||||
#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x00000000000f0000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000000000000020
|
||||
#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 20
|
||||
#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 31
|
||||
#define OFDMA_TRIGGER_DETAILS_NR2_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0x00000000fff00000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_RESERVED_OFFSET 0x0000000000000020
|
||||
#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_RESERVED_LSB 32
|
||||
#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_RESERVED_MSB 43
|
||||
#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_RESERVED_MASK 0x00000fff00000000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_TID_VALUE_OFFSET 0x0000000000000020
|
||||
#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_TID_VALUE_LSB 44
|
||||
#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_TID_VALUE_MSB 47
|
||||
#define OFDMA_TRIGGER_DETAILS_NR3_PER_TID_INFO_TID_VALUE_MASK 0x0000f00000000000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000000000000020
|
||||
#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_FRAG_NUMBER_LSB 48
|
||||
#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_FRAG_NUMBER_MSB 51
|
||||
#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x000f000000000000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000000000000020
|
||||
#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 52
|
||||
#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 63
|
||||
#define OFDMA_TRIGGER_DETAILS_NR3_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0xfff0000000000000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_RESERVED_OFFSET 0x0000000000000028
|
||||
#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_RESERVED_LSB 0
|
||||
#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_RESERVED_MSB 11
|
||||
#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_RESERVED_MASK 0x0000000000000fff
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_TID_VALUE_OFFSET 0x0000000000000028
|
||||
#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_TID_VALUE_LSB 12
|
||||
#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_TID_VALUE_MSB 15
|
||||
#define OFDMA_TRIGGER_DETAILS_NR4_PER_TID_INFO_TID_VALUE_MASK 0x000000000000f000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000000000000028
|
||||
#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_FRAG_NUMBER_LSB 16
|
||||
#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_FRAG_NUMBER_MSB 19
|
||||
#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x00000000000f0000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000000000000028
|
||||
#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 20
|
||||
#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 31
|
||||
#define OFDMA_TRIGGER_DETAILS_NR4_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0x00000000fff00000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_RESERVED_OFFSET 0x0000000000000028
|
||||
#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_RESERVED_LSB 32
|
||||
#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_RESERVED_MSB 43
|
||||
#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_RESERVED_MASK 0x00000fff00000000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_TID_VALUE_OFFSET 0x0000000000000028
|
||||
#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_TID_VALUE_LSB 44
|
||||
#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_TID_VALUE_MSB 47
|
||||
#define OFDMA_TRIGGER_DETAILS_NR5_PER_TID_INFO_TID_VALUE_MASK 0x0000f00000000000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000000000000028
|
||||
#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_FRAG_NUMBER_LSB 48
|
||||
#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_FRAG_NUMBER_MSB 51
|
||||
#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x000f000000000000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000000000000028
|
||||
#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 52
|
||||
#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 63
|
||||
#define OFDMA_TRIGGER_DETAILS_NR5_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0xfff0000000000000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_RESERVED_OFFSET 0x0000000000000030
|
||||
#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_RESERVED_LSB 0
|
||||
#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_RESERVED_MSB 11
|
||||
#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_RESERVED_MASK 0x0000000000000fff
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_TID_VALUE_OFFSET 0x0000000000000030
|
||||
#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_TID_VALUE_LSB 12
|
||||
#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_TID_VALUE_MSB 15
|
||||
#define OFDMA_TRIGGER_DETAILS_NR6_PER_TID_INFO_TID_VALUE_MASK 0x000000000000f000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000000000000030
|
||||
#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_FRAG_NUMBER_LSB 16
|
||||
#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_FRAG_NUMBER_MSB 19
|
||||
#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x00000000000f0000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000000000000030
|
||||
#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 20
|
||||
#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 31
|
||||
#define OFDMA_TRIGGER_DETAILS_NR6_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0x00000000fff00000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_RESERVED_OFFSET 0x0000000000000030
|
||||
#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_RESERVED_LSB 32
|
||||
#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_RESERVED_MSB 43
|
||||
#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_RESERVED_MASK 0x00000fff00000000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_TID_VALUE_OFFSET 0x0000000000000030
|
||||
#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_TID_VALUE_LSB 44
|
||||
#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_TID_VALUE_MSB 47
|
||||
#define OFDMA_TRIGGER_DETAILS_NR7_PER_TID_INFO_TID_VALUE_MASK 0x0000f00000000000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_FRAG_NUMBER_OFFSET 0x0000000000000030
|
||||
#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_FRAG_NUMBER_LSB 48
|
||||
#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_FRAG_NUMBER_MSB 51
|
||||
#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_FRAG_NUMBER_MASK 0x000f000000000000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_START_SEQ_NUMBER_OFFSET 0x0000000000000030
|
||||
#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_START_SEQ_NUMBER_LSB 52
|
||||
#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_START_SEQ_NUMBER_MSB 63
|
||||
#define OFDMA_TRIGGER_DETAILS_NR7_START_SEQ_CTRL_START_SEQ_NUMBER_MASK 0xfff0000000000000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_FB_SEGMENT_RETRANSMISSION_BITMAP_OFFSET 0x0000000000000038
|
||||
#define OFDMA_TRIGGER_DETAILS_FB_SEGMENT_RETRANSMISSION_BITMAP_LSB 0
|
||||
#define OFDMA_TRIGGER_DETAILS_FB_SEGMENT_RETRANSMISSION_BITMAP_MSB 7
|
||||
#define OFDMA_TRIGGER_DETAILS_FB_SEGMENT_RETRANSMISSION_BITMAP_MASK 0x00000000000000ff
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_RESERVED_14A_OFFSET 0x0000000000000038
|
||||
#define OFDMA_TRIGGER_DETAILS_RESERVED_14A_LSB 8
|
||||
#define OFDMA_TRIGGER_DETAILS_RESERVED_14A_MSB 9
|
||||
#define OFDMA_TRIGGER_DETAILS_RESERVED_14A_MASK 0x0000000000000300
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000038
|
||||
#define OFDMA_TRIGGER_DETAILS_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 10
|
||||
#define OFDMA_TRIGGER_DETAILS_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 15
|
||||
#define OFDMA_TRIGGER_DETAILS_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0x000000000000fc00
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_DOT11BE_PUNCTURE_BITMAP_OFFSET 0x0000000000000038
|
||||
#define OFDMA_TRIGGER_DETAILS_DOT11BE_PUNCTURE_BITMAP_LSB 16
|
||||
#define OFDMA_TRIGGER_DETAILS_DOT11BE_PUNCTURE_BITMAP_MSB 31
|
||||
#define OFDMA_TRIGGER_DETAILS_DOT11BE_PUNCTURE_BITMAP_MASK 0x00000000ffff0000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_OFFSET 0x0000000000000038
|
||||
#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_LSB 32
|
||||
#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_MSB 39
|
||||
#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_MASK 0x000000ff00000000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_RX_DURATION_FIELD_OFFSET 0x0000000000000038
|
||||
#define OFDMA_TRIGGER_DETAILS_RX_DURATION_FIELD_LSB 40
|
||||
#define OFDMA_TRIGGER_DETAILS_RX_DURATION_FIELD_MSB 55
|
||||
#define OFDMA_TRIGGER_DETAILS_RX_DURATION_FIELD_MASK 0x00ffff0000000000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_SCRAMBLER_SEED_OFFSET 0x0000000000000038
|
||||
#define OFDMA_TRIGGER_DETAILS_SCRAMBLER_SEED_LSB 56
|
||||
#define OFDMA_TRIGGER_DETAILS_SCRAMBLER_SEED_MSB 62
|
||||
#define OFDMA_TRIGGER_DETAILS_SCRAMBLER_SEED_MASK 0x7f00000000000000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_TYPE_OFFSET 0x0000000000000038
|
||||
#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_TYPE_LSB 63
|
||||
#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_TYPE_MSB 63
|
||||
#define OFDMA_TRIGGER_DETAILS_RX_CHAIN_MASK_TYPE_MASK 0x8000000000000000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000000000000040
|
||||
#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0
|
||||
#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9
|
||||
#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x00000000000003ff
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000000000000040
|
||||
#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10
|
||||
#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10
|
||||
#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000000000000400
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000040
|
||||
#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11
|
||||
#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11
|
||||
#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000000000000800
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000040
|
||||
#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12
|
||||
#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12
|
||||
#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000000000001000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000000000000040
|
||||
#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13
|
||||
#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15
|
||||
#define OFDMA_TRIGGER_DETAILS_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x000000000000e000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_NORMALIZED_PRE_RSSI_COMB_OFFSET 0x0000000000000040
|
||||
#define OFDMA_TRIGGER_DETAILS_NORMALIZED_PRE_RSSI_COMB_LSB 16
|
||||
#define OFDMA_TRIGGER_DETAILS_NORMALIZED_PRE_RSSI_COMB_MSB 23
|
||||
#define OFDMA_TRIGGER_DETAILS_NORMALIZED_PRE_RSSI_COMB_MASK 0x0000000000ff0000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_NORMALIZED_RSSI_COMB_OFFSET 0x0000000000000040
|
||||
#define OFDMA_TRIGGER_DETAILS_NORMALIZED_RSSI_COMB_LSB 24
|
||||
#define OFDMA_TRIGGER_DETAILS_NORMALIZED_RSSI_COMB_MSB 31
|
||||
#define OFDMA_TRIGGER_DETAILS_NORMALIZED_RSSI_COMB_MASK 0x00000000ff000000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_SW_PEER_ID_OFFSET 0x0000000000000040
|
||||
#define OFDMA_TRIGGER_DETAILS_SW_PEER_ID_LSB 32
|
||||
#define OFDMA_TRIGGER_DETAILS_SW_PEER_ID_MSB 47
|
||||
#define OFDMA_TRIGGER_DETAILS_SW_PEER_ID_MASK 0x0000ffff00000000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_RESPONSE_TX_DURATION_OFFSET 0x0000000000000040
|
||||
#define OFDMA_TRIGGER_DETAILS_RESPONSE_TX_DURATION_LSB 48
|
||||
#define OFDMA_TRIGGER_DETAILS_RESPONSE_TX_DURATION_MSB 63
|
||||
#define OFDMA_TRIGGER_DETAILS_RESPONSE_TX_DURATION_MASK 0xffff000000000000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_RANGING_TRIGGER_SUBTYPE_OFFSET 0x0000000000000048
|
||||
#define OFDMA_TRIGGER_DETAILS_RANGING_TRIGGER_SUBTYPE_LSB 0
|
||||
#define OFDMA_TRIGGER_DETAILS_RANGING_TRIGGER_SUBTYPE_MSB 3
|
||||
#define OFDMA_TRIGGER_DETAILS_RANGING_TRIGGER_SUBTYPE_MASK 0x000000000000000f
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_COMMON_INFO_79_68_OFFSET 0x0000000000000048
|
||||
#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_COMMON_INFO_79_68_LSB 4
|
||||
#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_COMMON_INFO_79_68_MSB 15
|
||||
#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_COMMON_INFO_79_68_MASK 0x000000000000fff0
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_20_12_OFFSET 0x0000000000000048
|
||||
#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_20_12_LSB 16
|
||||
#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_20_12_MSB 24
|
||||
#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_20_12_MASK 0x0000000001ff0000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_I2R_REP_OFFSET 0x0000000000000048
|
||||
#define OFDMA_TRIGGER_DETAILS_I2R_REP_LSB 25
|
||||
#define OFDMA_TRIGGER_DETAILS_I2R_REP_MSB 27
|
||||
#define OFDMA_TRIGGER_DETAILS_I2R_REP_MASK 0x000000000e000000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_25_24_OFFSET 0x0000000000000048
|
||||
#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_25_24_LSB 28
|
||||
#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_25_24_MSB 29
|
||||
#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_RESERVED_25_24_MASK 0x0000000030000000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_RESERVED_18A_OFFSET 0x0000000000000048
|
||||
#define OFDMA_TRIGGER_DETAILS_RESERVED_18A_LSB 30
|
||||
#define OFDMA_TRIGGER_DETAILS_RESERVED_18A_MSB 30
|
||||
#define OFDMA_TRIGGER_DETAILS_RESERVED_18A_MASK 0x0000000040000000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_QOS_NULL_ONLY_RESPONSE_TX_OFFSET 0x0000000000000048
|
||||
#define OFDMA_TRIGGER_DETAILS_QOS_NULL_ONLY_RESPONSE_TX_LSB 31
|
||||
#define OFDMA_TRIGGER_DETAILS_QOS_NULL_ONLY_RESPONSE_TX_MSB 31
|
||||
#define OFDMA_TRIGGER_DETAILS_QOS_NULL_ONLY_RESPONSE_TX_MASK 0x0000000080000000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_SAC_OFFSET 0x0000000000000048
|
||||
#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_SAC_LSB 32
|
||||
#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_SAC_MSB 47
|
||||
#define OFDMA_TRIGGER_DETAILS_TBR_TRIGGER_SOUND_SAC_MASK 0x0000ffff00000000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_RESERVED_19A_OFFSET 0x0000000000000048
|
||||
#define OFDMA_TRIGGER_DETAILS_RESERVED_19A_LSB 48
|
||||
#define OFDMA_TRIGGER_DETAILS_RESERVED_19A_MSB 55
|
||||
#define OFDMA_TRIGGER_DETAILS_RESERVED_19A_MASK 0x00ff000000000000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED2_OFFSET 0x0000000000000048
|
||||
#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED2_LSB 56
|
||||
#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED2_MSB 60
|
||||
#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED2_MASK 0x1f00000000000000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_RESERVED_19B_OFFSET 0x0000000000000048
|
||||
#define OFDMA_TRIGGER_DETAILS_RESERVED_19B_LSB 61
|
||||
#define OFDMA_TRIGGER_DETAILS_RESERVED_19B_MSB 63
|
||||
#define OFDMA_TRIGGER_DETAILS_RESERVED_19B_MASK 0xe000000000000000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_EHT_SPECIAL_AID12_OFFSET 0x0000000000000050
|
||||
#define OFDMA_TRIGGER_DETAILS_EHT_SPECIAL_AID12_LSB 0
|
||||
#define OFDMA_TRIGGER_DETAILS_EHT_SPECIAL_AID12_MSB 11
|
||||
#define OFDMA_TRIGGER_DETAILS_EHT_SPECIAL_AID12_MASK 0x0000000000000fff
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_PHY_VERSION_OFFSET 0x0000000000000050
|
||||
#define OFDMA_TRIGGER_DETAILS_PHY_VERSION_LSB 12
|
||||
#define OFDMA_TRIGGER_DETAILS_PHY_VERSION_MSB 14
|
||||
#define OFDMA_TRIGGER_DETAILS_PHY_VERSION_MASK 0x0000000000007000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_EXT_OFFSET 0x0000000000000050
|
||||
#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_EXT_LSB 15
|
||||
#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_EXT_MSB 16
|
||||
#define OFDMA_TRIGGER_DETAILS_BANDWIDTH_EXT_MASK 0x0000000000018000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_EHT_SPATIAL_REUSE_OFFSET 0x0000000000000050
|
||||
#define OFDMA_TRIGGER_DETAILS_EHT_SPATIAL_REUSE_LSB 17
|
||||
#define OFDMA_TRIGGER_DETAILS_EHT_SPATIAL_REUSE_MSB 24
|
||||
#define OFDMA_TRIGGER_DETAILS_EHT_SPATIAL_REUSE_MASK 0x0000000001fe0000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED1_OFFSET 0x0000000000000050
|
||||
#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED1_LSB 25
|
||||
#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED1_MSB 31
|
||||
#define OFDMA_TRIGGER_DETAILS_U_SIG_RESERVED1_MASK 0x00000000fe000000
|
||||
|
||||
#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_SPECIAL_USER_INFO_71_40_OFFSET 0x0000000000000050
|
||||
#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_SPECIAL_USER_INFO_71_40_LSB 32
|
||||
#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_SPECIAL_USER_INFO_71_40_MSB 63
|
||||
#define OFDMA_TRIGGER_DETAILS_EHT_TRIGGER_SPECIAL_USER_INFO_71_40_MASK 0xffffffff00000000
|
||||
|
||||
#endif
|
||||
2288
hw/kiwi/v2/pcu_ppdu_setup_init.h
Normal file
2288
hw/kiwi/v2/pcu_ppdu_setup_init.h
Normal file
File diff suppressed because it is too large
Load diff
479
hw/kiwi/v2/pdg_response.h
Normal file
479
hw/kiwi/v2/pdg_response.h
Normal file
|
|
@ -0,0 +1,479 @@
|
|||
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
#ifndef _PDG_RESPONSE_H_
|
||||
#define _PDG_RESPONSE_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#include "pdg_response_rate_setting.h"
|
||||
#define NUM_OF_DWORDS_PDG_RESPONSE 12
|
||||
|
||||
#define NUM_OF_QWORDS_PDG_RESPONSE 6
|
||||
|
||||
struct pdg_response {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
struct pdg_response_rate_setting hw_response_rate_info;
|
||||
uint32_t hw_response_tx_duration : 16,
|
||||
rx_duration_field : 16;
|
||||
uint32_t punctured_response_transmission : 1,
|
||||
cca_subband_channel_bonding_mask : 16,
|
||||
scrambler_seed_override : 2,
|
||||
response_density_valid : 1,
|
||||
response_density : 5,
|
||||
more_data : 1,
|
||||
duration_indication : 1,
|
||||
relayed_frame : 1,
|
||||
address_indicator : 1,
|
||||
bandwidth : 3;
|
||||
uint32_t ack_id : 16,
|
||||
block_ack_bitmap : 16;
|
||||
uint32_t response_frame_type : 4,
|
||||
ack_id_ext : 10,
|
||||
ftm_en : 1,
|
||||
group_id : 6,
|
||||
sta_partial_aid : 11;
|
||||
uint32_t ndp_ba_start_seq_ctrl : 12,
|
||||
active_channel : 3,
|
||||
txop_duration_all_ones : 1,
|
||||
frame_length : 16;
|
||||
#else
|
||||
struct pdg_response_rate_setting hw_response_rate_info;
|
||||
uint32_t rx_duration_field : 16,
|
||||
hw_response_tx_duration : 16;
|
||||
uint32_t bandwidth : 3,
|
||||
address_indicator : 1,
|
||||
relayed_frame : 1,
|
||||
duration_indication : 1,
|
||||
more_data : 1,
|
||||
response_density : 5,
|
||||
response_density_valid : 1,
|
||||
scrambler_seed_override : 2,
|
||||
cca_subband_channel_bonding_mask : 16,
|
||||
punctured_response_transmission : 1;
|
||||
uint32_t block_ack_bitmap : 16,
|
||||
ack_id : 16;
|
||||
uint32_t sta_partial_aid : 11,
|
||||
group_id : 6,
|
||||
ftm_en : 1,
|
||||
ack_id_ext : 10,
|
||||
response_frame_type : 4;
|
||||
uint32_t frame_length : 16,
|
||||
txop_duration_all_ones : 1,
|
||||
active_channel : 3,
|
||||
ndp_ba_start_seq_ctrl : 12;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_0A_OFFSET 0x0000000000000000
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_0A_LSB 0
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_0A_MSB 0
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_0A_MASK 0x0000000000000001
|
||||
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x0000000000000000
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_ANTENNA_SECTOR_CTRL_LSB 1
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_ANTENNA_SECTOR_CTRL_MSB 24
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_ANTENNA_SECTOR_CTRL_MASK 0x0000000001fffffe
|
||||
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_PKT_TYPE_OFFSET 0x0000000000000000
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_PKT_TYPE_LSB 25
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_PKT_TYPE_MSB 28
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_PKT_TYPE_MASK 0x000000001e000000
|
||||
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SMOOTHING_OFFSET 0x0000000000000000
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SMOOTHING_LSB 29
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SMOOTHING_MSB 29
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SMOOTHING_MASK 0x0000000020000000
|
||||
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_OFFSET 0x0000000000000000
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_LSB 30
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_MSB 30
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_LDPC_MASK 0x0000000040000000
|
||||
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STBC_OFFSET 0x0000000000000000
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STBC_LSB 31
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STBC_MSB 31
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STBC_MASK 0x0000000080000000
|
||||
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_OFFSET 0x0000000000000000
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_LSB 32
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_MSB 39
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_MASK 0x000000ff00000000
|
||||
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_MIN_TX_PWR_OFFSET 0x0000000000000000
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_MIN_TX_PWR_LSB 40
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_MIN_TX_PWR_MSB 47
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_MIN_TX_PWR_MASK 0x0000ff0000000000
|
||||
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_NSS_OFFSET 0x0000000000000000
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_NSS_LSB 48
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_NSS_MSB 50
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_NSS_MASK 0x0007000000000000
|
||||
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_CHAIN_MASK_OFFSET 0x0000000000000000
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_CHAIN_MASK_LSB 51
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_CHAIN_MASK_MSB 58
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_CHAIN_MASK_MASK 0x07f8000000000000
|
||||
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_BW_OFFSET 0x0000000000000000
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_BW_LSB 59
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_BW_MSB 61
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_BW_MASK 0x3800000000000000
|
||||
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STF_LTF_3DB_BOOST_OFFSET 0x0000000000000000
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STF_LTF_3DB_BOOST_LSB 62
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STF_LTF_3DB_BOOST_MSB 62
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_STF_LTF_3DB_BOOST_MASK 0x4000000000000000
|
||||
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000000
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_FORCE_EXTRA_SYMBOL_LSB 63
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_FORCE_EXTRA_SYMBOL_MSB 63
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_FORCE_EXTRA_SYMBOL_MASK 0x8000000000000000
|
||||
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_RATE_MCS_OFFSET 0x0000000000000008
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_RATE_MCS_LSB 0
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_RATE_MCS_MSB 3
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_RATE_MCS_MASK 0x000000000000000f
|
||||
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NSS_OFFSET 0x0000000000000008
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NSS_LSB 4
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NSS_MSB 6
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NSS_MASK 0x0000000000000070
|
||||
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DPD_ENABLE_OFFSET 0x0000000000000008
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DPD_ENABLE_LSB 7
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DPD_ENABLE_MSB 7
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DPD_ENABLE_MASK 0x0000000000000080
|
||||
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_OFFSET 0x0000000000000008
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_LSB 8
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_MSB 15
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_MASK 0x000000000000ff00
|
||||
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MIN_TX_PWR_OFFSET 0x0000000000000008
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MIN_TX_PWR_LSB 16
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MIN_TX_PWR_MSB 23
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MIN_TX_PWR_MASK 0x0000000000ff0000
|
||||
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_CHAIN_MASK_OFFSET 0x0000000000000008
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_CHAIN_MASK_LSB 24
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_CHAIN_MASK_MSB 31
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_CHAIN_MASK_MASK 0x00000000ff000000
|
||||
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3A_OFFSET 0x0000000000000008
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3A_LSB 32
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3A_MSB 39
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3A_MASK 0x000000ff00000000
|
||||
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SGI_OFFSET 0x0000000000000008
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SGI_LSB 40
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SGI_MSB 41
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_SGI_MASK 0x0000030000000000
|
||||
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RATE_MCS_OFFSET 0x0000000000000008
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RATE_MCS_LSB 42
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RATE_MCS_MSB 45
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RATE_MCS_MASK 0x00003c0000000000
|
||||
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3B_OFFSET 0x0000000000000008
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3B_LSB 46
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3B_MSB 47
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_3B_MASK 0x0000c00000000000
|
||||
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_1_OFFSET 0x0000000000000008
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_1_LSB 48
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_1_MSB 55
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_TX_PWR_1_MASK 0x00ff000000000000
|
||||
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_1_OFFSET 0x0000000000000008
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_1_LSB 56
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_1_MSB 63
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_ALT_TX_PWR_1_MASK 0xff00000000000000
|
||||
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_AGGREGATION_OFFSET 0x0000000000000010
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_AGGREGATION_LSB 0
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_AGGREGATION_MSB 0
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_AGGREGATION_MASK 0x0000000000000001
|
||||
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_BSS_COLOR_ID_OFFSET 0x0000000000000010
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_BSS_COLOR_ID_LSB 1
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_BSS_COLOR_ID_MSB 6
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_BSS_COLOR_ID_MASK 0x000000000000007e
|
||||
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SPATIAL_REUSE_OFFSET 0x0000000000000010
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SPATIAL_REUSE_LSB 7
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SPATIAL_REUSE_MSB 10
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SPATIAL_REUSE_MASK 0x0000000000000780
|
||||
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CP_LTF_SIZE_OFFSET 0x0000000000000010
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CP_LTF_SIZE_LSB 11
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CP_LTF_SIZE_MSB 12
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CP_LTF_SIZE_MASK 0x0000000000001800
|
||||
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DCM_OFFSET 0x0000000000000010
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DCM_LSB 13
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DCM_MSB 13
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DCM_MASK 0x0000000000002000
|
||||
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DOPPLER_INDICATION_OFFSET 0x0000000000000010
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DOPPLER_INDICATION_LSB 14
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DOPPLER_INDICATION_MSB 14
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DOPPLER_INDICATION_MASK 0x0000000000004000
|
||||
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000010
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SU_EXTENDED_LSB 15
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SU_EXTENDED_MSB 15
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_SU_EXTENDED_MASK 0x0000000000008000
|
||||
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x0000000000000010
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_MIN_PACKET_EXTENSION_LSB 16
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_MIN_PACKET_EXTENSION_MSB 17
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x0000000000030000
|
||||
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_NSS_OFFSET 0x0000000000000010
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_NSS_LSB 18
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_NSS_MSB 20
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_NSS_MASK 0x00000000001c0000
|
||||
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CONTENT_OFFSET 0x0000000000000010
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CONTENT_LSB 21
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CONTENT_MSB 21
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CONTENT_MASK 0x0000000000200000
|
||||
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_LTF_SIZE_OFFSET 0x0000000000000010
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_LTF_SIZE_LSB 22
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_LTF_SIZE_MSB 23
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_LTF_SIZE_MASK 0x0000000000c00000
|
||||
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CHAIN_CSD_EN_OFFSET 0x0000000000000010
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CHAIN_CSD_EN_LSB 24
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CHAIN_CSD_EN_MSB 24
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_CHAIN_CSD_EN_MASK 0x0000000001000000
|
||||
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x0000000000000010
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CHAIN_CSD_EN_LSB 25
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CHAIN_CSD_EN_MSB 25
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x0000000002000000
|
||||
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DL_UL_FLAG_OFFSET 0x0000000000000010
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DL_UL_FLAG_LSB 26
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DL_UL_FLAG_MSB 26
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_DL_UL_FLAG_MASK 0x0000000004000000
|
||||
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_4A_OFFSET 0x0000000000000010
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_4A_LSB 27
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_4A_MSB 31
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_4A_MASK 0x00000000f8000000
|
||||
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x0000000000000010
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_START_INDEX_LSB 32
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_START_INDEX_MSB 35
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_START_INDEX_MASK 0x0000000f00000000
|
||||
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_SIZE_OFFSET 0x0000000000000010
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_SIZE_LSB 36
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_SIZE_MSB 39
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11AX_EXT_RU_SIZE_MASK 0x000000f000000000
|
||||
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_EHT_DUPLICATE_MODE_OFFSET 0x0000000000000010
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_EHT_DUPLICATE_MODE_LSB 40
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_EHT_DUPLICATE_MODE_MSB 41
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_EHT_DUPLICATE_MODE_MASK 0x0000030000000000
|
||||
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_DCM_OFFSET 0x0000000000000010
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_DCM_LSB 42
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_DCM_MSB 42
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_DCM_MASK 0x0000040000000000
|
||||
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_0_MCS_OFFSET 0x0000000000000010
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_0_MCS_LSB 43
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_0_MCS_MSB 45
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_HE_SIGB_0_MCS_MASK 0x0000380000000000
|
||||
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NUM_HE_SIGB_SYM_OFFSET 0x0000000000000010
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NUM_HE_SIGB_SYM_LSB 46
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NUM_HE_SIGB_SYM_MSB 50
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_NUM_HE_SIGB_SYM_MASK 0x0007c00000000000
|
||||
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x0000000000000010
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_SOURCE_LSB 51
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_SOURCE_MSB 51
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x0008000000000000
|
||||
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_5A_OFFSET 0x0000000000000010
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_5A_LSB 52
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_5A_MSB 57
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_RESERVED_5A_MASK 0x03f0000000000000
|
||||
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000010
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 58
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 63
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc00000000000000
|
||||
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000000000000018
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x00000000000003ff
|
||||
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000000000000018
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000000000000400
|
||||
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000018
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000000000000800
|
||||
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000018
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000000000001000
|
||||
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000000000000018
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x000000000000e000
|
||||
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_OFFSET 0x0000000000000018
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_LSB 16
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_MSB 27
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_REQUIRED_RESPONSE_TIME_MASK 0x000000000fff0000
|
||||
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x0000000000000018
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11BE_PARAMS_PLACEHOLDER_LSB 28
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11BE_PARAMS_PLACEHOLDER_MSB 31
|
||||
#define PDG_RESPONSE_HW_RESPONSE_RATE_INFO_DOT11BE_PARAMS_PLACEHOLDER_MASK 0x00000000f0000000
|
||||
|
||||
#define PDG_RESPONSE_HW_RESPONSE_TX_DURATION_OFFSET 0x0000000000000018
|
||||
#define PDG_RESPONSE_HW_RESPONSE_TX_DURATION_LSB 32
|
||||
#define PDG_RESPONSE_HW_RESPONSE_TX_DURATION_MSB 47
|
||||
#define PDG_RESPONSE_HW_RESPONSE_TX_DURATION_MASK 0x0000ffff00000000
|
||||
|
||||
#define PDG_RESPONSE_RX_DURATION_FIELD_OFFSET 0x0000000000000018
|
||||
#define PDG_RESPONSE_RX_DURATION_FIELD_LSB 48
|
||||
#define PDG_RESPONSE_RX_DURATION_FIELD_MSB 63
|
||||
#define PDG_RESPONSE_RX_DURATION_FIELD_MASK 0xffff000000000000
|
||||
|
||||
#define PDG_RESPONSE_PUNCTURED_RESPONSE_TRANSMISSION_OFFSET 0x0000000000000020
|
||||
#define PDG_RESPONSE_PUNCTURED_RESPONSE_TRANSMISSION_LSB 0
|
||||
#define PDG_RESPONSE_PUNCTURED_RESPONSE_TRANSMISSION_MSB 0
|
||||
#define PDG_RESPONSE_PUNCTURED_RESPONSE_TRANSMISSION_MASK 0x0000000000000001
|
||||
|
||||
#define PDG_RESPONSE_CCA_SUBBAND_CHANNEL_BONDING_MASK_OFFSET 0x0000000000000020
|
||||
#define PDG_RESPONSE_CCA_SUBBAND_CHANNEL_BONDING_MASK_LSB 1
|
||||
#define PDG_RESPONSE_CCA_SUBBAND_CHANNEL_BONDING_MASK_MSB 16
|
||||
#define PDG_RESPONSE_CCA_SUBBAND_CHANNEL_BONDING_MASK_MASK 0x000000000001fffe
|
||||
|
||||
#define PDG_RESPONSE_SCRAMBLER_SEED_OVERRIDE_OFFSET 0x0000000000000020
|
||||
#define PDG_RESPONSE_SCRAMBLER_SEED_OVERRIDE_LSB 17
|
||||
#define PDG_RESPONSE_SCRAMBLER_SEED_OVERRIDE_MSB 18
|
||||
#define PDG_RESPONSE_SCRAMBLER_SEED_OVERRIDE_MASK 0x0000000000060000
|
||||
|
||||
#define PDG_RESPONSE_RESPONSE_DENSITY_VALID_OFFSET 0x0000000000000020
|
||||
#define PDG_RESPONSE_RESPONSE_DENSITY_VALID_LSB 19
|
||||
#define PDG_RESPONSE_RESPONSE_DENSITY_VALID_MSB 19
|
||||
#define PDG_RESPONSE_RESPONSE_DENSITY_VALID_MASK 0x0000000000080000
|
||||
|
||||
#define PDG_RESPONSE_RESPONSE_DENSITY_OFFSET 0x0000000000000020
|
||||
#define PDG_RESPONSE_RESPONSE_DENSITY_LSB 20
|
||||
#define PDG_RESPONSE_RESPONSE_DENSITY_MSB 24
|
||||
#define PDG_RESPONSE_RESPONSE_DENSITY_MASK 0x0000000001f00000
|
||||
|
||||
#define PDG_RESPONSE_MORE_DATA_OFFSET 0x0000000000000020
|
||||
#define PDG_RESPONSE_MORE_DATA_LSB 25
|
||||
#define PDG_RESPONSE_MORE_DATA_MSB 25
|
||||
#define PDG_RESPONSE_MORE_DATA_MASK 0x0000000002000000
|
||||
|
||||
#define PDG_RESPONSE_DURATION_INDICATION_OFFSET 0x0000000000000020
|
||||
#define PDG_RESPONSE_DURATION_INDICATION_LSB 26
|
||||
#define PDG_RESPONSE_DURATION_INDICATION_MSB 26
|
||||
#define PDG_RESPONSE_DURATION_INDICATION_MASK 0x0000000004000000
|
||||
|
||||
#define PDG_RESPONSE_RELAYED_FRAME_OFFSET 0x0000000000000020
|
||||
#define PDG_RESPONSE_RELAYED_FRAME_LSB 27
|
||||
#define PDG_RESPONSE_RELAYED_FRAME_MSB 27
|
||||
#define PDG_RESPONSE_RELAYED_FRAME_MASK 0x0000000008000000
|
||||
|
||||
#define PDG_RESPONSE_ADDRESS_INDICATOR_OFFSET 0x0000000000000020
|
||||
#define PDG_RESPONSE_ADDRESS_INDICATOR_LSB 28
|
||||
#define PDG_RESPONSE_ADDRESS_INDICATOR_MSB 28
|
||||
#define PDG_RESPONSE_ADDRESS_INDICATOR_MASK 0x0000000010000000
|
||||
|
||||
#define PDG_RESPONSE_BANDWIDTH_OFFSET 0x0000000000000020
|
||||
#define PDG_RESPONSE_BANDWIDTH_LSB 29
|
||||
#define PDG_RESPONSE_BANDWIDTH_MSB 31
|
||||
#define PDG_RESPONSE_BANDWIDTH_MASK 0x00000000e0000000
|
||||
|
||||
#define PDG_RESPONSE_ACK_ID_OFFSET 0x0000000000000020
|
||||
#define PDG_RESPONSE_ACK_ID_LSB 32
|
||||
#define PDG_RESPONSE_ACK_ID_MSB 47
|
||||
#define PDG_RESPONSE_ACK_ID_MASK 0x0000ffff00000000
|
||||
|
||||
#define PDG_RESPONSE_BLOCK_ACK_BITMAP_OFFSET 0x0000000000000020
|
||||
#define PDG_RESPONSE_BLOCK_ACK_BITMAP_LSB 48
|
||||
#define PDG_RESPONSE_BLOCK_ACK_BITMAP_MSB 63
|
||||
#define PDG_RESPONSE_BLOCK_ACK_BITMAP_MASK 0xffff000000000000
|
||||
|
||||
#define PDG_RESPONSE_RESPONSE_FRAME_TYPE_OFFSET 0x0000000000000028
|
||||
#define PDG_RESPONSE_RESPONSE_FRAME_TYPE_LSB 0
|
||||
#define PDG_RESPONSE_RESPONSE_FRAME_TYPE_MSB 3
|
||||
#define PDG_RESPONSE_RESPONSE_FRAME_TYPE_MASK 0x000000000000000f
|
||||
|
||||
#define PDG_RESPONSE_ACK_ID_EXT_OFFSET 0x0000000000000028
|
||||
#define PDG_RESPONSE_ACK_ID_EXT_LSB 4
|
||||
#define PDG_RESPONSE_ACK_ID_EXT_MSB 13
|
||||
#define PDG_RESPONSE_ACK_ID_EXT_MASK 0x0000000000003ff0
|
||||
|
||||
#define PDG_RESPONSE_FTM_EN_OFFSET 0x0000000000000028
|
||||
#define PDG_RESPONSE_FTM_EN_LSB 14
|
||||
#define PDG_RESPONSE_FTM_EN_MSB 14
|
||||
#define PDG_RESPONSE_FTM_EN_MASK 0x0000000000004000
|
||||
|
||||
#define PDG_RESPONSE_GROUP_ID_OFFSET 0x0000000000000028
|
||||
#define PDG_RESPONSE_GROUP_ID_LSB 15
|
||||
#define PDG_RESPONSE_GROUP_ID_MSB 20
|
||||
#define PDG_RESPONSE_GROUP_ID_MASK 0x00000000001f8000
|
||||
|
||||
#define PDG_RESPONSE_STA_PARTIAL_AID_OFFSET 0x0000000000000028
|
||||
#define PDG_RESPONSE_STA_PARTIAL_AID_LSB 21
|
||||
#define PDG_RESPONSE_STA_PARTIAL_AID_MSB 31
|
||||
#define PDG_RESPONSE_STA_PARTIAL_AID_MASK 0x00000000ffe00000
|
||||
|
||||
#define PDG_RESPONSE_NDP_BA_START_SEQ_CTRL_OFFSET 0x0000000000000028
|
||||
#define PDG_RESPONSE_NDP_BA_START_SEQ_CTRL_LSB 32
|
||||
#define PDG_RESPONSE_NDP_BA_START_SEQ_CTRL_MSB 43
|
||||
#define PDG_RESPONSE_NDP_BA_START_SEQ_CTRL_MASK 0x00000fff00000000
|
||||
|
||||
#define PDG_RESPONSE_ACTIVE_CHANNEL_OFFSET 0x0000000000000028
|
||||
#define PDG_RESPONSE_ACTIVE_CHANNEL_LSB 44
|
||||
#define PDG_RESPONSE_ACTIVE_CHANNEL_MSB 46
|
||||
#define PDG_RESPONSE_ACTIVE_CHANNEL_MASK 0x0000700000000000
|
||||
|
||||
#define PDG_RESPONSE_TXOP_DURATION_ALL_ONES_OFFSET 0x0000000000000028
|
||||
#define PDG_RESPONSE_TXOP_DURATION_ALL_ONES_LSB 47
|
||||
#define PDG_RESPONSE_TXOP_DURATION_ALL_ONES_MSB 47
|
||||
#define PDG_RESPONSE_TXOP_DURATION_ALL_ONES_MASK 0x0000800000000000
|
||||
|
||||
#define PDG_RESPONSE_FRAME_LENGTH_OFFSET 0x0000000000000028
|
||||
#define PDG_RESPONSE_FRAME_LENGTH_LSB 48
|
||||
#define PDG_RESPONSE_FRAME_LENGTH_MSB 63
|
||||
#define PDG_RESPONSE_FRAME_LENGTH_MASK 0xffff000000000000
|
||||
|
||||
#endif
|
||||
418
hw/kiwi/v2/pdg_response_rate_setting.h
Normal file
418
hw/kiwi/v2/pdg_response_rate_setting.h
Normal file
|
|
@ -0,0 +1,418 @@
|
|||
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
#ifndef _PDG_RESPONSE_RATE_SETTING_H_
|
||||
#define _PDG_RESPONSE_RATE_SETTING_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#include "mlo_sta_id_details.h"
|
||||
#define NUM_OF_DWORDS_PDG_RESPONSE_RATE_SETTING 7
|
||||
|
||||
struct pdg_response_rate_setting {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t reserved_0a : 1,
|
||||
tx_antenna_sector_ctrl : 24,
|
||||
pkt_type : 4,
|
||||
smoothing : 1,
|
||||
ldpc : 1,
|
||||
stbc : 1;
|
||||
uint32_t alt_tx_pwr : 8,
|
||||
alt_min_tx_pwr : 8,
|
||||
alt_nss : 3,
|
||||
alt_tx_chain_mask : 8,
|
||||
alt_bw : 3,
|
||||
stf_ltf_3db_boost : 1,
|
||||
force_extra_symbol : 1;
|
||||
uint32_t alt_rate_mcs : 4,
|
||||
nss : 3,
|
||||
dpd_enable : 1,
|
||||
tx_pwr : 8,
|
||||
min_tx_pwr : 8,
|
||||
tx_chain_mask : 8;
|
||||
uint32_t reserved_3a : 8,
|
||||
sgi : 2,
|
||||
rate_mcs : 4,
|
||||
reserved_3b : 2,
|
||||
tx_pwr_1 : 8,
|
||||
alt_tx_pwr_1 : 8;
|
||||
uint32_t aggregation : 1,
|
||||
dot11ax_bss_color_id : 6,
|
||||
dot11ax_spatial_reuse : 4,
|
||||
dot11ax_cp_ltf_size : 2,
|
||||
dot11ax_dcm : 1,
|
||||
dot11ax_doppler_indication : 1,
|
||||
dot11ax_su_extended : 1,
|
||||
dot11ax_min_packet_extension : 2,
|
||||
dot11ax_pe_nss : 3,
|
||||
dot11ax_pe_content : 1,
|
||||
dot11ax_pe_ltf_size : 2,
|
||||
dot11ax_chain_csd_en : 1,
|
||||
dot11ax_pe_chain_csd_en : 1,
|
||||
dot11ax_dl_ul_flag : 1,
|
||||
reserved_4a : 5;
|
||||
uint32_t dot11ax_ext_ru_start_index : 4,
|
||||
dot11ax_ext_ru_size : 4,
|
||||
eht_duplicate_mode : 2,
|
||||
he_sigb_dcm : 1,
|
||||
he_sigb_0_mcs : 3,
|
||||
num_he_sigb_sym : 5,
|
||||
required_response_time_source : 1,
|
||||
reserved_5a : 6,
|
||||
u_sig_puncture_pattern_encoding : 6;
|
||||
struct mlo_sta_id_details mlo_sta_id_details_rx;
|
||||
uint16_t required_response_time : 12,
|
||||
dot11be_params_placeholder : 4;
|
||||
#else
|
||||
uint32_t stbc : 1,
|
||||
ldpc : 1,
|
||||
smoothing : 1,
|
||||
pkt_type : 4,
|
||||
tx_antenna_sector_ctrl : 24,
|
||||
reserved_0a : 1;
|
||||
uint32_t force_extra_symbol : 1,
|
||||
stf_ltf_3db_boost : 1,
|
||||
alt_bw : 3,
|
||||
alt_tx_chain_mask : 8,
|
||||
alt_nss : 3,
|
||||
alt_min_tx_pwr : 8,
|
||||
alt_tx_pwr : 8;
|
||||
uint32_t tx_chain_mask : 8,
|
||||
min_tx_pwr : 8,
|
||||
tx_pwr : 8,
|
||||
dpd_enable : 1,
|
||||
nss : 3,
|
||||
alt_rate_mcs : 4;
|
||||
uint32_t alt_tx_pwr_1 : 8,
|
||||
tx_pwr_1 : 8,
|
||||
reserved_3b : 2,
|
||||
rate_mcs : 4,
|
||||
sgi : 2,
|
||||
reserved_3a : 8;
|
||||
uint32_t reserved_4a : 5,
|
||||
dot11ax_dl_ul_flag : 1,
|
||||
dot11ax_pe_chain_csd_en : 1,
|
||||
dot11ax_chain_csd_en : 1,
|
||||
dot11ax_pe_ltf_size : 2,
|
||||
dot11ax_pe_content : 1,
|
||||
dot11ax_pe_nss : 3,
|
||||
dot11ax_min_packet_extension : 2,
|
||||
dot11ax_su_extended : 1,
|
||||
dot11ax_doppler_indication : 1,
|
||||
dot11ax_dcm : 1,
|
||||
dot11ax_cp_ltf_size : 2,
|
||||
dot11ax_spatial_reuse : 4,
|
||||
dot11ax_bss_color_id : 6,
|
||||
aggregation : 1;
|
||||
uint32_t u_sig_puncture_pattern_encoding : 6,
|
||||
reserved_5a : 6,
|
||||
required_response_time_source : 1,
|
||||
num_he_sigb_sym : 5,
|
||||
he_sigb_0_mcs : 3,
|
||||
he_sigb_dcm : 1,
|
||||
eht_duplicate_mode : 2,
|
||||
dot11ax_ext_ru_size : 4,
|
||||
dot11ax_ext_ru_start_index : 4;
|
||||
uint32_t dot11be_params_placeholder : 4,
|
||||
required_response_time : 12;
|
||||
struct mlo_sta_id_details mlo_sta_id_details_rx;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_RESERVED_0A_OFFSET 0x00000000
|
||||
#define PDG_RESPONSE_RATE_SETTING_RESERVED_0A_LSB 0
|
||||
#define PDG_RESPONSE_RATE_SETTING_RESERVED_0A_MSB 0
|
||||
#define PDG_RESPONSE_RATE_SETTING_RESERVED_0A_MASK 0x00000001
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_TX_ANTENNA_SECTOR_CTRL_OFFSET 0x00000000
|
||||
#define PDG_RESPONSE_RATE_SETTING_TX_ANTENNA_SECTOR_CTRL_LSB 1
|
||||
#define PDG_RESPONSE_RATE_SETTING_TX_ANTENNA_SECTOR_CTRL_MSB 24
|
||||
#define PDG_RESPONSE_RATE_SETTING_TX_ANTENNA_SECTOR_CTRL_MASK 0x01fffffe
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_PKT_TYPE_OFFSET 0x00000000
|
||||
#define PDG_RESPONSE_RATE_SETTING_PKT_TYPE_LSB 25
|
||||
#define PDG_RESPONSE_RATE_SETTING_PKT_TYPE_MSB 28
|
||||
#define PDG_RESPONSE_RATE_SETTING_PKT_TYPE_MASK 0x1e000000
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_SMOOTHING_OFFSET 0x00000000
|
||||
#define PDG_RESPONSE_RATE_SETTING_SMOOTHING_LSB 29
|
||||
#define PDG_RESPONSE_RATE_SETTING_SMOOTHING_MSB 29
|
||||
#define PDG_RESPONSE_RATE_SETTING_SMOOTHING_MASK 0x20000000
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_LDPC_OFFSET 0x00000000
|
||||
#define PDG_RESPONSE_RATE_SETTING_LDPC_LSB 30
|
||||
#define PDG_RESPONSE_RATE_SETTING_LDPC_MSB 30
|
||||
#define PDG_RESPONSE_RATE_SETTING_LDPC_MASK 0x40000000
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_STBC_OFFSET 0x00000000
|
||||
#define PDG_RESPONSE_RATE_SETTING_STBC_LSB 31
|
||||
#define PDG_RESPONSE_RATE_SETTING_STBC_MSB 31
|
||||
#define PDG_RESPONSE_RATE_SETTING_STBC_MASK 0x80000000
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_OFFSET 0x00000004
|
||||
#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_LSB 0
|
||||
#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_MSB 7
|
||||
#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_MASK 0x000000ff
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_ALT_MIN_TX_PWR_OFFSET 0x00000004
|
||||
#define PDG_RESPONSE_RATE_SETTING_ALT_MIN_TX_PWR_LSB 8
|
||||
#define PDG_RESPONSE_RATE_SETTING_ALT_MIN_TX_PWR_MSB 15
|
||||
#define PDG_RESPONSE_RATE_SETTING_ALT_MIN_TX_PWR_MASK 0x0000ff00
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_ALT_NSS_OFFSET 0x00000004
|
||||
#define PDG_RESPONSE_RATE_SETTING_ALT_NSS_LSB 16
|
||||
#define PDG_RESPONSE_RATE_SETTING_ALT_NSS_MSB 18
|
||||
#define PDG_RESPONSE_RATE_SETTING_ALT_NSS_MASK 0x00070000
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_ALT_TX_CHAIN_MASK_OFFSET 0x00000004
|
||||
#define PDG_RESPONSE_RATE_SETTING_ALT_TX_CHAIN_MASK_LSB 19
|
||||
#define PDG_RESPONSE_RATE_SETTING_ALT_TX_CHAIN_MASK_MSB 26
|
||||
#define PDG_RESPONSE_RATE_SETTING_ALT_TX_CHAIN_MASK_MASK 0x07f80000
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_ALT_BW_OFFSET 0x00000004
|
||||
#define PDG_RESPONSE_RATE_SETTING_ALT_BW_LSB 27
|
||||
#define PDG_RESPONSE_RATE_SETTING_ALT_BW_MSB 29
|
||||
#define PDG_RESPONSE_RATE_SETTING_ALT_BW_MASK 0x38000000
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_STF_LTF_3DB_BOOST_OFFSET 0x00000004
|
||||
#define PDG_RESPONSE_RATE_SETTING_STF_LTF_3DB_BOOST_LSB 30
|
||||
#define PDG_RESPONSE_RATE_SETTING_STF_LTF_3DB_BOOST_MSB 30
|
||||
#define PDG_RESPONSE_RATE_SETTING_STF_LTF_3DB_BOOST_MASK 0x40000000
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_FORCE_EXTRA_SYMBOL_OFFSET 0x00000004
|
||||
#define PDG_RESPONSE_RATE_SETTING_FORCE_EXTRA_SYMBOL_LSB 31
|
||||
#define PDG_RESPONSE_RATE_SETTING_FORCE_EXTRA_SYMBOL_MSB 31
|
||||
#define PDG_RESPONSE_RATE_SETTING_FORCE_EXTRA_SYMBOL_MASK 0x80000000
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_ALT_RATE_MCS_OFFSET 0x00000008
|
||||
#define PDG_RESPONSE_RATE_SETTING_ALT_RATE_MCS_LSB 0
|
||||
#define PDG_RESPONSE_RATE_SETTING_ALT_RATE_MCS_MSB 3
|
||||
#define PDG_RESPONSE_RATE_SETTING_ALT_RATE_MCS_MASK 0x0000000f
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_NSS_OFFSET 0x00000008
|
||||
#define PDG_RESPONSE_RATE_SETTING_NSS_LSB 4
|
||||
#define PDG_RESPONSE_RATE_SETTING_NSS_MSB 6
|
||||
#define PDG_RESPONSE_RATE_SETTING_NSS_MASK 0x00000070
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_DPD_ENABLE_OFFSET 0x00000008
|
||||
#define PDG_RESPONSE_RATE_SETTING_DPD_ENABLE_LSB 7
|
||||
#define PDG_RESPONSE_RATE_SETTING_DPD_ENABLE_MSB 7
|
||||
#define PDG_RESPONSE_RATE_SETTING_DPD_ENABLE_MASK 0x00000080
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_TX_PWR_OFFSET 0x00000008
|
||||
#define PDG_RESPONSE_RATE_SETTING_TX_PWR_LSB 8
|
||||
#define PDG_RESPONSE_RATE_SETTING_TX_PWR_MSB 15
|
||||
#define PDG_RESPONSE_RATE_SETTING_TX_PWR_MASK 0x0000ff00
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_MIN_TX_PWR_OFFSET 0x00000008
|
||||
#define PDG_RESPONSE_RATE_SETTING_MIN_TX_PWR_LSB 16
|
||||
#define PDG_RESPONSE_RATE_SETTING_MIN_TX_PWR_MSB 23
|
||||
#define PDG_RESPONSE_RATE_SETTING_MIN_TX_PWR_MASK 0x00ff0000
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_TX_CHAIN_MASK_OFFSET 0x00000008
|
||||
#define PDG_RESPONSE_RATE_SETTING_TX_CHAIN_MASK_LSB 24
|
||||
#define PDG_RESPONSE_RATE_SETTING_TX_CHAIN_MASK_MSB 31
|
||||
#define PDG_RESPONSE_RATE_SETTING_TX_CHAIN_MASK_MASK 0xff000000
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_RESERVED_3A_OFFSET 0x0000000c
|
||||
#define PDG_RESPONSE_RATE_SETTING_RESERVED_3A_LSB 0
|
||||
#define PDG_RESPONSE_RATE_SETTING_RESERVED_3A_MSB 7
|
||||
#define PDG_RESPONSE_RATE_SETTING_RESERVED_3A_MASK 0x000000ff
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_SGI_OFFSET 0x0000000c
|
||||
#define PDG_RESPONSE_RATE_SETTING_SGI_LSB 8
|
||||
#define PDG_RESPONSE_RATE_SETTING_SGI_MSB 9
|
||||
#define PDG_RESPONSE_RATE_SETTING_SGI_MASK 0x00000300
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_RATE_MCS_OFFSET 0x0000000c
|
||||
#define PDG_RESPONSE_RATE_SETTING_RATE_MCS_LSB 10
|
||||
#define PDG_RESPONSE_RATE_SETTING_RATE_MCS_MSB 13
|
||||
#define PDG_RESPONSE_RATE_SETTING_RATE_MCS_MASK 0x00003c00
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_RESERVED_3B_OFFSET 0x0000000c
|
||||
#define PDG_RESPONSE_RATE_SETTING_RESERVED_3B_LSB 14
|
||||
#define PDG_RESPONSE_RATE_SETTING_RESERVED_3B_MSB 15
|
||||
#define PDG_RESPONSE_RATE_SETTING_RESERVED_3B_MASK 0x0000c000
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_TX_PWR_1_OFFSET 0x0000000c
|
||||
#define PDG_RESPONSE_RATE_SETTING_TX_PWR_1_LSB 16
|
||||
#define PDG_RESPONSE_RATE_SETTING_TX_PWR_1_MSB 23
|
||||
#define PDG_RESPONSE_RATE_SETTING_TX_PWR_1_MASK 0x00ff0000
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_1_OFFSET 0x0000000c
|
||||
#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_1_LSB 24
|
||||
#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_1_MSB 31
|
||||
#define PDG_RESPONSE_RATE_SETTING_ALT_TX_PWR_1_MASK 0xff000000
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_AGGREGATION_OFFSET 0x00000010
|
||||
#define PDG_RESPONSE_RATE_SETTING_AGGREGATION_LSB 0
|
||||
#define PDG_RESPONSE_RATE_SETTING_AGGREGATION_MSB 0
|
||||
#define PDG_RESPONSE_RATE_SETTING_AGGREGATION_MASK 0x00000001
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_BSS_COLOR_ID_OFFSET 0x00000010
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_BSS_COLOR_ID_LSB 1
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_BSS_COLOR_ID_MSB 6
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_BSS_COLOR_ID_MASK 0x0000007e
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SPATIAL_REUSE_OFFSET 0x00000010
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SPATIAL_REUSE_LSB 7
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SPATIAL_REUSE_MSB 10
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SPATIAL_REUSE_MASK 0x00000780
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CP_LTF_SIZE_OFFSET 0x00000010
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CP_LTF_SIZE_LSB 11
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CP_LTF_SIZE_MSB 12
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CP_LTF_SIZE_MASK 0x00001800
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DCM_OFFSET 0x00000010
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DCM_LSB 13
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DCM_MSB 13
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DCM_MASK 0x00002000
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DOPPLER_INDICATION_OFFSET 0x00000010
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DOPPLER_INDICATION_LSB 14
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DOPPLER_INDICATION_MSB 14
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DOPPLER_INDICATION_MASK 0x00004000
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SU_EXTENDED_OFFSET 0x00000010
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SU_EXTENDED_LSB 15
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SU_EXTENDED_MSB 15
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_SU_EXTENDED_MASK 0x00008000
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_MIN_PACKET_EXTENSION_OFFSET 0x00000010
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_MIN_PACKET_EXTENSION_LSB 16
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_MIN_PACKET_EXTENSION_MSB 17
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_MIN_PACKET_EXTENSION_MASK 0x00030000
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_NSS_OFFSET 0x00000010
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_NSS_LSB 18
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_NSS_MSB 20
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_NSS_MASK 0x001c0000
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CONTENT_OFFSET 0x00000010
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CONTENT_LSB 21
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CONTENT_MSB 21
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CONTENT_MASK 0x00200000
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_LTF_SIZE_OFFSET 0x00000010
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_LTF_SIZE_LSB 22
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_LTF_SIZE_MSB 23
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_LTF_SIZE_MASK 0x00c00000
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CHAIN_CSD_EN_OFFSET 0x00000010
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CHAIN_CSD_EN_LSB 24
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CHAIN_CSD_EN_MSB 24
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_CHAIN_CSD_EN_MASK 0x01000000
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CHAIN_CSD_EN_OFFSET 0x00000010
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CHAIN_CSD_EN_LSB 25
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CHAIN_CSD_EN_MSB 25
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_PE_CHAIN_CSD_EN_MASK 0x02000000
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DL_UL_FLAG_OFFSET 0x00000010
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DL_UL_FLAG_LSB 26
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DL_UL_FLAG_MSB 26
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_DL_UL_FLAG_MASK 0x04000000
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_RESERVED_4A_OFFSET 0x00000010
|
||||
#define PDG_RESPONSE_RATE_SETTING_RESERVED_4A_LSB 27
|
||||
#define PDG_RESPONSE_RATE_SETTING_RESERVED_4A_MSB 31
|
||||
#define PDG_RESPONSE_RATE_SETTING_RESERVED_4A_MASK 0xf8000000
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_START_INDEX_OFFSET 0x00000014
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_START_INDEX_LSB 0
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_START_INDEX_MSB 3
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_START_INDEX_MASK 0x0000000f
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_SIZE_OFFSET 0x00000014
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_SIZE_LSB 4
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_SIZE_MSB 7
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11AX_EXT_RU_SIZE_MASK 0x000000f0
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_EHT_DUPLICATE_MODE_OFFSET 0x00000014
|
||||
#define PDG_RESPONSE_RATE_SETTING_EHT_DUPLICATE_MODE_LSB 8
|
||||
#define PDG_RESPONSE_RATE_SETTING_EHT_DUPLICATE_MODE_MSB 9
|
||||
#define PDG_RESPONSE_RATE_SETTING_EHT_DUPLICATE_MODE_MASK 0x00000300
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_DCM_OFFSET 0x00000014
|
||||
#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_DCM_LSB 10
|
||||
#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_DCM_MSB 10
|
||||
#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_DCM_MASK 0x00000400
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_0_MCS_OFFSET 0x00000014
|
||||
#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_0_MCS_LSB 11
|
||||
#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_0_MCS_MSB 13
|
||||
#define PDG_RESPONSE_RATE_SETTING_HE_SIGB_0_MCS_MASK 0x00003800
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_NUM_HE_SIGB_SYM_OFFSET 0x00000014
|
||||
#define PDG_RESPONSE_RATE_SETTING_NUM_HE_SIGB_SYM_LSB 14
|
||||
#define PDG_RESPONSE_RATE_SETTING_NUM_HE_SIGB_SYM_MSB 18
|
||||
#define PDG_RESPONSE_RATE_SETTING_NUM_HE_SIGB_SYM_MASK 0x0007c000
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_SOURCE_OFFSET 0x00000014
|
||||
#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_SOURCE_LSB 19
|
||||
#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_SOURCE_MSB 19
|
||||
#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_SOURCE_MASK 0x00080000
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_RESERVED_5A_OFFSET 0x00000014
|
||||
#define PDG_RESPONSE_RATE_SETTING_RESERVED_5A_LSB 20
|
||||
#define PDG_RESPONSE_RATE_SETTING_RESERVED_5A_MSB 25
|
||||
#define PDG_RESPONSE_RATE_SETTING_RESERVED_5A_MASK 0x03f00000
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x00000014
|
||||
#define PDG_RESPONSE_RATE_SETTING_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26
|
||||
#define PDG_RESPONSE_RATE_SETTING_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31
|
||||
#define PDG_RESPONSE_RATE_SETTING_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc000000
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x00000018
|
||||
#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0
|
||||
#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9
|
||||
#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x000003ff
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x00000018
|
||||
#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10
|
||||
#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10
|
||||
#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x00000400
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x00000018
|
||||
#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11
|
||||
#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11
|
||||
#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x00000800
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x00000018
|
||||
#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12
|
||||
#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12
|
||||
#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x00001000
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x00000018
|
||||
#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13
|
||||
#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15
|
||||
#define PDG_RESPONSE_RATE_SETTING_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x0000e000
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_OFFSET 0x00000018
|
||||
#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_LSB 16
|
||||
#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_MSB 27
|
||||
#define PDG_RESPONSE_RATE_SETTING_REQUIRED_RESPONSE_TIME_MASK 0x0fff0000
|
||||
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11BE_PARAMS_PLACEHOLDER_OFFSET 0x00000018
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11BE_PARAMS_PLACEHOLDER_LSB 28
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11BE_PARAMS_PLACEHOLDER_MSB 31
|
||||
#define PDG_RESPONSE_RATE_SETTING_DOT11BE_PARAMS_PLACEHOLDER_MASK 0xf0000000
|
||||
|
||||
#endif
|
||||
105
hw/kiwi/v2/pdg_tx_req.h
Normal file
105
hw/kiwi/v2/pdg_tx_req.h
Normal file
|
|
@ -0,0 +1,105 @@
|
|||
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
#ifndef _PDG_TX_REQ_H_
|
||||
#define _PDG_TX_REQ_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#define NUM_OF_DWORDS_PDG_TX_REQ 2
|
||||
|
||||
#define NUM_OF_QWORDS_PDG_TX_REQ 1
|
||||
|
||||
struct pdg_tx_req {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t tx_reason : 2,
|
||||
use_puncture_pattern : 2,
|
||||
req_bw : 3,
|
||||
puncture_pattern_number : 6,
|
||||
reserved_0b : 1,
|
||||
req_paprd : 1,
|
||||
duration_field_boundary_valid : 1,
|
||||
duration_field_boundary : 16;
|
||||
uint32_t puncture_subband_mask : 16,
|
||||
reserved_0c : 16;
|
||||
#else
|
||||
uint32_t duration_field_boundary : 16,
|
||||
duration_field_boundary_valid : 1,
|
||||
req_paprd : 1,
|
||||
reserved_0b : 1,
|
||||
puncture_pattern_number : 6,
|
||||
req_bw : 3,
|
||||
use_puncture_pattern : 2,
|
||||
tx_reason : 2;
|
||||
uint32_t reserved_0c : 16,
|
||||
puncture_subband_mask : 16;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define PDG_TX_REQ_TX_REASON_OFFSET 0x0000000000000000
|
||||
#define PDG_TX_REQ_TX_REASON_LSB 0
|
||||
#define PDG_TX_REQ_TX_REASON_MSB 1
|
||||
#define PDG_TX_REQ_TX_REASON_MASK 0x0000000000000003
|
||||
|
||||
#define PDG_TX_REQ_USE_PUNCTURE_PATTERN_OFFSET 0x0000000000000000
|
||||
#define PDG_TX_REQ_USE_PUNCTURE_PATTERN_LSB 2
|
||||
#define PDG_TX_REQ_USE_PUNCTURE_PATTERN_MSB 3
|
||||
#define PDG_TX_REQ_USE_PUNCTURE_PATTERN_MASK 0x000000000000000c
|
||||
|
||||
#define PDG_TX_REQ_REQ_BW_OFFSET 0x0000000000000000
|
||||
#define PDG_TX_REQ_REQ_BW_LSB 4
|
||||
#define PDG_TX_REQ_REQ_BW_MSB 6
|
||||
#define PDG_TX_REQ_REQ_BW_MASK 0x0000000000000070
|
||||
|
||||
#define PDG_TX_REQ_PUNCTURE_PATTERN_NUMBER_OFFSET 0x0000000000000000
|
||||
#define PDG_TX_REQ_PUNCTURE_PATTERN_NUMBER_LSB 7
|
||||
#define PDG_TX_REQ_PUNCTURE_PATTERN_NUMBER_MSB 12
|
||||
#define PDG_TX_REQ_PUNCTURE_PATTERN_NUMBER_MASK 0x0000000000001f80
|
||||
|
||||
#define PDG_TX_REQ_RESERVED_0B_OFFSET 0x0000000000000000
|
||||
#define PDG_TX_REQ_RESERVED_0B_LSB 13
|
||||
#define PDG_TX_REQ_RESERVED_0B_MSB 13
|
||||
#define PDG_TX_REQ_RESERVED_0B_MASK 0x0000000000002000
|
||||
|
||||
#define PDG_TX_REQ_REQ_PAPRD_OFFSET 0x0000000000000000
|
||||
#define PDG_TX_REQ_REQ_PAPRD_LSB 14
|
||||
#define PDG_TX_REQ_REQ_PAPRD_MSB 14
|
||||
#define PDG_TX_REQ_REQ_PAPRD_MASK 0x0000000000004000
|
||||
|
||||
#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_VALID_OFFSET 0x0000000000000000
|
||||
#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_VALID_LSB 15
|
||||
#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_VALID_MSB 15
|
||||
#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_VALID_MASK 0x0000000000008000
|
||||
|
||||
#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_OFFSET 0x0000000000000000
|
||||
#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_LSB 16
|
||||
#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_MSB 31
|
||||
#define PDG_TX_REQ_DURATION_FIELD_BOUNDARY_MASK 0x00000000ffff0000
|
||||
|
||||
#define PDG_TX_REQ_PUNCTURE_SUBBAND_MASK_OFFSET 0x0000000000000000
|
||||
#define PDG_TX_REQ_PUNCTURE_SUBBAND_MASK_LSB 32
|
||||
#define PDG_TX_REQ_PUNCTURE_SUBBAND_MASK_MSB 47
|
||||
#define PDG_TX_REQ_PUNCTURE_SUBBAND_MASK_MASK 0x0000ffff00000000
|
||||
|
||||
#define PDG_TX_REQ_RESERVED_0C_OFFSET 0x0000000000000000
|
||||
#define PDG_TX_REQ_RESERVED_0C_LSB 48
|
||||
#define PDG_TX_REQ_RESERVED_0C_MSB 63
|
||||
#define PDG_TX_REQ_RESERVED_0C_MASK 0xffff000000000000
|
||||
|
||||
#endif
|
||||
54
hw/kiwi/v2/phytx_abort_request_info.h
Normal file
54
hw/kiwi/v2/phytx_abort_request_info.h
Normal file
|
|
@ -0,0 +1,54 @@
|
|||
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
#ifndef _PHYTX_ABORT_REQUEST_INFO_H_
|
||||
#define _PHYTX_ABORT_REQUEST_INFO_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#define NUM_OF_WORDS_PHYTX_ABORT_REQUEST_INFO 1
|
||||
|
||||
struct phytx_abort_request_info {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint16_t phytx_abort_reason : 8,
|
||||
user_number : 6,
|
||||
reserved : 2;
|
||||
#else
|
||||
uint16_t reserved : 2,
|
||||
user_number : 6,
|
||||
phytx_abort_reason : 8;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define PHYTX_ABORT_REQUEST_INFO_PHYTX_ABORT_REASON_OFFSET 0x00000000
|
||||
#define PHYTX_ABORT_REQUEST_INFO_PHYTX_ABORT_REASON_LSB 0
|
||||
#define PHYTX_ABORT_REQUEST_INFO_PHYTX_ABORT_REASON_MSB 7
|
||||
#define PHYTX_ABORT_REQUEST_INFO_PHYTX_ABORT_REASON_MASK 0x000000ff
|
||||
|
||||
#define PHYTX_ABORT_REQUEST_INFO_USER_NUMBER_OFFSET 0x00000000
|
||||
#define PHYTX_ABORT_REQUEST_INFO_USER_NUMBER_LSB 8
|
||||
#define PHYTX_ABORT_REQUEST_INFO_USER_NUMBER_MSB 13
|
||||
#define PHYTX_ABORT_REQUEST_INFO_USER_NUMBER_MASK 0x00003f00
|
||||
|
||||
#define PHYTX_ABORT_REQUEST_INFO_RESERVED_OFFSET 0x00000000
|
||||
#define PHYTX_ABORT_REQUEST_INFO_RESERVED_LSB 14
|
||||
#define PHYTX_ABORT_REQUEST_INFO_RESERVED_MSB 15
|
||||
#define PHYTX_ABORT_REQUEST_INFO_RESERVED_MASK 0x0000c000
|
||||
|
||||
#endif
|
||||
56
hw/kiwi/v2/phytx_ppdu_header_info_request.h
Normal file
56
hw/kiwi/v2/phytx_ppdu_header_info_request.h
Normal file
|
|
@ -0,0 +1,56 @@
|
|||
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
#ifndef _PHYTX_PPDU_HEADER_INFO_REQUEST_H_
|
||||
#define _PHYTX_PPDU_HEADER_INFO_REQUEST_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#define NUM_OF_WORDS_PHYTX_PPDU_HEADER_INFO_REQUEST 2
|
||||
|
||||
#define NUM_OF_DWORDS_PHYTX_PPDU_HEADER_INFO_REQUEST 1
|
||||
|
||||
struct phytx_ppdu_header_info_request {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint16_t request_type : 5,
|
||||
reserved : 11;
|
||||
uint16_t tlv32_padding : 16;
|
||||
#else
|
||||
uint16_t reserved : 11,
|
||||
request_type : 5;
|
||||
uint16_t tlv32_padding : 16;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define PHYTX_PPDU_HEADER_INFO_REQUEST_REQUEST_TYPE_OFFSET 0x00000000
|
||||
#define PHYTX_PPDU_HEADER_INFO_REQUEST_REQUEST_TYPE_LSB 0
|
||||
#define PHYTX_PPDU_HEADER_INFO_REQUEST_REQUEST_TYPE_MSB 4
|
||||
#define PHYTX_PPDU_HEADER_INFO_REQUEST_REQUEST_TYPE_MASK 0x0000001f
|
||||
|
||||
#define PHYTX_PPDU_HEADER_INFO_REQUEST_RESERVED_OFFSET 0x00000000
|
||||
#define PHYTX_PPDU_HEADER_INFO_REQUEST_RESERVED_LSB 5
|
||||
#define PHYTX_PPDU_HEADER_INFO_REQUEST_RESERVED_MSB 15
|
||||
#define PHYTX_PPDU_HEADER_INFO_REQUEST_RESERVED_MASK 0x0000ffe0
|
||||
|
||||
#define PHYTX_PPDU_HEADER_INFO_REQUEST_TLV32_PADDING_OFFSET 0x00000002
|
||||
#define PHYTX_PPDU_HEADER_INFO_REQUEST_TLV32_PADDING_LSB 0
|
||||
#define PHYTX_PPDU_HEADER_INFO_REQUEST_TLV32_PADDING_MSB 15
|
||||
#define PHYTX_PPDU_HEADER_INFO_REQUEST_TLV32_PADDING_MASK 0x0000ffff
|
||||
|
||||
#endif
|
||||
1132
hw/kiwi/v2/received_response_user_15_8.h
Normal file
1132
hw/kiwi/v2/received_response_user_15_8.h
Normal file
File diff suppressed because it is too large
Load diff
1132
hw/kiwi/v2/received_response_user_23_16.h
Normal file
1132
hw/kiwi/v2/received_response_user_23_16.h
Normal file
File diff suppressed because it is too large
Load diff
1132
hw/kiwi/v2/received_response_user_31_24.h
Normal file
1132
hw/kiwi/v2/received_response_user_31_24.h
Normal file
File diff suppressed because it is too large
Load diff
721
hw/kiwi/v2/received_response_user_36_32.h
Normal file
721
hw/kiwi/v2/received_response_user_36_32.h
Normal file
|
|
@ -0,0 +1,721 @@
|
|||
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
#ifndef _RECEIVED_RESPONSE_USER_36_32_H_
|
||||
#define _RECEIVED_RESPONSE_USER_36_32_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#include "received_response_user_info.h"
|
||||
#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_36_32 40
|
||||
|
||||
#define NUM_OF_QWORDS_RECEIVED_RESPONSE_USER_36_32 20
|
||||
|
||||
struct received_response_user_36_32 {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
struct received_response_user_info received_response_details_user32;
|
||||
struct received_response_user_info received_response_details_user33;
|
||||
struct received_response_user_info received_response_details_user34;
|
||||
struct received_response_user_info received_response_details_user35;
|
||||
struct received_response_user_info received_response_details_user36;
|
||||
#else
|
||||
struct received_response_user_info received_response_details_user32;
|
||||
struct received_response_user_info received_response_details_user33;
|
||||
struct received_response_user_info received_response_details_user34;
|
||||
struct received_response_user_info received_response_details_user35;
|
||||
struct received_response_user_info received_response_details_user36;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000000
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_PASS_COUNT_LSB 0
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_PASS_COUNT_MSB 11
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000000
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_FAIL_COUNT_LSB 12
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_FAIL_COUNT_MSB 23
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000000
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOSNULL_FRAME_COUNT_LSB 24
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOSNULL_FRAME_COUNT_MSB 27
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_0A_OFFSET 0x0000000000000000
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_0A_LSB 28
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_0A_MSB 30
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_0A_MASK 0x0000000070000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_USER_INFO_VALID_OFFSET 0x0000000000000000
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_USER_INFO_VALID_LSB 31
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_USER_INFO_VALID_MSB 31
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_USER_INFO_VALID_MASK 0x0000000080000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000000
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_NULL_DELIMITER_COUNT_LSB 32
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_NULL_DELIMITER_COUNT_MSB 53
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_1A_OFFSET 0x0000000000000000
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_1A_LSB 54
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_1A_MSB 62
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_RESERVED_1A_MASK 0x7fc0000000000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_VALID_OFFSET 0x0000000000000000
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_VALID_LSB 63
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_VALID_MSB 63
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_VALID_MASK 0x8000000000000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_OFFSET 0x0000000000000008
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_LSB 0
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_MSB 31
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_HT_CONTROL_MASK 0x00000000ffffffff
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_VALID_OFFSET 0x0000000000000008
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_VALID_LSB 32
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_VALID_MSB 47
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_VALID_MASK 0x0000ffff00000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_EOSP_OFFSET 0x0000000000000008
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_EOSP_LSB 48
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_EOSP_MSB 63
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_EOSP_MASK 0xffff000000000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000010
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_0_LSB 0
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_0_MSB 7
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000010
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_1_LSB 8
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_1_MSB 15
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000010
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_2_LSB 16
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_2_MSB 23
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000010
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_3_LSB 24
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_3_MSB 31
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000010
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_4_LSB 32
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_4_MSB 39
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000010
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_5_LSB 40
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_5_MSB 47
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000010
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_6_LSB 48
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_6_MSB 55
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000010
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_7_LSB 56
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_7_MSB 63
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000018
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_8_LSB 0
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_8_MSB 7
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000018
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_9_LSB 8
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_9_MSB 15
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000018
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_10_LSB 16
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_10_MSB 23
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000018
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_11_LSB 24
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_11_MSB 31
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000018
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_12_LSB 32
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_12_MSB 39
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000018
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_13_LSB 40
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_13_MSB 47
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000018
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_14_LSB 48
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_14_MSB 55
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000018
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_15_LSB 56
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_15_MSB 63
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER32_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000020
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_PASS_COUNT_LSB 0
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_PASS_COUNT_MSB 11
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000020
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_FAIL_COUNT_LSB 12
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_FAIL_COUNT_MSB 23
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000020
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOSNULL_FRAME_COUNT_LSB 24
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOSNULL_FRAME_COUNT_MSB 27
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_0A_OFFSET 0x0000000000000020
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_0A_LSB 28
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_0A_MSB 30
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_0A_MASK 0x0000000070000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_USER_INFO_VALID_OFFSET 0x0000000000000020
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_USER_INFO_VALID_LSB 31
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_USER_INFO_VALID_MSB 31
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_USER_INFO_VALID_MASK 0x0000000080000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000020
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_NULL_DELIMITER_COUNT_LSB 32
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_NULL_DELIMITER_COUNT_MSB 53
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_1A_OFFSET 0x0000000000000020
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_1A_LSB 54
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_1A_MSB 62
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_RESERVED_1A_MASK 0x7fc0000000000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_VALID_OFFSET 0x0000000000000020
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_VALID_LSB 63
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_VALID_MSB 63
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_VALID_MASK 0x8000000000000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_OFFSET 0x0000000000000028
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_LSB 0
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_MSB 31
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_HT_CONTROL_MASK 0x00000000ffffffff
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_VALID_OFFSET 0x0000000000000028
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_VALID_LSB 32
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_VALID_MSB 47
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_VALID_MASK 0x0000ffff00000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_EOSP_OFFSET 0x0000000000000028
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_EOSP_LSB 48
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_EOSP_MSB 63
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_EOSP_MASK 0xffff000000000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000030
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_0_LSB 0
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_0_MSB 7
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000030
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_1_LSB 8
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_1_MSB 15
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000030
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_2_LSB 16
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_2_MSB 23
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000030
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_3_LSB 24
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_3_MSB 31
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000030
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_4_LSB 32
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_4_MSB 39
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000030
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_5_LSB 40
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_5_MSB 47
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000030
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_6_LSB 48
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_6_MSB 55
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000030
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_7_LSB 56
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_7_MSB 63
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000038
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_8_LSB 0
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_8_MSB 7
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000038
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_9_LSB 8
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_9_MSB 15
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000038
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_10_LSB 16
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_10_MSB 23
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000038
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_11_LSB 24
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_11_MSB 31
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000038
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_12_LSB 32
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_12_MSB 39
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000038
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_13_LSB 40
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_13_MSB 47
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000038
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_14_LSB 48
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_14_MSB 55
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000038
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_15_LSB 56
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_15_MSB 63
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER33_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000040
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_PASS_COUNT_LSB 0
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_PASS_COUNT_MSB 11
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000040
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_FAIL_COUNT_LSB 12
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_FAIL_COUNT_MSB 23
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000040
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOSNULL_FRAME_COUNT_LSB 24
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOSNULL_FRAME_COUNT_MSB 27
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_0A_OFFSET 0x0000000000000040
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_0A_LSB 28
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_0A_MSB 30
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_0A_MASK 0x0000000070000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_USER_INFO_VALID_OFFSET 0x0000000000000040
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_USER_INFO_VALID_LSB 31
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_USER_INFO_VALID_MSB 31
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_USER_INFO_VALID_MASK 0x0000000080000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000040
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_NULL_DELIMITER_COUNT_LSB 32
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_NULL_DELIMITER_COUNT_MSB 53
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_1A_OFFSET 0x0000000000000040
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_1A_LSB 54
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_1A_MSB 62
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_RESERVED_1A_MASK 0x7fc0000000000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_VALID_OFFSET 0x0000000000000040
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_VALID_LSB 63
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_VALID_MSB 63
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_VALID_MASK 0x8000000000000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_OFFSET 0x0000000000000048
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_LSB 0
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_MSB 31
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_HT_CONTROL_MASK 0x00000000ffffffff
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_VALID_OFFSET 0x0000000000000048
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_VALID_LSB 32
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_VALID_MSB 47
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_VALID_MASK 0x0000ffff00000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_EOSP_OFFSET 0x0000000000000048
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_EOSP_LSB 48
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_EOSP_MSB 63
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_EOSP_MASK 0xffff000000000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000050
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_0_LSB 0
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_0_MSB 7
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000050
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_1_LSB 8
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_1_MSB 15
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000050
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_2_LSB 16
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_2_MSB 23
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000050
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_3_LSB 24
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_3_MSB 31
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000050
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_4_LSB 32
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_4_MSB 39
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000050
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_5_LSB 40
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_5_MSB 47
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000050
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_6_LSB 48
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_6_MSB 55
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000050
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_7_LSB 56
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_7_MSB 63
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000058
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_8_LSB 0
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_8_MSB 7
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000058
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_9_LSB 8
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_9_MSB 15
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000058
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_10_LSB 16
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_10_MSB 23
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000058
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_11_LSB 24
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_11_MSB 31
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000058
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_12_LSB 32
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_12_MSB 39
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000058
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_13_LSB 40
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_13_MSB 47
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000058
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_14_LSB 48
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_14_MSB 55
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000058
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_15_LSB 56
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_15_MSB 63
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER34_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000060
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_PASS_COUNT_LSB 0
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_PASS_COUNT_MSB 11
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000060
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_FAIL_COUNT_LSB 12
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_FAIL_COUNT_MSB 23
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000060
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOSNULL_FRAME_COUNT_LSB 24
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOSNULL_FRAME_COUNT_MSB 27
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_0A_OFFSET 0x0000000000000060
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_0A_LSB 28
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_0A_MSB 30
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_0A_MASK 0x0000000070000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_USER_INFO_VALID_OFFSET 0x0000000000000060
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_USER_INFO_VALID_LSB 31
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_USER_INFO_VALID_MSB 31
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_USER_INFO_VALID_MASK 0x0000000080000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000060
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_NULL_DELIMITER_COUNT_LSB 32
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_NULL_DELIMITER_COUNT_MSB 53
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_1A_OFFSET 0x0000000000000060
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_1A_LSB 54
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_1A_MSB 62
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_RESERVED_1A_MASK 0x7fc0000000000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_VALID_OFFSET 0x0000000000000060
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_VALID_LSB 63
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_VALID_MSB 63
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_VALID_MASK 0x8000000000000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_OFFSET 0x0000000000000068
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_LSB 0
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_MSB 31
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_HT_CONTROL_MASK 0x00000000ffffffff
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_VALID_OFFSET 0x0000000000000068
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_VALID_LSB 32
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_VALID_MSB 47
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_VALID_MASK 0x0000ffff00000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_EOSP_OFFSET 0x0000000000000068
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_EOSP_LSB 48
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_EOSP_MSB 63
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_EOSP_MASK 0xffff000000000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000070
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_0_LSB 0
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_0_MSB 7
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000070
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_1_LSB 8
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_1_MSB 15
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000070
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_2_LSB 16
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_2_MSB 23
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000070
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_3_LSB 24
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_3_MSB 31
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000070
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_4_LSB 32
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_4_MSB 39
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000070
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_5_LSB 40
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_5_MSB 47
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000070
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_6_LSB 48
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_6_MSB 55
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000070
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_7_LSB 56
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_7_MSB 63
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000078
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_8_LSB 0
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_8_MSB 7
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000078
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_9_LSB 8
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_9_MSB 15
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000078
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_10_LSB 16
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_10_MSB 23
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000078
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_11_LSB 24
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_11_MSB 31
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000078
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_12_LSB 32
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_12_MSB 39
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000078
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_13_LSB 40
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_13_MSB 47
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000078
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_14_LSB 48
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_14_MSB 55
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000078
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_15_LSB 56
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_15_MSB 63
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER35_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_PASS_COUNT_OFFSET 0x0000000000000080
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_PASS_COUNT_LSB 0
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_PASS_COUNT_MSB 11
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_PASS_COUNT_MASK 0x0000000000000fff
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_FAIL_COUNT_OFFSET 0x0000000000000080
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_FAIL_COUNT_LSB 12
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_FAIL_COUNT_MSB 23
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_MPDU_FCS_FAIL_COUNT_MASK 0x0000000000fff000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOSNULL_FRAME_COUNT_OFFSET 0x0000000000000080
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOSNULL_FRAME_COUNT_LSB 24
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOSNULL_FRAME_COUNT_MSB 27
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOSNULL_FRAME_COUNT_MASK 0x000000000f000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_0A_OFFSET 0x0000000000000080
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_0A_LSB 28
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_0A_MSB 30
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_0A_MASK 0x0000000070000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_USER_INFO_VALID_OFFSET 0x0000000000000080
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_USER_INFO_VALID_LSB 31
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_USER_INFO_VALID_MSB 31
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_USER_INFO_VALID_MASK 0x0000000080000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_NULL_DELIMITER_COUNT_OFFSET 0x0000000000000080
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_NULL_DELIMITER_COUNT_LSB 32
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_NULL_DELIMITER_COUNT_MSB 53
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_NULL_DELIMITER_COUNT_MASK 0x003fffff00000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_1A_OFFSET 0x0000000000000080
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_1A_LSB 54
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_1A_MSB 62
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_RESERVED_1A_MASK 0x7fc0000000000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_VALID_OFFSET 0x0000000000000080
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_VALID_LSB 63
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_VALID_MSB 63
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_VALID_MASK 0x8000000000000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_OFFSET 0x0000000000000088
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_LSB 0
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_MSB 31
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_HT_CONTROL_MASK 0x00000000ffffffff
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_VALID_OFFSET 0x0000000000000088
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_VALID_LSB 32
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_VALID_MSB 47
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_VALID_MASK 0x0000ffff00000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_EOSP_OFFSET 0x0000000000000088
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_EOSP_LSB 48
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_EOSP_MSB 63
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_EOSP_MASK 0xffff000000000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_0_OFFSET 0x0000000000000090
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_0_LSB 0
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_0_MSB 7
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_0_MASK 0x00000000000000ff
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_1_OFFSET 0x0000000000000090
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_1_LSB 8
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_1_MSB 15
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_1_MASK 0x000000000000ff00
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_2_OFFSET 0x0000000000000090
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_2_LSB 16
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_2_MSB 23
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_2_MASK 0x0000000000ff0000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_3_OFFSET 0x0000000000000090
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_3_LSB 24
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_3_MSB 31
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_3_MASK 0x00000000ff000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_4_OFFSET 0x0000000000000090
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_4_LSB 32
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_4_MSB 39
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff00000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_5_OFFSET 0x0000000000000090
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_5_LSB 40
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_5_MSB 47
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff0000000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_6_OFFSET 0x0000000000000090
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_6_LSB 48
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_6_MSB 55
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_6_MASK 0x00ff000000000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_7_OFFSET 0x0000000000000090
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_7_LSB 56
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_7_MSB 63
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_7_MASK 0xff00000000000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_8_OFFSET 0x0000000000000098
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_8_LSB 0
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_8_MSB 7
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_8_MASK 0x00000000000000ff
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_9_OFFSET 0x0000000000000098
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_9_LSB 8
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_9_MSB 15
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_9_MASK 0x000000000000ff00
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_10_OFFSET 0x0000000000000098
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_10_LSB 16
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_10_MSB 23
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_10_MASK 0x0000000000ff0000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_11_OFFSET 0x0000000000000098
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_11_LSB 24
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_11_MSB 31
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_11_MASK 0x00000000ff000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000000000000098
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_12_LSB 32
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_12_MSB 39
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff00000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000000000000098
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_13_LSB 40
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_13_MSB 47
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff0000000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000000000000098
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_14_LSB 48
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_14_MSB 55
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_14_MASK 0x00ff000000000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000000000000098
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_15_LSB 56
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_15_MSB 63
|
||||
#define RECEIVED_RESPONSE_USER_36_32_RECEIVED_RESPONSE_DETAILS_USER36_QOS_CONTROL_15_8_TID_15_MASK 0xff00000000000000
|
||||
|
||||
#endif
|
||||
1132
hw/kiwi/v2/received_response_user_7_0.h
Normal file
1132
hw/kiwi/v2/received_response_user_7_0.h
Normal file
File diff suppressed because it is too large
Load diff
222
hw/kiwi/v2/received_response_user_info.h
Normal file
222
hw/kiwi/v2/received_response_user_info.h
Normal file
|
|
@ -0,0 +1,222 @@
|
|||
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
#ifndef _RECEIVED_RESPONSE_USER_INFO_H_
|
||||
#define _RECEIVED_RESPONSE_USER_INFO_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#define NUM_OF_DWORDS_RECEIVED_RESPONSE_USER_INFO 8
|
||||
|
||||
struct received_response_user_info {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t mpdu_fcs_pass_count : 12,
|
||||
mpdu_fcs_fail_count : 12,
|
||||
qosnull_frame_count : 4,
|
||||
reserved_0a : 3,
|
||||
user_info_valid : 1;
|
||||
uint32_t null_delimiter_count : 22,
|
||||
reserved_1a : 9,
|
||||
ht_control_valid : 1;
|
||||
uint32_t ht_control : 32;
|
||||
uint32_t qos_control_valid : 16,
|
||||
eosp : 16;
|
||||
uint32_t qos_control_15_8_tid_0 : 8,
|
||||
qos_control_15_8_tid_1 : 8,
|
||||
qos_control_15_8_tid_2 : 8,
|
||||
qos_control_15_8_tid_3 : 8;
|
||||
uint32_t qos_control_15_8_tid_4 : 8,
|
||||
qos_control_15_8_tid_5 : 8,
|
||||
qos_control_15_8_tid_6 : 8,
|
||||
qos_control_15_8_tid_7 : 8;
|
||||
uint32_t qos_control_15_8_tid_8 : 8,
|
||||
qos_control_15_8_tid_9 : 8,
|
||||
qos_control_15_8_tid_10 : 8,
|
||||
qos_control_15_8_tid_11 : 8;
|
||||
uint32_t qos_control_15_8_tid_12 : 8,
|
||||
qos_control_15_8_tid_13 : 8,
|
||||
qos_control_15_8_tid_14 : 8,
|
||||
qos_control_15_8_tid_15 : 8;
|
||||
#else
|
||||
uint32_t user_info_valid : 1,
|
||||
reserved_0a : 3,
|
||||
qosnull_frame_count : 4,
|
||||
mpdu_fcs_fail_count : 12,
|
||||
mpdu_fcs_pass_count : 12;
|
||||
uint32_t ht_control_valid : 1,
|
||||
reserved_1a : 9,
|
||||
null_delimiter_count : 22;
|
||||
uint32_t ht_control : 32;
|
||||
uint32_t eosp : 16,
|
||||
qos_control_valid : 16;
|
||||
uint32_t qos_control_15_8_tid_3 : 8,
|
||||
qos_control_15_8_tid_2 : 8,
|
||||
qos_control_15_8_tid_1 : 8,
|
||||
qos_control_15_8_tid_0 : 8;
|
||||
uint32_t qos_control_15_8_tid_7 : 8,
|
||||
qos_control_15_8_tid_6 : 8,
|
||||
qos_control_15_8_tid_5 : 8,
|
||||
qos_control_15_8_tid_4 : 8;
|
||||
uint32_t qos_control_15_8_tid_11 : 8,
|
||||
qos_control_15_8_tid_10 : 8,
|
||||
qos_control_15_8_tid_9 : 8,
|
||||
qos_control_15_8_tid_8 : 8;
|
||||
uint32_t qos_control_15_8_tid_15 : 8,
|
||||
qos_control_15_8_tid_14 : 8,
|
||||
qos_control_15_8_tid_13 : 8,
|
||||
qos_control_15_8_tid_12 : 8;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_PASS_COUNT_OFFSET 0x00000000
|
||||
#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_PASS_COUNT_LSB 0
|
||||
#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_PASS_COUNT_MSB 11
|
||||
#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_PASS_COUNT_MASK 0x00000fff
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_FAIL_COUNT_OFFSET 0x00000000
|
||||
#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_FAIL_COUNT_LSB 12
|
||||
#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_FAIL_COUNT_MSB 23
|
||||
#define RECEIVED_RESPONSE_USER_INFO_MPDU_FCS_FAIL_COUNT_MASK 0x00fff000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOSNULL_FRAME_COUNT_OFFSET 0x00000000
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOSNULL_FRAME_COUNT_LSB 24
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOSNULL_FRAME_COUNT_MSB 27
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOSNULL_FRAME_COUNT_MASK 0x0f000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_INFO_RESERVED_0A_OFFSET 0x00000000
|
||||
#define RECEIVED_RESPONSE_USER_INFO_RESERVED_0A_LSB 28
|
||||
#define RECEIVED_RESPONSE_USER_INFO_RESERVED_0A_MSB 30
|
||||
#define RECEIVED_RESPONSE_USER_INFO_RESERVED_0A_MASK 0x70000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_INFO_USER_INFO_VALID_OFFSET 0x00000000
|
||||
#define RECEIVED_RESPONSE_USER_INFO_USER_INFO_VALID_LSB 31
|
||||
#define RECEIVED_RESPONSE_USER_INFO_USER_INFO_VALID_MSB 31
|
||||
#define RECEIVED_RESPONSE_USER_INFO_USER_INFO_VALID_MASK 0x80000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_INFO_NULL_DELIMITER_COUNT_OFFSET 0x00000004
|
||||
#define RECEIVED_RESPONSE_USER_INFO_NULL_DELIMITER_COUNT_LSB 0
|
||||
#define RECEIVED_RESPONSE_USER_INFO_NULL_DELIMITER_COUNT_MSB 21
|
||||
#define RECEIVED_RESPONSE_USER_INFO_NULL_DELIMITER_COUNT_MASK 0x003fffff
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_INFO_RESERVED_1A_OFFSET 0x00000004
|
||||
#define RECEIVED_RESPONSE_USER_INFO_RESERVED_1A_LSB 22
|
||||
#define RECEIVED_RESPONSE_USER_INFO_RESERVED_1A_MSB 30
|
||||
#define RECEIVED_RESPONSE_USER_INFO_RESERVED_1A_MASK 0x7fc00000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_VALID_OFFSET 0x00000004
|
||||
#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_VALID_LSB 31
|
||||
#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_VALID_MSB 31
|
||||
#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_VALID_MASK 0x80000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_OFFSET 0x00000008
|
||||
#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_LSB 0
|
||||
#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_MSB 31
|
||||
#define RECEIVED_RESPONSE_USER_INFO_HT_CONTROL_MASK 0xffffffff
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_VALID_OFFSET 0x0000000c
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_VALID_LSB 0
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_VALID_MSB 15
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_VALID_MASK 0x0000ffff
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_INFO_EOSP_OFFSET 0x0000000c
|
||||
#define RECEIVED_RESPONSE_USER_INFO_EOSP_LSB 16
|
||||
#define RECEIVED_RESPONSE_USER_INFO_EOSP_MSB 31
|
||||
#define RECEIVED_RESPONSE_USER_INFO_EOSP_MASK 0xffff0000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_0_OFFSET 0x00000010
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_0_LSB 0
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_0_MSB 7
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_0_MASK 0x000000ff
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_1_OFFSET 0x00000010
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_1_LSB 8
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_1_MSB 15
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_1_MASK 0x0000ff00
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_2_OFFSET 0x00000010
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_2_LSB 16
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_2_MSB 23
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_2_MASK 0x00ff0000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_3_OFFSET 0x00000010
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_3_LSB 24
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_3_MSB 31
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_3_MASK 0xff000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_4_OFFSET 0x00000014
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_4_LSB 0
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_4_MSB 7
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_4_MASK 0x000000ff
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_5_OFFSET 0x00000014
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_5_LSB 8
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_5_MSB 15
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_5_MASK 0x0000ff00
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_6_OFFSET 0x00000014
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_6_LSB 16
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_6_MSB 23
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_6_MASK 0x00ff0000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_7_OFFSET 0x00000014
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_7_LSB 24
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_7_MSB 31
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_7_MASK 0xff000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_8_OFFSET 0x00000018
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_8_LSB 0
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_8_MSB 7
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_8_MASK 0x000000ff
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_9_OFFSET 0x00000018
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_9_LSB 8
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_9_MSB 15
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_9_MASK 0x0000ff00
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_10_OFFSET 0x00000018
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_10_LSB 16
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_10_MSB 23
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_10_MASK 0x00ff0000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_11_OFFSET 0x00000018
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_11_LSB 24
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_11_MSB 31
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_11_MASK 0xff000000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_12_OFFSET 0x0000001c
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_12_LSB 0
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_12_MSB 7
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_12_MASK 0x000000ff
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_13_OFFSET 0x0000001c
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_13_LSB 8
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_13_MSB 15
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_13_MASK 0x0000ff00
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_14_OFFSET 0x0000001c
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_14_LSB 16
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_14_MSB 23
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_14_MASK 0x00ff0000
|
||||
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_15_OFFSET 0x0000001c
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_15_LSB 24
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_15_MSB 31
|
||||
#define RECEIVED_RESPONSE_USER_INFO_QOS_CONTROL_15_8_TID_15_MASK 0xff000000
|
||||
|
||||
#endif
|
||||
130
hw/kiwi/v2/received_trigger_info.h
Normal file
130
hw/kiwi/v2/received_trigger_info.h
Normal file
|
|
@ -0,0 +1,130 @@
|
|||
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
#ifndef _RECEIVED_TRIGGER_INFO_H_
|
||||
#define _RECEIVED_TRIGGER_INFO_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#include "received_trigger_info_details.h"
|
||||
#define NUM_OF_DWORDS_RECEIVED_TRIGGER_INFO 6
|
||||
|
||||
#define NUM_OF_QWORDS_RECEIVED_TRIGGER_INFO 3
|
||||
|
||||
struct received_trigger_info {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
struct received_trigger_info_details received_trigger_details;
|
||||
uint32_t tlv64_padding : 32;
|
||||
#else
|
||||
struct received_trigger_info_details received_trigger_details;
|
||||
uint32_t tlv64_padding : 32;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_TYPE_OFFSET 0x0000000000000000
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_TYPE_LSB 0
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_TYPE_MSB 3
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_TYPE_MASK 0x000000000000000f
|
||||
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_OFFSET 0x0000000000000000
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_LSB 4
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_MSB 4
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_SOURCE_MASK 0x0000000000000010
|
||||
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_TYPE_OFFSET 0x0000000000000000
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_TYPE_LSB 5
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_TYPE_MSB 8
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_AX_TRIGGER_TYPE_MASK 0x00000000000001e0
|
||||
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_OFFSET 0x0000000000000000
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_LSB 9
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_MSB 21
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_MASK 0x00000000003ffe00
|
||||
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_VALID_OFFSET 0x0000000000000000
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_VALID_LSB 22
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_VALID_MSB 22
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_VALID_MASK 0x0000000000400000
|
||||
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_VALID_OFFSET 0x0000000000000000
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_VALID_LSB 23
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_VALID_MSB 23
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_VALID_MASK 0x0000000000800000
|
||||
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_INFO_VALID_OFFSET 0x0000000000000000
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_INFO_VALID_LSB 24
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_INFO_VALID_MSB 24
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_INFO_VALID_MASK 0x0000000001000000
|
||||
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RANGING_TRIGGER_SUBTYPE_OFFSET 0x0000000000000000
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RANGING_TRIGGER_SUBTYPE_LSB 25
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RANGING_TRIGGER_SUBTYPE_MSB 28
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RANGING_TRIGGER_SUBTYPE_MASK 0x000000001e000000
|
||||
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_0B_OFFSET 0x0000000000000000
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_0B_LSB 29
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_0B_MSB 31
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_0B_MASK 0x00000000e0000000
|
||||
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_PHY_PPDU_ID_OFFSET 0x0000000000000000
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_PHY_PPDU_ID_LSB 32
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_PHY_PPDU_ID_MSB 47
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_PHY_PPDU_ID_MASK 0x0000ffff00000000
|
||||
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_OFFSET 0x0000000000000000
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_LSB 48
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_MSB 59
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_LSIG_RESPONSE_LENGTH_MASK 0x0fff000000000000
|
||||
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_1A_OFFSET 0x0000000000000000
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_1A_LSB 60
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_1A_MSB 63
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_1A_MASK 0xf000000000000000
|
||||
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_OFFSET 0x0000000000000008
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_LSB 0
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_MSB 15
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_FRAME_CONTROL_MASK 0x000000000000ffff
|
||||
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_OFFSET 0x0000000000000008
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_LSB 16
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_MSB 31
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_QOS_CONTROL_MASK 0x00000000ffff0000
|
||||
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SW_PEER_ID_OFFSET 0x0000000000000008
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SW_PEER_ID_LSB 32
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SW_PEER_ID_MSB 47
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_SW_PEER_ID_MASK 0x0000ffff00000000
|
||||
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_3A_OFFSET 0x0000000000000008
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_3A_LSB 48
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_3A_MSB 63
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_RESERVED_3A_MASK 0xffff000000000000
|
||||
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_OFFSET 0x0000000000000010
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_LSB 0
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_MSB 31
|
||||
#define RECEIVED_TRIGGER_INFO_RECEIVED_TRIGGER_DETAILS_HE_CONTROL_MASK 0x00000000ffffffff
|
||||
|
||||
#define RECEIVED_TRIGGER_INFO_TLV64_PADDING_OFFSET 0x0000000000000010
|
||||
#define RECEIVED_TRIGGER_INFO_TLV64_PADDING_LSB 32
|
||||
#define RECEIVED_TRIGGER_INFO_TLV64_PADDING_MSB 63
|
||||
#define RECEIVED_TRIGGER_INFO_TLV64_PADDING_MASK 0xffffffff00000000
|
||||
|
||||
#endif
|
||||
152
hw/kiwi/v2/received_trigger_info_details.h
Normal file
152
hw/kiwi/v2/received_trigger_info_details.h
Normal file
|
|
@ -0,0 +1,152 @@
|
|||
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
#ifndef _RECEIVED_TRIGGER_INFO_DETAILS_H_
|
||||
#define _RECEIVED_TRIGGER_INFO_DETAILS_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#define NUM_OF_DWORDS_RECEIVED_TRIGGER_INFO_DETAILS 5
|
||||
|
||||
struct received_trigger_info_details {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t trigger_type : 4,
|
||||
ax_trigger_source : 1,
|
||||
ax_trigger_type : 4,
|
||||
trigger_source_sta_full_aid : 13,
|
||||
frame_control_valid : 1,
|
||||
qos_control_valid : 1,
|
||||
he_control_info_valid : 1,
|
||||
__reserved_g_0005_trigger_subtype : 4,
|
||||
reserved_0b : 3;
|
||||
uint32_t phy_ppdu_id : 16,
|
||||
lsig_response_length : 12,
|
||||
reserved_1a : 4;
|
||||
uint32_t frame_control : 16,
|
||||
qos_control : 16;
|
||||
uint32_t sw_peer_id : 16,
|
||||
reserved_3a : 16;
|
||||
uint32_t he_control : 32;
|
||||
#else
|
||||
uint32_t reserved_0b : 3,
|
||||
__reserved_g_0005_trigger_subtype : 4,
|
||||
he_control_info_valid : 1,
|
||||
qos_control_valid : 1,
|
||||
frame_control_valid : 1,
|
||||
trigger_source_sta_full_aid : 13,
|
||||
ax_trigger_type : 4,
|
||||
ax_trigger_source : 1,
|
||||
trigger_type : 4;
|
||||
uint32_t reserved_1a : 4,
|
||||
lsig_response_length : 12,
|
||||
phy_ppdu_id : 16;
|
||||
uint32_t qos_control : 16,
|
||||
frame_control : 16;
|
||||
uint32_t reserved_3a : 16,
|
||||
sw_peer_id : 16;
|
||||
uint32_t he_control : 32;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_TYPE_OFFSET 0x00000000
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_TYPE_LSB 0
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_TYPE_MSB 3
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_TYPE_MASK 0x0000000f
|
||||
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_SOURCE_OFFSET 0x00000000
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_SOURCE_LSB 4
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_SOURCE_MSB 4
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_SOURCE_MASK 0x00000010
|
||||
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_TYPE_OFFSET 0x00000000
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_TYPE_LSB 5
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_TYPE_MSB 8
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_AX_TRIGGER_TYPE_MASK 0x000001e0
|
||||
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_OFFSET 0x00000000
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_LSB 9
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_MSB 21
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_TRIGGER_SOURCE_STA_FULL_AID_MASK 0x003ffe00
|
||||
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_VALID_OFFSET 0x00000000
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_VALID_LSB 22
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_VALID_MSB 22
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_VALID_MASK 0x00400000
|
||||
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_VALID_OFFSET 0x00000000
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_VALID_LSB 23
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_VALID_MSB 23
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_VALID_MASK 0x00800000
|
||||
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_INFO_VALID_OFFSET 0x00000000
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_INFO_VALID_LSB 24
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_INFO_VALID_MSB 24
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_INFO_VALID_MASK 0x01000000
|
||||
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_RANGING_TRIGGER_SUBTYPE_OFFSET 0x00000000
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_RANGING_TRIGGER_SUBTYPE_LSB 25
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_RANGING_TRIGGER_SUBTYPE_MSB 28
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_RANGING_TRIGGER_SUBTYPE_MASK 0x1e000000
|
||||
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_0B_OFFSET 0x00000000
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_0B_LSB 29
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_0B_MSB 31
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_0B_MASK 0xe0000000
|
||||
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_PHY_PPDU_ID_OFFSET 0x00000004
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_PHY_PPDU_ID_LSB 0
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_PHY_PPDU_ID_MSB 15
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_PHY_PPDU_ID_MASK 0x0000ffff
|
||||
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_LSIG_RESPONSE_LENGTH_OFFSET 0x00000004
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_LSIG_RESPONSE_LENGTH_LSB 16
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_LSIG_RESPONSE_LENGTH_MSB 27
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_LSIG_RESPONSE_LENGTH_MASK 0x0fff0000
|
||||
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_1A_OFFSET 0x00000004
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_1A_LSB 28
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_1A_MSB 31
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_1A_MASK 0xf0000000
|
||||
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_OFFSET 0x00000008
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_LSB 0
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_MSB 15
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_FRAME_CONTROL_MASK 0x0000ffff
|
||||
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_OFFSET 0x00000008
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_LSB 16
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_MSB 31
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_QOS_CONTROL_MASK 0xffff0000
|
||||
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_SW_PEER_ID_OFFSET 0x0000000c
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_SW_PEER_ID_LSB 0
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_SW_PEER_ID_MSB 15
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_SW_PEER_ID_MASK 0x0000ffff
|
||||
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_3A_OFFSET 0x0000000c
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_3A_LSB 16
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_3A_MSB 31
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_RESERVED_3A_MASK 0xffff0000
|
||||
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_OFFSET 0x00000010
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_LSB 0
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_MSB 31
|
||||
#define RECEIVED_TRIGGER_INFO_DETAILS_HE_CONTROL_MASK 0xffffffff
|
||||
|
||||
#endif
|
||||
468
hw/kiwi/v2/response_end_status.h
Normal file
468
hw/kiwi/v2/response_end_status.h
Normal file
|
|
@ -0,0 +1,468 @@
|
|||
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
#ifndef _RESPONSE_END_STATUS_H_
|
||||
#define _RESPONSE_END_STATUS_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#include "phytx_abort_request_info.h"
|
||||
#define NUM_OF_DWORDS_RESPONSE_END_STATUS 22
|
||||
|
||||
#define NUM_OF_QWORDS_RESPONSE_END_STATUS 11
|
||||
|
||||
struct response_end_status {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t coex_bt_tx_while_wlan_tx : 1,
|
||||
coex_wan_tx_while_wlan_tx : 1,
|
||||
coex_wlan_tx_while_wlan_tx : 1,
|
||||
global_data_underflow_warning : 1,
|
||||
response_transmit_status : 4,
|
||||
phytx_pkt_end_info_valid : 1,
|
||||
phytx_abort_request_info_valid : 1,
|
||||
generated_response : 3,
|
||||
mba_user_count : 7,
|
||||
mba_fake_bitmap_count : 7,
|
||||
coex_based_tx_bw : 3,
|
||||
trig_response_related : 1,
|
||||
dpdtrain_done : 1;
|
||||
struct phytx_abort_request_info phytx_abort_request_info_details;
|
||||
uint16_t cbf_segment_request_mask : 8,
|
||||
cbf_segment_sent_mask : 8;
|
||||
uint32_t underflow_mpdu_count : 9,
|
||||
data_underflow_warning : 2,
|
||||
phy_tx_gain_setting : 8,
|
||||
timing_status : 2,
|
||||
only_null_delim_sent : 1,
|
||||
brp_info_valid : 1,
|
||||
reserved_2a : 9;
|
||||
uint32_t mu_response_bitmap_31_0 : 32;
|
||||
uint32_t mu_response_bitmap_36_32 : 5,
|
||||
reserved_4a : 11,
|
||||
transmit_delay : 16;
|
||||
uint32_t start_of_frame_timestamp_15_0 : 16,
|
||||
start_of_frame_timestamp_31_16 : 16;
|
||||
uint32_t end_of_frame_timestamp_15_0 : 16,
|
||||
end_of_frame_timestamp_31_16 : 16;
|
||||
uint32_t tx_group_delay : 12,
|
||||
reserved_7a : 4,
|
||||
tpc_dbg_info_cmn_15_0 : 16;
|
||||
uint32_t tpc_dbg_info_31_16 : 16,
|
||||
tpc_dbg_info_47_32 : 16;
|
||||
uint32_t tpc_dbg_info_chn1_15_0 : 16,
|
||||
tpc_dbg_info_chn1_31_16 : 16;
|
||||
uint32_t tpc_dbg_info_chn1_47_32 : 16,
|
||||
tpc_dbg_info_chn1_63_48 : 16;
|
||||
uint32_t tpc_dbg_info_chn1_79_64 : 16,
|
||||
tpc_dbg_info_chn2_15_0 : 16;
|
||||
uint32_t tpc_dbg_info_chn2_31_16 : 16,
|
||||
tpc_dbg_info_chn2_47_32 : 16;
|
||||
uint32_t tpc_dbg_info_chn2_63_48 : 16,
|
||||
tpc_dbg_info_chn2_79_64 : 16;
|
||||
uint32_t phytx_tx_end_sw_info_15_0 : 16,
|
||||
phytx_tx_end_sw_info_31_16 : 16;
|
||||
uint32_t phytx_tx_end_sw_info_47_32 : 16,
|
||||
phytx_tx_end_sw_info_63_48 : 16;
|
||||
uint32_t addr1_31_0 : 32;
|
||||
uint32_t addr1_47_32 : 16,
|
||||
addr2_15_0 : 16;
|
||||
uint32_t addr2_47_16 : 32;
|
||||
uint32_t addr3_31_0 : 32;
|
||||
uint32_t addr3_47_32 : 16,
|
||||
__reserved_g_0005 : 1,
|
||||
secure : 1,
|
||||
__reserved_g_0005_ftm_frame_sent : 1,
|
||||
reserved_20a : 13;
|
||||
uint32_t tlv64_padding : 32;
|
||||
#else
|
||||
uint32_t dpdtrain_done : 1,
|
||||
trig_response_related : 1,
|
||||
coex_based_tx_bw : 3,
|
||||
mba_fake_bitmap_count : 7,
|
||||
mba_user_count : 7,
|
||||
generated_response : 3,
|
||||
phytx_abort_request_info_valid : 1,
|
||||
phytx_pkt_end_info_valid : 1,
|
||||
response_transmit_status : 4,
|
||||
global_data_underflow_warning : 1,
|
||||
coex_wlan_tx_while_wlan_tx : 1,
|
||||
coex_wan_tx_while_wlan_tx : 1,
|
||||
coex_bt_tx_while_wlan_tx : 1;
|
||||
uint32_t cbf_segment_sent_mask : 8,
|
||||
cbf_segment_request_mask : 8;
|
||||
struct phytx_abort_request_info phytx_abort_request_info_details;
|
||||
uint32_t reserved_2a : 9,
|
||||
brp_info_valid : 1,
|
||||
only_null_delim_sent : 1,
|
||||
timing_status : 2,
|
||||
phy_tx_gain_setting : 8,
|
||||
data_underflow_warning : 2,
|
||||
underflow_mpdu_count : 9;
|
||||
uint32_t mu_response_bitmap_31_0 : 32;
|
||||
uint32_t transmit_delay : 16,
|
||||
reserved_4a : 11,
|
||||
mu_response_bitmap_36_32 : 5;
|
||||
uint32_t start_of_frame_timestamp_31_16 : 16,
|
||||
start_of_frame_timestamp_15_0 : 16;
|
||||
uint32_t end_of_frame_timestamp_31_16 : 16,
|
||||
end_of_frame_timestamp_15_0 : 16;
|
||||
uint32_t tpc_dbg_info_cmn_15_0 : 16,
|
||||
reserved_7a : 4,
|
||||
tx_group_delay : 12;
|
||||
uint32_t tpc_dbg_info_47_32 : 16,
|
||||
tpc_dbg_info_31_16 : 16;
|
||||
uint32_t tpc_dbg_info_chn1_31_16 : 16,
|
||||
tpc_dbg_info_chn1_15_0 : 16;
|
||||
uint32_t tpc_dbg_info_chn1_63_48 : 16,
|
||||
tpc_dbg_info_chn1_47_32 : 16;
|
||||
uint32_t tpc_dbg_info_chn2_15_0 : 16,
|
||||
tpc_dbg_info_chn1_79_64 : 16;
|
||||
uint32_t tpc_dbg_info_chn2_47_32 : 16,
|
||||
tpc_dbg_info_chn2_31_16 : 16;
|
||||
uint32_t tpc_dbg_info_chn2_79_64 : 16,
|
||||
tpc_dbg_info_chn2_63_48 : 16;
|
||||
uint32_t phytx_tx_end_sw_info_31_16 : 16,
|
||||
phytx_tx_end_sw_info_15_0 : 16;
|
||||
uint32_t phytx_tx_end_sw_info_63_48 : 16,
|
||||
phytx_tx_end_sw_info_47_32 : 16;
|
||||
uint32_t addr1_31_0 : 32;
|
||||
uint32_t addr2_15_0 : 16,
|
||||
addr1_47_32 : 16;
|
||||
uint32_t addr2_47_16 : 32;
|
||||
uint32_t addr3_31_0 : 32;
|
||||
uint32_t reserved_20a : 13,
|
||||
__reserved_g_0005_ftm_frame_sent : 1,
|
||||
secure : 1,
|
||||
__reserved_g_0005 : 1,
|
||||
addr3_47_32 : 16;
|
||||
uint32_t tlv64_padding : 32;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define RESPONSE_END_STATUS_COEX_BT_TX_WHILE_WLAN_TX_OFFSET 0x0000000000000000
|
||||
#define RESPONSE_END_STATUS_COEX_BT_TX_WHILE_WLAN_TX_LSB 0
|
||||
#define RESPONSE_END_STATUS_COEX_BT_TX_WHILE_WLAN_TX_MSB 0
|
||||
#define RESPONSE_END_STATUS_COEX_BT_TX_WHILE_WLAN_TX_MASK 0x0000000000000001
|
||||
|
||||
#define RESPONSE_END_STATUS_COEX_WAN_TX_WHILE_WLAN_TX_OFFSET 0x0000000000000000
|
||||
#define RESPONSE_END_STATUS_COEX_WAN_TX_WHILE_WLAN_TX_LSB 1
|
||||
#define RESPONSE_END_STATUS_COEX_WAN_TX_WHILE_WLAN_TX_MSB 1
|
||||
#define RESPONSE_END_STATUS_COEX_WAN_TX_WHILE_WLAN_TX_MASK 0x0000000000000002
|
||||
|
||||
#define RESPONSE_END_STATUS_COEX_WLAN_TX_WHILE_WLAN_TX_OFFSET 0x0000000000000000
|
||||
#define RESPONSE_END_STATUS_COEX_WLAN_TX_WHILE_WLAN_TX_LSB 2
|
||||
#define RESPONSE_END_STATUS_COEX_WLAN_TX_WHILE_WLAN_TX_MSB 2
|
||||
#define RESPONSE_END_STATUS_COEX_WLAN_TX_WHILE_WLAN_TX_MASK 0x0000000000000004
|
||||
|
||||
#define RESPONSE_END_STATUS_GLOBAL_DATA_UNDERFLOW_WARNING_OFFSET 0x0000000000000000
|
||||
#define RESPONSE_END_STATUS_GLOBAL_DATA_UNDERFLOW_WARNING_LSB 3
|
||||
#define RESPONSE_END_STATUS_GLOBAL_DATA_UNDERFLOW_WARNING_MSB 3
|
||||
#define RESPONSE_END_STATUS_GLOBAL_DATA_UNDERFLOW_WARNING_MASK 0x0000000000000008
|
||||
|
||||
#define RESPONSE_END_STATUS_RESPONSE_TRANSMIT_STATUS_OFFSET 0x0000000000000000
|
||||
#define RESPONSE_END_STATUS_RESPONSE_TRANSMIT_STATUS_LSB 4
|
||||
#define RESPONSE_END_STATUS_RESPONSE_TRANSMIT_STATUS_MSB 7
|
||||
#define RESPONSE_END_STATUS_RESPONSE_TRANSMIT_STATUS_MASK 0x00000000000000f0
|
||||
|
||||
#define RESPONSE_END_STATUS_PHYTX_PKT_END_INFO_VALID_OFFSET 0x0000000000000000
|
||||
#define RESPONSE_END_STATUS_PHYTX_PKT_END_INFO_VALID_LSB 8
|
||||
#define RESPONSE_END_STATUS_PHYTX_PKT_END_INFO_VALID_MSB 8
|
||||
#define RESPONSE_END_STATUS_PHYTX_PKT_END_INFO_VALID_MASK 0x0000000000000100
|
||||
|
||||
#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_VALID_OFFSET 0x0000000000000000
|
||||
#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_VALID_LSB 9
|
||||
#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_VALID_MSB 9
|
||||
#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_VALID_MASK 0x0000000000000200
|
||||
|
||||
#define RESPONSE_END_STATUS_GENERATED_RESPONSE_OFFSET 0x0000000000000000
|
||||
#define RESPONSE_END_STATUS_GENERATED_RESPONSE_LSB 10
|
||||
#define RESPONSE_END_STATUS_GENERATED_RESPONSE_MSB 12
|
||||
#define RESPONSE_END_STATUS_GENERATED_RESPONSE_MASK 0x0000000000001c00
|
||||
|
||||
#define RESPONSE_END_STATUS_MBA_USER_COUNT_OFFSET 0x0000000000000000
|
||||
#define RESPONSE_END_STATUS_MBA_USER_COUNT_LSB 13
|
||||
#define RESPONSE_END_STATUS_MBA_USER_COUNT_MSB 19
|
||||
#define RESPONSE_END_STATUS_MBA_USER_COUNT_MASK 0x00000000000fe000
|
||||
|
||||
#define RESPONSE_END_STATUS_MBA_FAKE_BITMAP_COUNT_OFFSET 0x0000000000000000
|
||||
#define RESPONSE_END_STATUS_MBA_FAKE_BITMAP_COUNT_LSB 20
|
||||
#define RESPONSE_END_STATUS_MBA_FAKE_BITMAP_COUNT_MSB 26
|
||||
#define RESPONSE_END_STATUS_MBA_FAKE_BITMAP_COUNT_MASK 0x0000000007f00000
|
||||
|
||||
#define RESPONSE_END_STATUS_COEX_BASED_TX_BW_OFFSET 0x0000000000000000
|
||||
#define RESPONSE_END_STATUS_COEX_BASED_TX_BW_LSB 27
|
||||
#define RESPONSE_END_STATUS_COEX_BASED_TX_BW_MSB 29
|
||||
#define RESPONSE_END_STATUS_COEX_BASED_TX_BW_MASK 0x0000000038000000
|
||||
|
||||
#define RESPONSE_END_STATUS_TRIG_RESPONSE_RELATED_OFFSET 0x0000000000000000
|
||||
#define RESPONSE_END_STATUS_TRIG_RESPONSE_RELATED_LSB 30
|
||||
#define RESPONSE_END_STATUS_TRIG_RESPONSE_RELATED_MSB 30
|
||||
#define RESPONSE_END_STATUS_TRIG_RESPONSE_RELATED_MASK 0x0000000040000000
|
||||
|
||||
#define RESPONSE_END_STATUS_DPDTRAIN_DONE_OFFSET 0x0000000000000000
|
||||
#define RESPONSE_END_STATUS_DPDTRAIN_DONE_LSB 31
|
||||
#define RESPONSE_END_STATUS_DPDTRAIN_DONE_MSB 31
|
||||
#define RESPONSE_END_STATUS_DPDTRAIN_DONE_MASK 0x0000000080000000
|
||||
|
||||
#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_OFFSET 0x0000000000000000
|
||||
#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_LSB 32
|
||||
#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MSB 39
|
||||
#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MASK 0x000000ff00000000
|
||||
|
||||
#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_OFFSET 0x0000000000000000
|
||||
#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_LSB 40
|
||||
#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MSB 45
|
||||
#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MASK 0x00003f0000000000
|
||||
|
||||
#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000
|
||||
#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_LSB 46
|
||||
#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MSB 47
|
||||
#define RESPONSE_END_STATUS_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MASK 0x0000c00000000000
|
||||
|
||||
#define RESPONSE_END_STATUS_CBF_SEGMENT_REQUEST_MASK_OFFSET 0x0000000000000000
|
||||
#define RESPONSE_END_STATUS_CBF_SEGMENT_REQUEST_MASK_LSB 48
|
||||
#define RESPONSE_END_STATUS_CBF_SEGMENT_REQUEST_MASK_MSB 55
|
||||
#define RESPONSE_END_STATUS_CBF_SEGMENT_REQUEST_MASK_MASK 0x00ff000000000000
|
||||
|
||||
#define RESPONSE_END_STATUS_CBF_SEGMENT_SENT_MASK_OFFSET 0x0000000000000000
|
||||
#define RESPONSE_END_STATUS_CBF_SEGMENT_SENT_MASK_LSB 56
|
||||
#define RESPONSE_END_STATUS_CBF_SEGMENT_SENT_MASK_MSB 63
|
||||
#define RESPONSE_END_STATUS_CBF_SEGMENT_SENT_MASK_MASK 0xff00000000000000
|
||||
|
||||
#define RESPONSE_END_STATUS_UNDERFLOW_MPDU_COUNT_OFFSET 0x0000000000000008
|
||||
#define RESPONSE_END_STATUS_UNDERFLOW_MPDU_COUNT_LSB 0
|
||||
#define RESPONSE_END_STATUS_UNDERFLOW_MPDU_COUNT_MSB 8
|
||||
#define RESPONSE_END_STATUS_UNDERFLOW_MPDU_COUNT_MASK 0x00000000000001ff
|
||||
|
||||
#define RESPONSE_END_STATUS_DATA_UNDERFLOW_WARNING_OFFSET 0x0000000000000008
|
||||
#define RESPONSE_END_STATUS_DATA_UNDERFLOW_WARNING_LSB 9
|
||||
#define RESPONSE_END_STATUS_DATA_UNDERFLOW_WARNING_MSB 10
|
||||
#define RESPONSE_END_STATUS_DATA_UNDERFLOW_WARNING_MASK 0x0000000000000600
|
||||
|
||||
#define RESPONSE_END_STATUS_PHY_TX_GAIN_SETTING_OFFSET 0x0000000000000008
|
||||
#define RESPONSE_END_STATUS_PHY_TX_GAIN_SETTING_LSB 11
|
||||
#define RESPONSE_END_STATUS_PHY_TX_GAIN_SETTING_MSB 18
|
||||
#define RESPONSE_END_STATUS_PHY_TX_GAIN_SETTING_MASK 0x000000000007f800
|
||||
|
||||
#define RESPONSE_END_STATUS_TIMING_STATUS_OFFSET 0x0000000000000008
|
||||
#define RESPONSE_END_STATUS_TIMING_STATUS_LSB 19
|
||||
#define RESPONSE_END_STATUS_TIMING_STATUS_MSB 20
|
||||
#define RESPONSE_END_STATUS_TIMING_STATUS_MASK 0x0000000000180000
|
||||
|
||||
#define RESPONSE_END_STATUS_ONLY_NULL_DELIM_SENT_OFFSET 0x0000000000000008
|
||||
#define RESPONSE_END_STATUS_ONLY_NULL_DELIM_SENT_LSB 21
|
||||
#define RESPONSE_END_STATUS_ONLY_NULL_DELIM_SENT_MSB 21
|
||||
#define RESPONSE_END_STATUS_ONLY_NULL_DELIM_SENT_MASK 0x0000000000200000
|
||||
|
||||
#define RESPONSE_END_STATUS_BRP_INFO_VALID_OFFSET 0x0000000000000008
|
||||
#define RESPONSE_END_STATUS_BRP_INFO_VALID_LSB 22
|
||||
#define RESPONSE_END_STATUS_BRP_INFO_VALID_MSB 22
|
||||
#define RESPONSE_END_STATUS_BRP_INFO_VALID_MASK 0x0000000000400000
|
||||
|
||||
#define RESPONSE_END_STATUS_RESERVED_2A_OFFSET 0x0000000000000008
|
||||
#define RESPONSE_END_STATUS_RESERVED_2A_LSB 23
|
||||
#define RESPONSE_END_STATUS_RESERVED_2A_MSB 31
|
||||
#define RESPONSE_END_STATUS_RESERVED_2A_MASK 0x00000000ff800000
|
||||
|
||||
#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_31_0_OFFSET 0x0000000000000008
|
||||
#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_31_0_LSB 32
|
||||
#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_31_0_MSB 63
|
||||
#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_31_0_MASK 0xffffffff00000000
|
||||
|
||||
#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_36_32_OFFSET 0x0000000000000010
|
||||
#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_36_32_LSB 0
|
||||
#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_36_32_MSB 4
|
||||
#define RESPONSE_END_STATUS_MU_RESPONSE_BITMAP_36_32_MASK 0x000000000000001f
|
||||
|
||||
#define RESPONSE_END_STATUS_RESERVED_4A_OFFSET 0x0000000000000010
|
||||
#define RESPONSE_END_STATUS_RESERVED_4A_LSB 5
|
||||
#define RESPONSE_END_STATUS_RESERVED_4A_MSB 15
|
||||
#define RESPONSE_END_STATUS_RESERVED_4A_MASK 0x000000000000ffe0
|
||||
|
||||
#define RESPONSE_END_STATUS_TRANSMIT_DELAY_OFFSET 0x0000000000000010
|
||||
#define RESPONSE_END_STATUS_TRANSMIT_DELAY_LSB 16
|
||||
#define RESPONSE_END_STATUS_TRANSMIT_DELAY_MSB 31
|
||||
#define RESPONSE_END_STATUS_TRANSMIT_DELAY_MASK 0x00000000ffff0000
|
||||
|
||||
#define RESPONSE_END_STATUS_START_OF_FRAME_TIMESTAMP_15_0_OFFSET 0x0000000000000010
|
||||
#define RESPONSE_END_STATUS_START_OF_FRAME_TIMESTAMP_15_0_LSB 32
|
||||
#define RESPONSE_END_STATUS_START_OF_FRAME_TIMESTAMP_15_0_MSB 47
|
||||
#define RESPONSE_END_STATUS_START_OF_FRAME_TIMESTAMP_15_0_MASK 0x0000ffff00000000
|
||||
|
||||
#define RESPONSE_END_STATUS_START_OF_FRAME_TIMESTAMP_31_16_OFFSET 0x0000000000000010
|
||||
#define RESPONSE_END_STATUS_START_OF_FRAME_TIMESTAMP_31_16_LSB 48
|
||||
#define RESPONSE_END_STATUS_START_OF_FRAME_TIMESTAMP_31_16_MSB 63
|
||||
#define RESPONSE_END_STATUS_START_OF_FRAME_TIMESTAMP_31_16_MASK 0xffff000000000000
|
||||
|
||||
#define RESPONSE_END_STATUS_END_OF_FRAME_TIMESTAMP_15_0_OFFSET 0x0000000000000018
|
||||
#define RESPONSE_END_STATUS_END_OF_FRAME_TIMESTAMP_15_0_LSB 0
|
||||
#define RESPONSE_END_STATUS_END_OF_FRAME_TIMESTAMP_15_0_MSB 15
|
||||
#define RESPONSE_END_STATUS_END_OF_FRAME_TIMESTAMP_15_0_MASK 0x000000000000ffff
|
||||
|
||||
#define RESPONSE_END_STATUS_END_OF_FRAME_TIMESTAMP_31_16_OFFSET 0x0000000000000018
|
||||
#define RESPONSE_END_STATUS_END_OF_FRAME_TIMESTAMP_31_16_LSB 16
|
||||
#define RESPONSE_END_STATUS_END_OF_FRAME_TIMESTAMP_31_16_MSB 31
|
||||
#define RESPONSE_END_STATUS_END_OF_FRAME_TIMESTAMP_31_16_MASK 0x00000000ffff0000
|
||||
|
||||
#define RESPONSE_END_STATUS_TX_GROUP_DELAY_OFFSET 0x0000000000000018
|
||||
#define RESPONSE_END_STATUS_TX_GROUP_DELAY_LSB 32
|
||||
#define RESPONSE_END_STATUS_TX_GROUP_DELAY_MSB 43
|
||||
#define RESPONSE_END_STATUS_TX_GROUP_DELAY_MASK 0x00000fff00000000
|
||||
|
||||
#define RESPONSE_END_STATUS_RESERVED_7A_OFFSET 0x0000000000000018
|
||||
#define RESPONSE_END_STATUS_RESERVED_7A_LSB 44
|
||||
#define RESPONSE_END_STATUS_RESERVED_7A_MSB 47
|
||||
#define RESPONSE_END_STATUS_RESERVED_7A_MASK 0x0000f00000000000
|
||||
|
||||
#define RESPONSE_END_STATUS_TPC_DBG_INFO_CMN_15_0_OFFSET 0x0000000000000018
|
||||
#define RESPONSE_END_STATUS_TPC_DBG_INFO_CMN_15_0_LSB 48
|
||||
#define RESPONSE_END_STATUS_TPC_DBG_INFO_CMN_15_0_MSB 63
|
||||
#define RESPONSE_END_STATUS_TPC_DBG_INFO_CMN_15_0_MASK 0xffff000000000000
|
||||
|
||||
#define RESPONSE_END_STATUS_TPC_DBG_INFO_31_16_OFFSET 0x0000000000000020
|
||||
#define RESPONSE_END_STATUS_TPC_DBG_INFO_31_16_LSB 0
|
||||
#define RESPONSE_END_STATUS_TPC_DBG_INFO_31_16_MSB 15
|
||||
#define RESPONSE_END_STATUS_TPC_DBG_INFO_31_16_MASK 0x000000000000ffff
|
||||
|
||||
#define RESPONSE_END_STATUS_TPC_DBG_INFO_47_32_OFFSET 0x0000000000000020
|
||||
#define RESPONSE_END_STATUS_TPC_DBG_INFO_47_32_LSB 16
|
||||
#define RESPONSE_END_STATUS_TPC_DBG_INFO_47_32_MSB 31
|
||||
#define RESPONSE_END_STATUS_TPC_DBG_INFO_47_32_MASK 0x00000000ffff0000
|
||||
|
||||
#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_15_0_OFFSET 0x0000000000000020
|
||||
#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_15_0_LSB 32
|
||||
#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_15_0_MSB 47
|
||||
#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_15_0_MASK 0x0000ffff00000000
|
||||
|
||||
#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_31_16_OFFSET 0x0000000000000020
|
||||
#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_31_16_LSB 48
|
||||
#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_31_16_MSB 63
|
||||
#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_31_16_MASK 0xffff000000000000
|
||||
|
||||
#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_47_32_OFFSET 0x0000000000000028
|
||||
#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_47_32_LSB 0
|
||||
#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_47_32_MSB 15
|
||||
#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_47_32_MASK 0x000000000000ffff
|
||||
|
||||
#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_63_48_OFFSET 0x0000000000000028
|
||||
#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_63_48_LSB 16
|
||||
#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_63_48_MSB 31
|
||||
#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_63_48_MASK 0x00000000ffff0000
|
||||
|
||||
#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_79_64_OFFSET 0x0000000000000028
|
||||
#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_79_64_LSB 32
|
||||
#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_79_64_MSB 47
|
||||
#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN1_79_64_MASK 0x0000ffff00000000
|
||||
|
||||
#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_15_0_OFFSET 0x0000000000000028
|
||||
#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_15_0_LSB 48
|
||||
#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_15_0_MSB 63
|
||||
#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_15_0_MASK 0xffff000000000000
|
||||
|
||||
#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_31_16_OFFSET 0x0000000000000030
|
||||
#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_31_16_LSB 0
|
||||
#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_31_16_MSB 15
|
||||
#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_31_16_MASK 0x000000000000ffff
|
||||
|
||||
#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_47_32_OFFSET 0x0000000000000030
|
||||
#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_47_32_LSB 16
|
||||
#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_47_32_MSB 31
|
||||
#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_47_32_MASK 0x00000000ffff0000
|
||||
|
||||
#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_63_48_OFFSET 0x0000000000000030
|
||||
#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_63_48_LSB 32
|
||||
#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_63_48_MSB 47
|
||||
#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_63_48_MASK 0x0000ffff00000000
|
||||
|
||||
#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_79_64_OFFSET 0x0000000000000030
|
||||
#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_79_64_LSB 48
|
||||
#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_79_64_MSB 63
|
||||
#define RESPONSE_END_STATUS_TPC_DBG_INFO_CHN2_79_64_MASK 0xffff000000000000
|
||||
|
||||
#define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_15_0_OFFSET 0x0000000000000038
|
||||
#define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_15_0_LSB 0
|
||||
#define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_15_0_MSB 15
|
||||
#define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_15_0_MASK 0x000000000000ffff
|
||||
|
||||
#define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_31_16_OFFSET 0x0000000000000038
|
||||
#define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_31_16_LSB 16
|
||||
#define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_31_16_MSB 31
|
||||
#define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_31_16_MASK 0x00000000ffff0000
|
||||
|
||||
#define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_47_32_OFFSET 0x0000000000000038
|
||||
#define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_47_32_LSB 32
|
||||
#define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_47_32_MSB 47
|
||||
#define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_47_32_MASK 0x0000ffff00000000
|
||||
|
||||
#define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_63_48_OFFSET 0x0000000000000038
|
||||
#define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_63_48_LSB 48
|
||||
#define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_63_48_MSB 63
|
||||
#define RESPONSE_END_STATUS_PHYTX_TX_END_SW_INFO_63_48_MASK 0xffff000000000000
|
||||
|
||||
#define RESPONSE_END_STATUS_ADDR1_31_0_OFFSET 0x0000000000000040
|
||||
#define RESPONSE_END_STATUS_ADDR1_31_0_LSB 0
|
||||
#define RESPONSE_END_STATUS_ADDR1_31_0_MSB 31
|
||||
#define RESPONSE_END_STATUS_ADDR1_31_0_MASK 0x00000000ffffffff
|
||||
|
||||
#define RESPONSE_END_STATUS_ADDR1_47_32_OFFSET 0x0000000000000040
|
||||
#define RESPONSE_END_STATUS_ADDR1_47_32_LSB 32
|
||||
#define RESPONSE_END_STATUS_ADDR1_47_32_MSB 47
|
||||
#define RESPONSE_END_STATUS_ADDR1_47_32_MASK 0x0000ffff00000000
|
||||
|
||||
#define RESPONSE_END_STATUS_ADDR2_15_0_OFFSET 0x0000000000000040
|
||||
#define RESPONSE_END_STATUS_ADDR2_15_0_LSB 48
|
||||
#define RESPONSE_END_STATUS_ADDR2_15_0_MSB 63
|
||||
#define RESPONSE_END_STATUS_ADDR2_15_0_MASK 0xffff000000000000
|
||||
|
||||
#define RESPONSE_END_STATUS_ADDR2_47_16_OFFSET 0x0000000000000048
|
||||
#define RESPONSE_END_STATUS_ADDR2_47_16_LSB 0
|
||||
#define RESPONSE_END_STATUS_ADDR2_47_16_MSB 31
|
||||
#define RESPONSE_END_STATUS_ADDR2_47_16_MASK 0x00000000ffffffff
|
||||
|
||||
#define RESPONSE_END_STATUS_ADDR3_31_0_OFFSET 0x0000000000000048
|
||||
#define RESPONSE_END_STATUS_ADDR3_31_0_LSB 32
|
||||
#define RESPONSE_END_STATUS_ADDR3_31_0_MSB 63
|
||||
#define RESPONSE_END_STATUS_ADDR3_31_0_MASK 0xffffffff00000000
|
||||
|
||||
#define RESPONSE_END_STATUS_ADDR3_47_32_OFFSET 0x0000000000000050
|
||||
#define RESPONSE_END_STATUS_ADDR3_47_32_LSB 0
|
||||
#define RESPONSE_END_STATUS_ADDR3_47_32_MSB 15
|
||||
#define RESPONSE_END_STATUS_ADDR3_47_32_MASK 0x000000000000ffff
|
||||
|
||||
#define RESPONSE_END_STATUS_SECURE_OFFSET 0x0000000000000050
|
||||
#define RESPONSE_END_STATUS_SECURE_LSB 17
|
||||
#define RESPONSE_END_STATUS_SECURE_MSB 17
|
||||
#define RESPONSE_END_STATUS_SECURE_MASK 0x0000000000020000
|
||||
|
||||
#define RESPONSE_END_STATUS_RANGING_FTM_FRAME_SENT_OFFSET 0x0000000000000050
|
||||
#define RESPONSE_END_STATUS_RANGING_FTM_FRAME_SENT_LSB 18
|
||||
#define RESPONSE_END_STATUS_RANGING_FTM_FRAME_SENT_MSB 18
|
||||
#define RESPONSE_END_STATUS_RANGING_FTM_FRAME_SENT_MASK 0x0000000000040000
|
||||
|
||||
#define RESPONSE_END_STATUS_RESERVED_20A_OFFSET 0x0000000000000050
|
||||
#define RESPONSE_END_STATUS_RESERVED_20A_LSB 19
|
||||
#define RESPONSE_END_STATUS_RESERVED_20A_MSB 31
|
||||
#define RESPONSE_END_STATUS_RESERVED_20A_MASK 0x00000000fff80000
|
||||
|
||||
#define RESPONSE_END_STATUS_TLV64_PADDING_OFFSET 0x0000000000000050
|
||||
#define RESPONSE_END_STATUS_TLV64_PADDING_LSB 32
|
||||
#define RESPONSE_END_STATUS_TLV64_PADDING_MSB 63
|
||||
#define RESPONSE_END_STATUS_TLV64_PADDING_MASK 0xffffffff00000000
|
||||
|
||||
#endif
|
||||
79
hw/kiwi/v2/response_start_status.h
Normal file
79
hw/kiwi/v2/response_start_status.h
Normal file
|
|
@ -0,0 +1,79 @@
|
|||
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
#ifndef _RESPONSE_START_STATUS_H_
|
||||
#define _RESPONSE_START_STATUS_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#define NUM_OF_DWORDS_RESPONSE_START_STATUS 2
|
||||
|
||||
#define NUM_OF_QWORDS_RESPONSE_START_STATUS 1
|
||||
|
||||
struct response_start_status {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t generated_response : 3,
|
||||
__reserved_g_0012 : 2,
|
||||
trig_response_related : 1,
|
||||
response_sta_count : 7,
|
||||
reserved : 19;
|
||||
uint32_t phy_ppdu_id : 16,
|
||||
sw_peer_id : 16;
|
||||
#else
|
||||
uint32_t reserved : 19,
|
||||
response_sta_count : 7,
|
||||
trig_response_related : 1,
|
||||
__reserved_g_0012 : 2,
|
||||
generated_response : 3;
|
||||
uint32_t sw_peer_id : 16,
|
||||
phy_ppdu_id : 16;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define RESPONSE_START_STATUS_GENERATED_RESPONSE_OFFSET 0x0000000000000000
|
||||
#define RESPONSE_START_STATUS_GENERATED_RESPONSE_LSB 0
|
||||
#define RESPONSE_START_STATUS_GENERATED_RESPONSE_MSB 2
|
||||
#define RESPONSE_START_STATUS_GENERATED_RESPONSE_MASK 0x0000000000000007
|
||||
|
||||
#define RESPONSE_START_STATUS_TRIG_RESPONSE_RELATED_OFFSET 0x0000000000000000
|
||||
#define RESPONSE_START_STATUS_TRIG_RESPONSE_RELATED_LSB 5
|
||||
#define RESPONSE_START_STATUS_TRIG_RESPONSE_RELATED_MSB 5
|
||||
#define RESPONSE_START_STATUS_TRIG_RESPONSE_RELATED_MASK 0x0000000000000020
|
||||
|
||||
#define RESPONSE_START_STATUS_RESPONSE_STA_COUNT_OFFSET 0x0000000000000000
|
||||
#define RESPONSE_START_STATUS_RESPONSE_STA_COUNT_LSB 6
|
||||
#define RESPONSE_START_STATUS_RESPONSE_STA_COUNT_MSB 12
|
||||
#define RESPONSE_START_STATUS_RESPONSE_STA_COUNT_MASK 0x0000000000001fc0
|
||||
|
||||
#define RESPONSE_START_STATUS_RESERVED_OFFSET 0x0000000000000000
|
||||
#define RESPONSE_START_STATUS_RESERVED_LSB 13
|
||||
#define RESPONSE_START_STATUS_RESERVED_MSB 31
|
||||
#define RESPONSE_START_STATUS_RESERVED_MASK 0x00000000ffffe000
|
||||
|
||||
#define RESPONSE_START_STATUS_PHY_PPDU_ID_OFFSET 0x0000000000000000
|
||||
#define RESPONSE_START_STATUS_PHY_PPDU_ID_LSB 32
|
||||
#define RESPONSE_START_STATUS_PHY_PPDU_ID_MSB 47
|
||||
#define RESPONSE_START_STATUS_PHY_PPDU_ID_MASK 0x0000ffff00000000
|
||||
|
||||
#define RESPONSE_START_STATUS_SW_PEER_ID_OFFSET 0x0000000000000000
|
||||
#define RESPONSE_START_STATUS_SW_PEER_ID_LSB 48
|
||||
#define RESPONSE_START_STATUS_SW_PEER_ID_MSB 63
|
||||
#define RESPONSE_START_STATUS_SW_PEER_ID_MASK 0xffff000000000000
|
||||
|
||||
#endif
|
||||
131
hw/kiwi/v2/ru_allocation_160_info.h
Normal file
131
hw/kiwi/v2/ru_allocation_160_info.h
Normal file
|
|
@ -0,0 +1,131 @@
|
|||
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
#ifndef _RU_ALLOCATION_160_INFO_H_
|
||||
#define _RU_ALLOCATION_160_INFO_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#define NUM_OF_DWORDS_RU_ALLOCATION_160_INFO 4
|
||||
|
||||
struct ru_allocation_160_info {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t ru_allocation_band0_0 : 9,
|
||||
ru_allocation_band0_1 : 9,
|
||||
reserved_0a : 6,
|
||||
ru_allocations_01_subband80_mask : 4,
|
||||
ru_allocations_23_subband80_mask : 4;
|
||||
uint32_t ru_allocation_band0_2 : 9,
|
||||
ru_allocation_band0_3 : 9,
|
||||
reserved_1a : 14;
|
||||
uint32_t ru_allocation_band1_0 : 9,
|
||||
ru_allocation_band1_1 : 9,
|
||||
reserved_2a : 14;
|
||||
uint32_t ru_allocation_band1_2 : 9,
|
||||
ru_allocation_band1_3 : 9,
|
||||
reserved_3a : 14;
|
||||
#else
|
||||
uint32_t ru_allocations_23_subband80_mask : 4,
|
||||
ru_allocations_01_subband80_mask : 4,
|
||||
reserved_0a : 6,
|
||||
ru_allocation_band0_1 : 9,
|
||||
ru_allocation_band0_0 : 9;
|
||||
uint32_t reserved_1a : 14,
|
||||
ru_allocation_band0_3 : 9,
|
||||
ru_allocation_band0_2 : 9;
|
||||
uint32_t reserved_2a : 14,
|
||||
ru_allocation_band1_1 : 9,
|
||||
ru_allocation_band1_0 : 9;
|
||||
uint32_t reserved_3a : 14,
|
||||
ru_allocation_band1_3 : 9,
|
||||
ru_allocation_band1_2 : 9;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_0_OFFSET 0x00000000
|
||||
#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_0_LSB 0
|
||||
#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_0_MSB 8
|
||||
#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_0_MASK 0x000001ff
|
||||
|
||||
#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_1_OFFSET 0x00000000
|
||||
#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_1_LSB 9
|
||||
#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_1_MSB 17
|
||||
#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_1_MASK 0x0003fe00
|
||||
|
||||
#define RU_ALLOCATION_160_INFO_RESERVED_0A_OFFSET 0x00000000
|
||||
#define RU_ALLOCATION_160_INFO_RESERVED_0A_LSB 18
|
||||
#define RU_ALLOCATION_160_INFO_RESERVED_0A_MSB 23
|
||||
#define RU_ALLOCATION_160_INFO_RESERVED_0A_MASK 0x00fc0000
|
||||
|
||||
#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_01_SUBBAND80_MASK_OFFSET 0x00000000
|
||||
#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_01_SUBBAND80_MASK_LSB 24
|
||||
#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_01_SUBBAND80_MASK_MSB 27
|
||||
#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_01_SUBBAND80_MASK_MASK 0x0f000000
|
||||
|
||||
#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_23_SUBBAND80_MASK_OFFSET 0x00000000
|
||||
#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_23_SUBBAND80_MASK_LSB 28
|
||||
#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_23_SUBBAND80_MASK_MSB 31
|
||||
#define RU_ALLOCATION_160_INFO_RU_ALLOCATIONS_23_SUBBAND80_MASK_MASK 0xf0000000
|
||||
|
||||
#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_2_OFFSET 0x00000004
|
||||
#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_2_LSB 0
|
||||
#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_2_MSB 8
|
||||
#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_2_MASK 0x000001ff
|
||||
|
||||
#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_3_OFFSET 0x00000004
|
||||
#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_3_LSB 9
|
||||
#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_3_MSB 17
|
||||
#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND0_3_MASK 0x0003fe00
|
||||
|
||||
#define RU_ALLOCATION_160_INFO_RESERVED_1A_OFFSET 0x00000004
|
||||
#define RU_ALLOCATION_160_INFO_RESERVED_1A_LSB 18
|
||||
#define RU_ALLOCATION_160_INFO_RESERVED_1A_MSB 31
|
||||
#define RU_ALLOCATION_160_INFO_RESERVED_1A_MASK 0xfffc0000
|
||||
|
||||
#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_0_OFFSET 0x00000008
|
||||
#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_0_LSB 0
|
||||
#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_0_MSB 8
|
||||
#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_0_MASK 0x000001ff
|
||||
|
||||
#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_1_OFFSET 0x00000008
|
||||
#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_1_LSB 9
|
||||
#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_1_MSB 17
|
||||
#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_1_MASK 0x0003fe00
|
||||
|
||||
#define RU_ALLOCATION_160_INFO_RESERVED_2A_OFFSET 0x00000008
|
||||
#define RU_ALLOCATION_160_INFO_RESERVED_2A_LSB 18
|
||||
#define RU_ALLOCATION_160_INFO_RESERVED_2A_MSB 31
|
||||
#define RU_ALLOCATION_160_INFO_RESERVED_2A_MASK 0xfffc0000
|
||||
|
||||
#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_2_OFFSET 0x0000000c
|
||||
#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_2_LSB 0
|
||||
#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_2_MSB 8
|
||||
#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_2_MASK 0x000001ff
|
||||
|
||||
#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_3_OFFSET 0x0000000c
|
||||
#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_3_LSB 9
|
||||
#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_3_MSB 17
|
||||
#define RU_ALLOCATION_160_INFO_RU_ALLOCATION_BAND1_3_MASK 0x0003fe00
|
||||
|
||||
#define RU_ALLOCATION_160_INFO_RESERVED_3A_OFFSET 0x0000000c
|
||||
#define RU_ALLOCATION_160_INFO_RESERVED_3A_LSB 18
|
||||
#define RU_ALLOCATION_160_INFO_RESERVED_3A_MSB 31
|
||||
#define RU_ALLOCATION_160_INFO_RESERVED_3A_MASK 0xfffc0000
|
||||
|
||||
#endif
|
||||
350
hw/kiwi/v2/rx_frame_1k_bitmap_ack.h
Normal file
350
hw/kiwi/v2/rx_frame_1k_bitmap_ack.h
Normal file
|
|
@ -0,0 +1,350 @@
|
|||
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
#ifndef _RX_FRAME_1K_BITMAP_ACK_H_
|
||||
#define _RX_FRAME_1K_BITMAP_ACK_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#define NUM_OF_DWORDS_RX_FRAME_1K_BITMAP_ACK 38
|
||||
|
||||
#define NUM_OF_QWORDS_RX_FRAME_1K_BITMAP_ACK 19
|
||||
|
||||
struct rx_frame_1k_bitmap_ack {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t reserved_0a : 5,
|
||||
ba_bitmap_size : 2,
|
||||
reserved_0b : 3,
|
||||
ba_tid : 4,
|
||||
sta_full_aid : 13,
|
||||
reserved_0c : 5;
|
||||
uint32_t addr1_31_0 : 32;
|
||||
uint32_t addr1_47_32 : 16,
|
||||
addr2_15_0 : 16;
|
||||
uint32_t addr2_47_16 : 32;
|
||||
uint32_t ba_ts_ctrl : 16,
|
||||
ba_ts_seq : 16;
|
||||
uint32_t ba_ts_bitmap_31_0 : 32;
|
||||
uint32_t ba_ts_bitmap_63_32 : 32;
|
||||
uint32_t ba_ts_bitmap_95_64 : 32;
|
||||
uint32_t ba_ts_bitmap_127_96 : 32;
|
||||
uint32_t ba_ts_bitmap_159_128 : 32;
|
||||
uint32_t ba_ts_bitmap_191_160 : 32;
|
||||
uint32_t ba_ts_bitmap_223_192 : 32;
|
||||
uint32_t ba_ts_bitmap_255_224 : 32;
|
||||
uint32_t ba_ts_bitmap_287_256 : 32;
|
||||
uint32_t ba_ts_bitmap_319_288 : 32;
|
||||
uint32_t ba_ts_bitmap_351_320 : 32;
|
||||
uint32_t ba_ts_bitmap_383_352 : 32;
|
||||
uint32_t ba_ts_bitmap_415_384 : 32;
|
||||
uint32_t ba_ts_bitmap_447_416 : 32;
|
||||
uint32_t ba_ts_bitmap_479_448 : 32;
|
||||
uint32_t ba_ts_bitmap_511_480 : 32;
|
||||
uint32_t ba_ts_bitmap_543_512 : 32;
|
||||
uint32_t ba_ts_bitmap_575_544 : 32;
|
||||
uint32_t ba_ts_bitmap_607_576 : 32;
|
||||
uint32_t ba_ts_bitmap_639_608 : 32;
|
||||
uint32_t ba_ts_bitmap_671_640 : 32;
|
||||
uint32_t ba_ts_bitmap_703_672 : 32;
|
||||
uint32_t ba_ts_bitmap_735_704 : 32;
|
||||
uint32_t ba_ts_bitmap_767_736 : 32;
|
||||
uint32_t ba_ts_bitmap_799_768 : 32;
|
||||
uint32_t ba_ts_bitmap_831_800 : 32;
|
||||
uint32_t ba_ts_bitmap_863_832 : 32;
|
||||
uint32_t ba_ts_bitmap_895_864 : 32;
|
||||
uint32_t ba_ts_bitmap_927_896 : 32;
|
||||
uint32_t ba_ts_bitmap_959_928 : 32;
|
||||
uint32_t ba_ts_bitmap_991_960 : 32;
|
||||
uint32_t ba_ts_bitmap_1023_992 : 32;
|
||||
uint32_t tlv64_padding : 32;
|
||||
#else
|
||||
uint32_t reserved_0c : 5,
|
||||
sta_full_aid : 13,
|
||||
ba_tid : 4,
|
||||
reserved_0b : 3,
|
||||
ba_bitmap_size : 2,
|
||||
reserved_0a : 5;
|
||||
uint32_t addr1_31_0 : 32;
|
||||
uint32_t addr2_15_0 : 16,
|
||||
addr1_47_32 : 16;
|
||||
uint32_t addr2_47_16 : 32;
|
||||
uint32_t ba_ts_seq : 16,
|
||||
ba_ts_ctrl : 16;
|
||||
uint32_t ba_ts_bitmap_31_0 : 32;
|
||||
uint32_t ba_ts_bitmap_63_32 : 32;
|
||||
uint32_t ba_ts_bitmap_95_64 : 32;
|
||||
uint32_t ba_ts_bitmap_127_96 : 32;
|
||||
uint32_t ba_ts_bitmap_159_128 : 32;
|
||||
uint32_t ba_ts_bitmap_191_160 : 32;
|
||||
uint32_t ba_ts_bitmap_223_192 : 32;
|
||||
uint32_t ba_ts_bitmap_255_224 : 32;
|
||||
uint32_t ba_ts_bitmap_287_256 : 32;
|
||||
uint32_t ba_ts_bitmap_319_288 : 32;
|
||||
uint32_t ba_ts_bitmap_351_320 : 32;
|
||||
uint32_t ba_ts_bitmap_383_352 : 32;
|
||||
uint32_t ba_ts_bitmap_415_384 : 32;
|
||||
uint32_t ba_ts_bitmap_447_416 : 32;
|
||||
uint32_t ba_ts_bitmap_479_448 : 32;
|
||||
uint32_t ba_ts_bitmap_511_480 : 32;
|
||||
uint32_t ba_ts_bitmap_543_512 : 32;
|
||||
uint32_t ba_ts_bitmap_575_544 : 32;
|
||||
uint32_t ba_ts_bitmap_607_576 : 32;
|
||||
uint32_t ba_ts_bitmap_639_608 : 32;
|
||||
uint32_t ba_ts_bitmap_671_640 : 32;
|
||||
uint32_t ba_ts_bitmap_703_672 : 32;
|
||||
uint32_t ba_ts_bitmap_735_704 : 32;
|
||||
uint32_t ba_ts_bitmap_767_736 : 32;
|
||||
uint32_t ba_ts_bitmap_799_768 : 32;
|
||||
uint32_t ba_ts_bitmap_831_800 : 32;
|
||||
uint32_t ba_ts_bitmap_863_832 : 32;
|
||||
uint32_t ba_ts_bitmap_895_864 : 32;
|
||||
uint32_t ba_ts_bitmap_927_896 : 32;
|
||||
uint32_t ba_ts_bitmap_959_928 : 32;
|
||||
uint32_t ba_ts_bitmap_991_960 : 32;
|
||||
uint32_t ba_ts_bitmap_1023_992 : 32;
|
||||
uint32_t tlv64_padding : 32;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0A_OFFSET 0x0000000000000000
|
||||
#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0A_LSB 0
|
||||
#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0A_MSB 4
|
||||
#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0A_MASK 0x000000000000001f
|
||||
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_BITMAP_SIZE_OFFSET 0x0000000000000000
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_BITMAP_SIZE_LSB 5
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_BITMAP_SIZE_MSB 6
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_BITMAP_SIZE_MASK 0x0000000000000060
|
||||
|
||||
#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0B_OFFSET 0x0000000000000000
|
||||
#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0B_LSB 7
|
||||
#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0B_MSB 9
|
||||
#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0B_MASK 0x0000000000000380
|
||||
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TID_OFFSET 0x0000000000000000
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TID_LSB 10
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TID_MSB 13
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TID_MASK 0x0000000000003c00
|
||||
|
||||
#define RX_FRAME_1K_BITMAP_ACK_STA_FULL_AID_OFFSET 0x0000000000000000
|
||||
#define RX_FRAME_1K_BITMAP_ACK_STA_FULL_AID_LSB 14
|
||||
#define RX_FRAME_1K_BITMAP_ACK_STA_FULL_AID_MSB 26
|
||||
#define RX_FRAME_1K_BITMAP_ACK_STA_FULL_AID_MASK 0x0000000007ffc000
|
||||
|
||||
#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0C_OFFSET 0x0000000000000000
|
||||
#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0C_LSB 27
|
||||
#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0C_MSB 31
|
||||
#define RX_FRAME_1K_BITMAP_ACK_RESERVED_0C_MASK 0x00000000f8000000
|
||||
|
||||
#define RX_FRAME_1K_BITMAP_ACK_ADDR1_31_0_OFFSET 0x0000000000000000
|
||||
#define RX_FRAME_1K_BITMAP_ACK_ADDR1_31_0_LSB 32
|
||||
#define RX_FRAME_1K_BITMAP_ACK_ADDR1_31_0_MSB 63
|
||||
#define RX_FRAME_1K_BITMAP_ACK_ADDR1_31_0_MASK 0xffffffff00000000
|
||||
|
||||
#define RX_FRAME_1K_BITMAP_ACK_ADDR1_47_32_OFFSET 0x0000000000000008
|
||||
#define RX_FRAME_1K_BITMAP_ACK_ADDR1_47_32_LSB 0
|
||||
#define RX_FRAME_1K_BITMAP_ACK_ADDR1_47_32_MSB 15
|
||||
#define RX_FRAME_1K_BITMAP_ACK_ADDR1_47_32_MASK 0x000000000000ffff
|
||||
|
||||
#define RX_FRAME_1K_BITMAP_ACK_ADDR2_15_0_OFFSET 0x0000000000000008
|
||||
#define RX_FRAME_1K_BITMAP_ACK_ADDR2_15_0_LSB 16
|
||||
#define RX_FRAME_1K_BITMAP_ACK_ADDR2_15_0_MSB 31
|
||||
#define RX_FRAME_1K_BITMAP_ACK_ADDR2_15_0_MASK 0x00000000ffff0000
|
||||
|
||||
#define RX_FRAME_1K_BITMAP_ACK_ADDR2_47_16_OFFSET 0x0000000000000008
|
||||
#define RX_FRAME_1K_BITMAP_ACK_ADDR2_47_16_LSB 32
|
||||
#define RX_FRAME_1K_BITMAP_ACK_ADDR2_47_16_MSB 63
|
||||
#define RX_FRAME_1K_BITMAP_ACK_ADDR2_47_16_MASK 0xffffffff00000000
|
||||
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_CTRL_OFFSET 0x0000000000000010
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_CTRL_LSB 0
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_CTRL_MSB 15
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_CTRL_MASK 0x000000000000ffff
|
||||
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_SEQ_OFFSET 0x0000000000000010
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_SEQ_LSB 16
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_SEQ_MSB 31
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_SEQ_MASK 0x00000000ffff0000
|
||||
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_31_0_OFFSET 0x0000000000000010
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_31_0_LSB 32
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_31_0_MSB 63
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_31_0_MASK 0xffffffff00000000
|
||||
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_63_32_OFFSET 0x0000000000000018
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_63_32_LSB 0
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_63_32_MSB 31
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_63_32_MASK 0x00000000ffffffff
|
||||
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_95_64_OFFSET 0x0000000000000018
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_95_64_LSB 32
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_95_64_MSB 63
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_95_64_MASK 0xffffffff00000000
|
||||
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_127_96_OFFSET 0x0000000000000020
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_127_96_LSB 0
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_127_96_MSB 31
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_127_96_MASK 0x00000000ffffffff
|
||||
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_159_128_OFFSET 0x0000000000000020
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_159_128_LSB 32
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_159_128_MSB 63
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_159_128_MASK 0xffffffff00000000
|
||||
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_191_160_OFFSET 0x0000000000000028
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_191_160_LSB 0
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_191_160_MSB 31
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_191_160_MASK 0x00000000ffffffff
|
||||
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_223_192_OFFSET 0x0000000000000028
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_223_192_LSB 32
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_223_192_MSB 63
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_223_192_MASK 0xffffffff00000000
|
||||
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_255_224_OFFSET 0x0000000000000030
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_255_224_LSB 0
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_255_224_MSB 31
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_255_224_MASK 0x00000000ffffffff
|
||||
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_287_256_OFFSET 0x0000000000000030
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_287_256_LSB 32
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_287_256_MSB 63
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_287_256_MASK 0xffffffff00000000
|
||||
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_319_288_OFFSET 0x0000000000000038
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_319_288_LSB 0
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_319_288_MSB 31
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_319_288_MASK 0x00000000ffffffff
|
||||
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_351_320_OFFSET 0x0000000000000038
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_351_320_LSB 32
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_351_320_MSB 63
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_351_320_MASK 0xffffffff00000000
|
||||
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_383_352_OFFSET 0x0000000000000040
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_383_352_LSB 0
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_383_352_MSB 31
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_383_352_MASK 0x00000000ffffffff
|
||||
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_415_384_OFFSET 0x0000000000000040
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_415_384_LSB 32
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_415_384_MSB 63
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_415_384_MASK 0xffffffff00000000
|
||||
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_447_416_OFFSET 0x0000000000000048
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_447_416_LSB 0
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_447_416_MSB 31
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_447_416_MASK 0x00000000ffffffff
|
||||
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_479_448_OFFSET 0x0000000000000048
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_479_448_LSB 32
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_479_448_MSB 63
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_479_448_MASK 0xffffffff00000000
|
||||
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_511_480_OFFSET 0x0000000000000050
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_511_480_LSB 0
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_511_480_MSB 31
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_511_480_MASK 0x00000000ffffffff
|
||||
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_543_512_OFFSET 0x0000000000000050
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_543_512_LSB 32
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_543_512_MSB 63
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_543_512_MASK 0xffffffff00000000
|
||||
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_575_544_OFFSET 0x0000000000000058
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_575_544_LSB 0
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_575_544_MSB 31
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_575_544_MASK 0x00000000ffffffff
|
||||
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_607_576_OFFSET 0x0000000000000058
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_607_576_LSB 32
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_607_576_MSB 63
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_607_576_MASK 0xffffffff00000000
|
||||
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_639_608_OFFSET 0x0000000000000060
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_639_608_LSB 0
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_639_608_MSB 31
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_639_608_MASK 0x00000000ffffffff
|
||||
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_671_640_OFFSET 0x0000000000000060
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_671_640_LSB 32
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_671_640_MSB 63
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_671_640_MASK 0xffffffff00000000
|
||||
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_703_672_OFFSET 0x0000000000000068
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_703_672_LSB 0
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_703_672_MSB 31
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_703_672_MASK 0x00000000ffffffff
|
||||
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_735_704_OFFSET 0x0000000000000068
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_735_704_LSB 32
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_735_704_MSB 63
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_735_704_MASK 0xffffffff00000000
|
||||
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_767_736_OFFSET 0x0000000000000070
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_767_736_LSB 0
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_767_736_MSB 31
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_767_736_MASK 0x00000000ffffffff
|
||||
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_799_768_OFFSET 0x0000000000000070
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_799_768_LSB 32
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_799_768_MSB 63
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_799_768_MASK 0xffffffff00000000
|
||||
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_831_800_OFFSET 0x0000000000000078
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_831_800_LSB 0
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_831_800_MSB 31
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_831_800_MASK 0x00000000ffffffff
|
||||
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_863_832_OFFSET 0x0000000000000078
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_863_832_LSB 32
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_863_832_MSB 63
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_863_832_MASK 0xffffffff00000000
|
||||
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_895_864_OFFSET 0x0000000000000080
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_895_864_LSB 0
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_895_864_MSB 31
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_895_864_MASK 0x00000000ffffffff
|
||||
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_927_896_OFFSET 0x0000000000000080
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_927_896_LSB 32
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_927_896_MSB 63
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_927_896_MASK 0xffffffff00000000
|
||||
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_959_928_OFFSET 0x0000000000000088
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_959_928_LSB 0
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_959_928_MSB 31
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_959_928_MASK 0x00000000ffffffff
|
||||
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_991_960_OFFSET 0x0000000000000088
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_991_960_LSB 32
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_991_960_MSB 63
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_991_960_MASK 0xffffffff00000000
|
||||
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_1023_992_OFFSET 0x0000000000000090
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_1023_992_LSB 0
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_1023_992_MSB 31
|
||||
#define RX_FRAME_1K_BITMAP_ACK_BA_TS_BITMAP_1023_992_MASK 0x00000000ffffffff
|
||||
|
||||
#define RX_FRAME_1K_BITMAP_ACK_TLV64_PADDING_OFFSET 0x0000000000000090
|
||||
#define RX_FRAME_1K_BITMAP_ACK_TLV64_PADDING_LSB 32
|
||||
#define RX_FRAME_1K_BITMAP_ACK_TLV64_PADDING_MSB 63
|
||||
#define RX_FRAME_1K_BITMAP_ACK_TLV64_PADDING_MASK 0xffffffff00000000
|
||||
|
||||
#endif
|
||||
196
hw/kiwi/v2/rx_frame_bitmap_ack.h
Normal file
196
hw/kiwi/v2/rx_frame_bitmap_ack.h
Normal file
|
|
@ -0,0 +1,196 @@
|
|||
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
#ifndef _RX_FRAME_BITMAP_ACK_H_
|
||||
#define _RX_FRAME_BITMAP_ACK_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#define NUM_OF_DWORDS_RX_FRAME_BITMAP_ACK 14
|
||||
|
||||
#define NUM_OF_QWORDS_RX_FRAME_BITMAP_ACK 7
|
||||
|
||||
struct rx_frame_bitmap_ack {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t no_bitmap_available : 1,
|
||||
explicit_ack : 1,
|
||||
explict_ack_type : 3,
|
||||
ba_bitmap_size : 2,
|
||||
reserved_0a : 3,
|
||||
ba_tid : 4,
|
||||
sta_full_aid : 13,
|
||||
reserved_0b : 5;
|
||||
uint32_t addr1_31_0 : 32;
|
||||
uint32_t addr1_47_32 : 16,
|
||||
addr2_15_0 : 16;
|
||||
uint32_t addr2_47_16 : 32;
|
||||
uint32_t ba_ts_ctrl : 16,
|
||||
ba_ts_seq : 16;
|
||||
uint32_t ba_ts_bitmap_31_0 : 32;
|
||||
uint32_t ba_ts_bitmap_63_32 : 32;
|
||||
uint32_t ba_ts_bitmap_95_64 : 32;
|
||||
uint32_t ba_ts_bitmap_127_96 : 32;
|
||||
uint32_t ba_ts_bitmap_159_128 : 32;
|
||||
uint32_t ba_ts_bitmap_191_160 : 32;
|
||||
uint32_t ba_ts_bitmap_223_192 : 32;
|
||||
uint32_t ba_ts_bitmap_255_224 : 32;
|
||||
uint32_t tlv64_padding : 32;
|
||||
#else
|
||||
uint32_t reserved_0b : 5,
|
||||
sta_full_aid : 13,
|
||||
ba_tid : 4,
|
||||
reserved_0a : 3,
|
||||
ba_bitmap_size : 2,
|
||||
explict_ack_type : 3,
|
||||
explicit_ack : 1,
|
||||
no_bitmap_available : 1;
|
||||
uint32_t addr1_31_0 : 32;
|
||||
uint32_t addr2_15_0 : 16,
|
||||
addr1_47_32 : 16;
|
||||
uint32_t addr2_47_16 : 32;
|
||||
uint32_t ba_ts_seq : 16,
|
||||
ba_ts_ctrl : 16;
|
||||
uint32_t ba_ts_bitmap_31_0 : 32;
|
||||
uint32_t ba_ts_bitmap_63_32 : 32;
|
||||
uint32_t ba_ts_bitmap_95_64 : 32;
|
||||
uint32_t ba_ts_bitmap_127_96 : 32;
|
||||
uint32_t ba_ts_bitmap_159_128 : 32;
|
||||
uint32_t ba_ts_bitmap_191_160 : 32;
|
||||
uint32_t ba_ts_bitmap_223_192 : 32;
|
||||
uint32_t ba_ts_bitmap_255_224 : 32;
|
||||
uint32_t tlv64_padding : 32;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define RX_FRAME_BITMAP_ACK_NO_BITMAP_AVAILABLE_OFFSET 0x0000000000000000
|
||||
#define RX_FRAME_BITMAP_ACK_NO_BITMAP_AVAILABLE_LSB 0
|
||||
#define RX_FRAME_BITMAP_ACK_NO_BITMAP_AVAILABLE_MSB 0
|
||||
#define RX_FRAME_BITMAP_ACK_NO_BITMAP_AVAILABLE_MASK 0x0000000000000001
|
||||
|
||||
#define RX_FRAME_BITMAP_ACK_EXPLICIT_ACK_OFFSET 0x0000000000000000
|
||||
#define RX_FRAME_BITMAP_ACK_EXPLICIT_ACK_LSB 1
|
||||
#define RX_FRAME_BITMAP_ACK_EXPLICIT_ACK_MSB 1
|
||||
#define RX_FRAME_BITMAP_ACK_EXPLICIT_ACK_MASK 0x0000000000000002
|
||||
|
||||
#define RX_FRAME_BITMAP_ACK_EXPLICT_ACK_TYPE_OFFSET 0x0000000000000000
|
||||
#define RX_FRAME_BITMAP_ACK_EXPLICT_ACK_TYPE_LSB 2
|
||||
#define RX_FRAME_BITMAP_ACK_EXPLICT_ACK_TYPE_MSB 4
|
||||
#define RX_FRAME_BITMAP_ACK_EXPLICT_ACK_TYPE_MASK 0x000000000000001c
|
||||
|
||||
#define RX_FRAME_BITMAP_ACK_BA_BITMAP_SIZE_OFFSET 0x0000000000000000
|
||||
#define RX_FRAME_BITMAP_ACK_BA_BITMAP_SIZE_LSB 5
|
||||
#define RX_FRAME_BITMAP_ACK_BA_BITMAP_SIZE_MSB 6
|
||||
#define RX_FRAME_BITMAP_ACK_BA_BITMAP_SIZE_MASK 0x0000000000000060
|
||||
|
||||
#define RX_FRAME_BITMAP_ACK_RESERVED_0A_OFFSET 0x0000000000000000
|
||||
#define RX_FRAME_BITMAP_ACK_RESERVED_0A_LSB 7
|
||||
#define RX_FRAME_BITMAP_ACK_RESERVED_0A_MSB 9
|
||||
#define RX_FRAME_BITMAP_ACK_RESERVED_0A_MASK 0x0000000000000380
|
||||
|
||||
#define RX_FRAME_BITMAP_ACK_BA_TID_OFFSET 0x0000000000000000
|
||||
#define RX_FRAME_BITMAP_ACK_BA_TID_LSB 10
|
||||
#define RX_FRAME_BITMAP_ACK_BA_TID_MSB 13
|
||||
#define RX_FRAME_BITMAP_ACK_BA_TID_MASK 0x0000000000003c00
|
||||
|
||||
#define RX_FRAME_BITMAP_ACK_STA_FULL_AID_OFFSET 0x0000000000000000
|
||||
#define RX_FRAME_BITMAP_ACK_STA_FULL_AID_LSB 14
|
||||
#define RX_FRAME_BITMAP_ACK_STA_FULL_AID_MSB 26
|
||||
#define RX_FRAME_BITMAP_ACK_STA_FULL_AID_MASK 0x0000000007ffc000
|
||||
|
||||
#define RX_FRAME_BITMAP_ACK_RESERVED_0B_OFFSET 0x0000000000000000
|
||||
#define RX_FRAME_BITMAP_ACK_RESERVED_0B_LSB 27
|
||||
#define RX_FRAME_BITMAP_ACK_RESERVED_0B_MSB 31
|
||||
#define RX_FRAME_BITMAP_ACK_RESERVED_0B_MASK 0x00000000f8000000
|
||||
|
||||
#define RX_FRAME_BITMAP_ACK_ADDR1_31_0_OFFSET 0x0000000000000000
|
||||
#define RX_FRAME_BITMAP_ACK_ADDR1_31_0_LSB 32
|
||||
#define RX_FRAME_BITMAP_ACK_ADDR1_31_0_MSB 63
|
||||
#define RX_FRAME_BITMAP_ACK_ADDR1_31_0_MASK 0xffffffff00000000
|
||||
|
||||
#define RX_FRAME_BITMAP_ACK_ADDR1_47_32_OFFSET 0x0000000000000008
|
||||
#define RX_FRAME_BITMAP_ACK_ADDR1_47_32_LSB 0
|
||||
#define RX_FRAME_BITMAP_ACK_ADDR1_47_32_MSB 15
|
||||
#define RX_FRAME_BITMAP_ACK_ADDR1_47_32_MASK 0x000000000000ffff
|
||||
|
||||
#define RX_FRAME_BITMAP_ACK_ADDR2_15_0_OFFSET 0x0000000000000008
|
||||
#define RX_FRAME_BITMAP_ACK_ADDR2_15_0_LSB 16
|
||||
#define RX_FRAME_BITMAP_ACK_ADDR2_15_0_MSB 31
|
||||
#define RX_FRAME_BITMAP_ACK_ADDR2_15_0_MASK 0x00000000ffff0000
|
||||
|
||||
#define RX_FRAME_BITMAP_ACK_ADDR2_47_16_OFFSET 0x0000000000000008
|
||||
#define RX_FRAME_BITMAP_ACK_ADDR2_47_16_LSB 32
|
||||
#define RX_FRAME_BITMAP_ACK_ADDR2_47_16_MSB 63
|
||||
#define RX_FRAME_BITMAP_ACK_ADDR2_47_16_MASK 0xffffffff00000000
|
||||
|
||||
#define RX_FRAME_BITMAP_ACK_BA_TS_CTRL_OFFSET 0x0000000000000010
|
||||
#define RX_FRAME_BITMAP_ACK_BA_TS_CTRL_LSB 0
|
||||
#define RX_FRAME_BITMAP_ACK_BA_TS_CTRL_MSB 15
|
||||
#define RX_FRAME_BITMAP_ACK_BA_TS_CTRL_MASK 0x000000000000ffff
|
||||
|
||||
#define RX_FRAME_BITMAP_ACK_BA_TS_SEQ_OFFSET 0x0000000000000010
|
||||
#define RX_FRAME_BITMAP_ACK_BA_TS_SEQ_LSB 16
|
||||
#define RX_FRAME_BITMAP_ACK_BA_TS_SEQ_MSB 31
|
||||
#define RX_FRAME_BITMAP_ACK_BA_TS_SEQ_MASK 0x00000000ffff0000
|
||||
|
||||
#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_31_0_OFFSET 0x0000000000000010
|
||||
#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_31_0_LSB 32
|
||||
#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_31_0_MSB 63
|
||||
#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_31_0_MASK 0xffffffff00000000
|
||||
|
||||
#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_63_32_OFFSET 0x0000000000000018
|
||||
#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_63_32_LSB 0
|
||||
#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_63_32_MSB 31
|
||||
#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_63_32_MASK 0x00000000ffffffff
|
||||
|
||||
#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_95_64_OFFSET 0x0000000000000018
|
||||
#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_95_64_LSB 32
|
||||
#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_95_64_MSB 63
|
||||
#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_95_64_MASK 0xffffffff00000000
|
||||
|
||||
#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_127_96_OFFSET 0x0000000000000020
|
||||
#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_127_96_LSB 0
|
||||
#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_127_96_MSB 31
|
||||
#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_127_96_MASK 0x00000000ffffffff
|
||||
|
||||
#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_159_128_OFFSET 0x0000000000000020
|
||||
#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_159_128_LSB 32
|
||||
#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_159_128_MSB 63
|
||||
#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_159_128_MASK 0xffffffff00000000
|
||||
|
||||
#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_191_160_OFFSET 0x0000000000000028
|
||||
#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_191_160_LSB 0
|
||||
#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_191_160_MSB 31
|
||||
#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_191_160_MASK 0x00000000ffffffff
|
||||
|
||||
#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_223_192_OFFSET 0x0000000000000028
|
||||
#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_223_192_LSB 32
|
||||
#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_223_192_MSB 63
|
||||
#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_223_192_MASK 0xffffffff00000000
|
||||
|
||||
#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_255_224_OFFSET 0x0000000000000030
|
||||
#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_255_224_LSB 0
|
||||
#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_255_224_MSB 31
|
||||
#define RX_FRAME_BITMAP_ACK_BA_TS_BITMAP_255_224_MASK 0x00000000ffffffff
|
||||
|
||||
#define RX_FRAME_BITMAP_ACK_TLV64_PADDING_OFFSET 0x0000000000000030
|
||||
#define RX_FRAME_BITMAP_ACK_TLV64_PADDING_LSB 32
|
||||
#define RX_FRAME_BITMAP_ACK_TLV64_PADDING_MSB 63
|
||||
#define RX_FRAME_BITMAP_ACK_TLV64_PADDING_MASK 0xffffffff00000000
|
||||
|
||||
#endif
|
||||
91
hw/kiwi/v2/rx_frame_bitmap_req.h
Normal file
91
hw/kiwi/v2/rx_frame_bitmap_req.h
Normal file
|
|
@ -0,0 +1,91 @@
|
|||
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
#ifndef _RX_FRAME_BITMAP_REQ_H_
|
||||
#define _RX_FRAME_BITMAP_REQ_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#define NUM_OF_DWORDS_RX_FRAME_BITMAP_REQ 2
|
||||
|
||||
#define NUM_OF_QWORDS_RX_FRAME_BITMAP_REQ 1
|
||||
|
||||
struct rx_frame_bitmap_req {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t explicit_user_request : 1,
|
||||
user_request_type : 1,
|
||||
user_number : 6,
|
||||
sw_peer_id : 16,
|
||||
tid_specific_request : 1,
|
||||
requested_tid : 4,
|
||||
reserved_0 : 3;
|
||||
uint32_t tlv64_padding : 32;
|
||||
#else
|
||||
uint32_t reserved_0 : 3,
|
||||
requested_tid : 4,
|
||||
tid_specific_request : 1,
|
||||
sw_peer_id : 16,
|
||||
user_number : 6,
|
||||
user_request_type : 1,
|
||||
explicit_user_request : 1;
|
||||
uint32_t tlv64_padding : 32;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define RX_FRAME_BITMAP_REQ_EXPLICIT_USER_REQUEST_OFFSET 0x0000000000000000
|
||||
#define RX_FRAME_BITMAP_REQ_EXPLICIT_USER_REQUEST_LSB 0
|
||||
#define RX_FRAME_BITMAP_REQ_EXPLICIT_USER_REQUEST_MSB 0
|
||||
#define RX_FRAME_BITMAP_REQ_EXPLICIT_USER_REQUEST_MASK 0x0000000000000001
|
||||
|
||||
#define RX_FRAME_BITMAP_REQ_USER_REQUEST_TYPE_OFFSET 0x0000000000000000
|
||||
#define RX_FRAME_BITMAP_REQ_USER_REQUEST_TYPE_LSB 1
|
||||
#define RX_FRAME_BITMAP_REQ_USER_REQUEST_TYPE_MSB 1
|
||||
#define RX_FRAME_BITMAP_REQ_USER_REQUEST_TYPE_MASK 0x0000000000000002
|
||||
|
||||
#define RX_FRAME_BITMAP_REQ_USER_NUMBER_OFFSET 0x0000000000000000
|
||||
#define RX_FRAME_BITMAP_REQ_USER_NUMBER_LSB 2
|
||||
#define RX_FRAME_BITMAP_REQ_USER_NUMBER_MSB 7
|
||||
#define RX_FRAME_BITMAP_REQ_USER_NUMBER_MASK 0x00000000000000fc
|
||||
|
||||
#define RX_FRAME_BITMAP_REQ_SW_PEER_ID_OFFSET 0x0000000000000000
|
||||
#define RX_FRAME_BITMAP_REQ_SW_PEER_ID_LSB 8
|
||||
#define RX_FRAME_BITMAP_REQ_SW_PEER_ID_MSB 23
|
||||
#define RX_FRAME_BITMAP_REQ_SW_PEER_ID_MASK 0x0000000000ffff00
|
||||
|
||||
#define RX_FRAME_BITMAP_REQ_TID_SPECIFIC_REQUEST_OFFSET 0x0000000000000000
|
||||
#define RX_FRAME_BITMAP_REQ_TID_SPECIFIC_REQUEST_LSB 24
|
||||
#define RX_FRAME_BITMAP_REQ_TID_SPECIFIC_REQUEST_MSB 24
|
||||
#define RX_FRAME_BITMAP_REQ_TID_SPECIFIC_REQUEST_MASK 0x0000000001000000
|
||||
|
||||
#define RX_FRAME_BITMAP_REQ_REQUESTED_TID_OFFSET 0x0000000000000000
|
||||
#define RX_FRAME_BITMAP_REQ_REQUESTED_TID_LSB 25
|
||||
#define RX_FRAME_BITMAP_REQ_REQUESTED_TID_MSB 28
|
||||
#define RX_FRAME_BITMAP_REQ_REQUESTED_TID_MASK 0x000000001e000000
|
||||
|
||||
#define RX_FRAME_BITMAP_REQ_RESERVED_0_OFFSET 0x0000000000000000
|
||||
#define RX_FRAME_BITMAP_REQ_RESERVED_0_LSB 29
|
||||
#define RX_FRAME_BITMAP_REQ_RESERVED_0_MSB 31
|
||||
#define RX_FRAME_BITMAP_REQ_RESERVED_0_MASK 0x00000000e0000000
|
||||
|
||||
#define RX_FRAME_BITMAP_REQ_TLV64_PADDING_OFFSET 0x0000000000000000
|
||||
#define RX_FRAME_BITMAP_REQ_TLV64_PADDING_LSB 32
|
||||
#define RX_FRAME_BITMAP_REQ_TLV64_PADDING_MSB 63
|
||||
#define RX_FRAME_BITMAP_REQ_TLV64_PADDING_MASK 0xffffffff00000000
|
||||
|
||||
#endif
|
||||
70
hw/kiwi/v2/rx_ppdu_ack_report.h
Normal file
70
hw/kiwi/v2/rx_ppdu_ack_report.h
Normal file
|
|
@ -0,0 +1,70 @@
|
|||
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
#ifndef _RX_PPDU_ACK_REPORT_H_
|
||||
#define _RX_PPDU_ACK_REPORT_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#include "ack_report.h"
|
||||
#define NUM_OF_DWORDS_RX_PPDU_ACK_REPORT 2
|
||||
|
||||
#define NUM_OF_QWORDS_RX_PPDU_ACK_REPORT 1
|
||||
|
||||
struct rx_ppdu_ack_report {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
struct ack_report ack_report_details;
|
||||
uint32_t tlv64_padding : 32;
|
||||
#else
|
||||
struct ack_report ack_report_details;
|
||||
uint32_t tlv64_padding : 32;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_OFFSET 0x0000000000000000
|
||||
#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_LSB 0
|
||||
#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_MSB 3
|
||||
#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_MASK 0x000000000000000f
|
||||
|
||||
#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_AX_TRIGGER_TYPE_OFFSET 0x0000000000000000
|
||||
#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_AX_TRIGGER_TYPE_LSB 4
|
||||
#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_AX_TRIGGER_TYPE_MSB 7
|
||||
#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_AX_TRIGGER_TYPE_MASK 0x00000000000000f0
|
||||
|
||||
#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SR_PPDU_OFFSET 0x0000000000000000
|
||||
#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SR_PPDU_LSB 8
|
||||
#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SR_PPDU_MSB 8
|
||||
#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_SR_PPDU_MASK 0x0000000000000100
|
||||
|
||||
#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_RESERVED_OFFSET 0x0000000000000000
|
||||
#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_RESERVED_LSB 9
|
||||
#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_RESERVED_MSB 15
|
||||
#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_RESERVED_MASK 0x000000000000fe00
|
||||
|
||||
#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_FRAME_CONTROL_OFFSET 0x0000000000000000
|
||||
#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_FRAME_CONTROL_LSB 16
|
||||
#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_FRAME_CONTROL_MSB 31
|
||||
#define RX_PPDU_ACK_REPORT_ACK_REPORT_DETAILS_FRAME_CONTROL_MASK 0x00000000ffff0000
|
||||
|
||||
#define RX_PPDU_ACK_REPORT_TLV64_PADDING_OFFSET 0x0000000000000000
|
||||
#define RX_PPDU_ACK_REPORT_TLV64_PADDING_LSB 32
|
||||
#define RX_PPDU_ACK_REPORT_TLV64_PADDING_MSB 63
|
||||
#define RX_PPDU_ACK_REPORT_TLV64_PADDING_MASK 0xffffffff00000000
|
||||
|
||||
#endif
|
||||
103
hw/kiwi/v2/rx_ppdu_no_ack_report.h
Normal file
103
hw/kiwi/v2/rx_ppdu_no_ack_report.h
Normal file
|
|
@ -0,0 +1,103 @@
|
|||
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
#ifndef _RX_PPDU_NO_ACK_REPORT_H_
|
||||
#define _RX_PPDU_NO_ACK_REPORT_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#include "no_ack_report.h"
|
||||
#define NUM_OF_DWORDS_RX_PPDU_NO_ACK_REPORT 4
|
||||
|
||||
#define NUM_OF_QWORDS_RX_PPDU_NO_ACK_REPORT 2
|
||||
|
||||
struct rx_ppdu_no_ack_report {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
struct no_ack_report no_ack_report_details;
|
||||
#else
|
||||
struct no_ack_report no_ack_report_details;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_NO_ACK_TRANSMIT_REASON_OFFSET 0x0000000000000000
|
||||
#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_NO_ACK_TRANSMIT_REASON_LSB 0
|
||||
#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_NO_ACK_TRANSMIT_REASON_MSB 3
|
||||
#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_NO_ACK_TRANSMIT_REASON_MASK 0x000000000000000f
|
||||
|
||||
#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_MACRX_ABORT_REASON_OFFSET 0x0000000000000000
|
||||
#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_MACRX_ABORT_REASON_LSB 4
|
||||
#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_MACRX_ABORT_REASON_MSB 7
|
||||
#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_MACRX_ABORT_REASON_MASK 0x00000000000000f0
|
||||
|
||||
#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PHYRX_ABORT_REASON_OFFSET 0x0000000000000000
|
||||
#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PHYRX_ABORT_REASON_LSB 8
|
||||
#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PHYRX_ABORT_REASON_MSB 15
|
||||
#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PHYRX_ABORT_REASON_MASK 0x000000000000ff00
|
||||
|
||||
#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FRAME_CONTROL_OFFSET 0x0000000000000000
|
||||
#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FRAME_CONTROL_LSB 16
|
||||
#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FRAME_CONTROL_MSB 31
|
||||
#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FRAME_CONTROL_MASK 0x00000000ffff0000
|
||||
|
||||
#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RX_PPDU_DURATION_OFFSET 0x0000000000000000
|
||||
#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RX_PPDU_DURATION_LSB 32
|
||||
#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RX_PPDU_DURATION_MSB 55
|
||||
#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RX_PPDU_DURATION_MASK 0x00ffffff00000000
|
||||
|
||||
#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SR_PPDU_DURING_OBSS_OFFSET 0x0000000000000000
|
||||
#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SR_PPDU_DURING_OBSS_LSB 56
|
||||
#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SR_PPDU_DURING_OBSS_MSB 56
|
||||
#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SR_PPDU_DURING_OBSS_MASK 0x0100000000000000
|
||||
|
||||
#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_OFFSET 0x0000000000000000
|
||||
#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_LSB 57
|
||||
#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_MSB 60
|
||||
#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SELFGEN_RESPONSE_REASON_TO_SR_PPDU_MASK 0x1e00000000000000
|
||||
|
||||
#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_1_OFFSET 0x0000000000000000
|
||||
#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_1_LSB 61
|
||||
#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_1_MSB 63
|
||||
#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_1_MASK 0xe000000000000000
|
||||
|
||||
#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PRE_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x0000000000000008
|
||||
#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PRE_BT_BROADCAST_STATUS_DETAILS_LSB 0
|
||||
#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PRE_BT_BROADCAST_STATUS_DETAILS_MSB 11
|
||||
#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_PRE_BT_BROADCAST_STATUS_DETAILS_MASK 0x0000000000000fff
|
||||
|
||||
#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FIRST_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x0000000000000008
|
||||
#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FIRST_BT_BROADCAST_STATUS_DETAILS_LSB 12
|
||||
#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FIRST_BT_BROADCAST_STATUS_DETAILS_MSB 23
|
||||
#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_FIRST_BT_BROADCAST_STATUS_DETAILS_MASK 0x0000000000fff000
|
||||
|
||||
#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_2_OFFSET 0x0000000000000008
|
||||
#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_2_LSB 24
|
||||
#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_2_MSB 31
|
||||
#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_2_MASK 0x00000000ff000000
|
||||
|
||||
#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SECOND_BT_BROADCAST_STATUS_DETAILS_OFFSET 0x0000000000000008
|
||||
#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SECOND_BT_BROADCAST_STATUS_DETAILS_LSB 32
|
||||
#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SECOND_BT_BROADCAST_STATUS_DETAILS_MSB 43
|
||||
#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_SECOND_BT_BROADCAST_STATUS_DETAILS_MASK 0x00000fff00000000
|
||||
|
||||
#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_3_OFFSET 0x0000000000000008
|
||||
#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_3_LSB 44
|
||||
#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_3_MSB 63
|
||||
#define RX_PPDU_NO_ACK_REPORT_NO_ACK_REPORT_DETAILS_RESERVED_3_MASK 0xfffff00000000000
|
||||
|
||||
#endif
|
||||
70
hw/kiwi/v2/rx_preamble.h
Normal file
70
hw/kiwi/v2/rx_preamble.h
Normal file
|
|
@ -0,0 +1,70 @@
|
|||
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
#ifndef _RX_PREAMBLE_H_
|
||||
#define _RX_PREAMBLE_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#define NUM_OF_DWORDS_RX_PREAMBLE 2
|
||||
|
||||
#define NUM_OF_QWORDS_RX_PREAMBLE 1
|
||||
|
||||
struct rx_preamble {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t num_users : 6,
|
||||
pkt_type : 4,
|
||||
direction : 1,
|
||||
reserved_0a : 21;
|
||||
uint32_t tlv64_padding : 32;
|
||||
#else
|
||||
uint32_t reserved_0a : 21,
|
||||
direction : 1,
|
||||
pkt_type : 4,
|
||||
num_users : 6;
|
||||
uint32_t tlv64_padding : 32;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define RX_PREAMBLE_NUM_USERS_OFFSET 0x0000000000000000
|
||||
#define RX_PREAMBLE_NUM_USERS_LSB 0
|
||||
#define RX_PREAMBLE_NUM_USERS_MSB 5
|
||||
#define RX_PREAMBLE_NUM_USERS_MASK 0x000000000000003f
|
||||
|
||||
#define RX_PREAMBLE_PKT_TYPE_OFFSET 0x0000000000000000
|
||||
#define RX_PREAMBLE_PKT_TYPE_LSB 6
|
||||
#define RX_PREAMBLE_PKT_TYPE_MSB 9
|
||||
#define RX_PREAMBLE_PKT_TYPE_MASK 0x00000000000003c0
|
||||
|
||||
#define RX_PREAMBLE_DIRECTION_OFFSET 0x0000000000000000
|
||||
#define RX_PREAMBLE_DIRECTION_LSB 10
|
||||
#define RX_PREAMBLE_DIRECTION_MSB 10
|
||||
#define RX_PREAMBLE_DIRECTION_MASK 0x0000000000000400
|
||||
|
||||
#define RX_PREAMBLE_RESERVED_0A_OFFSET 0x0000000000000000
|
||||
#define RX_PREAMBLE_RESERVED_0A_LSB 11
|
||||
#define RX_PREAMBLE_RESERVED_0A_MSB 31
|
||||
#define RX_PREAMBLE_RESERVED_0A_MASK 0x00000000fffff800
|
||||
|
||||
#define RX_PREAMBLE_TLV64_PADDING_OFFSET 0x0000000000000000
|
||||
#define RX_PREAMBLE_TLV64_PADDING_LSB 32
|
||||
#define RX_PREAMBLE_TLV64_PADDING_MSB 63
|
||||
#define RX_PREAMBLE_TLV64_PADDING_MASK 0xffffffff00000000
|
||||
|
||||
#endif
|
||||
709
hw/kiwi/v2/rx_response_required_info.h
Normal file
709
hw/kiwi/v2/rx_response_required_info.h
Normal file
|
|
@ -0,0 +1,709 @@
|
|||
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
#ifndef _RX_RESPONSE_REQUIRED_INFO_H_
|
||||
#define _RX_RESPONSE_REQUIRED_INFO_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#include "mlo_sta_id_details.h"
|
||||
#define NUM_OF_DWORDS_RX_RESPONSE_REQUIRED_INFO 16
|
||||
|
||||
#define NUM_OF_QWORDS_RX_RESPONSE_REQUIRED_INFO 8
|
||||
|
||||
struct rx_response_required_info {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t phy_ppdu_id : 16,
|
||||
su_or_uplink_mu_reception : 1,
|
||||
trigger_frame_received : 1,
|
||||
__reserved_g_0012 : 2,
|
||||
tb___reserved_g_0005_response_required : 2,
|
||||
mac_security : 1,
|
||||
filter_pass_monitor_ovrd : 1,
|
||||
ast_search_incomplete : 1,
|
||||
r2r_end_status_to_follow : 1,
|
||||
reserved_0a : 2,
|
||||
three_or_more_type_subtypes : 1,
|
||||
wait_sifs_config_valid : 1,
|
||||
wait_sifs : 2;
|
||||
uint32_t general_frame_control : 16,
|
||||
second_frame_control : 16;
|
||||
uint32_t duration : 16,
|
||||
pkt_type : 4,
|
||||
dot11ax_su_extended : 1,
|
||||
rate_mcs : 4,
|
||||
sgi : 2,
|
||||
stbc : 1,
|
||||
ldpc : 1,
|
||||
ampdu : 1,
|
||||
vht_ack : 1,
|
||||
rts_ta_grp_bit : 1;
|
||||
uint32_t ctrl_frame_soliciting_resp : 1,
|
||||
ast_fail_for_dot11ax_su_ext : 1,
|
||||
service_dynamic : 1,
|
||||
m_pkt : 1,
|
||||
sta_partial_aid : 12,
|
||||
group_id : 6,
|
||||
ctrl_resp_pwr_mgmt : 1,
|
||||
response_indication : 2,
|
||||
ndp_indication : 1,
|
||||
ndp_frame_type : 3,
|
||||
second_frame_control_valid : 1,
|
||||
reserved_3a : 2;
|
||||
uint32_t ack_id : 16,
|
||||
ack_id_ext : 10,
|
||||
agc_cbw : 3,
|
||||
service_cbw : 3;
|
||||
uint32_t response_sta_count : 7,
|
||||
reserved : 4,
|
||||
ht_vht_sig_cbw : 3,
|
||||
cts_cbw : 3,
|
||||
response_ack_count : 7,
|
||||
response_assoc_ack_count : 7,
|
||||
txop_duration_all_ones : 1;
|
||||
uint32_t response_ba32_count : 7,
|
||||
response_ba64_count : 7,
|
||||
response_ba128_count : 7,
|
||||
response_ba256_count : 7,
|
||||
multi_tid : 1,
|
||||
sw_response_tlv_from_crypto : 1,
|
||||
dot11ax_dl_ul_flag : 1,
|
||||
reserved_6a : 1;
|
||||
uint32_t sw_response_frame_length : 16,
|
||||
response_ba512_count : 7,
|
||||
response_ba1024_count : 7,
|
||||
reserved_7a : 2;
|
||||
uint32_t addr1_31_0 : 32;
|
||||
uint32_t addr1_47_32 : 16,
|
||||
addr2_15_0 : 16;
|
||||
uint32_t addr2_47_16 : 32;
|
||||
uint32_t dot11ax_received_format_indication : 1,
|
||||
dot11ax_received_dl_ul_flag : 1,
|
||||
dot11ax_received_bss_color_id : 6,
|
||||
dot11ax_received_spatial_reuse : 4,
|
||||
dot11ax_received_cp_size : 2,
|
||||
dot11ax_received_ltf_size : 2,
|
||||
dot11ax_received_coding : 1,
|
||||
dot11ax_received_dcm : 1,
|
||||
dot11ax_received_doppler_indication : 1,
|
||||
dot11ax_received_ext_ru_size : 4,
|
||||
ftm_fields_valid : 1,
|
||||
ftm_pe_nss : 3,
|
||||
ftm_pe_ltf_size : 2,
|
||||
ftm_pe_content : 1,
|
||||
ftm_chain_csd_en : 1,
|
||||
ftm_pe_chain_csd_en : 1;
|
||||
uint32_t dot11ax_response_rate_source : 8,
|
||||
dot11ax_ext_response_rate_source : 8,
|
||||
sw_peer_id : 16;
|
||||
uint32_t dot11be_puncture_bitmap : 16,
|
||||
dot11be_response : 1,
|
||||
punctured_response : 1,
|
||||
eht_duplicate_mode : 2,
|
||||
force_extra_symbol : 1,
|
||||
reserved_13a : 5,
|
||||
u_sig_puncture_pattern_encoding : 6;
|
||||
struct mlo_sta_id_details mlo_sta_id_details_rx;
|
||||
uint16_t he_a_control_response_time : 12,
|
||||
reserved_after_struct16 : 4;
|
||||
uint32_t tlv64_padding : 32;
|
||||
#else
|
||||
uint32_t wait_sifs : 2,
|
||||
wait_sifs_config_valid : 1,
|
||||
three_or_more_type_subtypes : 1,
|
||||
reserved_0a : 2,
|
||||
r2r_end_status_to_follow : 1,
|
||||
ast_search_incomplete : 1,
|
||||
filter_pass_monitor_ovrd : 1,
|
||||
mac_security : 1,
|
||||
tb___reserved_g_0005_response_required : 2,
|
||||
__reserved_g_0012 : 2,
|
||||
trigger_frame_received : 1,
|
||||
su_or_uplink_mu_reception : 1,
|
||||
phy_ppdu_id : 16;
|
||||
uint32_t second_frame_control : 16,
|
||||
general_frame_control : 16;
|
||||
uint32_t rts_ta_grp_bit : 1,
|
||||
vht_ack : 1,
|
||||
ampdu : 1,
|
||||
ldpc : 1,
|
||||
stbc : 1,
|
||||
sgi : 2,
|
||||
rate_mcs : 4,
|
||||
dot11ax_su_extended : 1,
|
||||
pkt_type : 4,
|
||||
duration : 16;
|
||||
uint32_t reserved_3a : 2,
|
||||
second_frame_control_valid : 1,
|
||||
ndp_frame_type : 3,
|
||||
ndp_indication : 1,
|
||||
response_indication : 2,
|
||||
ctrl_resp_pwr_mgmt : 1,
|
||||
group_id : 6,
|
||||
sta_partial_aid : 12,
|
||||
m_pkt : 1,
|
||||
service_dynamic : 1,
|
||||
ast_fail_for_dot11ax_su_ext : 1,
|
||||
ctrl_frame_soliciting_resp : 1;
|
||||
uint32_t service_cbw : 3,
|
||||
agc_cbw : 3,
|
||||
ack_id_ext : 10,
|
||||
ack_id : 16;
|
||||
uint32_t txop_duration_all_ones : 1,
|
||||
response_assoc_ack_count : 7,
|
||||
response_ack_count : 7,
|
||||
cts_cbw : 3,
|
||||
ht_vht_sig_cbw : 3,
|
||||
reserved : 4,
|
||||
response_sta_count : 7;
|
||||
uint32_t reserved_6a : 1,
|
||||
dot11ax_dl_ul_flag : 1,
|
||||
sw_response_tlv_from_crypto : 1,
|
||||
multi_tid : 1,
|
||||
response_ba256_count : 7,
|
||||
response_ba128_count : 7,
|
||||
response_ba64_count : 7,
|
||||
response_ba32_count : 7;
|
||||
uint32_t reserved_7a : 2,
|
||||
response_ba1024_count : 7,
|
||||
response_ba512_count : 7,
|
||||
sw_response_frame_length : 16;
|
||||
uint32_t addr1_31_0 : 32;
|
||||
uint32_t addr2_15_0 : 16,
|
||||
addr1_47_32 : 16;
|
||||
uint32_t addr2_47_16 : 32;
|
||||
uint32_t ftm_pe_chain_csd_en : 1,
|
||||
ftm_chain_csd_en : 1,
|
||||
ftm_pe_content : 1,
|
||||
ftm_pe_ltf_size : 2,
|
||||
ftm_pe_nss : 3,
|
||||
ftm_fields_valid : 1,
|
||||
dot11ax_received_ext_ru_size : 4,
|
||||
dot11ax_received_doppler_indication : 1,
|
||||
dot11ax_received_dcm : 1,
|
||||
dot11ax_received_coding : 1,
|
||||
dot11ax_received_ltf_size : 2,
|
||||
dot11ax_received_cp_size : 2,
|
||||
dot11ax_received_spatial_reuse : 4,
|
||||
dot11ax_received_bss_color_id : 6,
|
||||
dot11ax_received_dl_ul_flag : 1,
|
||||
dot11ax_received_format_indication : 1;
|
||||
uint32_t sw_peer_id : 16,
|
||||
dot11ax_ext_response_rate_source : 8,
|
||||
dot11ax_response_rate_source : 8;
|
||||
uint32_t u_sig_puncture_pattern_encoding : 6,
|
||||
reserved_13a : 5,
|
||||
force_extra_symbol : 1,
|
||||
eht_duplicate_mode : 2,
|
||||
punctured_response : 1,
|
||||
dot11be_response : 1,
|
||||
dot11be_puncture_bitmap : 16;
|
||||
uint32_t reserved_after_struct16 : 4,
|
||||
he_a_control_response_time : 12;
|
||||
struct mlo_sta_id_details mlo_sta_id_details_rx;
|
||||
uint32_t tlv64_padding : 32;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define RX_RESPONSE_REQUIRED_INFO_PHY_PPDU_ID_OFFSET 0x0000000000000000
|
||||
#define RX_RESPONSE_REQUIRED_INFO_PHY_PPDU_ID_LSB 0
|
||||
#define RX_RESPONSE_REQUIRED_INFO_PHY_PPDU_ID_MSB 15
|
||||
#define RX_RESPONSE_REQUIRED_INFO_PHY_PPDU_ID_MASK 0x000000000000ffff
|
||||
|
||||
#define RX_RESPONSE_REQUIRED_INFO_SU_OR_UPLINK_MU_RECEPTION_OFFSET 0x0000000000000000
|
||||
#define RX_RESPONSE_REQUIRED_INFO_SU_OR_UPLINK_MU_RECEPTION_LSB 16
|
||||
#define RX_RESPONSE_REQUIRED_INFO_SU_OR_UPLINK_MU_RECEPTION_MSB 16
|
||||
#define RX_RESPONSE_REQUIRED_INFO_SU_OR_UPLINK_MU_RECEPTION_MASK 0x0000000000010000
|
||||
|
||||
#define RX_RESPONSE_REQUIRED_INFO_TRIGGER_FRAME_RECEIVED_OFFSET 0x0000000000000000
|
||||
#define RX_RESPONSE_REQUIRED_INFO_TRIGGER_FRAME_RECEIVED_LSB 17
|
||||
#define RX_RESPONSE_REQUIRED_INFO_TRIGGER_FRAME_RECEIVED_MSB 17
|
||||
#define RX_RESPONSE_REQUIRED_INFO_TRIGGER_FRAME_RECEIVED_MASK 0x0000000000020000
|
||||
|
||||
#define RX_RESPONSE_REQUIRED_INFO_TB_RANGING_RESPONSE_REQUIRED_OFFSET 0x0000000000000000
|
||||
#define RX_RESPONSE_REQUIRED_INFO_TB_RANGING_RESPONSE_REQUIRED_LSB 20
|
||||
#define RX_RESPONSE_REQUIRED_INFO_TB_RANGING_RESPONSE_REQUIRED_MSB 21
|
||||
#define RX_RESPONSE_REQUIRED_INFO_TB_RANGING_RESPONSE_REQUIRED_MASK 0x0000000000300000
|
||||
|
||||
#define RX_RESPONSE_REQUIRED_INFO_MAC_SECURITY_OFFSET 0x0000000000000000
|
||||
#define RX_RESPONSE_REQUIRED_INFO_MAC_SECURITY_LSB 22
|
||||
#define RX_RESPONSE_REQUIRED_INFO_MAC_SECURITY_MSB 22
|
||||
#define RX_RESPONSE_REQUIRED_INFO_MAC_SECURITY_MASK 0x0000000000400000
|
||||
|
||||
#define RX_RESPONSE_REQUIRED_INFO_FILTER_PASS_MONITOR_OVRD_OFFSET 0x0000000000000000
|
||||
#define RX_RESPONSE_REQUIRED_INFO_FILTER_PASS_MONITOR_OVRD_LSB 23
|
||||
#define RX_RESPONSE_REQUIRED_INFO_FILTER_PASS_MONITOR_OVRD_MSB 23
|
||||
#define RX_RESPONSE_REQUIRED_INFO_FILTER_PASS_MONITOR_OVRD_MASK 0x0000000000800000
|
||||
|
||||
#define RX_RESPONSE_REQUIRED_INFO_AST_SEARCH_INCOMPLETE_OFFSET 0x0000000000000000
|
||||
#define RX_RESPONSE_REQUIRED_INFO_AST_SEARCH_INCOMPLETE_LSB 24
|
||||
#define RX_RESPONSE_REQUIRED_INFO_AST_SEARCH_INCOMPLETE_MSB 24
|
||||
#define RX_RESPONSE_REQUIRED_INFO_AST_SEARCH_INCOMPLETE_MASK 0x0000000001000000
|
||||
|
||||
#define RX_RESPONSE_REQUIRED_INFO_R2R_END_STATUS_TO_FOLLOW_OFFSET 0x0000000000000000
|
||||
#define RX_RESPONSE_REQUIRED_INFO_R2R_END_STATUS_TO_FOLLOW_LSB 25
|
||||
#define RX_RESPONSE_REQUIRED_INFO_R2R_END_STATUS_TO_FOLLOW_MSB 25
|
||||
#define RX_RESPONSE_REQUIRED_INFO_R2R_END_STATUS_TO_FOLLOW_MASK 0x0000000002000000
|
||||
|
||||
#define RX_RESPONSE_REQUIRED_INFO_RESERVED_0A_OFFSET 0x0000000000000000
|
||||
#define RX_RESPONSE_REQUIRED_INFO_RESERVED_0A_LSB 26
|
||||
#define RX_RESPONSE_REQUIRED_INFO_RESERVED_0A_MSB 27
|
||||
#define RX_RESPONSE_REQUIRED_INFO_RESERVED_0A_MASK 0x000000000c000000
|
||||
|
||||
#define RX_RESPONSE_REQUIRED_INFO_THREE_OR_MORE_TYPE_SUBTYPES_OFFSET 0x0000000000000000
|
||||
#define RX_RESPONSE_REQUIRED_INFO_THREE_OR_MORE_TYPE_SUBTYPES_LSB 28
|
||||
#define RX_RESPONSE_REQUIRED_INFO_THREE_OR_MORE_TYPE_SUBTYPES_MSB 28
|
||||
#define RX_RESPONSE_REQUIRED_INFO_THREE_OR_MORE_TYPE_SUBTYPES_MASK 0x0000000010000000
|
||||
|
||||
#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_CONFIG_VALID_OFFSET 0x0000000000000000
|
||||
#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_CONFIG_VALID_LSB 29
|
||||
#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_CONFIG_VALID_MSB 29
|
||||
#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_CONFIG_VALID_MASK 0x0000000020000000
|
||||
|
||||
#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_OFFSET 0x0000000000000000
|
||||
#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_LSB 30
|
||||
#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_MSB 31
|
||||
#define RX_RESPONSE_REQUIRED_INFO_WAIT_SIFS_MASK 0x00000000c0000000
|
||||
|
||||
#define RX_RESPONSE_REQUIRED_INFO_GENERAL_FRAME_CONTROL_OFFSET 0x0000000000000000
|
||||
#define RX_RESPONSE_REQUIRED_INFO_GENERAL_FRAME_CONTROL_LSB 32
|
||||
#define RX_RESPONSE_REQUIRED_INFO_GENERAL_FRAME_CONTROL_MSB 47
|
||||
#define RX_RESPONSE_REQUIRED_INFO_GENERAL_FRAME_CONTROL_MASK 0x0000ffff00000000
|
||||
|
||||
#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_OFFSET 0x0000000000000000
|
||||
#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_LSB 48
|
||||
#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_MSB 63
|
||||
#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_MASK 0xffff000000000000
|
||||
|
||||
#define RX_RESPONSE_REQUIRED_INFO_DURATION_OFFSET 0x0000000000000008
|
||||
#define RX_RESPONSE_REQUIRED_INFO_DURATION_LSB 0
|
||||
#define RX_RESPONSE_REQUIRED_INFO_DURATION_MSB 15
|
||||
#define RX_RESPONSE_REQUIRED_INFO_DURATION_MASK 0x000000000000ffff
|
||||
|
||||
#define RX_RESPONSE_REQUIRED_INFO_PKT_TYPE_OFFSET 0x0000000000000008
|
||||
#define RX_RESPONSE_REQUIRED_INFO_PKT_TYPE_LSB 16
|
||||
#define RX_RESPONSE_REQUIRED_INFO_PKT_TYPE_MSB 19
|
||||
#define RX_RESPONSE_REQUIRED_INFO_PKT_TYPE_MASK 0x00000000000f0000
|
||||
|
||||
#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000008
|
||||
#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_SU_EXTENDED_LSB 20
|
||||
#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_SU_EXTENDED_MSB 20
|
||||
#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_SU_EXTENDED_MASK 0x0000000000100000
|
||||
|
||||
#define RX_RESPONSE_REQUIRED_INFO_RATE_MCS_OFFSET 0x0000000000000008
|
||||
#define RX_RESPONSE_REQUIRED_INFO_RATE_MCS_LSB 21
|
||||
#define RX_RESPONSE_REQUIRED_INFO_RATE_MCS_MSB 24
|
||||
#define RX_RESPONSE_REQUIRED_INFO_RATE_MCS_MASK 0x0000000001e00000
|
||||
|
||||
#define RX_RESPONSE_REQUIRED_INFO_SGI_OFFSET 0x0000000000000008
|
||||
#define RX_RESPONSE_REQUIRED_INFO_SGI_LSB 25
|
||||
#define RX_RESPONSE_REQUIRED_INFO_SGI_MSB 26
|
||||
#define RX_RESPONSE_REQUIRED_INFO_SGI_MASK 0x0000000006000000
|
||||
|
||||
#define RX_RESPONSE_REQUIRED_INFO_STBC_OFFSET 0x0000000000000008
|
||||
#define RX_RESPONSE_REQUIRED_INFO_STBC_LSB 27
|
||||
#define RX_RESPONSE_REQUIRED_INFO_STBC_MSB 27
|
||||
#define RX_RESPONSE_REQUIRED_INFO_STBC_MASK 0x0000000008000000
|
||||
|
||||
#define RX_RESPONSE_REQUIRED_INFO_LDPC_OFFSET 0x0000000000000008
|
||||
#define RX_RESPONSE_REQUIRED_INFO_LDPC_LSB 28
|
||||
#define RX_RESPONSE_REQUIRED_INFO_LDPC_MSB 28
|
||||
#define RX_RESPONSE_REQUIRED_INFO_LDPC_MASK 0x0000000010000000
|
||||
|
||||
#define RX_RESPONSE_REQUIRED_INFO_AMPDU_OFFSET 0x0000000000000008
|
||||
#define RX_RESPONSE_REQUIRED_INFO_AMPDU_LSB 29
|
||||
#define RX_RESPONSE_REQUIRED_INFO_AMPDU_MSB 29
|
||||
#define RX_RESPONSE_REQUIRED_INFO_AMPDU_MASK 0x0000000020000000
|
||||
|
||||
#define RX_RESPONSE_REQUIRED_INFO_VHT_ACK_OFFSET 0x0000000000000008
|
||||
#define RX_RESPONSE_REQUIRED_INFO_VHT_ACK_LSB 30
|
||||
#define RX_RESPONSE_REQUIRED_INFO_VHT_ACK_MSB 30
|
||||
#define RX_RESPONSE_REQUIRED_INFO_VHT_ACK_MASK 0x0000000040000000
|
||||
|
||||
#define RX_RESPONSE_REQUIRED_INFO_RTS_TA_GRP_BIT_OFFSET 0x0000000000000008
|
||||
#define RX_RESPONSE_REQUIRED_INFO_RTS_TA_GRP_BIT_LSB 31
|
||||
#define RX_RESPONSE_REQUIRED_INFO_RTS_TA_GRP_BIT_MSB 31
|
||||
#define RX_RESPONSE_REQUIRED_INFO_RTS_TA_GRP_BIT_MASK 0x0000000080000000
|
||||
|
||||
#define RX_RESPONSE_REQUIRED_INFO_CTRL_FRAME_SOLICITING_RESP_OFFSET 0x0000000000000008
|
||||
#define RX_RESPONSE_REQUIRED_INFO_CTRL_FRAME_SOLICITING_RESP_LSB 32
|
||||
#define RX_RESPONSE_REQUIRED_INFO_CTRL_FRAME_SOLICITING_RESP_MSB 32
|
||||
#define RX_RESPONSE_REQUIRED_INFO_CTRL_FRAME_SOLICITING_RESP_MASK 0x0000000100000000
|
||||
|
||||
#define RX_RESPONSE_REQUIRED_INFO_AST_FAIL_FOR_DOT11AX_SU_EXT_OFFSET 0x0000000000000008
|
||||
#define RX_RESPONSE_REQUIRED_INFO_AST_FAIL_FOR_DOT11AX_SU_EXT_LSB 33
|
||||
#define RX_RESPONSE_REQUIRED_INFO_AST_FAIL_FOR_DOT11AX_SU_EXT_MSB 33
|
||||
#define RX_RESPONSE_REQUIRED_INFO_AST_FAIL_FOR_DOT11AX_SU_EXT_MASK 0x0000000200000000
|
||||
|
||||
#define RX_RESPONSE_REQUIRED_INFO_SERVICE_DYNAMIC_OFFSET 0x0000000000000008
|
||||
#define RX_RESPONSE_REQUIRED_INFO_SERVICE_DYNAMIC_LSB 34
|
||||
#define RX_RESPONSE_REQUIRED_INFO_SERVICE_DYNAMIC_MSB 34
|
||||
#define RX_RESPONSE_REQUIRED_INFO_SERVICE_DYNAMIC_MASK 0x0000000400000000
|
||||
|
||||
#define RX_RESPONSE_REQUIRED_INFO_M_PKT_OFFSET 0x0000000000000008
|
||||
#define RX_RESPONSE_REQUIRED_INFO_M_PKT_LSB 35
|
||||
#define RX_RESPONSE_REQUIRED_INFO_M_PKT_MSB 35
|
||||
#define RX_RESPONSE_REQUIRED_INFO_M_PKT_MASK 0x0000000800000000
|
||||
|
||||
#define RX_RESPONSE_REQUIRED_INFO_STA_PARTIAL_AID_OFFSET 0x0000000000000008
|
||||
#define RX_RESPONSE_REQUIRED_INFO_STA_PARTIAL_AID_LSB 36
|
||||
#define RX_RESPONSE_REQUIRED_INFO_STA_PARTIAL_AID_MSB 47
|
||||
#define RX_RESPONSE_REQUIRED_INFO_STA_PARTIAL_AID_MASK 0x0000fff000000000
|
||||
|
||||
#define RX_RESPONSE_REQUIRED_INFO_GROUP_ID_OFFSET 0x0000000000000008
|
||||
#define RX_RESPONSE_REQUIRED_INFO_GROUP_ID_LSB 48
|
||||
#define RX_RESPONSE_REQUIRED_INFO_GROUP_ID_MSB 53
|
||||
#define RX_RESPONSE_REQUIRED_INFO_GROUP_ID_MASK 0x003f000000000000
|
||||
|
||||
#define RX_RESPONSE_REQUIRED_INFO_CTRL_RESP_PWR_MGMT_OFFSET 0x0000000000000008
|
||||
#define RX_RESPONSE_REQUIRED_INFO_CTRL_RESP_PWR_MGMT_LSB 54
|
||||
#define RX_RESPONSE_REQUIRED_INFO_CTRL_RESP_PWR_MGMT_MSB 54
|
||||
#define RX_RESPONSE_REQUIRED_INFO_CTRL_RESP_PWR_MGMT_MASK 0x0040000000000000
|
||||
|
||||
#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_INDICATION_OFFSET 0x0000000000000008
|
||||
#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_INDICATION_LSB 55
|
||||
#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_INDICATION_MSB 56
|
||||
#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_INDICATION_MASK 0x0180000000000000
|
||||
|
||||
#define RX_RESPONSE_REQUIRED_INFO_NDP_INDICATION_OFFSET 0x0000000000000008
|
||||
#define RX_RESPONSE_REQUIRED_INFO_NDP_INDICATION_LSB 57
|
||||
#define RX_RESPONSE_REQUIRED_INFO_NDP_INDICATION_MSB 57
|
||||
#define RX_RESPONSE_REQUIRED_INFO_NDP_INDICATION_MASK 0x0200000000000000
|
||||
|
||||
#define RX_RESPONSE_REQUIRED_INFO_NDP_FRAME_TYPE_OFFSET 0x0000000000000008
|
||||
#define RX_RESPONSE_REQUIRED_INFO_NDP_FRAME_TYPE_LSB 58
|
||||
#define RX_RESPONSE_REQUIRED_INFO_NDP_FRAME_TYPE_MSB 60
|
||||
#define RX_RESPONSE_REQUIRED_INFO_NDP_FRAME_TYPE_MASK 0x1c00000000000000
|
||||
|
||||
#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_VALID_OFFSET 0x0000000000000008
|
||||
#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_VALID_LSB 61
|
||||
#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_VALID_MSB 61
|
||||
#define RX_RESPONSE_REQUIRED_INFO_SECOND_FRAME_CONTROL_VALID_MASK 0x2000000000000000
|
||||
|
||||
#define RX_RESPONSE_REQUIRED_INFO_RESERVED_3A_OFFSET 0x0000000000000008
|
||||
#define RX_RESPONSE_REQUIRED_INFO_RESERVED_3A_LSB 62
|
||||
#define RX_RESPONSE_REQUIRED_INFO_RESERVED_3A_MSB 63
|
||||
#define RX_RESPONSE_REQUIRED_INFO_RESERVED_3A_MASK 0xc000000000000000
|
||||
|
||||
#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_OFFSET 0x0000000000000010
|
||||
#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_LSB 0
|
||||
#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_MSB 15
|
||||
#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_MASK 0x000000000000ffff
|
||||
|
||||
#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_EXT_OFFSET 0x0000000000000010
|
||||
#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_EXT_LSB 16
|
||||
#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_EXT_MSB 25
|
||||
#define RX_RESPONSE_REQUIRED_INFO_ACK_ID_EXT_MASK 0x0000000003ff0000
|
||||
|
||||
#define RX_RESPONSE_REQUIRED_INFO_AGC_CBW_OFFSET 0x0000000000000010
|
||||
#define RX_RESPONSE_REQUIRED_INFO_AGC_CBW_LSB 26
|
||||
#define RX_RESPONSE_REQUIRED_INFO_AGC_CBW_MSB 28
|
||||
#define RX_RESPONSE_REQUIRED_INFO_AGC_CBW_MASK 0x000000001c000000
|
||||
|
||||
#define RX_RESPONSE_REQUIRED_INFO_SERVICE_CBW_OFFSET 0x0000000000000010
|
||||
#define RX_RESPONSE_REQUIRED_INFO_SERVICE_CBW_LSB 29
|
||||
#define RX_RESPONSE_REQUIRED_INFO_SERVICE_CBW_MSB 31
|
||||
#define RX_RESPONSE_REQUIRED_INFO_SERVICE_CBW_MASK 0x00000000e0000000
|
||||
|
||||
#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_STA_COUNT_OFFSET 0x0000000000000010
|
||||
#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_STA_COUNT_LSB 32
|
||||
#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_STA_COUNT_MSB 38
|
||||
#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_STA_COUNT_MASK 0x0000007f00000000
|
||||
|
||||
#define RX_RESPONSE_REQUIRED_INFO_RESERVED_OFFSET 0x0000000000000010
|
||||
#define RX_RESPONSE_REQUIRED_INFO_RESERVED_LSB 39
|
||||
#define RX_RESPONSE_REQUIRED_INFO_RESERVED_MSB 42
|
||||
#define RX_RESPONSE_REQUIRED_INFO_RESERVED_MASK 0x0000078000000000
|
||||
|
||||
#define RX_RESPONSE_REQUIRED_INFO_HT_VHT_SIG_CBW_OFFSET 0x0000000000000010
|
||||
#define RX_RESPONSE_REQUIRED_INFO_HT_VHT_SIG_CBW_LSB 43
|
||||
#define RX_RESPONSE_REQUIRED_INFO_HT_VHT_SIG_CBW_MSB 45
|
||||
#define RX_RESPONSE_REQUIRED_INFO_HT_VHT_SIG_CBW_MASK 0x0000380000000000
|
||||
|
||||
#define RX_RESPONSE_REQUIRED_INFO_CTS_CBW_OFFSET 0x0000000000000010
|
||||
#define RX_RESPONSE_REQUIRED_INFO_CTS_CBW_LSB 46
|
||||
#define RX_RESPONSE_REQUIRED_INFO_CTS_CBW_MSB 48
|
||||
#define RX_RESPONSE_REQUIRED_INFO_CTS_CBW_MASK 0x0001c00000000000
|
||||
|
||||
#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ACK_COUNT_OFFSET 0x0000000000000010
|
||||
#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ACK_COUNT_LSB 49
|
||||
#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ACK_COUNT_MSB 55
|
||||
#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ACK_COUNT_MASK 0x00fe000000000000
|
||||
|
||||
#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ASSOC_ACK_COUNT_OFFSET 0x0000000000000010
|
||||
#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ASSOC_ACK_COUNT_LSB 56
|
||||
#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ASSOC_ACK_COUNT_MSB 62
|
||||
#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_ASSOC_ACK_COUNT_MASK 0x7f00000000000000
|
||||
|
||||
#define RX_RESPONSE_REQUIRED_INFO_TXOP_DURATION_ALL_ONES_OFFSET 0x0000000000000010
|
||||
#define RX_RESPONSE_REQUIRED_INFO_TXOP_DURATION_ALL_ONES_LSB 63
|
||||
#define RX_RESPONSE_REQUIRED_INFO_TXOP_DURATION_ALL_ONES_MSB 63
|
||||
#define RX_RESPONSE_REQUIRED_INFO_TXOP_DURATION_ALL_ONES_MASK 0x8000000000000000
|
||||
|
||||
#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA32_COUNT_OFFSET 0x0000000000000018
|
||||
#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA32_COUNT_LSB 0
|
||||
#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA32_COUNT_MSB 6
|
||||
#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA32_COUNT_MASK 0x000000000000007f
|
||||
|
||||
#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA64_COUNT_OFFSET 0x0000000000000018
|
||||
#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA64_COUNT_LSB 7
|
||||
#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA64_COUNT_MSB 13
|
||||
#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA64_COUNT_MASK 0x0000000000003f80
|
||||
|
||||
#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA128_COUNT_OFFSET 0x0000000000000018
|
||||
#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA128_COUNT_LSB 14
|
||||
#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA128_COUNT_MSB 20
|
||||
#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA128_COUNT_MASK 0x00000000001fc000
|
||||
|
||||
#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA256_COUNT_OFFSET 0x0000000000000018
|
||||
#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA256_COUNT_LSB 21
|
||||
#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA256_COUNT_MSB 27
|
||||
#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA256_COUNT_MASK 0x000000000fe00000
|
||||
|
||||
#define RX_RESPONSE_REQUIRED_INFO_MULTI_TID_OFFSET 0x0000000000000018
|
||||
#define RX_RESPONSE_REQUIRED_INFO_MULTI_TID_LSB 28
|
||||
#define RX_RESPONSE_REQUIRED_INFO_MULTI_TID_MSB 28
|
||||
#define RX_RESPONSE_REQUIRED_INFO_MULTI_TID_MASK 0x0000000010000000
|
||||
|
||||
#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_OFFSET 0x0000000000000018
|
||||
#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_LSB 29
|
||||
#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_MSB 29
|
||||
#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_MASK 0x0000000020000000
|
||||
|
||||
#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_DL_UL_FLAG_OFFSET 0x0000000000000018
|
||||
#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_DL_UL_FLAG_LSB 30
|
||||
#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_DL_UL_FLAG_MSB 30
|
||||
#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_DL_UL_FLAG_MASK 0x0000000040000000
|
||||
|
||||
#define RX_RESPONSE_REQUIRED_INFO_RESERVED_6A_OFFSET 0x0000000000000018
|
||||
#define RX_RESPONSE_REQUIRED_INFO_RESERVED_6A_LSB 31
|
||||
#define RX_RESPONSE_REQUIRED_INFO_RESERVED_6A_MSB 31
|
||||
#define RX_RESPONSE_REQUIRED_INFO_RESERVED_6A_MASK 0x0000000080000000
|
||||
|
||||
#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_FRAME_LENGTH_OFFSET 0x0000000000000018
|
||||
#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_FRAME_LENGTH_LSB 32
|
||||
#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_FRAME_LENGTH_MSB 47
|
||||
#define RX_RESPONSE_REQUIRED_INFO_SW_RESPONSE_FRAME_LENGTH_MASK 0x0000ffff00000000
|
||||
|
||||
#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA512_COUNT_OFFSET 0x0000000000000018
|
||||
#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA512_COUNT_LSB 48
|
||||
#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA512_COUNT_MSB 54
|
||||
#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA512_COUNT_MASK 0x007f000000000000
|
||||
|
||||
#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA1024_COUNT_OFFSET 0x0000000000000018
|
||||
#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA1024_COUNT_LSB 55
|
||||
#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA1024_COUNT_MSB 61
|
||||
#define RX_RESPONSE_REQUIRED_INFO_RESPONSE_BA1024_COUNT_MASK 0x3f80000000000000
|
||||
|
||||
#define RX_RESPONSE_REQUIRED_INFO_RESERVED_7A_OFFSET 0x0000000000000018
|
||||
#define RX_RESPONSE_REQUIRED_INFO_RESERVED_7A_LSB 62
|
||||
#define RX_RESPONSE_REQUIRED_INFO_RESERVED_7A_MSB 63
|
||||
#define RX_RESPONSE_REQUIRED_INFO_RESERVED_7A_MASK 0xc000000000000000
|
||||
|
||||
#define RX_RESPONSE_REQUIRED_INFO_ADDR1_31_0_OFFSET 0x0000000000000020
|
||||
#define RX_RESPONSE_REQUIRED_INFO_ADDR1_31_0_LSB 0
|
||||
#define RX_RESPONSE_REQUIRED_INFO_ADDR1_31_0_MSB 31
|
||||
#define RX_RESPONSE_REQUIRED_INFO_ADDR1_31_0_MASK 0x00000000ffffffff
|
||||
|
||||
#define RX_RESPONSE_REQUIRED_INFO_ADDR1_47_32_OFFSET 0x0000000000000020
|
||||
#define RX_RESPONSE_REQUIRED_INFO_ADDR1_47_32_LSB 32
|
||||
#define RX_RESPONSE_REQUIRED_INFO_ADDR1_47_32_MSB 47
|
||||
#define RX_RESPONSE_REQUIRED_INFO_ADDR1_47_32_MASK 0x0000ffff00000000
|
||||
|
||||
#define RX_RESPONSE_REQUIRED_INFO_ADDR2_15_0_OFFSET 0x0000000000000020
|
||||
#define RX_RESPONSE_REQUIRED_INFO_ADDR2_15_0_LSB 48
|
||||
#define RX_RESPONSE_REQUIRED_INFO_ADDR2_15_0_MSB 63
|
||||
#define RX_RESPONSE_REQUIRED_INFO_ADDR2_15_0_MASK 0xffff000000000000
|
||||
|
||||
#define RX_RESPONSE_REQUIRED_INFO_ADDR2_47_16_OFFSET 0x0000000000000028
|
||||
#define RX_RESPONSE_REQUIRED_INFO_ADDR2_47_16_LSB 0
|
||||
#define RX_RESPONSE_REQUIRED_INFO_ADDR2_47_16_MSB 31
|
||||
#define RX_RESPONSE_REQUIRED_INFO_ADDR2_47_16_MASK 0x00000000ffffffff
|
||||
|
||||
#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_OFFSET 0x0000000000000028
|
||||
#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_LSB 32
|
||||
#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_MSB 32
|
||||
#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_MASK 0x0000000100000000
|
||||
|
||||
#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_OFFSET 0x0000000000000028
|
||||
#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_LSB 33
|
||||
#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_MSB 33
|
||||
#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_MASK 0x0000000200000000
|
||||
|
||||
#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_OFFSET 0x0000000000000028
|
||||
#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_LSB 34
|
||||
#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_MSB 39
|
||||
#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_MASK 0x000000fc00000000
|
||||
|
||||
#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_OFFSET 0x0000000000000028
|
||||
#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_LSB 40
|
||||
#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_MSB 43
|
||||
#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_MASK 0x00000f0000000000
|
||||
|
||||
#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CP_SIZE_OFFSET 0x0000000000000028
|
||||
#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CP_SIZE_LSB 44
|
||||
#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CP_SIZE_MSB 45
|
||||
#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CP_SIZE_MASK 0x0000300000000000
|
||||
|
||||
#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_LTF_SIZE_OFFSET 0x0000000000000028
|
||||
#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_LTF_SIZE_LSB 46
|
||||
#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_LTF_SIZE_MSB 47
|
||||
#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_LTF_SIZE_MASK 0x0000c00000000000
|
||||
|
||||
#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CODING_OFFSET 0x0000000000000028
|
||||
#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CODING_LSB 48
|
||||
#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CODING_MSB 48
|
||||
#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_CODING_MASK 0x0001000000000000
|
||||
|
||||
#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DCM_OFFSET 0x0000000000000028
|
||||
#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DCM_LSB 49
|
||||
#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DCM_MSB 49
|
||||
#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DCM_MASK 0x0002000000000000
|
||||
|
||||
#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_OFFSET 0x0000000000000028
|
||||
#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_LSB 50
|
||||
#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_MSB 50
|
||||
#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_MASK 0x0004000000000000
|
||||
|
||||
#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_OFFSET 0x0000000000000028
|
||||
#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_LSB 51
|
||||
#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_MSB 54
|
||||
#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_MASK 0x0078000000000000
|
||||
|
||||
#define RX_RESPONSE_REQUIRED_INFO_FTM_FIELDS_VALID_OFFSET 0x0000000000000028
|
||||
#define RX_RESPONSE_REQUIRED_INFO_FTM_FIELDS_VALID_LSB 55
|
||||
#define RX_RESPONSE_REQUIRED_INFO_FTM_FIELDS_VALID_MSB 55
|
||||
#define RX_RESPONSE_REQUIRED_INFO_FTM_FIELDS_VALID_MASK 0x0080000000000000
|
||||
|
||||
#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_NSS_OFFSET 0x0000000000000028
|
||||
#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_NSS_LSB 56
|
||||
#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_NSS_MSB 58
|
||||
#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_NSS_MASK 0x0700000000000000
|
||||
|
||||
#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_LTF_SIZE_OFFSET 0x0000000000000028
|
||||
#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_LTF_SIZE_LSB 59
|
||||
#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_LTF_SIZE_MSB 60
|
||||
#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_LTF_SIZE_MASK 0x1800000000000000
|
||||
|
||||
#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CONTENT_OFFSET 0x0000000000000028
|
||||
#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CONTENT_LSB 61
|
||||
#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CONTENT_MSB 61
|
||||
#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CONTENT_MASK 0x2000000000000000
|
||||
|
||||
#define RX_RESPONSE_REQUIRED_INFO_FTM_CHAIN_CSD_EN_OFFSET 0x0000000000000028
|
||||
#define RX_RESPONSE_REQUIRED_INFO_FTM_CHAIN_CSD_EN_LSB 62
|
||||
#define RX_RESPONSE_REQUIRED_INFO_FTM_CHAIN_CSD_EN_MSB 62
|
||||
#define RX_RESPONSE_REQUIRED_INFO_FTM_CHAIN_CSD_EN_MASK 0x4000000000000000
|
||||
|
||||
#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CHAIN_CSD_EN_OFFSET 0x0000000000000028
|
||||
#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CHAIN_CSD_EN_LSB 63
|
||||
#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CHAIN_CSD_EN_MSB 63
|
||||
#define RX_RESPONSE_REQUIRED_INFO_FTM_PE_CHAIN_CSD_EN_MASK 0x8000000000000000
|
||||
|
||||
#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RESPONSE_RATE_SOURCE_OFFSET 0x0000000000000030
|
||||
#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RESPONSE_RATE_SOURCE_LSB 0
|
||||
#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RESPONSE_RATE_SOURCE_MSB 7
|
||||
#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_RESPONSE_RATE_SOURCE_MASK 0x00000000000000ff
|
||||
|
||||
#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_EXT_RESPONSE_RATE_SOURCE_OFFSET 0x0000000000000030
|
||||
#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_EXT_RESPONSE_RATE_SOURCE_LSB 8
|
||||
#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_EXT_RESPONSE_RATE_SOURCE_MSB 15
|
||||
#define RX_RESPONSE_REQUIRED_INFO_DOT11AX_EXT_RESPONSE_RATE_SOURCE_MASK 0x000000000000ff00
|
||||
|
||||
#define RX_RESPONSE_REQUIRED_INFO_SW_PEER_ID_OFFSET 0x0000000000000030
|
||||
#define RX_RESPONSE_REQUIRED_INFO_SW_PEER_ID_LSB 16
|
||||
#define RX_RESPONSE_REQUIRED_INFO_SW_PEER_ID_MSB 31
|
||||
#define RX_RESPONSE_REQUIRED_INFO_SW_PEER_ID_MASK 0x00000000ffff0000
|
||||
|
||||
#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_PUNCTURE_BITMAP_OFFSET 0x0000000000000030
|
||||
#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_PUNCTURE_BITMAP_LSB 32
|
||||
#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_PUNCTURE_BITMAP_MSB 47
|
||||
#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_PUNCTURE_BITMAP_MASK 0x0000ffff00000000
|
||||
|
||||
#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_RESPONSE_OFFSET 0x0000000000000030
|
||||
#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_RESPONSE_LSB 48
|
||||
#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_RESPONSE_MSB 48
|
||||
#define RX_RESPONSE_REQUIRED_INFO_DOT11BE_RESPONSE_MASK 0x0001000000000000
|
||||
|
||||
#define RX_RESPONSE_REQUIRED_INFO_PUNCTURED_RESPONSE_OFFSET 0x0000000000000030
|
||||
#define RX_RESPONSE_REQUIRED_INFO_PUNCTURED_RESPONSE_LSB 49
|
||||
#define RX_RESPONSE_REQUIRED_INFO_PUNCTURED_RESPONSE_MSB 49
|
||||
#define RX_RESPONSE_REQUIRED_INFO_PUNCTURED_RESPONSE_MASK 0x0002000000000000
|
||||
|
||||
#define RX_RESPONSE_REQUIRED_INFO_EHT_DUPLICATE_MODE_OFFSET 0x0000000000000030
|
||||
#define RX_RESPONSE_REQUIRED_INFO_EHT_DUPLICATE_MODE_LSB 50
|
||||
#define RX_RESPONSE_REQUIRED_INFO_EHT_DUPLICATE_MODE_MSB 51
|
||||
#define RX_RESPONSE_REQUIRED_INFO_EHT_DUPLICATE_MODE_MASK 0x000c000000000000
|
||||
|
||||
#define RX_RESPONSE_REQUIRED_INFO_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000030
|
||||
#define RX_RESPONSE_REQUIRED_INFO_FORCE_EXTRA_SYMBOL_LSB 52
|
||||
#define RX_RESPONSE_REQUIRED_INFO_FORCE_EXTRA_SYMBOL_MSB 52
|
||||
#define RX_RESPONSE_REQUIRED_INFO_FORCE_EXTRA_SYMBOL_MASK 0x0010000000000000
|
||||
|
||||
#define RX_RESPONSE_REQUIRED_INFO_RESERVED_13A_OFFSET 0x0000000000000030
|
||||
#define RX_RESPONSE_REQUIRED_INFO_RESERVED_13A_LSB 53
|
||||
#define RX_RESPONSE_REQUIRED_INFO_RESERVED_13A_MSB 57
|
||||
#define RX_RESPONSE_REQUIRED_INFO_RESERVED_13A_MASK 0x03e0000000000000
|
||||
|
||||
#define RX_RESPONSE_REQUIRED_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000030
|
||||
#define RX_RESPONSE_REQUIRED_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 58
|
||||
#define RX_RESPONSE_REQUIRED_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 63
|
||||
#define RX_RESPONSE_REQUIRED_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0xfc00000000000000
|
||||
|
||||
#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_OFFSET 0x0000000000000038
|
||||
#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_LSB 0
|
||||
#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MSB 9
|
||||
#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_MASK 0x00000000000003ff
|
||||
|
||||
#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_OFFSET 0x0000000000000038
|
||||
#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_LSB 10
|
||||
#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MSB 10
|
||||
#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_SELF_ML_SYNC_MASK 0x0000000000000400
|
||||
|
||||
#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_OFFSET 0x0000000000000038
|
||||
#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_LSB 11
|
||||
#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MSB 11
|
||||
#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_BLOCK_PARTNER_ML_SYNC_MASK 0x0000000000000800
|
||||
|
||||
#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_OFFSET 0x0000000000000038
|
||||
#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_LSB 12
|
||||
#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MSB 12
|
||||
#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_NSTR_MLO_STA_ID_VALID_MASK 0x0000000000001000
|
||||
|
||||
#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_OFFSET 0x0000000000000038
|
||||
#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_LSB 13
|
||||
#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MSB 15
|
||||
#define RX_RESPONSE_REQUIRED_INFO_MLO_STA_ID_DETAILS_RX_RESERVED_0A_MASK 0x000000000000e000
|
||||
|
||||
#define RX_RESPONSE_REQUIRED_INFO_HE_A_CONTROL_RESPONSE_TIME_OFFSET 0x0000000000000038
|
||||
#define RX_RESPONSE_REQUIRED_INFO_HE_A_CONTROL_RESPONSE_TIME_LSB 16
|
||||
#define RX_RESPONSE_REQUIRED_INFO_HE_A_CONTROL_RESPONSE_TIME_MSB 27
|
||||
#define RX_RESPONSE_REQUIRED_INFO_HE_A_CONTROL_RESPONSE_TIME_MASK 0x000000000fff0000
|
||||
|
||||
#define RX_RESPONSE_REQUIRED_INFO_RESERVED_AFTER_STRUCT16_OFFSET 0x0000000000000038
|
||||
#define RX_RESPONSE_REQUIRED_INFO_RESERVED_AFTER_STRUCT16_LSB 28
|
||||
#define RX_RESPONSE_REQUIRED_INFO_RESERVED_AFTER_STRUCT16_MSB 31
|
||||
#define RX_RESPONSE_REQUIRED_INFO_RESERVED_AFTER_STRUCT16_MASK 0x00000000f0000000
|
||||
|
||||
#define RX_RESPONSE_REQUIRED_INFO_TLV64_PADDING_OFFSET 0x0000000000000038
|
||||
#define RX_RESPONSE_REQUIRED_INFO_TLV64_PADDING_LSB 32
|
||||
#define RX_RESPONSE_REQUIRED_INFO_TLV64_PADDING_MSB 63
|
||||
#define RX_RESPONSE_REQUIRED_INFO_TLV64_PADDING_MASK 0xffffffff00000000
|
||||
|
||||
#endif
|
||||
63
hw/kiwi/v2/rx_start_param.h
Normal file
63
hw/kiwi/v2/rx_start_param.h
Normal file
|
|
@ -0,0 +1,63 @@
|
|||
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
#ifndef _RX_START_PARAM_H_
|
||||
#define _RX_START_PARAM_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#define NUM_OF_DWORDS_RX_START_PARAM 2
|
||||
|
||||
#define NUM_OF_QWORDS_RX_START_PARAM 1
|
||||
|
||||
struct rx_start_param {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t pkt_type : 4,
|
||||
reserved_0a : 12,
|
||||
remaining_rx_time : 16;
|
||||
uint32_t tlv64_padding : 32;
|
||||
#else
|
||||
uint32_t remaining_rx_time : 16,
|
||||
reserved_0a : 12,
|
||||
pkt_type : 4;
|
||||
uint32_t tlv64_padding : 32;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define RX_START_PARAM_PKT_TYPE_OFFSET 0x0000000000000000
|
||||
#define RX_START_PARAM_PKT_TYPE_LSB 0
|
||||
#define RX_START_PARAM_PKT_TYPE_MSB 3
|
||||
#define RX_START_PARAM_PKT_TYPE_MASK 0x000000000000000f
|
||||
|
||||
#define RX_START_PARAM_RESERVED_0A_OFFSET 0x0000000000000000
|
||||
#define RX_START_PARAM_RESERVED_0A_LSB 4
|
||||
#define RX_START_PARAM_RESERVED_0A_MSB 15
|
||||
#define RX_START_PARAM_RESERVED_0A_MASK 0x000000000000fff0
|
||||
|
||||
#define RX_START_PARAM_REMAINING_RX_TIME_OFFSET 0x0000000000000000
|
||||
#define RX_START_PARAM_REMAINING_RX_TIME_LSB 16
|
||||
#define RX_START_PARAM_REMAINING_RX_TIME_MSB 31
|
||||
#define RX_START_PARAM_REMAINING_RX_TIME_MASK 0x00000000ffff0000
|
||||
|
||||
#define RX_START_PARAM_TLV64_PADDING_OFFSET 0x0000000000000000
|
||||
#define RX_START_PARAM_TLV64_PADDING_LSB 32
|
||||
#define RX_START_PARAM_TLV64_PADDING_MSB 63
|
||||
#define RX_START_PARAM_TLV64_PADDING_MASK 0xffffffff00000000
|
||||
|
||||
#endif
|
||||
70
hw/kiwi/v2/rx_trig_info.h
Normal file
70
hw/kiwi/v2/rx_trig_info.h
Normal file
|
|
@ -0,0 +1,70 @@
|
|||
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
#ifndef _RX_TRIG_INFO_H_
|
||||
#define _RX_TRIG_INFO_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#define NUM_OF_DWORDS_RX_TRIG_INFO 2
|
||||
|
||||
#define NUM_OF_QWORDS_RX_TRIG_INFO 1
|
||||
|
||||
struct rx_trig_info {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t rx_trigger_frame_type : 2,
|
||||
trigger_resp_type : 3,
|
||||
reserved_0 : 27;
|
||||
uint32_t ppdu_duration : 16,
|
||||
unique_destination_id : 16;
|
||||
#else
|
||||
uint32_t reserved_0 : 27,
|
||||
trigger_resp_type : 3,
|
||||
rx_trigger_frame_type : 2;
|
||||
uint32_t unique_destination_id : 16,
|
||||
ppdu_duration : 16;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define RX_TRIG_INFO_RX_TRIGGER_FRAME_TYPE_OFFSET 0x0000000000000000
|
||||
#define RX_TRIG_INFO_RX_TRIGGER_FRAME_TYPE_LSB 0
|
||||
#define RX_TRIG_INFO_RX_TRIGGER_FRAME_TYPE_MSB 1
|
||||
#define RX_TRIG_INFO_RX_TRIGGER_FRAME_TYPE_MASK 0x0000000000000003
|
||||
|
||||
#define RX_TRIG_INFO_TRIGGER_RESP_TYPE_OFFSET 0x0000000000000000
|
||||
#define RX_TRIG_INFO_TRIGGER_RESP_TYPE_LSB 2
|
||||
#define RX_TRIG_INFO_TRIGGER_RESP_TYPE_MSB 4
|
||||
#define RX_TRIG_INFO_TRIGGER_RESP_TYPE_MASK 0x000000000000001c
|
||||
|
||||
#define RX_TRIG_INFO_RESERVED_0_OFFSET 0x0000000000000000
|
||||
#define RX_TRIG_INFO_RESERVED_0_LSB 5
|
||||
#define RX_TRIG_INFO_RESERVED_0_MSB 31
|
||||
#define RX_TRIG_INFO_RESERVED_0_MASK 0x00000000ffffffe0
|
||||
|
||||
#define RX_TRIG_INFO_PPDU_DURATION_OFFSET 0x0000000000000000
|
||||
#define RX_TRIG_INFO_PPDU_DURATION_LSB 32
|
||||
#define RX_TRIG_INFO_PPDU_DURATION_MSB 47
|
||||
#define RX_TRIG_INFO_PPDU_DURATION_MASK 0x0000ffff00000000
|
||||
|
||||
#define RX_TRIG_INFO_UNIQUE_DESTINATION_ID_OFFSET 0x0000000000000000
|
||||
#define RX_TRIG_INFO_UNIQUE_DESTINATION_ID_LSB 48
|
||||
#define RX_TRIG_INFO_UNIQUE_DESTINATION_ID_MSB 63
|
||||
#define RX_TRIG_INFO_UNIQUE_DESTINATION_ID_MASK 0xffff000000000000
|
||||
|
||||
#endif
|
||||
77
hw/kiwi/v2/rxpcu_early_rx_indication.h
Normal file
77
hw/kiwi/v2/rxpcu_early_rx_indication.h
Normal file
|
|
@ -0,0 +1,77 @@
|
|||
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
#ifndef _RXPCU_EARLY_RX_INDICATION_H_
|
||||
#define _RXPCU_EARLY_RX_INDICATION_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#define NUM_OF_DWORDS_RXPCU_EARLY_RX_INDICATION 2
|
||||
|
||||
#define NUM_OF_QWORDS_RXPCU_EARLY_RX_INDICATION 1
|
||||
|
||||
struct rxpcu_early_rx_indication {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t pkt_type : 4,
|
||||
dot11ax_su_extended : 1,
|
||||
rate_mcs : 4,
|
||||
dot11ax_received_ext_ru_size : 4,
|
||||
reserved_0a : 19;
|
||||
uint32_t tlv64_padding : 32;
|
||||
#else
|
||||
uint32_t reserved_0a : 19,
|
||||
dot11ax_received_ext_ru_size : 4,
|
||||
rate_mcs : 4,
|
||||
dot11ax_su_extended : 1,
|
||||
pkt_type : 4;
|
||||
uint32_t tlv64_padding : 32;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define RXPCU_EARLY_RX_INDICATION_PKT_TYPE_OFFSET 0x0000000000000000
|
||||
#define RXPCU_EARLY_RX_INDICATION_PKT_TYPE_LSB 0
|
||||
#define RXPCU_EARLY_RX_INDICATION_PKT_TYPE_MSB 3
|
||||
#define RXPCU_EARLY_RX_INDICATION_PKT_TYPE_MASK 0x000000000000000f
|
||||
|
||||
#define RXPCU_EARLY_RX_INDICATION_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000000
|
||||
#define RXPCU_EARLY_RX_INDICATION_DOT11AX_SU_EXTENDED_LSB 4
|
||||
#define RXPCU_EARLY_RX_INDICATION_DOT11AX_SU_EXTENDED_MSB 4
|
||||
#define RXPCU_EARLY_RX_INDICATION_DOT11AX_SU_EXTENDED_MASK 0x0000000000000010
|
||||
|
||||
#define RXPCU_EARLY_RX_INDICATION_RATE_MCS_OFFSET 0x0000000000000000
|
||||
#define RXPCU_EARLY_RX_INDICATION_RATE_MCS_LSB 5
|
||||
#define RXPCU_EARLY_RX_INDICATION_RATE_MCS_MSB 8
|
||||
#define RXPCU_EARLY_RX_INDICATION_RATE_MCS_MASK 0x00000000000001e0
|
||||
|
||||
#define RXPCU_EARLY_RX_INDICATION_DOT11AX_RECEIVED_EXT_RU_SIZE_OFFSET 0x0000000000000000
|
||||
#define RXPCU_EARLY_RX_INDICATION_DOT11AX_RECEIVED_EXT_RU_SIZE_LSB 9
|
||||
#define RXPCU_EARLY_RX_INDICATION_DOT11AX_RECEIVED_EXT_RU_SIZE_MSB 12
|
||||
#define RXPCU_EARLY_RX_INDICATION_DOT11AX_RECEIVED_EXT_RU_SIZE_MASK 0x0000000000001e00
|
||||
|
||||
#define RXPCU_EARLY_RX_INDICATION_RESERVED_0A_OFFSET 0x0000000000000000
|
||||
#define RXPCU_EARLY_RX_INDICATION_RESERVED_0A_LSB 13
|
||||
#define RXPCU_EARLY_RX_INDICATION_RESERVED_0A_MSB 31
|
||||
#define RXPCU_EARLY_RX_INDICATION_RESERVED_0A_MASK 0x00000000ffffe000
|
||||
|
||||
#define RXPCU_EARLY_RX_INDICATION_TLV64_PADDING_OFFSET 0x0000000000000000
|
||||
#define RXPCU_EARLY_RX_INDICATION_TLV64_PADDING_LSB 32
|
||||
#define RXPCU_EARLY_RX_INDICATION_TLV64_PADDING_MSB 63
|
||||
#define RXPCU_EARLY_RX_INDICATION_TLV64_PADDING_MASK 0xffffffff00000000
|
||||
|
||||
#endif
|
||||
464
hw/kiwi/v2/tx_cbf_info.h
Normal file
464
hw/kiwi/v2/tx_cbf_info.h
Normal file
|
|
@ -0,0 +1,464 @@
|
|||
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
#ifndef _TX_CBF_INFO_H_
|
||||
#define _TX_CBF_INFO_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#define NUM_OF_DWORDS_TX_CBF_INFO 16
|
||||
|
||||
#define NUM_OF_QWORDS_TX_CBF_INFO 8
|
||||
|
||||
struct tx_cbf_info {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t sw_peer_id : 16,
|
||||
pre_cbf_duration : 16;
|
||||
uint32_t brpoll_info_valid : 1,
|
||||
trigger_brpoll_info_valid : 1,
|
||||
npda_info_11ac_valid : 1,
|
||||
npda_info_11ax_valid : 1,
|
||||
dot11ax_su_extended : 1,
|
||||
bandwidth : 3,
|
||||
brpoll_info : 8,
|
||||
cbf_response_table_base_index : 8,
|
||||
peer_index : 3,
|
||||
pkt_type : 4,
|
||||
txop_duration_all_ones : 1;
|
||||
uint32_t trigger_brpoll_common_info_15_0 : 16,
|
||||
trigger_brpoll_common_info_31_16 : 16;
|
||||
uint32_t trigger_brpoll_user_info_15_0 : 16,
|
||||
trigger_brpoll_user_info_31_16 : 16;
|
||||
uint32_t addr1_31_0 : 32;
|
||||
uint32_t addr1_47_32 : 16,
|
||||
addr2_15_0 : 16;
|
||||
uint32_t addr2_47_16 : 32;
|
||||
uint32_t addr3_31_0 : 32;
|
||||
uint32_t addr3_47_32 : 16,
|
||||
sta_partial_aid : 11,
|
||||
reserved_8a : 4,
|
||||
cbf_resp_pwr_mgmt : 1;
|
||||
uint32_t group_id : 6,
|
||||
rssi_comb : 8,
|
||||
reserved_9a : 2,
|
||||
vht_ndpa_sta_info : 16;
|
||||
uint32_t he_eht_sta_info_15_0 : 16,
|
||||
he_eht_sta_info_31_16 : 16;
|
||||
uint32_t dot11ax_received_format_indication : 1,
|
||||
dot11ax_received_dl_ul_flag : 1,
|
||||
dot11ax_received_bss_color_id : 6,
|
||||
dot11ax_received_spatial_reuse : 4,
|
||||
dot11ax_received_cp_size : 2,
|
||||
dot11ax_received_ltf_size : 2,
|
||||
dot11ax_received_coding : 1,
|
||||
dot11ax_received_dcm : 1,
|
||||
dot11ax_received_doppler_indication : 1,
|
||||
dot11ax_received_ext_ru_size : 4,
|
||||
dot11ax_dl_ul_flag : 1,
|
||||
reserved_11a : 8;
|
||||
uint32_t sw_response_frame_length : 16,
|
||||
sw_response_tlv_from_crypto : 1,
|
||||
wait_sifs_config_valid : 1,
|
||||
wait_sifs : 2,
|
||||
__reserved_g_0005 : 1,
|
||||
secure : 1,
|
||||
tb___reserved_g_0005_response_required : 2,
|
||||
reserved_12a : 2,
|
||||
u_sig_puncture_pattern_encoding : 6;
|
||||
uint32_t dot11be_puncture_bitmap : 16,
|
||||
dot11be_response : 1,
|
||||
punctured_response : 1,
|
||||
npda_info_11be_valid : 1,
|
||||
eht_duplicate_mode : 2,
|
||||
reserved_13a : 11;
|
||||
uint32_t eht_sta_info_39_32 : 8,
|
||||
reserved_14a : 24;
|
||||
uint32_t tlv64_padding : 32;
|
||||
#else
|
||||
uint32_t pre_cbf_duration : 16,
|
||||
sw_peer_id : 16;
|
||||
uint32_t txop_duration_all_ones : 1,
|
||||
pkt_type : 4,
|
||||
peer_index : 3,
|
||||
cbf_response_table_base_index : 8,
|
||||
brpoll_info : 8,
|
||||
bandwidth : 3,
|
||||
dot11ax_su_extended : 1,
|
||||
npda_info_11ax_valid : 1,
|
||||
npda_info_11ac_valid : 1,
|
||||
trigger_brpoll_info_valid : 1,
|
||||
brpoll_info_valid : 1;
|
||||
uint32_t trigger_brpoll_common_info_31_16 : 16,
|
||||
trigger_brpoll_common_info_15_0 : 16;
|
||||
uint32_t trigger_brpoll_user_info_31_16 : 16,
|
||||
trigger_brpoll_user_info_15_0 : 16;
|
||||
uint32_t addr1_31_0 : 32;
|
||||
uint32_t addr2_15_0 : 16,
|
||||
addr1_47_32 : 16;
|
||||
uint32_t addr2_47_16 : 32;
|
||||
uint32_t addr3_31_0 : 32;
|
||||
uint32_t cbf_resp_pwr_mgmt : 1,
|
||||
reserved_8a : 4,
|
||||
sta_partial_aid : 11,
|
||||
addr3_47_32 : 16;
|
||||
uint32_t vht_ndpa_sta_info : 16,
|
||||
reserved_9a : 2,
|
||||
rssi_comb : 8,
|
||||
group_id : 6;
|
||||
uint32_t he_eht_sta_info_31_16 : 16,
|
||||
he_eht_sta_info_15_0 : 16;
|
||||
uint32_t reserved_11a : 8,
|
||||
dot11ax_dl_ul_flag : 1,
|
||||
dot11ax_received_ext_ru_size : 4,
|
||||
dot11ax_received_doppler_indication : 1,
|
||||
dot11ax_received_dcm : 1,
|
||||
dot11ax_received_coding : 1,
|
||||
dot11ax_received_ltf_size : 2,
|
||||
dot11ax_received_cp_size : 2,
|
||||
dot11ax_received_spatial_reuse : 4,
|
||||
dot11ax_received_bss_color_id : 6,
|
||||
dot11ax_received_dl_ul_flag : 1,
|
||||
dot11ax_received_format_indication : 1;
|
||||
uint32_t u_sig_puncture_pattern_encoding : 6,
|
||||
reserved_12a : 2,
|
||||
tb___reserved_g_0005_response_required : 2,
|
||||
secure : 1,
|
||||
__reserved_g_0005 : 1,
|
||||
wait_sifs : 2,
|
||||
wait_sifs_config_valid : 1,
|
||||
sw_response_tlv_from_crypto : 1,
|
||||
sw_response_frame_length : 16;
|
||||
uint32_t reserved_13a : 11,
|
||||
eht_duplicate_mode : 2,
|
||||
npda_info_11be_valid : 1,
|
||||
punctured_response : 1,
|
||||
dot11be_response : 1,
|
||||
dot11be_puncture_bitmap : 16;
|
||||
uint32_t reserved_14a : 24,
|
||||
eht_sta_info_39_32 : 8;
|
||||
uint32_t tlv64_padding : 32;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define TX_CBF_INFO_SW_PEER_ID_OFFSET 0x0000000000000000
|
||||
#define TX_CBF_INFO_SW_PEER_ID_LSB 0
|
||||
#define TX_CBF_INFO_SW_PEER_ID_MSB 15
|
||||
#define TX_CBF_INFO_SW_PEER_ID_MASK 0x000000000000ffff
|
||||
|
||||
#define TX_CBF_INFO_PRE_CBF_DURATION_OFFSET 0x0000000000000000
|
||||
#define TX_CBF_INFO_PRE_CBF_DURATION_LSB 16
|
||||
#define TX_CBF_INFO_PRE_CBF_DURATION_MSB 31
|
||||
#define TX_CBF_INFO_PRE_CBF_DURATION_MASK 0x00000000ffff0000
|
||||
|
||||
#define TX_CBF_INFO_BRPOLL_INFO_VALID_OFFSET 0x0000000000000000
|
||||
#define TX_CBF_INFO_BRPOLL_INFO_VALID_LSB 32
|
||||
#define TX_CBF_INFO_BRPOLL_INFO_VALID_MSB 32
|
||||
#define TX_CBF_INFO_BRPOLL_INFO_VALID_MASK 0x0000000100000000
|
||||
|
||||
#define TX_CBF_INFO_TRIGGER_BRPOLL_INFO_VALID_OFFSET 0x0000000000000000
|
||||
#define TX_CBF_INFO_TRIGGER_BRPOLL_INFO_VALID_LSB 33
|
||||
#define TX_CBF_INFO_TRIGGER_BRPOLL_INFO_VALID_MSB 33
|
||||
#define TX_CBF_INFO_TRIGGER_BRPOLL_INFO_VALID_MASK 0x0000000200000000
|
||||
|
||||
#define TX_CBF_INFO_NPDA_INFO_11AC_VALID_OFFSET 0x0000000000000000
|
||||
#define TX_CBF_INFO_NPDA_INFO_11AC_VALID_LSB 34
|
||||
#define TX_CBF_INFO_NPDA_INFO_11AC_VALID_MSB 34
|
||||
#define TX_CBF_INFO_NPDA_INFO_11AC_VALID_MASK 0x0000000400000000
|
||||
|
||||
#define TX_CBF_INFO_NPDA_INFO_11AX_VALID_OFFSET 0x0000000000000000
|
||||
#define TX_CBF_INFO_NPDA_INFO_11AX_VALID_LSB 35
|
||||
#define TX_CBF_INFO_NPDA_INFO_11AX_VALID_MSB 35
|
||||
#define TX_CBF_INFO_NPDA_INFO_11AX_VALID_MASK 0x0000000800000000
|
||||
|
||||
#define TX_CBF_INFO_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000000
|
||||
#define TX_CBF_INFO_DOT11AX_SU_EXTENDED_LSB 36
|
||||
#define TX_CBF_INFO_DOT11AX_SU_EXTENDED_MSB 36
|
||||
#define TX_CBF_INFO_DOT11AX_SU_EXTENDED_MASK 0x0000001000000000
|
||||
|
||||
#define TX_CBF_INFO_BANDWIDTH_OFFSET 0x0000000000000000
|
||||
#define TX_CBF_INFO_BANDWIDTH_LSB 37
|
||||
#define TX_CBF_INFO_BANDWIDTH_MSB 39
|
||||
#define TX_CBF_INFO_BANDWIDTH_MASK 0x000000e000000000
|
||||
|
||||
#define TX_CBF_INFO_BRPOLL_INFO_OFFSET 0x0000000000000000
|
||||
#define TX_CBF_INFO_BRPOLL_INFO_LSB 40
|
||||
#define TX_CBF_INFO_BRPOLL_INFO_MSB 47
|
||||
#define TX_CBF_INFO_BRPOLL_INFO_MASK 0x0000ff0000000000
|
||||
|
||||
#define TX_CBF_INFO_CBF_RESPONSE_TABLE_BASE_INDEX_OFFSET 0x0000000000000000
|
||||
#define TX_CBF_INFO_CBF_RESPONSE_TABLE_BASE_INDEX_LSB 48
|
||||
#define TX_CBF_INFO_CBF_RESPONSE_TABLE_BASE_INDEX_MSB 55
|
||||
#define TX_CBF_INFO_CBF_RESPONSE_TABLE_BASE_INDEX_MASK 0x00ff000000000000
|
||||
|
||||
#define TX_CBF_INFO_PEER_INDEX_OFFSET 0x0000000000000000
|
||||
#define TX_CBF_INFO_PEER_INDEX_LSB 56
|
||||
#define TX_CBF_INFO_PEER_INDEX_MSB 58
|
||||
#define TX_CBF_INFO_PEER_INDEX_MASK 0x0700000000000000
|
||||
|
||||
#define TX_CBF_INFO_PKT_TYPE_OFFSET 0x0000000000000000
|
||||
#define TX_CBF_INFO_PKT_TYPE_LSB 59
|
||||
#define TX_CBF_INFO_PKT_TYPE_MSB 62
|
||||
#define TX_CBF_INFO_PKT_TYPE_MASK 0x7800000000000000
|
||||
|
||||
#define TX_CBF_INFO_TXOP_DURATION_ALL_ONES_OFFSET 0x0000000000000000
|
||||
#define TX_CBF_INFO_TXOP_DURATION_ALL_ONES_LSB 63
|
||||
#define TX_CBF_INFO_TXOP_DURATION_ALL_ONES_MSB 63
|
||||
#define TX_CBF_INFO_TXOP_DURATION_ALL_ONES_MASK 0x8000000000000000
|
||||
|
||||
#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_15_0_OFFSET 0x0000000000000008
|
||||
#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_15_0_LSB 0
|
||||
#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_15_0_MSB 15
|
||||
#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_15_0_MASK 0x000000000000ffff
|
||||
|
||||
#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_31_16_OFFSET 0x0000000000000008
|
||||
#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_31_16_LSB 16
|
||||
#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_31_16_MSB 31
|
||||
#define TX_CBF_INFO_TRIGGER_BRPOLL_COMMON_INFO_31_16_MASK 0x00000000ffff0000
|
||||
|
||||
#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_15_0_OFFSET 0x0000000000000008
|
||||
#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_15_0_LSB 32
|
||||
#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_15_0_MSB 47
|
||||
#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_15_0_MASK 0x0000ffff00000000
|
||||
|
||||
#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_31_16_OFFSET 0x0000000000000008
|
||||
#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_31_16_LSB 48
|
||||
#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_31_16_MSB 63
|
||||
#define TX_CBF_INFO_TRIGGER_BRPOLL_USER_INFO_31_16_MASK 0xffff000000000000
|
||||
|
||||
#define TX_CBF_INFO_ADDR1_31_0_OFFSET 0x0000000000000010
|
||||
#define TX_CBF_INFO_ADDR1_31_0_LSB 0
|
||||
#define TX_CBF_INFO_ADDR1_31_0_MSB 31
|
||||
#define TX_CBF_INFO_ADDR1_31_0_MASK 0x00000000ffffffff
|
||||
|
||||
#define TX_CBF_INFO_ADDR1_47_32_OFFSET 0x0000000000000010
|
||||
#define TX_CBF_INFO_ADDR1_47_32_LSB 32
|
||||
#define TX_CBF_INFO_ADDR1_47_32_MSB 47
|
||||
#define TX_CBF_INFO_ADDR1_47_32_MASK 0x0000ffff00000000
|
||||
|
||||
#define TX_CBF_INFO_ADDR2_15_0_OFFSET 0x0000000000000010
|
||||
#define TX_CBF_INFO_ADDR2_15_0_LSB 48
|
||||
#define TX_CBF_INFO_ADDR2_15_0_MSB 63
|
||||
#define TX_CBF_INFO_ADDR2_15_0_MASK 0xffff000000000000
|
||||
|
||||
#define TX_CBF_INFO_ADDR2_47_16_OFFSET 0x0000000000000018
|
||||
#define TX_CBF_INFO_ADDR2_47_16_LSB 0
|
||||
#define TX_CBF_INFO_ADDR2_47_16_MSB 31
|
||||
#define TX_CBF_INFO_ADDR2_47_16_MASK 0x00000000ffffffff
|
||||
|
||||
#define TX_CBF_INFO_ADDR3_31_0_OFFSET 0x0000000000000018
|
||||
#define TX_CBF_INFO_ADDR3_31_0_LSB 32
|
||||
#define TX_CBF_INFO_ADDR3_31_0_MSB 63
|
||||
#define TX_CBF_INFO_ADDR3_31_0_MASK 0xffffffff00000000
|
||||
|
||||
#define TX_CBF_INFO_ADDR3_47_32_OFFSET 0x0000000000000020
|
||||
#define TX_CBF_INFO_ADDR3_47_32_LSB 0
|
||||
#define TX_CBF_INFO_ADDR3_47_32_MSB 15
|
||||
#define TX_CBF_INFO_ADDR3_47_32_MASK 0x000000000000ffff
|
||||
|
||||
#define TX_CBF_INFO_STA_PARTIAL_AID_OFFSET 0x0000000000000020
|
||||
#define TX_CBF_INFO_STA_PARTIAL_AID_LSB 16
|
||||
#define TX_CBF_INFO_STA_PARTIAL_AID_MSB 26
|
||||
#define TX_CBF_INFO_STA_PARTIAL_AID_MASK 0x0000000007ff0000
|
||||
|
||||
#define TX_CBF_INFO_RESERVED_8A_OFFSET 0x0000000000000020
|
||||
#define TX_CBF_INFO_RESERVED_8A_LSB 27
|
||||
#define TX_CBF_INFO_RESERVED_8A_MSB 30
|
||||
#define TX_CBF_INFO_RESERVED_8A_MASK 0x0000000078000000
|
||||
|
||||
#define TX_CBF_INFO_CBF_RESP_PWR_MGMT_OFFSET 0x0000000000000020
|
||||
#define TX_CBF_INFO_CBF_RESP_PWR_MGMT_LSB 31
|
||||
#define TX_CBF_INFO_CBF_RESP_PWR_MGMT_MSB 31
|
||||
#define TX_CBF_INFO_CBF_RESP_PWR_MGMT_MASK 0x0000000080000000
|
||||
|
||||
#define TX_CBF_INFO_GROUP_ID_OFFSET 0x0000000000000020
|
||||
#define TX_CBF_INFO_GROUP_ID_LSB 32
|
||||
#define TX_CBF_INFO_GROUP_ID_MSB 37
|
||||
#define TX_CBF_INFO_GROUP_ID_MASK 0x0000003f00000000
|
||||
|
||||
#define TX_CBF_INFO_RSSI_COMB_OFFSET 0x0000000000000020
|
||||
#define TX_CBF_INFO_RSSI_COMB_LSB 38
|
||||
#define TX_CBF_INFO_RSSI_COMB_MSB 45
|
||||
#define TX_CBF_INFO_RSSI_COMB_MASK 0x00003fc000000000
|
||||
|
||||
#define TX_CBF_INFO_RESERVED_9A_OFFSET 0x0000000000000020
|
||||
#define TX_CBF_INFO_RESERVED_9A_LSB 46
|
||||
#define TX_CBF_INFO_RESERVED_9A_MSB 47
|
||||
#define TX_CBF_INFO_RESERVED_9A_MASK 0x0000c00000000000
|
||||
|
||||
#define TX_CBF_INFO_VHT_NDPA_STA_INFO_OFFSET 0x0000000000000020
|
||||
#define TX_CBF_INFO_VHT_NDPA_STA_INFO_LSB 48
|
||||
#define TX_CBF_INFO_VHT_NDPA_STA_INFO_MSB 63
|
||||
#define TX_CBF_INFO_VHT_NDPA_STA_INFO_MASK 0xffff000000000000
|
||||
|
||||
#define TX_CBF_INFO_HE_EHT_STA_INFO_15_0_OFFSET 0x0000000000000028
|
||||
#define TX_CBF_INFO_HE_EHT_STA_INFO_15_0_LSB 0
|
||||
#define TX_CBF_INFO_HE_EHT_STA_INFO_15_0_MSB 15
|
||||
#define TX_CBF_INFO_HE_EHT_STA_INFO_15_0_MASK 0x000000000000ffff
|
||||
|
||||
#define TX_CBF_INFO_HE_EHT_STA_INFO_31_16_OFFSET 0x0000000000000028
|
||||
#define TX_CBF_INFO_HE_EHT_STA_INFO_31_16_LSB 16
|
||||
#define TX_CBF_INFO_HE_EHT_STA_INFO_31_16_MSB 31
|
||||
#define TX_CBF_INFO_HE_EHT_STA_INFO_31_16_MASK 0x00000000ffff0000
|
||||
|
||||
#define TX_CBF_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_OFFSET 0x0000000000000028
|
||||
#define TX_CBF_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_LSB 32
|
||||
#define TX_CBF_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_MSB 32
|
||||
#define TX_CBF_INFO_DOT11AX_RECEIVED_FORMAT_INDICATION_MASK 0x0000000100000000
|
||||
|
||||
#define TX_CBF_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_OFFSET 0x0000000000000028
|
||||
#define TX_CBF_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_LSB 33
|
||||
#define TX_CBF_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_MSB 33
|
||||
#define TX_CBF_INFO_DOT11AX_RECEIVED_DL_UL_FLAG_MASK 0x0000000200000000
|
||||
|
||||
#define TX_CBF_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_OFFSET 0x0000000000000028
|
||||
#define TX_CBF_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_LSB 34
|
||||
#define TX_CBF_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_MSB 39
|
||||
#define TX_CBF_INFO_DOT11AX_RECEIVED_BSS_COLOR_ID_MASK 0x000000fc00000000
|
||||
|
||||
#define TX_CBF_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_OFFSET 0x0000000000000028
|
||||
#define TX_CBF_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_LSB 40
|
||||
#define TX_CBF_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_MSB 43
|
||||
#define TX_CBF_INFO_DOT11AX_RECEIVED_SPATIAL_REUSE_MASK 0x00000f0000000000
|
||||
|
||||
#define TX_CBF_INFO_DOT11AX_RECEIVED_CP_SIZE_OFFSET 0x0000000000000028
|
||||
#define TX_CBF_INFO_DOT11AX_RECEIVED_CP_SIZE_LSB 44
|
||||
#define TX_CBF_INFO_DOT11AX_RECEIVED_CP_SIZE_MSB 45
|
||||
#define TX_CBF_INFO_DOT11AX_RECEIVED_CP_SIZE_MASK 0x0000300000000000
|
||||
|
||||
#define TX_CBF_INFO_DOT11AX_RECEIVED_LTF_SIZE_OFFSET 0x0000000000000028
|
||||
#define TX_CBF_INFO_DOT11AX_RECEIVED_LTF_SIZE_LSB 46
|
||||
#define TX_CBF_INFO_DOT11AX_RECEIVED_LTF_SIZE_MSB 47
|
||||
#define TX_CBF_INFO_DOT11AX_RECEIVED_LTF_SIZE_MASK 0x0000c00000000000
|
||||
|
||||
#define TX_CBF_INFO_DOT11AX_RECEIVED_CODING_OFFSET 0x0000000000000028
|
||||
#define TX_CBF_INFO_DOT11AX_RECEIVED_CODING_LSB 48
|
||||
#define TX_CBF_INFO_DOT11AX_RECEIVED_CODING_MSB 48
|
||||
#define TX_CBF_INFO_DOT11AX_RECEIVED_CODING_MASK 0x0001000000000000
|
||||
|
||||
#define TX_CBF_INFO_DOT11AX_RECEIVED_DCM_OFFSET 0x0000000000000028
|
||||
#define TX_CBF_INFO_DOT11AX_RECEIVED_DCM_LSB 49
|
||||
#define TX_CBF_INFO_DOT11AX_RECEIVED_DCM_MSB 49
|
||||
#define TX_CBF_INFO_DOT11AX_RECEIVED_DCM_MASK 0x0002000000000000
|
||||
|
||||
#define TX_CBF_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_OFFSET 0x0000000000000028
|
||||
#define TX_CBF_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_LSB 50
|
||||
#define TX_CBF_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_MSB 50
|
||||
#define TX_CBF_INFO_DOT11AX_RECEIVED_DOPPLER_INDICATION_MASK 0x0004000000000000
|
||||
|
||||
#define TX_CBF_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_OFFSET 0x0000000000000028
|
||||
#define TX_CBF_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_LSB 51
|
||||
#define TX_CBF_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_MSB 54
|
||||
#define TX_CBF_INFO_DOT11AX_RECEIVED_EXT_RU_SIZE_MASK 0x0078000000000000
|
||||
|
||||
#define TX_CBF_INFO_DOT11AX_DL_UL_FLAG_OFFSET 0x0000000000000028
|
||||
#define TX_CBF_INFO_DOT11AX_DL_UL_FLAG_LSB 55
|
||||
#define TX_CBF_INFO_DOT11AX_DL_UL_FLAG_MSB 55
|
||||
#define TX_CBF_INFO_DOT11AX_DL_UL_FLAG_MASK 0x0080000000000000
|
||||
|
||||
#define TX_CBF_INFO_RESERVED_11A_OFFSET 0x0000000000000028
|
||||
#define TX_CBF_INFO_RESERVED_11A_LSB 56
|
||||
#define TX_CBF_INFO_RESERVED_11A_MSB 63
|
||||
#define TX_CBF_INFO_RESERVED_11A_MASK 0xff00000000000000
|
||||
|
||||
#define TX_CBF_INFO_SW_RESPONSE_FRAME_LENGTH_OFFSET 0x0000000000000030
|
||||
#define TX_CBF_INFO_SW_RESPONSE_FRAME_LENGTH_LSB 0
|
||||
#define TX_CBF_INFO_SW_RESPONSE_FRAME_LENGTH_MSB 15
|
||||
#define TX_CBF_INFO_SW_RESPONSE_FRAME_LENGTH_MASK 0x000000000000ffff
|
||||
|
||||
#define TX_CBF_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_OFFSET 0x0000000000000030
|
||||
#define TX_CBF_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_LSB 16
|
||||
#define TX_CBF_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_MSB 16
|
||||
#define TX_CBF_INFO_SW_RESPONSE_TLV_FROM_CRYPTO_MASK 0x0000000000010000
|
||||
|
||||
#define TX_CBF_INFO_WAIT_SIFS_CONFIG_VALID_OFFSET 0x0000000000000030
|
||||
#define TX_CBF_INFO_WAIT_SIFS_CONFIG_VALID_LSB 17
|
||||
#define TX_CBF_INFO_WAIT_SIFS_CONFIG_VALID_MSB 17
|
||||
#define TX_CBF_INFO_WAIT_SIFS_CONFIG_VALID_MASK 0x0000000000020000
|
||||
|
||||
#define TX_CBF_INFO_WAIT_SIFS_OFFSET 0x0000000000000030
|
||||
#define TX_CBF_INFO_WAIT_SIFS_LSB 18
|
||||
#define TX_CBF_INFO_WAIT_SIFS_MSB 19
|
||||
#define TX_CBF_INFO_WAIT_SIFS_MASK 0x00000000000c0000
|
||||
|
||||
#define TX_CBF_INFO_SECURE_OFFSET 0x0000000000000030
|
||||
#define TX_CBF_INFO_SECURE_LSB 21
|
||||
#define TX_CBF_INFO_SECURE_MSB 21
|
||||
#define TX_CBF_INFO_SECURE_MASK 0x0000000000200000
|
||||
|
||||
#define TX_CBF_INFO_TB_RANGING_RESPONSE_REQUIRED_OFFSET 0x0000000000000030
|
||||
#define TX_CBF_INFO_TB_RANGING_RESPONSE_REQUIRED_LSB 22
|
||||
#define TX_CBF_INFO_TB_RANGING_RESPONSE_REQUIRED_MSB 23
|
||||
#define TX_CBF_INFO_TB_RANGING_RESPONSE_REQUIRED_MASK 0x0000000000c00000
|
||||
|
||||
#define TX_CBF_INFO_RESERVED_12A_OFFSET 0x0000000000000030
|
||||
#define TX_CBF_INFO_RESERVED_12A_LSB 24
|
||||
#define TX_CBF_INFO_RESERVED_12A_MSB 25
|
||||
#define TX_CBF_INFO_RESERVED_12A_MASK 0x0000000003000000
|
||||
|
||||
#define TX_CBF_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_OFFSET 0x0000000000000030
|
||||
#define TX_CBF_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_LSB 26
|
||||
#define TX_CBF_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MSB 31
|
||||
#define TX_CBF_INFO_U_SIG_PUNCTURE_PATTERN_ENCODING_MASK 0x00000000fc000000
|
||||
|
||||
#define TX_CBF_INFO_DOT11BE_PUNCTURE_BITMAP_OFFSET 0x0000000000000030
|
||||
#define TX_CBF_INFO_DOT11BE_PUNCTURE_BITMAP_LSB 32
|
||||
#define TX_CBF_INFO_DOT11BE_PUNCTURE_BITMAP_MSB 47
|
||||
#define TX_CBF_INFO_DOT11BE_PUNCTURE_BITMAP_MASK 0x0000ffff00000000
|
||||
|
||||
#define TX_CBF_INFO_DOT11BE_RESPONSE_OFFSET 0x0000000000000030
|
||||
#define TX_CBF_INFO_DOT11BE_RESPONSE_LSB 48
|
||||
#define TX_CBF_INFO_DOT11BE_RESPONSE_MSB 48
|
||||
#define TX_CBF_INFO_DOT11BE_RESPONSE_MASK 0x0001000000000000
|
||||
|
||||
#define TX_CBF_INFO_PUNCTURED_RESPONSE_OFFSET 0x0000000000000030
|
||||
#define TX_CBF_INFO_PUNCTURED_RESPONSE_LSB 49
|
||||
#define TX_CBF_INFO_PUNCTURED_RESPONSE_MSB 49
|
||||
#define TX_CBF_INFO_PUNCTURED_RESPONSE_MASK 0x0002000000000000
|
||||
|
||||
#define TX_CBF_INFO_NPDA_INFO_11BE_VALID_OFFSET 0x0000000000000030
|
||||
#define TX_CBF_INFO_NPDA_INFO_11BE_VALID_LSB 50
|
||||
#define TX_CBF_INFO_NPDA_INFO_11BE_VALID_MSB 50
|
||||
#define TX_CBF_INFO_NPDA_INFO_11BE_VALID_MASK 0x0004000000000000
|
||||
|
||||
#define TX_CBF_INFO_EHT_DUPLICATE_MODE_OFFSET 0x0000000000000030
|
||||
#define TX_CBF_INFO_EHT_DUPLICATE_MODE_LSB 51
|
||||
#define TX_CBF_INFO_EHT_DUPLICATE_MODE_MSB 52
|
||||
#define TX_CBF_INFO_EHT_DUPLICATE_MODE_MASK 0x0018000000000000
|
||||
|
||||
#define TX_CBF_INFO_RESERVED_13A_OFFSET 0x0000000000000030
|
||||
#define TX_CBF_INFO_RESERVED_13A_LSB 53
|
||||
#define TX_CBF_INFO_RESERVED_13A_MSB 63
|
||||
#define TX_CBF_INFO_RESERVED_13A_MASK 0xffe0000000000000
|
||||
|
||||
#define TX_CBF_INFO_EHT_STA_INFO_39_32_OFFSET 0x0000000000000038
|
||||
#define TX_CBF_INFO_EHT_STA_INFO_39_32_LSB 0
|
||||
#define TX_CBF_INFO_EHT_STA_INFO_39_32_MSB 7
|
||||
#define TX_CBF_INFO_EHT_STA_INFO_39_32_MASK 0x00000000000000ff
|
||||
|
||||
#define TX_CBF_INFO_RESERVED_14A_OFFSET 0x0000000000000038
|
||||
#define TX_CBF_INFO_RESERVED_14A_LSB 8
|
||||
#define TX_CBF_INFO_RESERVED_14A_MSB 31
|
||||
#define TX_CBF_INFO_RESERVED_14A_MASK 0x00000000ffffff00
|
||||
|
||||
#define TX_CBF_INFO_TLV64_PADDING_OFFSET 0x0000000000000038
|
||||
#define TX_CBF_INFO_TLV64_PADDING_LSB 32
|
||||
#define TX_CBF_INFO_TLV64_PADDING_MSB 63
|
||||
#define TX_CBF_INFO_TLV64_PADDING_MASK 0xffffffff00000000
|
||||
|
||||
#endif
|
||||
487
hw/kiwi/v2/tx_fes_setup.h
Normal file
487
hw/kiwi/v2/tx_fes_setup.h
Normal file
|
|
@ -0,0 +1,487 @@
|
|||
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
#ifndef _TX_FES_SETUP_H_
|
||||
#define _TX_FES_SETUP_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#define NUM_OF_DWORDS_TX_FES_SETUP 10
|
||||
|
||||
#define NUM_OF_QWORDS_TX_FES_SETUP 5
|
||||
|
||||
struct tx_fes_setup {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t schedule_id : 32;
|
||||
uint32_t fes_in_11ax_trigger_response_config : 1,
|
||||
bo_based_tid_aggregation_limit : 4,
|
||||
__reserved_g_0005 : 1,
|
||||
expect_i2r_lmr : 1,
|
||||
transmit_start_reason : 3,
|
||||
use_alt_power_sr : 1,
|
||||
static_2_pwr_mode_status : 1,
|
||||
obss_srg_opport_transmit_status : 1,
|
||||
srp_based_transmit_status : 1,
|
||||
obss_pd_based_transmit_status : 1,
|
||||
puncture_from_all_allowed_modes : 1,
|
||||
schedule_cmd_ring_id : 5,
|
||||
fes_control_mode : 2,
|
||||
number_of_users : 6,
|
||||
mu_type : 1,
|
||||
ofdma_triggered_response : 1,
|
||||
response_to_response_cmd : 1;
|
||||
uint32_t schedule_try : 4,
|
||||
ndp_frame : 2,
|
||||
txbf : 1,
|
||||
allow_txop_exceed_in_1st_pkt : 1,
|
||||
ignore_bw_available : 1,
|
||||
ignore_tbtt : 1,
|
||||
static_bandwidth : 3,
|
||||
set_txop_duration_all_ones : 1,
|
||||
transmission_contains_mu_rts : 1,
|
||||
bw_restricted_frames_embedded : 1,
|
||||
ast_index : 16;
|
||||
uint32_t cv_id : 8,
|
||||
trigger_resp_txpdu_ppdu_boundary : 2,
|
||||
rxpcu_setup_complete_present : 1,
|
||||
rbo_must_have_data_user_limit : 4,
|
||||
mu_ndp : 1,
|
||||
bf_type : 2,
|
||||
cbf_nc_index_mask : 1,
|
||||
cbf_nc_index : 3,
|
||||
cbf_nr_index_mask : 1,
|
||||
cbf_nr_index : 3,
|
||||
secure___reserved_g_0005_ista : 1,
|
||||
ndpa : 1,
|
||||
wait_sifs : 2,
|
||||
cbf_feedback_type_mask : 1,
|
||||
cbf_feedback_type : 1;
|
||||
uint32_t cbf_sounding_token : 6,
|
||||
cbf_sounding_token_mask : 1,
|
||||
cbf_bw_mask : 1,
|
||||
cbf_bw : 3,
|
||||
use_static_bw : 1,
|
||||
coex_nack_count : 5,
|
||||
sch_tx_burst_ongoing : 1,
|
||||
gen_tqm_update_mpdu_count_tlv : 1,
|
||||
transmit_vif : 4,
|
||||
optimal_bw_retry_count : 4,
|
||||
fes_continuation_ratio_threshold : 5;
|
||||
uint32_t transmit_cca_bitmap : 32;
|
||||
uint32_t tb___reserved_g_0005 : 1,
|
||||
__reserved_g_0005_trigger_subtype : 4,
|
||||
min_cts2self_count : 4,
|
||||
max_cts2self_count : 4,
|
||||
wifi_radar_enable : 1,
|
||||
reserved_6a : 18;
|
||||
uint32_t monitor_override_sta_31_0 : 32;
|
||||
uint32_t monitor_override_sta_36_32 : 5,
|
||||
reserved_8a : 27;
|
||||
uint32_t fw2sw_info : 32;
|
||||
#else
|
||||
uint32_t schedule_id : 32;
|
||||
uint32_t response_to_response_cmd : 1,
|
||||
ofdma_triggered_response : 1,
|
||||
mu_type : 1,
|
||||
number_of_users : 6,
|
||||
fes_control_mode : 2,
|
||||
schedule_cmd_ring_id : 5,
|
||||
puncture_from_all_allowed_modes : 1,
|
||||
obss_pd_based_transmit_status : 1,
|
||||
srp_based_transmit_status : 1,
|
||||
obss_srg_opport_transmit_status : 1,
|
||||
static_2_pwr_mode_status : 1,
|
||||
use_alt_power_sr : 1,
|
||||
transmit_start_reason : 3,
|
||||
expect_i2r_lmr : 1,
|
||||
__reserved_g_0005 : 1,
|
||||
bo_based_tid_aggregation_limit : 4,
|
||||
fes_in_11ax_trigger_response_config : 1;
|
||||
uint32_t ast_index : 16,
|
||||
bw_restricted_frames_embedded : 1,
|
||||
transmission_contains_mu_rts : 1,
|
||||
set_txop_duration_all_ones : 1,
|
||||
static_bandwidth : 3,
|
||||
ignore_tbtt : 1,
|
||||
ignore_bw_available : 1,
|
||||
allow_txop_exceed_in_1st_pkt : 1,
|
||||
txbf : 1,
|
||||
ndp_frame : 2,
|
||||
schedule_try : 4;
|
||||
uint32_t cbf_feedback_type : 1,
|
||||
cbf_feedback_type_mask : 1,
|
||||
wait_sifs : 2,
|
||||
ndpa : 1,
|
||||
secure___reserved_g_0005_ista : 1,
|
||||
cbf_nr_index : 3,
|
||||
cbf_nr_index_mask : 1,
|
||||
cbf_nc_index : 3,
|
||||
cbf_nc_index_mask : 1,
|
||||
bf_type : 2,
|
||||
mu_ndp : 1,
|
||||
rbo_must_have_data_user_limit : 4,
|
||||
rxpcu_setup_complete_present : 1,
|
||||
trigger_resp_txpdu_ppdu_boundary : 2,
|
||||
cv_id : 8;
|
||||
uint32_t fes_continuation_ratio_threshold : 5,
|
||||
optimal_bw_retry_count : 4,
|
||||
transmit_vif : 4,
|
||||
gen_tqm_update_mpdu_count_tlv : 1,
|
||||
sch_tx_burst_ongoing : 1,
|
||||
coex_nack_count : 5,
|
||||
use_static_bw : 1,
|
||||
cbf_bw : 3,
|
||||
cbf_bw_mask : 1,
|
||||
cbf_sounding_token_mask : 1,
|
||||
cbf_sounding_token : 6;
|
||||
uint32_t transmit_cca_bitmap : 32;
|
||||
uint32_t reserved_6a : 18,
|
||||
wifi_radar_enable : 1,
|
||||
max_cts2self_count : 4,
|
||||
min_cts2self_count : 4,
|
||||
__reserved_g_0005_trigger_subtype : 4,
|
||||
tb___reserved_g_0005 : 1;
|
||||
uint32_t monitor_override_sta_31_0 : 32;
|
||||
uint32_t reserved_8a : 27,
|
||||
monitor_override_sta_36_32 : 5;
|
||||
uint32_t fw2sw_info : 32;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define TX_FES_SETUP_SCHEDULE_ID_OFFSET 0x0000000000000000
|
||||
#define TX_FES_SETUP_SCHEDULE_ID_LSB 0
|
||||
#define TX_FES_SETUP_SCHEDULE_ID_MSB 31
|
||||
#define TX_FES_SETUP_SCHEDULE_ID_MASK 0x00000000ffffffff
|
||||
|
||||
#define TX_FES_SETUP_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_OFFSET 0x0000000000000000
|
||||
#define TX_FES_SETUP_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_LSB 32
|
||||
#define TX_FES_SETUP_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_MSB 32
|
||||
#define TX_FES_SETUP_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_MASK 0x0000000100000000
|
||||
|
||||
#define TX_FES_SETUP_BO_BASED_TID_AGGREGATION_LIMIT_OFFSET 0x0000000000000000
|
||||
#define TX_FES_SETUP_BO_BASED_TID_AGGREGATION_LIMIT_LSB 33
|
||||
#define TX_FES_SETUP_BO_BASED_TID_AGGREGATION_LIMIT_MSB 36
|
||||
#define TX_FES_SETUP_BO_BASED_TID_AGGREGATION_LIMIT_MASK 0x0000001e00000000
|
||||
|
||||
#define TX_FES_SETUP_EXPECT_I2R_LMR_OFFSET 0x0000000000000000
|
||||
#define TX_FES_SETUP_EXPECT_I2R_LMR_LSB 38
|
||||
#define TX_FES_SETUP_EXPECT_I2R_LMR_MSB 38
|
||||
#define TX_FES_SETUP_EXPECT_I2R_LMR_MASK 0x0000004000000000
|
||||
|
||||
#define TX_FES_SETUP_TRANSMIT_START_REASON_OFFSET 0x0000000000000000
|
||||
#define TX_FES_SETUP_TRANSMIT_START_REASON_LSB 39
|
||||
#define TX_FES_SETUP_TRANSMIT_START_REASON_MSB 41
|
||||
#define TX_FES_SETUP_TRANSMIT_START_REASON_MASK 0x0000038000000000
|
||||
|
||||
#define TX_FES_SETUP_USE_ALT_POWER_SR_OFFSET 0x0000000000000000
|
||||
#define TX_FES_SETUP_USE_ALT_POWER_SR_LSB 42
|
||||
#define TX_FES_SETUP_USE_ALT_POWER_SR_MSB 42
|
||||
#define TX_FES_SETUP_USE_ALT_POWER_SR_MASK 0x0000040000000000
|
||||
|
||||
#define TX_FES_SETUP_STATIC_2_PWR_MODE_STATUS_OFFSET 0x0000000000000000
|
||||
#define TX_FES_SETUP_STATIC_2_PWR_MODE_STATUS_LSB 43
|
||||
#define TX_FES_SETUP_STATIC_2_PWR_MODE_STATUS_MSB 43
|
||||
#define TX_FES_SETUP_STATIC_2_PWR_MODE_STATUS_MASK 0x0000080000000000
|
||||
|
||||
#define TX_FES_SETUP_OBSS_SRG_OPPORT_TRANSMIT_STATUS_OFFSET 0x0000000000000000
|
||||
#define TX_FES_SETUP_OBSS_SRG_OPPORT_TRANSMIT_STATUS_LSB 44
|
||||
#define TX_FES_SETUP_OBSS_SRG_OPPORT_TRANSMIT_STATUS_MSB 44
|
||||
#define TX_FES_SETUP_OBSS_SRG_OPPORT_TRANSMIT_STATUS_MASK 0x0000100000000000
|
||||
|
||||
#define TX_FES_SETUP_SRP_BASED_TRANSMIT_STATUS_OFFSET 0x0000000000000000
|
||||
#define TX_FES_SETUP_SRP_BASED_TRANSMIT_STATUS_LSB 45
|
||||
#define TX_FES_SETUP_SRP_BASED_TRANSMIT_STATUS_MSB 45
|
||||
#define TX_FES_SETUP_SRP_BASED_TRANSMIT_STATUS_MASK 0x0000200000000000
|
||||
|
||||
#define TX_FES_SETUP_OBSS_PD_BASED_TRANSMIT_STATUS_OFFSET 0x0000000000000000
|
||||
#define TX_FES_SETUP_OBSS_PD_BASED_TRANSMIT_STATUS_LSB 46
|
||||
#define TX_FES_SETUP_OBSS_PD_BASED_TRANSMIT_STATUS_MSB 46
|
||||
#define TX_FES_SETUP_OBSS_PD_BASED_TRANSMIT_STATUS_MASK 0x0000400000000000
|
||||
|
||||
#define TX_FES_SETUP_PUNCTURE_FROM_ALL_ALLOWED_MODES_OFFSET 0x0000000000000000
|
||||
#define TX_FES_SETUP_PUNCTURE_FROM_ALL_ALLOWED_MODES_LSB 47
|
||||
#define TX_FES_SETUP_PUNCTURE_FROM_ALL_ALLOWED_MODES_MSB 47
|
||||
#define TX_FES_SETUP_PUNCTURE_FROM_ALL_ALLOWED_MODES_MASK 0x0000800000000000
|
||||
|
||||
#define TX_FES_SETUP_SCHEDULE_CMD_RING_ID_OFFSET 0x0000000000000000
|
||||
#define TX_FES_SETUP_SCHEDULE_CMD_RING_ID_LSB 48
|
||||
#define TX_FES_SETUP_SCHEDULE_CMD_RING_ID_MSB 52
|
||||
#define TX_FES_SETUP_SCHEDULE_CMD_RING_ID_MASK 0x001f000000000000
|
||||
|
||||
#define TX_FES_SETUP_FES_CONTROL_MODE_OFFSET 0x0000000000000000
|
||||
#define TX_FES_SETUP_FES_CONTROL_MODE_LSB 53
|
||||
#define TX_FES_SETUP_FES_CONTROL_MODE_MSB 54
|
||||
#define TX_FES_SETUP_FES_CONTROL_MODE_MASK 0x0060000000000000
|
||||
|
||||
#define TX_FES_SETUP_NUMBER_OF_USERS_OFFSET 0x0000000000000000
|
||||
#define TX_FES_SETUP_NUMBER_OF_USERS_LSB 55
|
||||
#define TX_FES_SETUP_NUMBER_OF_USERS_MSB 60
|
||||
#define TX_FES_SETUP_NUMBER_OF_USERS_MASK 0x1f80000000000000
|
||||
|
||||
#define TX_FES_SETUP_MU_TYPE_OFFSET 0x0000000000000000
|
||||
#define TX_FES_SETUP_MU_TYPE_LSB 61
|
||||
#define TX_FES_SETUP_MU_TYPE_MSB 61
|
||||
#define TX_FES_SETUP_MU_TYPE_MASK 0x2000000000000000
|
||||
|
||||
#define TX_FES_SETUP_OFDMA_TRIGGERED_RESPONSE_OFFSET 0x0000000000000000
|
||||
#define TX_FES_SETUP_OFDMA_TRIGGERED_RESPONSE_LSB 62
|
||||
#define TX_FES_SETUP_OFDMA_TRIGGERED_RESPONSE_MSB 62
|
||||
#define TX_FES_SETUP_OFDMA_TRIGGERED_RESPONSE_MASK 0x4000000000000000
|
||||
|
||||
#define TX_FES_SETUP_RESPONSE_TO_RESPONSE_CMD_OFFSET 0x0000000000000000
|
||||
#define TX_FES_SETUP_RESPONSE_TO_RESPONSE_CMD_LSB 63
|
||||
#define TX_FES_SETUP_RESPONSE_TO_RESPONSE_CMD_MSB 63
|
||||
#define TX_FES_SETUP_RESPONSE_TO_RESPONSE_CMD_MASK 0x8000000000000000
|
||||
|
||||
#define TX_FES_SETUP_SCHEDULE_TRY_OFFSET 0x0000000000000008
|
||||
#define TX_FES_SETUP_SCHEDULE_TRY_LSB 0
|
||||
#define TX_FES_SETUP_SCHEDULE_TRY_MSB 3
|
||||
#define TX_FES_SETUP_SCHEDULE_TRY_MASK 0x000000000000000f
|
||||
|
||||
#define TX_FES_SETUP_NDP_FRAME_OFFSET 0x0000000000000008
|
||||
#define TX_FES_SETUP_NDP_FRAME_LSB 4
|
||||
#define TX_FES_SETUP_NDP_FRAME_MSB 5
|
||||
#define TX_FES_SETUP_NDP_FRAME_MASK 0x0000000000000030
|
||||
|
||||
#define TX_FES_SETUP_TXBF_OFFSET 0x0000000000000008
|
||||
#define TX_FES_SETUP_TXBF_LSB 6
|
||||
#define TX_FES_SETUP_TXBF_MSB 6
|
||||
#define TX_FES_SETUP_TXBF_MASK 0x0000000000000040
|
||||
|
||||
#define TX_FES_SETUP_ALLOW_TXOP_EXCEED_IN_1ST_PKT_OFFSET 0x0000000000000008
|
||||
#define TX_FES_SETUP_ALLOW_TXOP_EXCEED_IN_1ST_PKT_LSB 7
|
||||
#define TX_FES_SETUP_ALLOW_TXOP_EXCEED_IN_1ST_PKT_MSB 7
|
||||
#define TX_FES_SETUP_ALLOW_TXOP_EXCEED_IN_1ST_PKT_MASK 0x0000000000000080
|
||||
|
||||
#define TX_FES_SETUP_IGNORE_BW_AVAILABLE_OFFSET 0x0000000000000008
|
||||
#define TX_FES_SETUP_IGNORE_BW_AVAILABLE_LSB 8
|
||||
#define TX_FES_SETUP_IGNORE_BW_AVAILABLE_MSB 8
|
||||
#define TX_FES_SETUP_IGNORE_BW_AVAILABLE_MASK 0x0000000000000100
|
||||
|
||||
#define TX_FES_SETUP_IGNORE_TBTT_OFFSET 0x0000000000000008
|
||||
#define TX_FES_SETUP_IGNORE_TBTT_LSB 9
|
||||
#define TX_FES_SETUP_IGNORE_TBTT_MSB 9
|
||||
#define TX_FES_SETUP_IGNORE_TBTT_MASK 0x0000000000000200
|
||||
|
||||
#define TX_FES_SETUP_STATIC_BANDWIDTH_OFFSET 0x0000000000000008
|
||||
#define TX_FES_SETUP_STATIC_BANDWIDTH_LSB 10
|
||||
#define TX_FES_SETUP_STATIC_BANDWIDTH_MSB 12
|
||||
#define TX_FES_SETUP_STATIC_BANDWIDTH_MASK 0x0000000000001c00
|
||||
|
||||
#define TX_FES_SETUP_SET_TXOP_DURATION_ALL_ONES_OFFSET 0x0000000000000008
|
||||
#define TX_FES_SETUP_SET_TXOP_DURATION_ALL_ONES_LSB 13
|
||||
#define TX_FES_SETUP_SET_TXOP_DURATION_ALL_ONES_MSB 13
|
||||
#define TX_FES_SETUP_SET_TXOP_DURATION_ALL_ONES_MASK 0x0000000000002000
|
||||
|
||||
#define TX_FES_SETUP_TRANSMISSION_CONTAINS_MU_RTS_OFFSET 0x0000000000000008
|
||||
#define TX_FES_SETUP_TRANSMISSION_CONTAINS_MU_RTS_LSB 14
|
||||
#define TX_FES_SETUP_TRANSMISSION_CONTAINS_MU_RTS_MSB 14
|
||||
#define TX_FES_SETUP_TRANSMISSION_CONTAINS_MU_RTS_MASK 0x0000000000004000
|
||||
|
||||
#define TX_FES_SETUP_BW_RESTRICTED_FRAMES_EMBEDDED_OFFSET 0x0000000000000008
|
||||
#define TX_FES_SETUP_BW_RESTRICTED_FRAMES_EMBEDDED_LSB 15
|
||||
#define TX_FES_SETUP_BW_RESTRICTED_FRAMES_EMBEDDED_MSB 15
|
||||
#define TX_FES_SETUP_BW_RESTRICTED_FRAMES_EMBEDDED_MASK 0x0000000000008000
|
||||
|
||||
#define TX_FES_SETUP_AST_INDEX_OFFSET 0x0000000000000008
|
||||
#define TX_FES_SETUP_AST_INDEX_LSB 16
|
||||
#define TX_FES_SETUP_AST_INDEX_MSB 31
|
||||
#define TX_FES_SETUP_AST_INDEX_MASK 0x00000000ffff0000
|
||||
|
||||
#define TX_FES_SETUP_CV_ID_OFFSET 0x0000000000000008
|
||||
#define TX_FES_SETUP_CV_ID_LSB 32
|
||||
#define TX_FES_SETUP_CV_ID_MSB 39
|
||||
#define TX_FES_SETUP_CV_ID_MASK 0x000000ff00000000
|
||||
|
||||
#define TX_FES_SETUP_TRIGGER_RESP_TXPDU_PPDU_BOUNDARY_OFFSET 0x0000000000000008
|
||||
#define TX_FES_SETUP_TRIGGER_RESP_TXPDU_PPDU_BOUNDARY_LSB 40
|
||||
#define TX_FES_SETUP_TRIGGER_RESP_TXPDU_PPDU_BOUNDARY_MSB 41
|
||||
#define TX_FES_SETUP_TRIGGER_RESP_TXPDU_PPDU_BOUNDARY_MASK 0x0000030000000000
|
||||
|
||||
#define TX_FES_SETUP_RXPCU_SETUP_COMPLETE_PRESENT_OFFSET 0x0000000000000008
|
||||
#define TX_FES_SETUP_RXPCU_SETUP_COMPLETE_PRESENT_LSB 42
|
||||
#define TX_FES_SETUP_RXPCU_SETUP_COMPLETE_PRESENT_MSB 42
|
||||
#define TX_FES_SETUP_RXPCU_SETUP_COMPLETE_PRESENT_MASK 0x0000040000000000
|
||||
|
||||
#define TX_FES_SETUP_RBO_MUST_HAVE_DATA_USER_LIMIT_OFFSET 0x0000000000000008
|
||||
#define TX_FES_SETUP_RBO_MUST_HAVE_DATA_USER_LIMIT_LSB 43
|
||||
#define TX_FES_SETUP_RBO_MUST_HAVE_DATA_USER_LIMIT_MSB 46
|
||||
#define TX_FES_SETUP_RBO_MUST_HAVE_DATA_USER_LIMIT_MASK 0x0000780000000000
|
||||
|
||||
#define TX_FES_SETUP_MU_NDP_OFFSET 0x0000000000000008
|
||||
#define TX_FES_SETUP_MU_NDP_LSB 47
|
||||
#define TX_FES_SETUP_MU_NDP_MSB 47
|
||||
#define TX_FES_SETUP_MU_NDP_MASK 0x0000800000000000
|
||||
|
||||
#define TX_FES_SETUP_BF_TYPE_OFFSET 0x0000000000000008
|
||||
#define TX_FES_SETUP_BF_TYPE_LSB 48
|
||||
#define TX_FES_SETUP_BF_TYPE_MSB 49
|
||||
#define TX_FES_SETUP_BF_TYPE_MASK 0x0003000000000000
|
||||
|
||||
#define TX_FES_SETUP_CBF_NC_INDEX_MASK_OFFSET 0x0000000000000008
|
||||
#define TX_FES_SETUP_CBF_NC_INDEX_MASK_LSB 50
|
||||
#define TX_FES_SETUP_CBF_NC_INDEX_MASK_MSB 50
|
||||
#define TX_FES_SETUP_CBF_NC_INDEX_MASK_MASK 0x0004000000000000
|
||||
|
||||
#define TX_FES_SETUP_CBF_NC_INDEX_OFFSET 0x0000000000000008
|
||||
#define TX_FES_SETUP_CBF_NC_INDEX_LSB 51
|
||||
#define TX_FES_SETUP_CBF_NC_INDEX_MSB 53
|
||||
#define TX_FES_SETUP_CBF_NC_INDEX_MASK 0x0038000000000000
|
||||
|
||||
#define TX_FES_SETUP_CBF_NR_INDEX_MASK_OFFSET 0x0000000000000008
|
||||
#define TX_FES_SETUP_CBF_NR_INDEX_MASK_LSB 54
|
||||
#define TX_FES_SETUP_CBF_NR_INDEX_MASK_MSB 54
|
||||
#define TX_FES_SETUP_CBF_NR_INDEX_MASK_MASK 0x0040000000000000
|
||||
|
||||
#define TX_FES_SETUP_CBF_NR_INDEX_OFFSET 0x0000000000000008
|
||||
#define TX_FES_SETUP_CBF_NR_INDEX_LSB 55
|
||||
#define TX_FES_SETUP_CBF_NR_INDEX_MSB 57
|
||||
#define TX_FES_SETUP_CBF_NR_INDEX_MASK 0x0380000000000000
|
||||
|
||||
#define TX_FES_SETUP_SECURE_RANGING_ISTA_OFFSET 0x0000000000000008
|
||||
#define TX_FES_SETUP_SECURE_RANGING_ISTA_LSB 58
|
||||
#define TX_FES_SETUP_SECURE_RANGING_ISTA_MSB 58
|
||||
#define TX_FES_SETUP_SECURE_RANGING_ISTA_MASK 0x0400000000000000
|
||||
|
||||
#define TX_FES_SETUP_NDPA_OFFSET 0x0000000000000008
|
||||
#define TX_FES_SETUP_NDPA_LSB 59
|
||||
#define TX_FES_SETUP_NDPA_MSB 59
|
||||
#define TX_FES_SETUP_NDPA_MASK 0x0800000000000000
|
||||
|
||||
#define TX_FES_SETUP_WAIT_SIFS_OFFSET 0x0000000000000008
|
||||
#define TX_FES_SETUP_WAIT_SIFS_LSB 60
|
||||
#define TX_FES_SETUP_WAIT_SIFS_MSB 61
|
||||
#define TX_FES_SETUP_WAIT_SIFS_MASK 0x3000000000000000
|
||||
|
||||
#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK_OFFSET 0x0000000000000008
|
||||
#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK_LSB 62
|
||||
#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK_MSB 62
|
||||
#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK_MASK 0x4000000000000000
|
||||
|
||||
#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_OFFSET 0x0000000000000008
|
||||
#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_LSB 63
|
||||
#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MSB 63
|
||||
#define TX_FES_SETUP_CBF_FEEDBACK_TYPE_MASK 0x8000000000000000
|
||||
|
||||
#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_OFFSET 0x0000000000000010
|
||||
#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_LSB 0
|
||||
#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MSB 5
|
||||
#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK 0x000000000000003f
|
||||
|
||||
#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK_OFFSET 0x0000000000000010
|
||||
#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK_LSB 6
|
||||
#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK_MSB 6
|
||||
#define TX_FES_SETUP_CBF_SOUNDING_TOKEN_MASK_MASK 0x0000000000000040
|
||||
|
||||
#define TX_FES_SETUP_CBF_BW_MASK_OFFSET 0x0000000000000010
|
||||
#define TX_FES_SETUP_CBF_BW_MASK_LSB 7
|
||||
#define TX_FES_SETUP_CBF_BW_MASK_MSB 7
|
||||
#define TX_FES_SETUP_CBF_BW_MASK_MASK 0x0000000000000080
|
||||
|
||||
#define TX_FES_SETUP_CBF_BW_OFFSET 0x0000000000000010
|
||||
#define TX_FES_SETUP_CBF_BW_LSB 8
|
||||
#define TX_FES_SETUP_CBF_BW_MSB 10
|
||||
#define TX_FES_SETUP_CBF_BW_MASK 0x0000000000000700
|
||||
|
||||
#define TX_FES_SETUP_USE_STATIC_BW_OFFSET 0x0000000000000010
|
||||
#define TX_FES_SETUP_USE_STATIC_BW_LSB 11
|
||||
#define TX_FES_SETUP_USE_STATIC_BW_MSB 11
|
||||
#define TX_FES_SETUP_USE_STATIC_BW_MASK 0x0000000000000800
|
||||
|
||||
#define TX_FES_SETUP_COEX_NACK_COUNT_OFFSET 0x0000000000000010
|
||||
#define TX_FES_SETUP_COEX_NACK_COUNT_LSB 12
|
||||
#define TX_FES_SETUP_COEX_NACK_COUNT_MSB 16
|
||||
#define TX_FES_SETUP_COEX_NACK_COUNT_MASK 0x000000000001f000
|
||||
|
||||
#define TX_FES_SETUP_SCH_TX_BURST_ONGOING_OFFSET 0x0000000000000010
|
||||
#define TX_FES_SETUP_SCH_TX_BURST_ONGOING_LSB 17
|
||||
#define TX_FES_SETUP_SCH_TX_BURST_ONGOING_MSB 17
|
||||
#define TX_FES_SETUP_SCH_TX_BURST_ONGOING_MASK 0x0000000000020000
|
||||
|
||||
#define TX_FES_SETUP_GEN_TQM_UPDATE_MPDU_COUNT_TLV_OFFSET 0x0000000000000010
|
||||
#define TX_FES_SETUP_GEN_TQM_UPDATE_MPDU_COUNT_TLV_LSB 18
|
||||
#define TX_FES_SETUP_GEN_TQM_UPDATE_MPDU_COUNT_TLV_MSB 18
|
||||
#define TX_FES_SETUP_GEN_TQM_UPDATE_MPDU_COUNT_TLV_MASK 0x0000000000040000
|
||||
|
||||
#define TX_FES_SETUP_TRANSMIT_VIF_OFFSET 0x0000000000000010
|
||||
#define TX_FES_SETUP_TRANSMIT_VIF_LSB 19
|
||||
#define TX_FES_SETUP_TRANSMIT_VIF_MSB 22
|
||||
#define TX_FES_SETUP_TRANSMIT_VIF_MASK 0x0000000000780000
|
||||
|
||||
#define TX_FES_SETUP_OPTIMAL_BW_RETRY_COUNT_OFFSET 0x0000000000000010
|
||||
#define TX_FES_SETUP_OPTIMAL_BW_RETRY_COUNT_LSB 23
|
||||
#define TX_FES_SETUP_OPTIMAL_BW_RETRY_COUNT_MSB 26
|
||||
#define TX_FES_SETUP_OPTIMAL_BW_RETRY_COUNT_MASK 0x0000000007800000
|
||||
|
||||
#define TX_FES_SETUP_FES_CONTINUATION_RATIO_THRESHOLD_OFFSET 0x0000000000000010
|
||||
#define TX_FES_SETUP_FES_CONTINUATION_RATIO_THRESHOLD_LSB 27
|
||||
#define TX_FES_SETUP_FES_CONTINUATION_RATIO_THRESHOLD_MSB 31
|
||||
#define TX_FES_SETUP_FES_CONTINUATION_RATIO_THRESHOLD_MASK 0x00000000f8000000
|
||||
|
||||
#define TX_FES_SETUP_TRANSMIT_CCA_BITMAP_OFFSET 0x0000000000000010
|
||||
#define TX_FES_SETUP_TRANSMIT_CCA_BITMAP_LSB 32
|
||||
#define TX_FES_SETUP_TRANSMIT_CCA_BITMAP_MSB 63
|
||||
#define TX_FES_SETUP_TRANSMIT_CCA_BITMAP_MASK 0xffffffff00000000
|
||||
|
||||
#define TX_FES_SETUP_RANGING_TRIGGER_SUBTYPE_OFFSET 0x0000000000000018
|
||||
#define TX_FES_SETUP_RANGING_TRIGGER_SUBTYPE_LSB 1
|
||||
#define TX_FES_SETUP_RANGING_TRIGGER_SUBTYPE_MSB 4
|
||||
#define TX_FES_SETUP_RANGING_TRIGGER_SUBTYPE_MASK 0x000000000000001e
|
||||
|
||||
#define TX_FES_SETUP_MIN_CTS2SELF_COUNT_OFFSET 0x0000000000000018
|
||||
#define TX_FES_SETUP_MIN_CTS2SELF_COUNT_LSB 5
|
||||
#define TX_FES_SETUP_MIN_CTS2SELF_COUNT_MSB 8
|
||||
#define TX_FES_SETUP_MIN_CTS2SELF_COUNT_MASK 0x00000000000001e0
|
||||
|
||||
#define TX_FES_SETUP_MAX_CTS2SELF_COUNT_OFFSET 0x0000000000000018
|
||||
#define TX_FES_SETUP_MAX_CTS2SELF_COUNT_LSB 9
|
||||
#define TX_FES_SETUP_MAX_CTS2SELF_COUNT_MSB 12
|
||||
#define TX_FES_SETUP_MAX_CTS2SELF_COUNT_MASK 0x0000000000001e00
|
||||
|
||||
#define TX_FES_SETUP_WIFI_RADAR_ENABLE_OFFSET 0x0000000000000018
|
||||
#define TX_FES_SETUP_WIFI_RADAR_ENABLE_LSB 13
|
||||
#define TX_FES_SETUP_WIFI_RADAR_ENABLE_MSB 13
|
||||
#define TX_FES_SETUP_WIFI_RADAR_ENABLE_MASK 0x0000000000002000
|
||||
|
||||
#define TX_FES_SETUP_RESERVED_6A_OFFSET 0x0000000000000018
|
||||
#define TX_FES_SETUP_RESERVED_6A_LSB 14
|
||||
#define TX_FES_SETUP_RESERVED_6A_MSB 31
|
||||
#define TX_FES_SETUP_RESERVED_6A_MASK 0x00000000ffffc000
|
||||
|
||||
#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_31_0_OFFSET 0x0000000000000018
|
||||
#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_31_0_LSB 32
|
||||
#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_31_0_MSB 63
|
||||
#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_31_0_MASK 0xffffffff00000000
|
||||
|
||||
#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_36_32_OFFSET 0x0000000000000020
|
||||
#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_36_32_LSB 0
|
||||
#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_36_32_MSB 4
|
||||
#define TX_FES_SETUP_MONITOR_OVERRIDE_STA_36_32_MASK 0x000000000000001f
|
||||
|
||||
#define TX_FES_SETUP_RESERVED_8A_OFFSET 0x0000000000000020
|
||||
#define TX_FES_SETUP_RESERVED_8A_LSB 5
|
||||
#define TX_FES_SETUP_RESERVED_8A_MSB 31
|
||||
#define TX_FES_SETUP_RESERVED_8A_MASK 0x00000000ffffffe0
|
||||
|
||||
#define TX_FES_SETUP_FW2SW_INFO_OFFSET 0x0000000000000020
|
||||
#define TX_FES_SETUP_FW2SW_INFO_LSB 32
|
||||
#define TX_FES_SETUP_FW2SW_INFO_MSB 63
|
||||
#define TX_FES_SETUP_FW2SW_INFO_MASK 0xffffffff00000000
|
||||
|
||||
#endif
|
||||
329
hw/kiwi/v2/tx_fes_status_1k_ba.h
Normal file
329
hw/kiwi/v2/tx_fes_status_1k_ba.h
Normal file
|
|
@ -0,0 +1,329 @@
|
|||
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
#ifndef _TX_FES_STATUS_1K_BA_H_
|
||||
#define _TX_FES_STATUS_1K_BA_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#define NUM_OF_DWORDS_TX_FES_STATUS_1K_BA 34
|
||||
|
||||
#define NUM_OF_QWORDS_TX_FES_STATUS_1K_BA 17
|
||||
|
||||
struct tx_fes_status_1k_ba {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t ack_ba_status_type : 1,
|
||||
ba_type : 1,
|
||||
ba_tid : 4,
|
||||
unexpected_ack_or_ba : 1,
|
||||
response_timeout : 1,
|
||||
ack_frame_rssi : 8,
|
||||
ssn : 12,
|
||||
reserved_0b : 4;
|
||||
uint32_t sw_peer_id : 16,
|
||||
reserved_1a : 16;
|
||||
uint32_t ba_bitmap_31_0 : 32;
|
||||
uint32_t ba_bitmap_63_32 : 32;
|
||||
uint32_t ba_bitmap_95_64 : 32;
|
||||
uint32_t ba_bitmap_127_96 : 32;
|
||||
uint32_t ba_bitmap_159_128 : 32;
|
||||
uint32_t ba_bitmap_191_160 : 32;
|
||||
uint32_t ba_bitmap_223_192 : 32;
|
||||
uint32_t ba_bitmap_255_224 : 32;
|
||||
uint32_t ba_bitmap_287_256 : 32;
|
||||
uint32_t ba_bitmap_319_288 : 32;
|
||||
uint32_t ba_bitmap_351_320 : 32;
|
||||
uint32_t ba_bitmap_383_352 : 32;
|
||||
uint32_t ba_bitmap_415_384 : 32;
|
||||
uint32_t ba_bitmap_447_416 : 32;
|
||||
uint32_t ba_bitmap_479_448 : 32;
|
||||
uint32_t ba_bitmap_511_480 : 32;
|
||||
uint32_t ba_bitmap_543_512 : 32;
|
||||
uint32_t ba_bitmap_575_544 : 32;
|
||||
uint32_t ba_bitmap_607_576 : 32;
|
||||
uint32_t ba_bitmap_639_608 : 32;
|
||||
uint32_t ba_bitmap_671_640 : 32;
|
||||
uint32_t ba_bitmap_703_672 : 32;
|
||||
uint32_t ba_bitmap_735_704 : 32;
|
||||
uint32_t ba_bitmap_767_736 : 32;
|
||||
uint32_t ba_bitmap_799_768 : 32;
|
||||
uint32_t ba_bitmap_831_800 : 32;
|
||||
uint32_t ba_bitmap_863_832 : 32;
|
||||
uint32_t ba_bitmap_895_864 : 32;
|
||||
uint32_t ba_bitmap_927_896 : 32;
|
||||
uint32_t ba_bitmap_959_928 : 32;
|
||||
uint32_t ba_bitmap_991_960 : 32;
|
||||
uint32_t ba_bitmap_1023_992 : 32;
|
||||
#else
|
||||
uint32_t reserved_0b : 4,
|
||||
ssn : 12,
|
||||
ack_frame_rssi : 8,
|
||||
response_timeout : 1,
|
||||
unexpected_ack_or_ba : 1,
|
||||
ba_tid : 4,
|
||||
ba_type : 1,
|
||||
ack_ba_status_type : 1;
|
||||
uint32_t reserved_1a : 16,
|
||||
sw_peer_id : 16;
|
||||
uint32_t ba_bitmap_31_0 : 32;
|
||||
uint32_t ba_bitmap_63_32 : 32;
|
||||
uint32_t ba_bitmap_95_64 : 32;
|
||||
uint32_t ba_bitmap_127_96 : 32;
|
||||
uint32_t ba_bitmap_159_128 : 32;
|
||||
uint32_t ba_bitmap_191_160 : 32;
|
||||
uint32_t ba_bitmap_223_192 : 32;
|
||||
uint32_t ba_bitmap_255_224 : 32;
|
||||
uint32_t ba_bitmap_287_256 : 32;
|
||||
uint32_t ba_bitmap_319_288 : 32;
|
||||
uint32_t ba_bitmap_351_320 : 32;
|
||||
uint32_t ba_bitmap_383_352 : 32;
|
||||
uint32_t ba_bitmap_415_384 : 32;
|
||||
uint32_t ba_bitmap_447_416 : 32;
|
||||
uint32_t ba_bitmap_479_448 : 32;
|
||||
uint32_t ba_bitmap_511_480 : 32;
|
||||
uint32_t ba_bitmap_543_512 : 32;
|
||||
uint32_t ba_bitmap_575_544 : 32;
|
||||
uint32_t ba_bitmap_607_576 : 32;
|
||||
uint32_t ba_bitmap_639_608 : 32;
|
||||
uint32_t ba_bitmap_671_640 : 32;
|
||||
uint32_t ba_bitmap_703_672 : 32;
|
||||
uint32_t ba_bitmap_735_704 : 32;
|
||||
uint32_t ba_bitmap_767_736 : 32;
|
||||
uint32_t ba_bitmap_799_768 : 32;
|
||||
uint32_t ba_bitmap_831_800 : 32;
|
||||
uint32_t ba_bitmap_863_832 : 32;
|
||||
uint32_t ba_bitmap_895_864 : 32;
|
||||
uint32_t ba_bitmap_927_896 : 32;
|
||||
uint32_t ba_bitmap_959_928 : 32;
|
||||
uint32_t ba_bitmap_991_960 : 32;
|
||||
uint32_t ba_bitmap_1023_992 : 32;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define TX_FES_STATUS_1K_BA_ACK_BA_STATUS_TYPE_OFFSET 0x0000000000000000
|
||||
#define TX_FES_STATUS_1K_BA_ACK_BA_STATUS_TYPE_LSB 0
|
||||
#define TX_FES_STATUS_1K_BA_ACK_BA_STATUS_TYPE_MSB 0
|
||||
#define TX_FES_STATUS_1K_BA_ACK_BA_STATUS_TYPE_MASK 0x0000000000000001
|
||||
|
||||
#define TX_FES_STATUS_1K_BA_BA_TYPE_OFFSET 0x0000000000000000
|
||||
#define TX_FES_STATUS_1K_BA_BA_TYPE_LSB 1
|
||||
#define TX_FES_STATUS_1K_BA_BA_TYPE_MSB 1
|
||||
#define TX_FES_STATUS_1K_BA_BA_TYPE_MASK 0x0000000000000002
|
||||
|
||||
#define TX_FES_STATUS_1K_BA_BA_TID_OFFSET 0x0000000000000000
|
||||
#define TX_FES_STATUS_1K_BA_BA_TID_LSB 2
|
||||
#define TX_FES_STATUS_1K_BA_BA_TID_MSB 5
|
||||
#define TX_FES_STATUS_1K_BA_BA_TID_MASK 0x000000000000003c
|
||||
|
||||
#define TX_FES_STATUS_1K_BA_UNEXPECTED_ACK_OR_BA_OFFSET 0x0000000000000000
|
||||
#define TX_FES_STATUS_1K_BA_UNEXPECTED_ACK_OR_BA_LSB 6
|
||||
#define TX_FES_STATUS_1K_BA_UNEXPECTED_ACK_OR_BA_MSB 6
|
||||
#define TX_FES_STATUS_1K_BA_UNEXPECTED_ACK_OR_BA_MASK 0x0000000000000040
|
||||
|
||||
#define TX_FES_STATUS_1K_BA_RESPONSE_TIMEOUT_OFFSET 0x0000000000000000
|
||||
#define TX_FES_STATUS_1K_BA_RESPONSE_TIMEOUT_LSB 7
|
||||
#define TX_FES_STATUS_1K_BA_RESPONSE_TIMEOUT_MSB 7
|
||||
#define TX_FES_STATUS_1K_BA_RESPONSE_TIMEOUT_MASK 0x0000000000000080
|
||||
|
||||
#define TX_FES_STATUS_1K_BA_ACK_FRAME_RSSI_OFFSET 0x0000000000000000
|
||||
#define TX_FES_STATUS_1K_BA_ACK_FRAME_RSSI_LSB 8
|
||||
#define TX_FES_STATUS_1K_BA_ACK_FRAME_RSSI_MSB 15
|
||||
#define TX_FES_STATUS_1K_BA_ACK_FRAME_RSSI_MASK 0x000000000000ff00
|
||||
|
||||
#define TX_FES_STATUS_1K_BA_SSN_OFFSET 0x0000000000000000
|
||||
#define TX_FES_STATUS_1K_BA_SSN_LSB 16
|
||||
#define TX_FES_STATUS_1K_BA_SSN_MSB 27
|
||||
#define TX_FES_STATUS_1K_BA_SSN_MASK 0x000000000fff0000
|
||||
|
||||
#define TX_FES_STATUS_1K_BA_RESERVED_0B_OFFSET 0x0000000000000000
|
||||
#define TX_FES_STATUS_1K_BA_RESERVED_0B_LSB 28
|
||||
#define TX_FES_STATUS_1K_BA_RESERVED_0B_MSB 31
|
||||
#define TX_FES_STATUS_1K_BA_RESERVED_0B_MASK 0x00000000f0000000
|
||||
|
||||
#define TX_FES_STATUS_1K_BA_SW_PEER_ID_OFFSET 0x0000000000000000
|
||||
#define TX_FES_STATUS_1K_BA_SW_PEER_ID_LSB 32
|
||||
#define TX_FES_STATUS_1K_BA_SW_PEER_ID_MSB 47
|
||||
#define TX_FES_STATUS_1K_BA_SW_PEER_ID_MASK 0x0000ffff00000000
|
||||
|
||||
#define TX_FES_STATUS_1K_BA_RESERVED_1A_OFFSET 0x0000000000000000
|
||||
#define TX_FES_STATUS_1K_BA_RESERVED_1A_LSB 48
|
||||
#define TX_FES_STATUS_1K_BA_RESERVED_1A_MSB 63
|
||||
#define TX_FES_STATUS_1K_BA_RESERVED_1A_MASK 0xffff000000000000
|
||||
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_31_0_OFFSET 0x0000000000000008
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_31_0_LSB 0
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_31_0_MSB 31
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_31_0_MASK 0x00000000ffffffff
|
||||
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_63_32_OFFSET 0x0000000000000008
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_63_32_LSB 32
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_63_32_MSB 63
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_63_32_MASK 0xffffffff00000000
|
||||
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_95_64_OFFSET 0x0000000000000010
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_95_64_LSB 0
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_95_64_MSB 31
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_95_64_MASK 0x00000000ffffffff
|
||||
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_127_96_OFFSET 0x0000000000000010
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_127_96_LSB 32
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_127_96_MSB 63
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_127_96_MASK 0xffffffff00000000
|
||||
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_159_128_OFFSET 0x0000000000000018
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_159_128_LSB 0
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_159_128_MSB 31
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_159_128_MASK 0x00000000ffffffff
|
||||
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_191_160_OFFSET 0x0000000000000018
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_191_160_LSB 32
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_191_160_MSB 63
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_191_160_MASK 0xffffffff00000000
|
||||
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_223_192_OFFSET 0x0000000000000020
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_223_192_LSB 0
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_223_192_MSB 31
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_223_192_MASK 0x00000000ffffffff
|
||||
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_255_224_OFFSET 0x0000000000000020
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_255_224_LSB 32
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_255_224_MSB 63
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_255_224_MASK 0xffffffff00000000
|
||||
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_287_256_OFFSET 0x0000000000000028
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_287_256_LSB 0
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_287_256_MSB 31
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_287_256_MASK 0x00000000ffffffff
|
||||
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_319_288_OFFSET 0x0000000000000028
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_319_288_LSB 32
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_319_288_MSB 63
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_319_288_MASK 0xffffffff00000000
|
||||
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_351_320_OFFSET 0x0000000000000030
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_351_320_LSB 0
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_351_320_MSB 31
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_351_320_MASK 0x00000000ffffffff
|
||||
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_383_352_OFFSET 0x0000000000000030
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_383_352_LSB 32
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_383_352_MSB 63
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_383_352_MASK 0xffffffff00000000
|
||||
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_415_384_OFFSET 0x0000000000000038
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_415_384_LSB 0
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_415_384_MSB 31
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_415_384_MASK 0x00000000ffffffff
|
||||
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_447_416_OFFSET 0x0000000000000038
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_447_416_LSB 32
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_447_416_MSB 63
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_447_416_MASK 0xffffffff00000000
|
||||
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_479_448_OFFSET 0x0000000000000040
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_479_448_LSB 0
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_479_448_MSB 31
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_479_448_MASK 0x00000000ffffffff
|
||||
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_511_480_OFFSET 0x0000000000000040
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_511_480_LSB 32
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_511_480_MSB 63
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_511_480_MASK 0xffffffff00000000
|
||||
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_543_512_OFFSET 0x0000000000000048
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_543_512_LSB 0
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_543_512_MSB 31
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_543_512_MASK 0x00000000ffffffff
|
||||
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_575_544_OFFSET 0x0000000000000048
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_575_544_LSB 32
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_575_544_MSB 63
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_575_544_MASK 0xffffffff00000000
|
||||
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_607_576_OFFSET 0x0000000000000050
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_607_576_LSB 0
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_607_576_MSB 31
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_607_576_MASK 0x00000000ffffffff
|
||||
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_639_608_OFFSET 0x0000000000000050
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_639_608_LSB 32
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_639_608_MSB 63
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_639_608_MASK 0xffffffff00000000
|
||||
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_671_640_OFFSET 0x0000000000000058
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_671_640_LSB 0
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_671_640_MSB 31
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_671_640_MASK 0x00000000ffffffff
|
||||
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_703_672_OFFSET 0x0000000000000058
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_703_672_LSB 32
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_703_672_MSB 63
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_703_672_MASK 0xffffffff00000000
|
||||
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_735_704_OFFSET 0x0000000000000060
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_735_704_LSB 0
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_735_704_MSB 31
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_735_704_MASK 0x00000000ffffffff
|
||||
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_767_736_OFFSET 0x0000000000000060
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_767_736_LSB 32
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_767_736_MSB 63
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_767_736_MASK 0xffffffff00000000
|
||||
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_799_768_OFFSET 0x0000000000000068
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_799_768_LSB 0
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_799_768_MSB 31
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_799_768_MASK 0x00000000ffffffff
|
||||
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_831_800_OFFSET 0x0000000000000068
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_831_800_LSB 32
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_831_800_MSB 63
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_831_800_MASK 0xffffffff00000000
|
||||
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_863_832_OFFSET 0x0000000000000070
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_863_832_LSB 0
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_863_832_MSB 31
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_863_832_MASK 0x00000000ffffffff
|
||||
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_895_864_OFFSET 0x0000000000000070
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_895_864_LSB 32
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_895_864_MSB 63
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_895_864_MASK 0xffffffff00000000
|
||||
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_927_896_OFFSET 0x0000000000000078
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_927_896_LSB 0
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_927_896_MSB 31
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_927_896_MASK 0x00000000ffffffff
|
||||
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_959_928_OFFSET 0x0000000000000078
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_959_928_LSB 32
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_959_928_MSB 63
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_959_928_MASK 0xffffffff00000000
|
||||
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_991_960_OFFSET 0x0000000000000080
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_991_960_LSB 0
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_991_960_MSB 31
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_991_960_MASK 0x00000000ffffffff
|
||||
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_1023_992_OFFSET 0x0000000000000080
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_1023_992_LSB 32
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_1023_992_MSB 63
|
||||
#define TX_FES_STATUS_1K_BA_BA_BITMAP_1023_992_MASK 0xffffffff00000000
|
||||
|
||||
#endif
|
||||
161
hw/kiwi/v2/tx_fes_status_ack_or_ba.h
Normal file
161
hw/kiwi/v2/tx_fes_status_ack_or_ba.h
Normal file
|
|
@ -0,0 +1,161 @@
|
|||
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
#ifndef _TX_FES_STATUS_ACK_OR_BA_H_
|
||||
#define _TX_FES_STATUS_ACK_OR_BA_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#define NUM_OF_DWORDS_TX_FES_STATUS_ACK_OR_BA 10
|
||||
|
||||
#define NUM_OF_QWORDS_TX_FES_STATUS_ACK_OR_BA 5
|
||||
|
||||
struct tx_fes_status_ack_or_ba {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t ack_ba_status_type : 1,
|
||||
ba_type : 1,
|
||||
ba_tid : 4,
|
||||
unexpected_ack_or_ba : 1,
|
||||
response_timeout : 1,
|
||||
ack_frame_rssi : 8,
|
||||
ssn : 12,
|
||||
reserved_0b : 4;
|
||||
uint32_t sw_peer_id : 16,
|
||||
reserved_1a : 16;
|
||||
uint32_t ba_bitmap_31_0 : 32;
|
||||
uint32_t ba_bitmap_63_32 : 32;
|
||||
uint32_t ba_bitmap_95_64 : 32;
|
||||
uint32_t ba_bitmap_127_96 : 32;
|
||||
uint32_t ba_bitmap_159_128 : 32;
|
||||
uint32_t ba_bitmap_191_160 : 32;
|
||||
uint32_t ba_bitmap_223_192 : 32;
|
||||
uint32_t ba_bitmap_255_224 : 32;
|
||||
#else
|
||||
uint32_t reserved_0b : 4,
|
||||
ssn : 12,
|
||||
ack_frame_rssi : 8,
|
||||
response_timeout : 1,
|
||||
unexpected_ack_or_ba : 1,
|
||||
ba_tid : 4,
|
||||
ba_type : 1,
|
||||
ack_ba_status_type : 1;
|
||||
uint32_t reserved_1a : 16,
|
||||
sw_peer_id : 16;
|
||||
uint32_t ba_bitmap_31_0 : 32;
|
||||
uint32_t ba_bitmap_63_32 : 32;
|
||||
uint32_t ba_bitmap_95_64 : 32;
|
||||
uint32_t ba_bitmap_127_96 : 32;
|
||||
uint32_t ba_bitmap_159_128 : 32;
|
||||
uint32_t ba_bitmap_191_160 : 32;
|
||||
uint32_t ba_bitmap_223_192 : 32;
|
||||
uint32_t ba_bitmap_255_224 : 32;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define TX_FES_STATUS_ACK_OR_BA_ACK_BA_STATUS_TYPE_OFFSET 0x0000000000000000
|
||||
#define TX_FES_STATUS_ACK_OR_BA_ACK_BA_STATUS_TYPE_LSB 0
|
||||
#define TX_FES_STATUS_ACK_OR_BA_ACK_BA_STATUS_TYPE_MSB 0
|
||||
#define TX_FES_STATUS_ACK_OR_BA_ACK_BA_STATUS_TYPE_MASK 0x0000000000000001
|
||||
|
||||
#define TX_FES_STATUS_ACK_OR_BA_BA_TYPE_OFFSET 0x0000000000000000
|
||||
#define TX_FES_STATUS_ACK_OR_BA_BA_TYPE_LSB 1
|
||||
#define TX_FES_STATUS_ACK_OR_BA_BA_TYPE_MSB 1
|
||||
#define TX_FES_STATUS_ACK_OR_BA_BA_TYPE_MASK 0x0000000000000002
|
||||
|
||||
#define TX_FES_STATUS_ACK_OR_BA_BA_TID_OFFSET 0x0000000000000000
|
||||
#define TX_FES_STATUS_ACK_OR_BA_BA_TID_LSB 2
|
||||
#define TX_FES_STATUS_ACK_OR_BA_BA_TID_MSB 5
|
||||
#define TX_FES_STATUS_ACK_OR_BA_BA_TID_MASK 0x000000000000003c
|
||||
|
||||
#define TX_FES_STATUS_ACK_OR_BA_UNEXPECTED_ACK_OR_BA_OFFSET 0x0000000000000000
|
||||
#define TX_FES_STATUS_ACK_OR_BA_UNEXPECTED_ACK_OR_BA_LSB 6
|
||||
#define TX_FES_STATUS_ACK_OR_BA_UNEXPECTED_ACK_OR_BA_MSB 6
|
||||
#define TX_FES_STATUS_ACK_OR_BA_UNEXPECTED_ACK_OR_BA_MASK 0x0000000000000040
|
||||
|
||||
#define TX_FES_STATUS_ACK_OR_BA_RESPONSE_TIMEOUT_OFFSET 0x0000000000000000
|
||||
#define TX_FES_STATUS_ACK_OR_BA_RESPONSE_TIMEOUT_LSB 7
|
||||
#define TX_FES_STATUS_ACK_OR_BA_RESPONSE_TIMEOUT_MSB 7
|
||||
#define TX_FES_STATUS_ACK_OR_BA_RESPONSE_TIMEOUT_MASK 0x0000000000000080
|
||||
|
||||
#define TX_FES_STATUS_ACK_OR_BA_ACK_FRAME_RSSI_OFFSET 0x0000000000000000
|
||||
#define TX_FES_STATUS_ACK_OR_BA_ACK_FRAME_RSSI_LSB 8
|
||||
#define TX_FES_STATUS_ACK_OR_BA_ACK_FRAME_RSSI_MSB 15
|
||||
#define TX_FES_STATUS_ACK_OR_BA_ACK_FRAME_RSSI_MASK 0x000000000000ff00
|
||||
|
||||
#define TX_FES_STATUS_ACK_OR_BA_SSN_OFFSET 0x0000000000000000
|
||||
#define TX_FES_STATUS_ACK_OR_BA_SSN_LSB 16
|
||||
#define TX_FES_STATUS_ACK_OR_BA_SSN_MSB 27
|
||||
#define TX_FES_STATUS_ACK_OR_BA_SSN_MASK 0x000000000fff0000
|
||||
|
||||
#define TX_FES_STATUS_ACK_OR_BA_RESERVED_0B_OFFSET 0x0000000000000000
|
||||
#define TX_FES_STATUS_ACK_OR_BA_RESERVED_0B_LSB 28
|
||||
#define TX_FES_STATUS_ACK_OR_BA_RESERVED_0B_MSB 31
|
||||
#define TX_FES_STATUS_ACK_OR_BA_RESERVED_0B_MASK 0x00000000f0000000
|
||||
|
||||
#define TX_FES_STATUS_ACK_OR_BA_SW_PEER_ID_OFFSET 0x0000000000000000
|
||||
#define TX_FES_STATUS_ACK_OR_BA_SW_PEER_ID_LSB 32
|
||||
#define TX_FES_STATUS_ACK_OR_BA_SW_PEER_ID_MSB 47
|
||||
#define TX_FES_STATUS_ACK_OR_BA_SW_PEER_ID_MASK 0x0000ffff00000000
|
||||
|
||||
#define TX_FES_STATUS_ACK_OR_BA_RESERVED_1A_OFFSET 0x0000000000000000
|
||||
#define TX_FES_STATUS_ACK_OR_BA_RESERVED_1A_LSB 48
|
||||
#define TX_FES_STATUS_ACK_OR_BA_RESERVED_1A_MSB 63
|
||||
#define TX_FES_STATUS_ACK_OR_BA_RESERVED_1A_MASK 0xffff000000000000
|
||||
|
||||
#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_31_0_OFFSET 0x0000000000000008
|
||||
#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_31_0_LSB 0
|
||||
#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_31_0_MSB 31
|
||||
#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_31_0_MASK 0x00000000ffffffff
|
||||
|
||||
#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_63_32_OFFSET 0x0000000000000008
|
||||
#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_63_32_LSB 32
|
||||
#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_63_32_MSB 63
|
||||
#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_63_32_MASK 0xffffffff00000000
|
||||
|
||||
#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_95_64_OFFSET 0x0000000000000010
|
||||
#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_95_64_LSB 0
|
||||
#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_95_64_MSB 31
|
||||
#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_95_64_MASK 0x00000000ffffffff
|
||||
|
||||
#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_127_96_OFFSET 0x0000000000000010
|
||||
#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_127_96_LSB 32
|
||||
#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_127_96_MSB 63
|
||||
#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_127_96_MASK 0xffffffff00000000
|
||||
|
||||
#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_159_128_OFFSET 0x0000000000000018
|
||||
#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_159_128_LSB 0
|
||||
#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_159_128_MSB 31
|
||||
#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_159_128_MASK 0x00000000ffffffff
|
||||
|
||||
#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_191_160_OFFSET 0x0000000000000018
|
||||
#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_191_160_LSB 32
|
||||
#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_191_160_MSB 63
|
||||
#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_191_160_MASK 0xffffffff00000000
|
||||
|
||||
#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_223_192_OFFSET 0x0000000000000020
|
||||
#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_223_192_LSB 0
|
||||
#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_223_192_MSB 31
|
||||
#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_223_192_MASK 0x00000000ffffffff
|
||||
|
||||
#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_255_224_OFFSET 0x0000000000000020
|
||||
#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_255_224_LSB 32
|
||||
#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_255_224_MSB 63
|
||||
#define TX_FES_STATUS_ACK_OR_BA_BA_BITMAP_255_224_MASK 0xffffffff00000000
|
||||
|
||||
#endif
|
||||
739
hw/kiwi/v2/tx_fes_status_end.h
Normal file
739
hw/kiwi/v2/tx_fes_status_end.h
Normal file
|
|
@ -0,0 +1,739 @@
|
|||
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
#ifndef _TX_FES_STATUS_END_H_
|
||||
#define _TX_FES_STATUS_END_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#include "phytx_abort_request_info.h"
|
||||
#define NUM_OF_DWORDS_TX_FES_STATUS_END 22
|
||||
|
||||
#define NUM_OF_QWORDS_TX_FES_STATUS_END 11
|
||||
|
||||
struct tx_fes_status_end {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t prot_coex_bt_tx_while_wlan_tx : 1,
|
||||
prot_coex_bt_tx_while_wlan_rx : 1,
|
||||
prot_coex_wan_tx_while_wlan_tx : 1,
|
||||
prot_coex_wan_tx_while_wlan_rx : 1,
|
||||
prot_coex_wlan_tx_while_wlan_tx : 1,
|
||||
prot_coex_wlan_tx_while_wlan_rx : 1,
|
||||
coex_bt_tx_while_wlan_tx : 1,
|
||||
coex_bt_tx_while_wlan_rx : 1,
|
||||
coex_wan_tx_while_wlan_tx : 1,
|
||||
coex_wan_tx_while_wlan_rx : 1,
|
||||
coex_wlan_tx_while_wlan_tx : 1,
|
||||
coex_wlan_tx_while_wlan_rx : 1,
|
||||
global_data_underflow_warning : 1,
|
||||
global_fes_transmit_result : 4,
|
||||
cbf_bw_received_valid : 1,
|
||||
cbf_bw_received : 3,
|
||||
actual_received_ack_type : 4,
|
||||
sta_response_count : 6,
|
||||
dpdtrain_done : 1;
|
||||
struct phytx_abort_request_info phytx_abort_request_info_details;
|
||||
uint16_t reserved_after_struct16 : 4,
|
||||
brp_info_valid : 1,
|
||||
reserved_1a : 6,
|
||||
phytx_pkt_end_info_valid : 1,
|
||||
phytx_abort_request_info_valid : 1,
|
||||
fes_in_11ax_trigger_response_config : 1,
|
||||
null_delim_inserted_before_mpdus : 1,
|
||||
only_null_delim_sent : 1;
|
||||
uint32_t start_of_frame_timestamp_15_0 : 16,
|
||||
start_of_frame_timestamp_31_16 : 16;
|
||||
uint32_t end_of_frame_timestamp_15_0 : 16,
|
||||
end_of_frame_timestamp_31_16 : 16;
|
||||
uint32_t terminate___reserved_g_0005_sequence : 1,
|
||||
reserved_4a : 7,
|
||||
timing_status : 2,
|
||||
response_type : 5,
|
||||
r2r_end_status_to_follow : 1,
|
||||
transmit_delay : 16;
|
||||
uint32_t tx_group_delay : 12,
|
||||
reserved_5a : 4,
|
||||
tpc_dbg_info_cmn_15_0 : 16;
|
||||
uint32_t tpc_dbg_info_cmn_31_16 : 16,
|
||||
tpc_dbg_info_47_32 : 16;
|
||||
uint32_t tpc_dbg_info_chn1_15_0 : 16,
|
||||
tpc_dbg_info_chn1_31_16 : 16;
|
||||
uint32_t tpc_dbg_info_chn1_47_32 : 16,
|
||||
tpc_dbg_info_chn1_63_48 : 16;
|
||||
uint32_t tpc_dbg_info_chn1_79_64 : 16,
|
||||
tpc_dbg_info_chn2_15_0 : 16;
|
||||
uint32_t tpc_dbg_info_chn2_31_16 : 16,
|
||||
tpc_dbg_info_chn2_47_32 : 16;
|
||||
uint32_t tpc_dbg_info_chn2_63_48 : 16,
|
||||
tpc_dbg_info_chn2_79_64 : 16;
|
||||
uint32_t phytx_tx_end_sw_info_15_0 : 16,
|
||||
phytx_tx_end_sw_info_31_16 : 16;
|
||||
uint32_t phytx_tx_end_sw_info_47_32 : 16,
|
||||
phytx_tx_end_sw_info_63_48 : 16;
|
||||
uint32_t beamform_masked_user_bitmap_15_0 : 16,
|
||||
beamform_masked_user_bitmap_31_16 : 16;
|
||||
uint32_t cbf_segment_request_mask : 8,
|
||||
cbf_segment_sent_mask : 8,
|
||||
highest_achieved_data_null_ratio : 5,
|
||||
use_alt_power_sr : 1,
|
||||
static_2_pwr_mode_status : 1,
|
||||
obss_srg_opport_transmit_status : 1,
|
||||
srp_based_transmit_status : 1,
|
||||
obss_pd_based_transmit_status : 1,
|
||||
beamform_masked_user_bitmap_36_32 : 5,
|
||||
pdg_mpdu_ready : 1;
|
||||
uint32_t pdg_mpdu_count : 16,
|
||||
pdg_est_mpdu_tx_count : 16;
|
||||
uint32_t pdg_overview_length : 24,
|
||||
txop_duration : 7,
|
||||
pdg_dropped_mpdu_warning : 1;
|
||||
uint32_t packet_extension_a_factor : 2,
|
||||
packet_extension_pe_disambiguity : 1,
|
||||
packet_extension : 3,
|
||||
fec_type : 1,
|
||||
stbc : 1,
|
||||
num_data_symbols : 16,
|
||||
ru_size : 4,
|
||||
reserved_17a : 4;
|
||||
uint32_t num_ltf_symbols : 3,
|
||||
ltf_size : 2,
|
||||
cp_setting : 2,
|
||||
reserved_18a : 5,
|
||||
dcm : 1,
|
||||
ldpc_extra_symbol : 1,
|
||||
force_extra_symbol : 1,
|
||||
reserved_18b : 1,
|
||||
tx_pwr_shared : 8,
|
||||
tx_pwr_unshared : 8;
|
||||
uint32_t __reserved_g_0005_active_user_map : 16,
|
||||
__reserved_g_0005_sent_dummy_tx : 1,
|
||||
__reserved_g_0005_ftm_frame_sent : 1,
|
||||
reserved_20a : 6,
|
||||
cv_corr_status : 8;
|
||||
uint32_t current_tx_duration : 16,
|
||||
reserved_21a : 16;
|
||||
#else
|
||||
uint32_t dpdtrain_done : 1,
|
||||
sta_response_count : 6,
|
||||
actual_received_ack_type : 4,
|
||||
cbf_bw_received : 3,
|
||||
cbf_bw_received_valid : 1,
|
||||
global_fes_transmit_result : 4,
|
||||
global_data_underflow_warning : 1,
|
||||
coex_wlan_tx_while_wlan_rx : 1,
|
||||
coex_wlan_tx_while_wlan_tx : 1,
|
||||
coex_wan_tx_while_wlan_rx : 1,
|
||||
coex_wan_tx_while_wlan_tx : 1,
|
||||
coex_bt_tx_while_wlan_rx : 1,
|
||||
coex_bt_tx_while_wlan_tx : 1,
|
||||
prot_coex_wlan_tx_while_wlan_rx : 1,
|
||||
prot_coex_wlan_tx_while_wlan_tx : 1,
|
||||
prot_coex_wan_tx_while_wlan_rx : 1,
|
||||
prot_coex_wan_tx_while_wlan_tx : 1,
|
||||
prot_coex_bt_tx_while_wlan_rx : 1,
|
||||
prot_coex_bt_tx_while_wlan_tx : 1;
|
||||
uint32_t only_null_delim_sent : 1,
|
||||
null_delim_inserted_before_mpdus : 1,
|
||||
fes_in_11ax_trigger_response_config : 1,
|
||||
phytx_abort_request_info_valid : 1,
|
||||
phytx_pkt_end_info_valid : 1,
|
||||
reserved_1a : 6,
|
||||
brp_info_valid : 1,
|
||||
reserved_after_struct16 : 4;
|
||||
struct phytx_abort_request_info phytx_abort_request_info_details;
|
||||
uint32_t start_of_frame_timestamp_31_16 : 16,
|
||||
start_of_frame_timestamp_15_0 : 16;
|
||||
uint32_t end_of_frame_timestamp_31_16 : 16,
|
||||
end_of_frame_timestamp_15_0 : 16;
|
||||
uint32_t transmit_delay : 16,
|
||||
r2r_end_status_to_follow : 1,
|
||||
response_type : 5,
|
||||
timing_status : 2,
|
||||
reserved_4a : 7,
|
||||
terminate___reserved_g_0005_sequence : 1;
|
||||
uint32_t tpc_dbg_info_cmn_15_0 : 16,
|
||||
reserved_5a : 4,
|
||||
tx_group_delay : 12;
|
||||
uint32_t tpc_dbg_info_47_32 : 16,
|
||||
tpc_dbg_info_cmn_31_16 : 16;
|
||||
uint32_t tpc_dbg_info_chn1_31_16 : 16,
|
||||
tpc_dbg_info_chn1_15_0 : 16;
|
||||
uint32_t tpc_dbg_info_chn1_63_48 : 16,
|
||||
tpc_dbg_info_chn1_47_32 : 16;
|
||||
uint32_t tpc_dbg_info_chn2_15_0 : 16,
|
||||
tpc_dbg_info_chn1_79_64 : 16;
|
||||
uint32_t tpc_dbg_info_chn2_47_32 : 16,
|
||||
tpc_dbg_info_chn2_31_16 : 16;
|
||||
uint32_t tpc_dbg_info_chn2_79_64 : 16,
|
||||
tpc_dbg_info_chn2_63_48 : 16;
|
||||
uint32_t phytx_tx_end_sw_info_31_16 : 16,
|
||||
phytx_tx_end_sw_info_15_0 : 16;
|
||||
uint32_t phytx_tx_end_sw_info_63_48 : 16,
|
||||
phytx_tx_end_sw_info_47_32 : 16;
|
||||
uint32_t beamform_masked_user_bitmap_31_16 : 16,
|
||||
beamform_masked_user_bitmap_15_0 : 16;
|
||||
uint32_t pdg_mpdu_ready : 1,
|
||||
beamform_masked_user_bitmap_36_32 : 5,
|
||||
obss_pd_based_transmit_status : 1,
|
||||
srp_based_transmit_status : 1,
|
||||
obss_srg_opport_transmit_status : 1,
|
||||
static_2_pwr_mode_status : 1,
|
||||
use_alt_power_sr : 1,
|
||||
highest_achieved_data_null_ratio : 5,
|
||||
cbf_segment_sent_mask : 8,
|
||||
cbf_segment_request_mask : 8;
|
||||
uint32_t pdg_est_mpdu_tx_count : 16,
|
||||
pdg_mpdu_count : 16;
|
||||
uint32_t pdg_dropped_mpdu_warning : 1,
|
||||
txop_duration : 7,
|
||||
pdg_overview_length : 24;
|
||||
uint32_t reserved_17a : 4,
|
||||
ru_size : 4,
|
||||
num_data_symbols : 16,
|
||||
stbc : 1,
|
||||
fec_type : 1,
|
||||
packet_extension : 3,
|
||||
packet_extension_pe_disambiguity : 1,
|
||||
packet_extension_a_factor : 2;
|
||||
uint32_t tx_pwr_unshared : 8,
|
||||
tx_pwr_shared : 8,
|
||||
reserved_18b : 1,
|
||||
force_extra_symbol : 1,
|
||||
ldpc_extra_symbol : 1,
|
||||
dcm : 1,
|
||||
reserved_18a : 5,
|
||||
cp_setting : 2,
|
||||
ltf_size : 2,
|
||||
num_ltf_symbols : 3;
|
||||
uint32_t cv_corr_status : 8,
|
||||
reserved_20a : 6,
|
||||
__reserved_g_0005_ftm_frame_sent : 1,
|
||||
__reserved_g_0005_sent_dummy_tx : 1,
|
||||
__reserved_g_0005_active_user_map : 16;
|
||||
uint32_t reserved_21a : 16,
|
||||
current_tx_duration : 16;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_TX_OFFSET 0x0000000000000000
|
||||
#define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_TX_LSB 0
|
||||
#define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_TX_MSB 0
|
||||
#define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_TX_MASK 0x0000000000000001
|
||||
|
||||
#define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_RX_OFFSET 0x0000000000000000
|
||||
#define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_RX_LSB 1
|
||||
#define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_RX_MSB 1
|
||||
#define TX_FES_STATUS_END_PROT_COEX_BT_TX_WHILE_WLAN_RX_MASK 0x0000000000000002
|
||||
|
||||
#define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_TX_OFFSET 0x0000000000000000
|
||||
#define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_TX_LSB 2
|
||||
#define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_TX_MSB 2
|
||||
#define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_TX_MASK 0x0000000000000004
|
||||
|
||||
#define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_RX_OFFSET 0x0000000000000000
|
||||
#define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_RX_LSB 3
|
||||
#define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_RX_MSB 3
|
||||
#define TX_FES_STATUS_END_PROT_COEX_WAN_TX_WHILE_WLAN_RX_MASK 0x0000000000000008
|
||||
|
||||
#define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_TX_OFFSET 0x0000000000000000
|
||||
#define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_TX_LSB 4
|
||||
#define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_TX_MSB 4
|
||||
#define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_TX_MASK 0x0000000000000010
|
||||
|
||||
#define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_RX_OFFSET 0x0000000000000000
|
||||
#define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_RX_LSB 5
|
||||
#define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_RX_MSB 5
|
||||
#define TX_FES_STATUS_END_PROT_COEX_WLAN_TX_WHILE_WLAN_RX_MASK 0x0000000000000020
|
||||
|
||||
#define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_TX_OFFSET 0x0000000000000000
|
||||
#define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_TX_LSB 6
|
||||
#define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_TX_MSB 6
|
||||
#define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_TX_MASK 0x0000000000000040
|
||||
|
||||
#define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_RX_OFFSET 0x0000000000000000
|
||||
#define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_RX_LSB 7
|
||||
#define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_RX_MSB 7
|
||||
#define TX_FES_STATUS_END_COEX_BT_TX_WHILE_WLAN_RX_MASK 0x0000000000000080
|
||||
|
||||
#define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_TX_OFFSET 0x0000000000000000
|
||||
#define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_TX_LSB 8
|
||||
#define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_TX_MSB 8
|
||||
#define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_TX_MASK 0x0000000000000100
|
||||
|
||||
#define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_RX_OFFSET 0x0000000000000000
|
||||
#define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_RX_LSB 9
|
||||
#define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_RX_MSB 9
|
||||
#define TX_FES_STATUS_END_COEX_WAN_TX_WHILE_WLAN_RX_MASK 0x0000000000000200
|
||||
|
||||
#define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_TX_OFFSET 0x0000000000000000
|
||||
#define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_TX_LSB 10
|
||||
#define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_TX_MSB 10
|
||||
#define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_TX_MASK 0x0000000000000400
|
||||
|
||||
#define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_RX_OFFSET 0x0000000000000000
|
||||
#define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_RX_LSB 11
|
||||
#define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_RX_MSB 11
|
||||
#define TX_FES_STATUS_END_COEX_WLAN_TX_WHILE_WLAN_RX_MASK 0x0000000000000800
|
||||
|
||||
#define TX_FES_STATUS_END_GLOBAL_DATA_UNDERFLOW_WARNING_OFFSET 0x0000000000000000
|
||||
#define TX_FES_STATUS_END_GLOBAL_DATA_UNDERFLOW_WARNING_LSB 12
|
||||
#define TX_FES_STATUS_END_GLOBAL_DATA_UNDERFLOW_WARNING_MSB 12
|
||||
#define TX_FES_STATUS_END_GLOBAL_DATA_UNDERFLOW_WARNING_MASK 0x0000000000001000
|
||||
|
||||
#define TX_FES_STATUS_END_GLOBAL_FES_TRANSMIT_RESULT_OFFSET 0x0000000000000000
|
||||
#define TX_FES_STATUS_END_GLOBAL_FES_TRANSMIT_RESULT_LSB 13
|
||||
#define TX_FES_STATUS_END_GLOBAL_FES_TRANSMIT_RESULT_MSB 16
|
||||
#define TX_FES_STATUS_END_GLOBAL_FES_TRANSMIT_RESULT_MASK 0x000000000001e000
|
||||
|
||||
#define TX_FES_STATUS_END_CBF_BW_RECEIVED_VALID_OFFSET 0x0000000000000000
|
||||
#define TX_FES_STATUS_END_CBF_BW_RECEIVED_VALID_LSB 17
|
||||
#define TX_FES_STATUS_END_CBF_BW_RECEIVED_VALID_MSB 17
|
||||
#define TX_FES_STATUS_END_CBF_BW_RECEIVED_VALID_MASK 0x0000000000020000
|
||||
|
||||
#define TX_FES_STATUS_END_CBF_BW_RECEIVED_OFFSET 0x0000000000000000
|
||||
#define TX_FES_STATUS_END_CBF_BW_RECEIVED_LSB 18
|
||||
#define TX_FES_STATUS_END_CBF_BW_RECEIVED_MSB 20
|
||||
#define TX_FES_STATUS_END_CBF_BW_RECEIVED_MASK 0x00000000001c0000
|
||||
|
||||
#define TX_FES_STATUS_END_ACTUAL_RECEIVED_ACK_TYPE_OFFSET 0x0000000000000000
|
||||
#define TX_FES_STATUS_END_ACTUAL_RECEIVED_ACK_TYPE_LSB 21
|
||||
#define TX_FES_STATUS_END_ACTUAL_RECEIVED_ACK_TYPE_MSB 24
|
||||
#define TX_FES_STATUS_END_ACTUAL_RECEIVED_ACK_TYPE_MASK 0x0000000001e00000
|
||||
|
||||
#define TX_FES_STATUS_END_STA_RESPONSE_COUNT_OFFSET 0x0000000000000000
|
||||
#define TX_FES_STATUS_END_STA_RESPONSE_COUNT_LSB 25
|
||||
#define TX_FES_STATUS_END_STA_RESPONSE_COUNT_MSB 30
|
||||
#define TX_FES_STATUS_END_STA_RESPONSE_COUNT_MASK 0x000000007e000000
|
||||
|
||||
#define TX_FES_STATUS_END_DPDTRAIN_DONE_OFFSET 0x0000000000000000
|
||||
#define TX_FES_STATUS_END_DPDTRAIN_DONE_LSB 31
|
||||
#define TX_FES_STATUS_END_DPDTRAIN_DONE_MSB 31
|
||||
#define TX_FES_STATUS_END_DPDTRAIN_DONE_MASK 0x0000000080000000
|
||||
|
||||
#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_OFFSET 0x0000000000000000
|
||||
#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_LSB 32
|
||||
#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MSB 39
|
||||
#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MASK 0x000000ff00000000
|
||||
|
||||
#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_OFFSET 0x0000000000000000
|
||||
#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_LSB 40
|
||||
#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MSB 45
|
||||
#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MASK 0x00003f0000000000
|
||||
|
||||
#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000
|
||||
#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_LSB 46
|
||||
#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MSB 47
|
||||
#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MASK 0x0000c00000000000
|
||||
|
||||
#define TX_FES_STATUS_END_RESERVED_AFTER_STRUCT16_OFFSET 0x0000000000000000
|
||||
#define TX_FES_STATUS_END_RESERVED_AFTER_STRUCT16_LSB 48
|
||||
#define TX_FES_STATUS_END_RESERVED_AFTER_STRUCT16_MSB 51
|
||||
#define TX_FES_STATUS_END_RESERVED_AFTER_STRUCT16_MASK 0x000f000000000000
|
||||
|
||||
#define TX_FES_STATUS_END_BRP_INFO_VALID_OFFSET 0x0000000000000000
|
||||
#define TX_FES_STATUS_END_BRP_INFO_VALID_LSB 52
|
||||
#define TX_FES_STATUS_END_BRP_INFO_VALID_MSB 52
|
||||
#define TX_FES_STATUS_END_BRP_INFO_VALID_MASK 0x0010000000000000
|
||||
|
||||
#define TX_FES_STATUS_END_RESERVED_1A_OFFSET 0x0000000000000000
|
||||
#define TX_FES_STATUS_END_RESERVED_1A_LSB 53
|
||||
#define TX_FES_STATUS_END_RESERVED_1A_MSB 58
|
||||
#define TX_FES_STATUS_END_RESERVED_1A_MASK 0x07e0000000000000
|
||||
|
||||
#define TX_FES_STATUS_END_PHYTX_PKT_END_INFO_VALID_OFFSET 0x0000000000000000
|
||||
#define TX_FES_STATUS_END_PHYTX_PKT_END_INFO_VALID_LSB 59
|
||||
#define TX_FES_STATUS_END_PHYTX_PKT_END_INFO_VALID_MSB 59
|
||||
#define TX_FES_STATUS_END_PHYTX_PKT_END_INFO_VALID_MASK 0x0800000000000000
|
||||
|
||||
#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_VALID_OFFSET 0x0000000000000000
|
||||
#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_VALID_LSB 60
|
||||
#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_VALID_MSB 60
|
||||
#define TX_FES_STATUS_END_PHYTX_ABORT_REQUEST_INFO_VALID_MASK 0x1000000000000000
|
||||
|
||||
#define TX_FES_STATUS_END_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_OFFSET 0x0000000000000000
|
||||
#define TX_FES_STATUS_END_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_LSB 61
|
||||
#define TX_FES_STATUS_END_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_MSB 61
|
||||
#define TX_FES_STATUS_END_FES_IN_11AX_TRIGGER_RESPONSE_CONFIG_MASK 0x2000000000000000
|
||||
|
||||
#define TX_FES_STATUS_END_NULL_DELIM_INSERTED_BEFORE_MPDUS_OFFSET 0x0000000000000000
|
||||
#define TX_FES_STATUS_END_NULL_DELIM_INSERTED_BEFORE_MPDUS_LSB 62
|
||||
#define TX_FES_STATUS_END_NULL_DELIM_INSERTED_BEFORE_MPDUS_MSB 62
|
||||
#define TX_FES_STATUS_END_NULL_DELIM_INSERTED_BEFORE_MPDUS_MASK 0x4000000000000000
|
||||
|
||||
#define TX_FES_STATUS_END_ONLY_NULL_DELIM_SENT_OFFSET 0x0000000000000000
|
||||
#define TX_FES_STATUS_END_ONLY_NULL_DELIM_SENT_LSB 63
|
||||
#define TX_FES_STATUS_END_ONLY_NULL_DELIM_SENT_MSB 63
|
||||
#define TX_FES_STATUS_END_ONLY_NULL_DELIM_SENT_MASK 0x8000000000000000
|
||||
|
||||
#define TX_FES_STATUS_END_START_OF_FRAME_TIMESTAMP_15_0_OFFSET 0x0000000000000008
|
||||
#define TX_FES_STATUS_END_START_OF_FRAME_TIMESTAMP_15_0_LSB 0
|
||||
#define TX_FES_STATUS_END_START_OF_FRAME_TIMESTAMP_15_0_MSB 15
|
||||
#define TX_FES_STATUS_END_START_OF_FRAME_TIMESTAMP_15_0_MASK 0x000000000000ffff
|
||||
|
||||
#define TX_FES_STATUS_END_START_OF_FRAME_TIMESTAMP_31_16_OFFSET 0x0000000000000008
|
||||
#define TX_FES_STATUS_END_START_OF_FRAME_TIMESTAMP_31_16_LSB 16
|
||||
#define TX_FES_STATUS_END_START_OF_FRAME_TIMESTAMP_31_16_MSB 31
|
||||
#define TX_FES_STATUS_END_START_OF_FRAME_TIMESTAMP_31_16_MASK 0x00000000ffff0000
|
||||
|
||||
#define TX_FES_STATUS_END_END_OF_FRAME_TIMESTAMP_15_0_OFFSET 0x0000000000000008
|
||||
#define TX_FES_STATUS_END_END_OF_FRAME_TIMESTAMP_15_0_LSB 32
|
||||
#define TX_FES_STATUS_END_END_OF_FRAME_TIMESTAMP_15_0_MSB 47
|
||||
#define TX_FES_STATUS_END_END_OF_FRAME_TIMESTAMP_15_0_MASK 0x0000ffff00000000
|
||||
|
||||
#define TX_FES_STATUS_END_END_OF_FRAME_TIMESTAMP_31_16_OFFSET 0x0000000000000008
|
||||
#define TX_FES_STATUS_END_END_OF_FRAME_TIMESTAMP_31_16_LSB 48
|
||||
#define TX_FES_STATUS_END_END_OF_FRAME_TIMESTAMP_31_16_MSB 63
|
||||
#define TX_FES_STATUS_END_END_OF_FRAME_TIMESTAMP_31_16_MASK 0xffff000000000000
|
||||
|
||||
#define TX_FES_STATUS_END_TERMINATE_RANGING_SEQUENCE_OFFSET 0x0000000000000010
|
||||
#define TX_FES_STATUS_END_TERMINATE_RANGING_SEQUENCE_LSB 0
|
||||
#define TX_FES_STATUS_END_TERMINATE_RANGING_SEQUENCE_MSB 0
|
||||
#define TX_FES_STATUS_END_TERMINATE_RANGING_SEQUENCE_MASK 0x0000000000000001
|
||||
|
||||
#define TX_FES_STATUS_END_RESERVED_4A_OFFSET 0x0000000000000010
|
||||
#define TX_FES_STATUS_END_RESERVED_4A_LSB 1
|
||||
#define TX_FES_STATUS_END_RESERVED_4A_MSB 7
|
||||
#define TX_FES_STATUS_END_RESERVED_4A_MASK 0x00000000000000fe
|
||||
|
||||
#define TX_FES_STATUS_END_TIMING_STATUS_OFFSET 0x0000000000000010
|
||||
#define TX_FES_STATUS_END_TIMING_STATUS_LSB 8
|
||||
#define TX_FES_STATUS_END_TIMING_STATUS_MSB 9
|
||||
#define TX_FES_STATUS_END_TIMING_STATUS_MASK 0x0000000000000300
|
||||
|
||||
#define TX_FES_STATUS_END_RESPONSE_TYPE_OFFSET 0x0000000000000010
|
||||
#define TX_FES_STATUS_END_RESPONSE_TYPE_LSB 10
|
||||
#define TX_FES_STATUS_END_RESPONSE_TYPE_MSB 14
|
||||
#define TX_FES_STATUS_END_RESPONSE_TYPE_MASK 0x0000000000007c00
|
||||
|
||||
#define TX_FES_STATUS_END_R2R_END_STATUS_TO_FOLLOW_OFFSET 0x0000000000000010
|
||||
#define TX_FES_STATUS_END_R2R_END_STATUS_TO_FOLLOW_LSB 15
|
||||
#define TX_FES_STATUS_END_R2R_END_STATUS_TO_FOLLOW_MSB 15
|
||||
#define TX_FES_STATUS_END_R2R_END_STATUS_TO_FOLLOW_MASK 0x0000000000008000
|
||||
|
||||
#define TX_FES_STATUS_END_TRANSMIT_DELAY_OFFSET 0x0000000000000010
|
||||
#define TX_FES_STATUS_END_TRANSMIT_DELAY_LSB 16
|
||||
#define TX_FES_STATUS_END_TRANSMIT_DELAY_MSB 31
|
||||
#define TX_FES_STATUS_END_TRANSMIT_DELAY_MASK 0x00000000ffff0000
|
||||
|
||||
#define TX_FES_STATUS_END_TX_GROUP_DELAY_OFFSET 0x0000000000000010
|
||||
#define TX_FES_STATUS_END_TX_GROUP_DELAY_LSB 32
|
||||
#define TX_FES_STATUS_END_TX_GROUP_DELAY_MSB 43
|
||||
#define TX_FES_STATUS_END_TX_GROUP_DELAY_MASK 0x00000fff00000000
|
||||
|
||||
#define TX_FES_STATUS_END_RESERVED_5A_OFFSET 0x0000000000000010
|
||||
#define TX_FES_STATUS_END_RESERVED_5A_LSB 44
|
||||
#define TX_FES_STATUS_END_RESERVED_5A_MSB 47
|
||||
#define TX_FES_STATUS_END_RESERVED_5A_MASK 0x0000f00000000000
|
||||
|
||||
#define TX_FES_STATUS_END_TPC_DBG_INFO_CMN_15_0_OFFSET 0x0000000000000010
|
||||
#define TX_FES_STATUS_END_TPC_DBG_INFO_CMN_15_0_LSB 48
|
||||
#define TX_FES_STATUS_END_TPC_DBG_INFO_CMN_15_0_MSB 63
|
||||
#define TX_FES_STATUS_END_TPC_DBG_INFO_CMN_15_0_MASK 0xffff000000000000
|
||||
|
||||
#define TX_FES_STATUS_END_TPC_DBG_INFO_CMN_31_16_OFFSET 0x0000000000000018
|
||||
#define TX_FES_STATUS_END_TPC_DBG_INFO_CMN_31_16_LSB 0
|
||||
#define TX_FES_STATUS_END_TPC_DBG_INFO_CMN_31_16_MSB 15
|
||||
#define TX_FES_STATUS_END_TPC_DBG_INFO_CMN_31_16_MASK 0x000000000000ffff
|
||||
|
||||
#define TX_FES_STATUS_END_TPC_DBG_INFO_47_32_OFFSET 0x0000000000000018
|
||||
#define TX_FES_STATUS_END_TPC_DBG_INFO_47_32_LSB 16
|
||||
#define TX_FES_STATUS_END_TPC_DBG_INFO_47_32_MSB 31
|
||||
#define TX_FES_STATUS_END_TPC_DBG_INFO_47_32_MASK 0x00000000ffff0000
|
||||
|
||||
#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_15_0_OFFSET 0x0000000000000018
|
||||
#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_15_0_LSB 32
|
||||
#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_15_0_MSB 47
|
||||
#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_15_0_MASK 0x0000ffff00000000
|
||||
|
||||
#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_31_16_OFFSET 0x0000000000000018
|
||||
#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_31_16_LSB 48
|
||||
#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_31_16_MSB 63
|
||||
#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_31_16_MASK 0xffff000000000000
|
||||
|
||||
#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_47_32_OFFSET 0x0000000000000020
|
||||
#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_47_32_LSB 0
|
||||
#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_47_32_MSB 15
|
||||
#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_47_32_MASK 0x000000000000ffff
|
||||
|
||||
#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_63_48_OFFSET 0x0000000000000020
|
||||
#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_63_48_LSB 16
|
||||
#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_63_48_MSB 31
|
||||
#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_63_48_MASK 0x00000000ffff0000
|
||||
|
||||
#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_79_64_OFFSET 0x0000000000000020
|
||||
#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_79_64_LSB 32
|
||||
#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_79_64_MSB 47
|
||||
#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN1_79_64_MASK 0x0000ffff00000000
|
||||
|
||||
#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_15_0_OFFSET 0x0000000000000020
|
||||
#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_15_0_LSB 48
|
||||
#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_15_0_MSB 63
|
||||
#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_15_0_MASK 0xffff000000000000
|
||||
|
||||
#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_31_16_OFFSET 0x0000000000000028
|
||||
#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_31_16_LSB 0
|
||||
#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_31_16_MSB 15
|
||||
#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_31_16_MASK 0x000000000000ffff
|
||||
|
||||
#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_47_32_OFFSET 0x0000000000000028
|
||||
#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_47_32_LSB 16
|
||||
#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_47_32_MSB 31
|
||||
#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_47_32_MASK 0x00000000ffff0000
|
||||
|
||||
#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_63_48_OFFSET 0x0000000000000028
|
||||
#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_63_48_LSB 32
|
||||
#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_63_48_MSB 47
|
||||
#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_63_48_MASK 0x0000ffff00000000
|
||||
|
||||
#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_79_64_OFFSET 0x0000000000000028
|
||||
#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_79_64_LSB 48
|
||||
#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_79_64_MSB 63
|
||||
#define TX_FES_STATUS_END_TPC_DBG_INFO_CHN2_79_64_MASK 0xffff000000000000
|
||||
|
||||
#define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_15_0_OFFSET 0x0000000000000030
|
||||
#define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_15_0_LSB 0
|
||||
#define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_15_0_MSB 15
|
||||
#define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_15_0_MASK 0x000000000000ffff
|
||||
|
||||
#define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_31_16_OFFSET 0x0000000000000030
|
||||
#define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_31_16_LSB 16
|
||||
#define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_31_16_MSB 31
|
||||
#define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_31_16_MASK 0x00000000ffff0000
|
||||
|
||||
#define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_47_32_OFFSET 0x0000000000000030
|
||||
#define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_47_32_LSB 32
|
||||
#define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_47_32_MSB 47
|
||||
#define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_47_32_MASK 0x0000ffff00000000
|
||||
|
||||
#define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_63_48_OFFSET 0x0000000000000030
|
||||
#define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_63_48_LSB 48
|
||||
#define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_63_48_MSB 63
|
||||
#define TX_FES_STATUS_END_PHYTX_TX_END_SW_INFO_63_48_MASK 0xffff000000000000
|
||||
|
||||
#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_15_0_OFFSET 0x0000000000000038
|
||||
#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_15_0_LSB 0
|
||||
#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_15_0_MSB 15
|
||||
#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_15_0_MASK 0x000000000000ffff
|
||||
|
||||
#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_31_16_OFFSET 0x0000000000000038
|
||||
#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_31_16_LSB 16
|
||||
#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_31_16_MSB 31
|
||||
#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_31_16_MASK 0x00000000ffff0000
|
||||
|
||||
#define TX_FES_STATUS_END_CBF_SEGMENT_REQUEST_MASK_OFFSET 0x0000000000000038
|
||||
#define TX_FES_STATUS_END_CBF_SEGMENT_REQUEST_MASK_LSB 32
|
||||
#define TX_FES_STATUS_END_CBF_SEGMENT_REQUEST_MASK_MSB 39
|
||||
#define TX_FES_STATUS_END_CBF_SEGMENT_REQUEST_MASK_MASK 0x000000ff00000000
|
||||
|
||||
#define TX_FES_STATUS_END_CBF_SEGMENT_SENT_MASK_OFFSET 0x0000000000000038
|
||||
#define TX_FES_STATUS_END_CBF_SEGMENT_SENT_MASK_LSB 40
|
||||
#define TX_FES_STATUS_END_CBF_SEGMENT_SENT_MASK_MSB 47
|
||||
#define TX_FES_STATUS_END_CBF_SEGMENT_SENT_MASK_MASK 0x0000ff0000000000
|
||||
|
||||
#define TX_FES_STATUS_END_HIGHEST_ACHIEVED_DATA_NULL_RATIO_OFFSET 0x0000000000000038
|
||||
#define TX_FES_STATUS_END_HIGHEST_ACHIEVED_DATA_NULL_RATIO_LSB 48
|
||||
#define TX_FES_STATUS_END_HIGHEST_ACHIEVED_DATA_NULL_RATIO_MSB 52
|
||||
#define TX_FES_STATUS_END_HIGHEST_ACHIEVED_DATA_NULL_RATIO_MASK 0x001f000000000000
|
||||
|
||||
#define TX_FES_STATUS_END_USE_ALT_POWER_SR_OFFSET 0x0000000000000038
|
||||
#define TX_FES_STATUS_END_USE_ALT_POWER_SR_LSB 53
|
||||
#define TX_FES_STATUS_END_USE_ALT_POWER_SR_MSB 53
|
||||
#define TX_FES_STATUS_END_USE_ALT_POWER_SR_MASK 0x0020000000000000
|
||||
|
||||
#define TX_FES_STATUS_END_STATIC_2_PWR_MODE_STATUS_OFFSET 0x0000000000000038
|
||||
#define TX_FES_STATUS_END_STATIC_2_PWR_MODE_STATUS_LSB 54
|
||||
#define TX_FES_STATUS_END_STATIC_2_PWR_MODE_STATUS_MSB 54
|
||||
#define TX_FES_STATUS_END_STATIC_2_PWR_MODE_STATUS_MASK 0x0040000000000000
|
||||
|
||||
#define TX_FES_STATUS_END_OBSS_SRG_OPPORT_TRANSMIT_STATUS_OFFSET 0x0000000000000038
|
||||
#define TX_FES_STATUS_END_OBSS_SRG_OPPORT_TRANSMIT_STATUS_LSB 55
|
||||
#define TX_FES_STATUS_END_OBSS_SRG_OPPORT_TRANSMIT_STATUS_MSB 55
|
||||
#define TX_FES_STATUS_END_OBSS_SRG_OPPORT_TRANSMIT_STATUS_MASK 0x0080000000000000
|
||||
|
||||
#define TX_FES_STATUS_END_SRP_BASED_TRANSMIT_STATUS_OFFSET 0x0000000000000038
|
||||
#define TX_FES_STATUS_END_SRP_BASED_TRANSMIT_STATUS_LSB 56
|
||||
#define TX_FES_STATUS_END_SRP_BASED_TRANSMIT_STATUS_MSB 56
|
||||
#define TX_FES_STATUS_END_SRP_BASED_TRANSMIT_STATUS_MASK 0x0100000000000000
|
||||
|
||||
#define TX_FES_STATUS_END_OBSS_PD_BASED_TRANSMIT_STATUS_OFFSET 0x0000000000000038
|
||||
#define TX_FES_STATUS_END_OBSS_PD_BASED_TRANSMIT_STATUS_LSB 57
|
||||
#define TX_FES_STATUS_END_OBSS_PD_BASED_TRANSMIT_STATUS_MSB 57
|
||||
#define TX_FES_STATUS_END_OBSS_PD_BASED_TRANSMIT_STATUS_MASK 0x0200000000000000
|
||||
|
||||
#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_36_32_OFFSET 0x0000000000000038
|
||||
#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_36_32_LSB 58
|
||||
#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_36_32_MSB 62
|
||||
#define TX_FES_STATUS_END_BEAMFORM_MASKED_USER_BITMAP_36_32_MASK 0x7c00000000000000
|
||||
|
||||
#define TX_FES_STATUS_END_PDG_MPDU_READY_OFFSET 0x0000000000000038
|
||||
#define TX_FES_STATUS_END_PDG_MPDU_READY_LSB 63
|
||||
#define TX_FES_STATUS_END_PDG_MPDU_READY_MSB 63
|
||||
#define TX_FES_STATUS_END_PDG_MPDU_READY_MASK 0x8000000000000000
|
||||
|
||||
#define TX_FES_STATUS_END_PDG_MPDU_COUNT_OFFSET 0x0000000000000040
|
||||
#define TX_FES_STATUS_END_PDG_MPDU_COUNT_LSB 0
|
||||
#define TX_FES_STATUS_END_PDG_MPDU_COUNT_MSB 15
|
||||
#define TX_FES_STATUS_END_PDG_MPDU_COUNT_MASK 0x000000000000ffff
|
||||
|
||||
#define TX_FES_STATUS_END_PDG_EST_MPDU_TX_COUNT_OFFSET 0x0000000000000040
|
||||
#define TX_FES_STATUS_END_PDG_EST_MPDU_TX_COUNT_LSB 16
|
||||
#define TX_FES_STATUS_END_PDG_EST_MPDU_TX_COUNT_MSB 31
|
||||
#define TX_FES_STATUS_END_PDG_EST_MPDU_TX_COUNT_MASK 0x00000000ffff0000
|
||||
|
||||
#define TX_FES_STATUS_END_PDG_OVERVIEW_LENGTH_OFFSET 0x0000000000000040
|
||||
#define TX_FES_STATUS_END_PDG_OVERVIEW_LENGTH_LSB 32
|
||||
#define TX_FES_STATUS_END_PDG_OVERVIEW_LENGTH_MSB 55
|
||||
#define TX_FES_STATUS_END_PDG_OVERVIEW_LENGTH_MASK 0x00ffffff00000000
|
||||
|
||||
#define TX_FES_STATUS_END_TXOP_DURATION_OFFSET 0x0000000000000040
|
||||
#define TX_FES_STATUS_END_TXOP_DURATION_LSB 56
|
||||
#define TX_FES_STATUS_END_TXOP_DURATION_MSB 62
|
||||
#define TX_FES_STATUS_END_TXOP_DURATION_MASK 0x7f00000000000000
|
||||
|
||||
#define TX_FES_STATUS_END_PDG_DROPPED_MPDU_WARNING_OFFSET 0x0000000000000040
|
||||
#define TX_FES_STATUS_END_PDG_DROPPED_MPDU_WARNING_LSB 63
|
||||
#define TX_FES_STATUS_END_PDG_DROPPED_MPDU_WARNING_MSB 63
|
||||
#define TX_FES_STATUS_END_PDG_DROPPED_MPDU_WARNING_MASK 0x8000000000000000
|
||||
|
||||
#define TX_FES_STATUS_END_PACKET_EXTENSION_A_FACTOR_OFFSET 0x0000000000000048
|
||||
#define TX_FES_STATUS_END_PACKET_EXTENSION_A_FACTOR_LSB 0
|
||||
#define TX_FES_STATUS_END_PACKET_EXTENSION_A_FACTOR_MSB 1
|
||||
#define TX_FES_STATUS_END_PACKET_EXTENSION_A_FACTOR_MASK 0x0000000000000003
|
||||
|
||||
#define TX_FES_STATUS_END_PACKET_EXTENSION_PE_DISAMBIGUITY_OFFSET 0x0000000000000048
|
||||
#define TX_FES_STATUS_END_PACKET_EXTENSION_PE_DISAMBIGUITY_LSB 2
|
||||
#define TX_FES_STATUS_END_PACKET_EXTENSION_PE_DISAMBIGUITY_MSB 2
|
||||
#define TX_FES_STATUS_END_PACKET_EXTENSION_PE_DISAMBIGUITY_MASK 0x0000000000000004
|
||||
|
||||
#define TX_FES_STATUS_END_PACKET_EXTENSION_OFFSET 0x0000000000000048
|
||||
#define TX_FES_STATUS_END_PACKET_EXTENSION_LSB 3
|
||||
#define TX_FES_STATUS_END_PACKET_EXTENSION_MSB 5
|
||||
#define TX_FES_STATUS_END_PACKET_EXTENSION_MASK 0x0000000000000038
|
||||
|
||||
#define TX_FES_STATUS_END_FEC_TYPE_OFFSET 0x0000000000000048
|
||||
#define TX_FES_STATUS_END_FEC_TYPE_LSB 6
|
||||
#define TX_FES_STATUS_END_FEC_TYPE_MSB 6
|
||||
#define TX_FES_STATUS_END_FEC_TYPE_MASK 0x0000000000000040
|
||||
|
||||
#define TX_FES_STATUS_END_STBC_OFFSET 0x0000000000000048
|
||||
#define TX_FES_STATUS_END_STBC_LSB 7
|
||||
#define TX_FES_STATUS_END_STBC_MSB 7
|
||||
#define TX_FES_STATUS_END_STBC_MASK 0x0000000000000080
|
||||
|
||||
#define TX_FES_STATUS_END_NUM_DATA_SYMBOLS_OFFSET 0x0000000000000048
|
||||
#define TX_FES_STATUS_END_NUM_DATA_SYMBOLS_LSB 8
|
||||
#define TX_FES_STATUS_END_NUM_DATA_SYMBOLS_MSB 23
|
||||
#define TX_FES_STATUS_END_NUM_DATA_SYMBOLS_MASK 0x0000000000ffff00
|
||||
|
||||
#define TX_FES_STATUS_END_RU_SIZE_OFFSET 0x0000000000000048
|
||||
#define TX_FES_STATUS_END_RU_SIZE_LSB 24
|
||||
#define TX_FES_STATUS_END_RU_SIZE_MSB 27
|
||||
#define TX_FES_STATUS_END_RU_SIZE_MASK 0x000000000f000000
|
||||
|
||||
#define TX_FES_STATUS_END_RESERVED_17A_OFFSET 0x0000000000000048
|
||||
#define TX_FES_STATUS_END_RESERVED_17A_LSB 28
|
||||
#define TX_FES_STATUS_END_RESERVED_17A_MSB 31
|
||||
#define TX_FES_STATUS_END_RESERVED_17A_MASK 0x00000000f0000000
|
||||
|
||||
#define TX_FES_STATUS_END_NUM_LTF_SYMBOLS_OFFSET 0x0000000000000048
|
||||
#define TX_FES_STATUS_END_NUM_LTF_SYMBOLS_LSB 32
|
||||
#define TX_FES_STATUS_END_NUM_LTF_SYMBOLS_MSB 34
|
||||
#define TX_FES_STATUS_END_NUM_LTF_SYMBOLS_MASK 0x0000000700000000
|
||||
|
||||
#define TX_FES_STATUS_END_LTF_SIZE_OFFSET 0x0000000000000048
|
||||
#define TX_FES_STATUS_END_LTF_SIZE_LSB 35
|
||||
#define TX_FES_STATUS_END_LTF_SIZE_MSB 36
|
||||
#define TX_FES_STATUS_END_LTF_SIZE_MASK 0x0000001800000000
|
||||
|
||||
#define TX_FES_STATUS_END_CP_SETTING_OFFSET 0x0000000000000048
|
||||
#define TX_FES_STATUS_END_CP_SETTING_LSB 37
|
||||
#define TX_FES_STATUS_END_CP_SETTING_MSB 38
|
||||
#define TX_FES_STATUS_END_CP_SETTING_MASK 0x0000006000000000
|
||||
|
||||
#define TX_FES_STATUS_END_RESERVED_18A_OFFSET 0x0000000000000048
|
||||
#define TX_FES_STATUS_END_RESERVED_18A_LSB 39
|
||||
#define TX_FES_STATUS_END_RESERVED_18A_MSB 43
|
||||
#define TX_FES_STATUS_END_RESERVED_18A_MASK 0x00000f8000000000
|
||||
|
||||
#define TX_FES_STATUS_END_DCM_OFFSET 0x0000000000000048
|
||||
#define TX_FES_STATUS_END_DCM_LSB 44
|
||||
#define TX_FES_STATUS_END_DCM_MSB 44
|
||||
#define TX_FES_STATUS_END_DCM_MASK 0x0000100000000000
|
||||
|
||||
#define TX_FES_STATUS_END_LDPC_EXTRA_SYMBOL_OFFSET 0x0000000000000048
|
||||
#define TX_FES_STATUS_END_LDPC_EXTRA_SYMBOL_LSB 45
|
||||
#define TX_FES_STATUS_END_LDPC_EXTRA_SYMBOL_MSB 45
|
||||
#define TX_FES_STATUS_END_LDPC_EXTRA_SYMBOL_MASK 0x0000200000000000
|
||||
|
||||
#define TX_FES_STATUS_END_FORCE_EXTRA_SYMBOL_OFFSET 0x0000000000000048
|
||||
#define TX_FES_STATUS_END_FORCE_EXTRA_SYMBOL_LSB 46
|
||||
#define TX_FES_STATUS_END_FORCE_EXTRA_SYMBOL_MSB 46
|
||||
#define TX_FES_STATUS_END_FORCE_EXTRA_SYMBOL_MASK 0x0000400000000000
|
||||
|
||||
#define TX_FES_STATUS_END_RESERVED_18B_OFFSET 0x0000000000000048
|
||||
#define TX_FES_STATUS_END_RESERVED_18B_LSB 47
|
||||
#define TX_FES_STATUS_END_RESERVED_18B_MSB 47
|
||||
#define TX_FES_STATUS_END_RESERVED_18B_MASK 0x0000800000000000
|
||||
|
||||
#define TX_FES_STATUS_END_TX_PWR_SHARED_OFFSET 0x0000000000000048
|
||||
#define TX_FES_STATUS_END_TX_PWR_SHARED_LSB 48
|
||||
#define TX_FES_STATUS_END_TX_PWR_SHARED_MSB 55
|
||||
#define TX_FES_STATUS_END_TX_PWR_SHARED_MASK 0x00ff000000000000
|
||||
|
||||
#define TX_FES_STATUS_END_TX_PWR_UNSHARED_OFFSET 0x0000000000000048
|
||||
#define TX_FES_STATUS_END_TX_PWR_UNSHARED_LSB 56
|
||||
#define TX_FES_STATUS_END_TX_PWR_UNSHARED_MSB 63
|
||||
#define TX_FES_STATUS_END_TX_PWR_UNSHARED_MASK 0xff00000000000000
|
||||
|
||||
#define TX_FES_STATUS_END_RANGING_ACTIVE_USER_MAP_OFFSET 0x0000000000000050
|
||||
#define TX_FES_STATUS_END_RANGING_ACTIVE_USER_MAP_LSB 0
|
||||
#define TX_FES_STATUS_END_RANGING_ACTIVE_USER_MAP_MSB 15
|
||||
#define TX_FES_STATUS_END_RANGING_ACTIVE_USER_MAP_MASK 0x000000000000ffff
|
||||
|
||||
#define TX_FES_STATUS_END_RANGING_SENT_DUMMY_TX_OFFSET 0x0000000000000050
|
||||
#define TX_FES_STATUS_END_RANGING_SENT_DUMMY_TX_LSB 16
|
||||
#define TX_FES_STATUS_END_RANGING_SENT_DUMMY_TX_MSB 16
|
||||
#define TX_FES_STATUS_END_RANGING_SENT_DUMMY_TX_MASK 0x0000000000010000
|
||||
|
||||
#define TX_FES_STATUS_END_RANGING_FTM_FRAME_SENT_OFFSET 0x0000000000000050
|
||||
#define TX_FES_STATUS_END_RANGING_FTM_FRAME_SENT_LSB 17
|
||||
#define TX_FES_STATUS_END_RANGING_FTM_FRAME_SENT_MSB 17
|
||||
#define TX_FES_STATUS_END_RANGING_FTM_FRAME_SENT_MASK 0x0000000000020000
|
||||
|
||||
#define TX_FES_STATUS_END_RESERVED_20A_OFFSET 0x0000000000000050
|
||||
#define TX_FES_STATUS_END_RESERVED_20A_LSB 18
|
||||
#define TX_FES_STATUS_END_RESERVED_20A_MSB 23
|
||||
#define TX_FES_STATUS_END_RESERVED_20A_MASK 0x0000000000fc0000
|
||||
|
||||
#define TX_FES_STATUS_END_CV_CORR_STATUS_OFFSET 0x0000000000000050
|
||||
#define TX_FES_STATUS_END_CV_CORR_STATUS_LSB 24
|
||||
#define TX_FES_STATUS_END_CV_CORR_STATUS_MSB 31
|
||||
#define TX_FES_STATUS_END_CV_CORR_STATUS_MASK 0x00000000ff000000
|
||||
|
||||
#define TX_FES_STATUS_END_CURRENT_TX_DURATION_OFFSET 0x0000000000000050
|
||||
#define TX_FES_STATUS_END_CURRENT_TX_DURATION_LSB 32
|
||||
#define TX_FES_STATUS_END_CURRENT_TX_DURATION_MSB 47
|
||||
#define TX_FES_STATUS_END_CURRENT_TX_DURATION_MASK 0x0000ffff00000000
|
||||
|
||||
#define TX_FES_STATUS_END_RESERVED_21A_OFFSET 0x0000000000000050
|
||||
#define TX_FES_STATUS_END_RESERVED_21A_LSB 48
|
||||
#define TX_FES_STATUS_END_RESERVED_21A_MSB 63
|
||||
#define TX_FES_STATUS_END_RESERVED_21A_MASK 0xffff000000000000
|
||||
|
||||
#endif
|
||||
340
hw/kiwi/v2/tx_fes_status_prot.h
Normal file
340
hw/kiwi/v2/tx_fes_status_prot.h
Normal file
|
|
@ -0,0 +1,340 @@
|
|||
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
#ifndef _TX_FES_STATUS_PROT_H_
|
||||
#define _TX_FES_STATUS_PROT_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#include "phytx_abort_request_info.h"
|
||||
#define NUM_OF_DWORDS_TX_FES_STATUS_PROT 14
|
||||
|
||||
#define NUM_OF_QWORDS_TX_FES_STATUS_PROT 7
|
||||
|
||||
struct tx_fes_status_prot {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t success : 1,
|
||||
phytx_pkt_end_info_valid : 1,
|
||||
phytx_abort_request_info_valid : 1,
|
||||
reserved_0 : 20,
|
||||
pkt_type : 4,
|
||||
dot11ax_su_extended : 1,
|
||||
rate_mcs : 4;
|
||||
uint32_t frame_type : 2,
|
||||
frame_subtype : 4,
|
||||
rx_pwr_mgmt : 1,
|
||||
status : 1,
|
||||
duration_field : 16,
|
||||
reserved_1a : 2,
|
||||
agc_cbw : 3,
|
||||
service_cbw : 3;
|
||||
uint32_t start_of_frame_timestamp_15_0 : 16,
|
||||
start_of_frame_timestamp_31_16 : 16;
|
||||
uint32_t end_of_frame_timestamp_15_0 : 16,
|
||||
end_of_frame_timestamp_31_16 : 16;
|
||||
uint32_t tx_group_delay : 12,
|
||||
timing_status : 2,
|
||||
dpdtrain_done : 1,
|
||||
reserved_4 : 1,
|
||||
transmit_delay : 16;
|
||||
uint32_t tpc_dbg_info_cmn_15_0 : 16,
|
||||
tpc_dbg_info_cmn_31_16 : 16;
|
||||
uint32_t tpc_dbg_info_cmn_47_32 : 16,
|
||||
tpc_dbg_info_chn1_15_0 : 16;
|
||||
uint32_t tpc_dbg_info_chn1_31_16 : 16,
|
||||
tpc_dbg_info_chn1_47_32 : 16;
|
||||
uint32_t tpc_dbg_info_chn1_63_48 : 16,
|
||||
tpc_dbg_info_chn1_79_64 : 16;
|
||||
uint32_t tpc_dbg_info_chn2_15_0 : 16,
|
||||
tpc_dbg_info_chn2_31_16 : 16;
|
||||
uint32_t tpc_dbg_info_chn2_47_32 : 16,
|
||||
tpc_dbg_info_chn2_63_48 : 16;
|
||||
uint32_t tpc_dbg_info_chn2_79_64 : 16;
|
||||
struct phytx_abort_request_info phytx_abort_request_info_details;
|
||||
uint32_t phytx_tx_end_sw_info_15_0 : 16,
|
||||
phytx_tx_end_sw_info_31_16 : 16;
|
||||
uint32_t phytx_tx_end_sw_info_47_32 : 16,
|
||||
phytx_tx_end_sw_info_63_48 : 16;
|
||||
#else
|
||||
uint32_t rate_mcs : 4,
|
||||
dot11ax_su_extended : 1,
|
||||
pkt_type : 4,
|
||||
reserved_0 : 20,
|
||||
phytx_abort_request_info_valid : 1,
|
||||
phytx_pkt_end_info_valid : 1,
|
||||
success : 1;
|
||||
uint32_t service_cbw : 3,
|
||||
agc_cbw : 3,
|
||||
reserved_1a : 2,
|
||||
duration_field : 16,
|
||||
status : 1,
|
||||
rx_pwr_mgmt : 1,
|
||||
frame_subtype : 4,
|
||||
frame_type : 2;
|
||||
uint32_t start_of_frame_timestamp_31_16 : 16,
|
||||
start_of_frame_timestamp_15_0 : 16;
|
||||
uint32_t end_of_frame_timestamp_31_16 : 16,
|
||||
end_of_frame_timestamp_15_0 : 16;
|
||||
uint32_t transmit_delay : 16,
|
||||
reserved_4 : 1,
|
||||
dpdtrain_done : 1,
|
||||
timing_status : 2,
|
||||
tx_group_delay : 12;
|
||||
uint32_t tpc_dbg_info_cmn_31_16 : 16,
|
||||
tpc_dbg_info_cmn_15_0 : 16;
|
||||
uint32_t tpc_dbg_info_chn1_15_0 : 16,
|
||||
tpc_dbg_info_cmn_47_32 : 16;
|
||||
uint32_t tpc_dbg_info_chn1_47_32 : 16,
|
||||
tpc_dbg_info_chn1_31_16 : 16;
|
||||
uint32_t tpc_dbg_info_chn1_79_64 : 16,
|
||||
tpc_dbg_info_chn1_63_48 : 16;
|
||||
uint32_t tpc_dbg_info_chn2_31_16 : 16,
|
||||
tpc_dbg_info_chn2_15_0 : 16;
|
||||
uint32_t tpc_dbg_info_chn2_63_48 : 16,
|
||||
tpc_dbg_info_chn2_47_32 : 16;
|
||||
struct phytx_abort_request_info phytx_abort_request_info_details;
|
||||
uint16_t tpc_dbg_info_chn2_79_64 : 16;
|
||||
uint32_t phytx_tx_end_sw_info_31_16 : 16,
|
||||
phytx_tx_end_sw_info_15_0 : 16;
|
||||
uint32_t phytx_tx_end_sw_info_63_48 : 16,
|
||||
phytx_tx_end_sw_info_47_32 : 16;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define TX_FES_STATUS_PROT_SUCCESS_OFFSET 0x0000000000000000
|
||||
#define TX_FES_STATUS_PROT_SUCCESS_LSB 0
|
||||
#define TX_FES_STATUS_PROT_SUCCESS_MSB 0
|
||||
#define TX_FES_STATUS_PROT_SUCCESS_MASK 0x0000000000000001
|
||||
|
||||
#define TX_FES_STATUS_PROT_PHYTX_PKT_END_INFO_VALID_OFFSET 0x0000000000000000
|
||||
#define TX_FES_STATUS_PROT_PHYTX_PKT_END_INFO_VALID_LSB 1
|
||||
#define TX_FES_STATUS_PROT_PHYTX_PKT_END_INFO_VALID_MSB 1
|
||||
#define TX_FES_STATUS_PROT_PHYTX_PKT_END_INFO_VALID_MASK 0x0000000000000002
|
||||
|
||||
#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_VALID_OFFSET 0x0000000000000000
|
||||
#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_VALID_LSB 2
|
||||
#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_VALID_MSB 2
|
||||
#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_VALID_MASK 0x0000000000000004
|
||||
|
||||
#define TX_FES_STATUS_PROT_RESERVED_0_OFFSET 0x0000000000000000
|
||||
#define TX_FES_STATUS_PROT_RESERVED_0_LSB 3
|
||||
#define TX_FES_STATUS_PROT_RESERVED_0_MSB 22
|
||||
#define TX_FES_STATUS_PROT_RESERVED_0_MASK 0x00000000007ffff8
|
||||
|
||||
#define TX_FES_STATUS_PROT_PKT_TYPE_OFFSET 0x0000000000000000
|
||||
#define TX_FES_STATUS_PROT_PKT_TYPE_LSB 23
|
||||
#define TX_FES_STATUS_PROT_PKT_TYPE_MSB 26
|
||||
#define TX_FES_STATUS_PROT_PKT_TYPE_MASK 0x0000000007800000
|
||||
|
||||
#define TX_FES_STATUS_PROT_DOT11AX_SU_EXTENDED_OFFSET 0x0000000000000000
|
||||
#define TX_FES_STATUS_PROT_DOT11AX_SU_EXTENDED_LSB 27
|
||||
#define TX_FES_STATUS_PROT_DOT11AX_SU_EXTENDED_MSB 27
|
||||
#define TX_FES_STATUS_PROT_DOT11AX_SU_EXTENDED_MASK 0x0000000008000000
|
||||
|
||||
#define TX_FES_STATUS_PROT_RATE_MCS_OFFSET 0x0000000000000000
|
||||
#define TX_FES_STATUS_PROT_RATE_MCS_LSB 28
|
||||
#define TX_FES_STATUS_PROT_RATE_MCS_MSB 31
|
||||
#define TX_FES_STATUS_PROT_RATE_MCS_MASK 0x00000000f0000000
|
||||
|
||||
#define TX_FES_STATUS_PROT_FRAME_TYPE_OFFSET 0x0000000000000000
|
||||
#define TX_FES_STATUS_PROT_FRAME_TYPE_LSB 32
|
||||
#define TX_FES_STATUS_PROT_FRAME_TYPE_MSB 33
|
||||
#define TX_FES_STATUS_PROT_FRAME_TYPE_MASK 0x0000000300000000
|
||||
|
||||
#define TX_FES_STATUS_PROT_FRAME_SUBTYPE_OFFSET 0x0000000000000000
|
||||
#define TX_FES_STATUS_PROT_FRAME_SUBTYPE_LSB 34
|
||||
#define TX_FES_STATUS_PROT_FRAME_SUBTYPE_MSB 37
|
||||
#define TX_FES_STATUS_PROT_FRAME_SUBTYPE_MASK 0x0000003c00000000
|
||||
|
||||
#define TX_FES_STATUS_PROT_RX_PWR_MGMT_OFFSET 0x0000000000000000
|
||||
#define TX_FES_STATUS_PROT_RX_PWR_MGMT_LSB 38
|
||||
#define TX_FES_STATUS_PROT_RX_PWR_MGMT_MSB 38
|
||||
#define TX_FES_STATUS_PROT_RX_PWR_MGMT_MASK 0x0000004000000000
|
||||
|
||||
#define TX_FES_STATUS_PROT_STATUS_OFFSET 0x0000000000000000
|
||||
#define TX_FES_STATUS_PROT_STATUS_LSB 39
|
||||
#define TX_FES_STATUS_PROT_STATUS_MSB 39
|
||||
#define TX_FES_STATUS_PROT_STATUS_MASK 0x0000008000000000
|
||||
|
||||
#define TX_FES_STATUS_PROT_DURATION_FIELD_OFFSET 0x0000000000000000
|
||||
#define TX_FES_STATUS_PROT_DURATION_FIELD_LSB 40
|
||||
#define TX_FES_STATUS_PROT_DURATION_FIELD_MSB 55
|
||||
#define TX_FES_STATUS_PROT_DURATION_FIELD_MASK 0x00ffff0000000000
|
||||
|
||||
#define TX_FES_STATUS_PROT_RESERVED_1A_OFFSET 0x0000000000000000
|
||||
#define TX_FES_STATUS_PROT_RESERVED_1A_LSB 56
|
||||
#define TX_FES_STATUS_PROT_RESERVED_1A_MSB 57
|
||||
#define TX_FES_STATUS_PROT_RESERVED_1A_MASK 0x0300000000000000
|
||||
|
||||
#define TX_FES_STATUS_PROT_AGC_CBW_OFFSET 0x0000000000000000
|
||||
#define TX_FES_STATUS_PROT_AGC_CBW_LSB 58
|
||||
#define TX_FES_STATUS_PROT_AGC_CBW_MSB 60
|
||||
#define TX_FES_STATUS_PROT_AGC_CBW_MASK 0x1c00000000000000
|
||||
|
||||
#define TX_FES_STATUS_PROT_SERVICE_CBW_OFFSET 0x0000000000000000
|
||||
#define TX_FES_STATUS_PROT_SERVICE_CBW_LSB 61
|
||||
#define TX_FES_STATUS_PROT_SERVICE_CBW_MSB 63
|
||||
#define TX_FES_STATUS_PROT_SERVICE_CBW_MASK 0xe000000000000000
|
||||
|
||||
#define TX_FES_STATUS_PROT_START_OF_FRAME_TIMESTAMP_15_0_OFFSET 0x0000000000000008
|
||||
#define TX_FES_STATUS_PROT_START_OF_FRAME_TIMESTAMP_15_0_LSB 0
|
||||
#define TX_FES_STATUS_PROT_START_OF_FRAME_TIMESTAMP_15_0_MSB 15
|
||||
#define TX_FES_STATUS_PROT_START_OF_FRAME_TIMESTAMP_15_0_MASK 0x000000000000ffff
|
||||
|
||||
#define TX_FES_STATUS_PROT_START_OF_FRAME_TIMESTAMP_31_16_OFFSET 0x0000000000000008
|
||||
#define TX_FES_STATUS_PROT_START_OF_FRAME_TIMESTAMP_31_16_LSB 16
|
||||
#define TX_FES_STATUS_PROT_START_OF_FRAME_TIMESTAMP_31_16_MSB 31
|
||||
#define TX_FES_STATUS_PROT_START_OF_FRAME_TIMESTAMP_31_16_MASK 0x00000000ffff0000
|
||||
|
||||
#define TX_FES_STATUS_PROT_END_OF_FRAME_TIMESTAMP_15_0_OFFSET 0x0000000000000008
|
||||
#define TX_FES_STATUS_PROT_END_OF_FRAME_TIMESTAMP_15_0_LSB 32
|
||||
#define TX_FES_STATUS_PROT_END_OF_FRAME_TIMESTAMP_15_0_MSB 47
|
||||
#define TX_FES_STATUS_PROT_END_OF_FRAME_TIMESTAMP_15_0_MASK 0x0000ffff00000000
|
||||
|
||||
#define TX_FES_STATUS_PROT_END_OF_FRAME_TIMESTAMP_31_16_OFFSET 0x0000000000000008
|
||||
#define TX_FES_STATUS_PROT_END_OF_FRAME_TIMESTAMP_31_16_LSB 48
|
||||
#define TX_FES_STATUS_PROT_END_OF_FRAME_TIMESTAMP_31_16_MSB 63
|
||||
#define TX_FES_STATUS_PROT_END_OF_FRAME_TIMESTAMP_31_16_MASK 0xffff000000000000
|
||||
|
||||
#define TX_FES_STATUS_PROT_TX_GROUP_DELAY_OFFSET 0x0000000000000010
|
||||
#define TX_FES_STATUS_PROT_TX_GROUP_DELAY_LSB 0
|
||||
#define TX_FES_STATUS_PROT_TX_GROUP_DELAY_MSB 11
|
||||
#define TX_FES_STATUS_PROT_TX_GROUP_DELAY_MASK 0x0000000000000fff
|
||||
|
||||
#define TX_FES_STATUS_PROT_TIMING_STATUS_OFFSET 0x0000000000000010
|
||||
#define TX_FES_STATUS_PROT_TIMING_STATUS_LSB 12
|
||||
#define TX_FES_STATUS_PROT_TIMING_STATUS_MSB 13
|
||||
#define TX_FES_STATUS_PROT_TIMING_STATUS_MASK 0x0000000000003000
|
||||
|
||||
#define TX_FES_STATUS_PROT_DPDTRAIN_DONE_OFFSET 0x0000000000000010
|
||||
#define TX_FES_STATUS_PROT_DPDTRAIN_DONE_LSB 14
|
||||
#define TX_FES_STATUS_PROT_DPDTRAIN_DONE_MSB 14
|
||||
#define TX_FES_STATUS_PROT_DPDTRAIN_DONE_MASK 0x0000000000004000
|
||||
|
||||
#define TX_FES_STATUS_PROT_RESERVED_4_OFFSET 0x0000000000000010
|
||||
#define TX_FES_STATUS_PROT_RESERVED_4_LSB 15
|
||||
#define TX_FES_STATUS_PROT_RESERVED_4_MSB 15
|
||||
#define TX_FES_STATUS_PROT_RESERVED_4_MASK 0x0000000000008000
|
||||
|
||||
#define TX_FES_STATUS_PROT_TRANSMIT_DELAY_OFFSET 0x0000000000000010
|
||||
#define TX_FES_STATUS_PROT_TRANSMIT_DELAY_LSB 16
|
||||
#define TX_FES_STATUS_PROT_TRANSMIT_DELAY_MSB 31
|
||||
#define TX_FES_STATUS_PROT_TRANSMIT_DELAY_MASK 0x00000000ffff0000
|
||||
|
||||
#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_15_0_OFFSET 0x0000000000000010
|
||||
#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_15_0_LSB 32
|
||||
#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_15_0_MSB 47
|
||||
#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_15_0_MASK 0x0000ffff00000000
|
||||
|
||||
#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_31_16_OFFSET 0x0000000000000010
|
||||
#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_31_16_LSB 48
|
||||
#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_31_16_MSB 63
|
||||
#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_31_16_MASK 0xffff000000000000
|
||||
|
||||
#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_47_32_OFFSET 0x0000000000000018
|
||||
#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_47_32_LSB 0
|
||||
#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_47_32_MSB 15
|
||||
#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CMN_47_32_MASK 0x000000000000ffff
|
||||
|
||||
#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_15_0_OFFSET 0x0000000000000018
|
||||
#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_15_0_LSB 16
|
||||
#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_15_0_MSB 31
|
||||
#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_15_0_MASK 0x00000000ffff0000
|
||||
|
||||
#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_31_16_OFFSET 0x0000000000000018
|
||||
#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_31_16_LSB 32
|
||||
#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_31_16_MSB 47
|
||||
#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_31_16_MASK 0x0000ffff00000000
|
||||
|
||||
#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_47_32_OFFSET 0x0000000000000018
|
||||
#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_47_32_LSB 48
|
||||
#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_47_32_MSB 63
|
||||
#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_47_32_MASK 0xffff000000000000
|
||||
|
||||
#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_63_48_OFFSET 0x0000000000000020
|
||||
#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_63_48_LSB 0
|
||||
#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_63_48_MSB 15
|
||||
#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_63_48_MASK 0x000000000000ffff
|
||||
|
||||
#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_79_64_OFFSET 0x0000000000000020
|
||||
#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_79_64_LSB 16
|
||||
#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_79_64_MSB 31
|
||||
#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN1_79_64_MASK 0x00000000ffff0000
|
||||
|
||||
#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_15_0_OFFSET 0x0000000000000020
|
||||
#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_15_0_LSB 32
|
||||
#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_15_0_MSB 47
|
||||
#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_15_0_MASK 0x0000ffff00000000
|
||||
|
||||
#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_31_16_OFFSET 0x0000000000000020
|
||||
#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_31_16_LSB 48
|
||||
#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_31_16_MSB 63
|
||||
#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_31_16_MASK 0xffff000000000000
|
||||
|
||||
#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_47_32_OFFSET 0x0000000000000028
|
||||
#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_47_32_LSB 0
|
||||
#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_47_32_MSB 15
|
||||
#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_47_32_MASK 0x000000000000ffff
|
||||
|
||||
#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_63_48_OFFSET 0x0000000000000028
|
||||
#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_63_48_LSB 16
|
||||
#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_63_48_MSB 31
|
||||
#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_63_48_MASK 0x00000000ffff0000
|
||||
|
||||
#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_79_64_OFFSET 0x0000000000000028
|
||||
#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_79_64_LSB 32
|
||||
#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_79_64_MSB 47
|
||||
#define TX_FES_STATUS_PROT_TPC_DBG_INFO_CHN2_79_64_MASK 0x0000ffff00000000
|
||||
|
||||
#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_OFFSET 0x0000000000000028
|
||||
#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_LSB 48
|
||||
#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MSB 55
|
||||
#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MASK 0x00ff000000000000
|
||||
|
||||
#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_OFFSET 0x0000000000000028
|
||||
#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_LSB 56
|
||||
#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MSB 61
|
||||
#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MASK 0x3f00000000000000
|
||||
|
||||
#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000028
|
||||
#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_LSB 62
|
||||
#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MSB 63
|
||||
#define TX_FES_STATUS_PROT_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MASK 0xc000000000000000
|
||||
|
||||
#define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_15_0_OFFSET 0x0000000000000030
|
||||
#define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_15_0_LSB 0
|
||||
#define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_15_0_MSB 15
|
||||
#define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_15_0_MASK 0x000000000000ffff
|
||||
|
||||
#define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_31_16_OFFSET 0x0000000000000030
|
||||
#define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_31_16_LSB 16
|
||||
#define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_31_16_MSB 31
|
||||
#define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_31_16_MASK 0x00000000ffff0000
|
||||
|
||||
#define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_47_32_OFFSET 0x0000000000000030
|
||||
#define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_47_32_LSB 32
|
||||
#define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_47_32_MSB 47
|
||||
#define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_47_32_MASK 0x0000ffff00000000
|
||||
|
||||
#define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_63_48_OFFSET 0x0000000000000030
|
||||
#define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_63_48_LSB 48
|
||||
#define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_63_48_MSB 63
|
||||
#define TX_FES_STATUS_PROT_PHYTX_TX_END_SW_INFO_63_48_MASK 0xffff000000000000
|
||||
|
||||
#endif
|
||||
133
hw/kiwi/v2/tx_fes_status_start.h
Normal file
133
hw/kiwi/v2/tx_fes_status_start.h
Normal file
|
|
@ -0,0 +1,133 @@
|
|||
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
#ifndef _TX_FES_STATUS_START_H_
|
||||
#define _TX_FES_STATUS_START_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#define NUM_OF_DWORDS_TX_FES_STATUS_START 4
|
||||
|
||||
#define NUM_OF_QWORDS_TX_FES_STATUS_START 2
|
||||
|
||||
struct tx_fes_status_start {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t schedule_id : 32;
|
||||
uint32_t reserved_1a : 8,
|
||||
transmit_start_reason : 3,
|
||||
disabled_user_bitmap_36_32 : 5,
|
||||
schedule_cmd_ring_id : 5,
|
||||
fes_control_mode : 2,
|
||||
schedule_try : 4,
|
||||
medium_prot_type : 3,
|
||||
reserved_1b : 2;
|
||||
uint32_t optimal_bw_try_count : 4,
|
||||
number_of_users : 7,
|
||||
coex_nack_count : 5,
|
||||
cca_ed0 : 16;
|
||||
uint32_t disabled_user_bitmap_31_0 : 32;
|
||||
#else
|
||||
uint32_t schedule_id : 32;
|
||||
uint32_t reserved_1b : 2,
|
||||
medium_prot_type : 3,
|
||||
schedule_try : 4,
|
||||
fes_control_mode : 2,
|
||||
schedule_cmd_ring_id : 5,
|
||||
disabled_user_bitmap_36_32 : 5,
|
||||
transmit_start_reason : 3,
|
||||
reserved_1a : 8;
|
||||
uint32_t cca_ed0 : 16,
|
||||
coex_nack_count : 5,
|
||||
number_of_users : 7,
|
||||
optimal_bw_try_count : 4;
|
||||
uint32_t disabled_user_bitmap_31_0 : 32;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define TX_FES_STATUS_START_SCHEDULE_ID_OFFSET 0x0000000000000000
|
||||
#define TX_FES_STATUS_START_SCHEDULE_ID_LSB 0
|
||||
#define TX_FES_STATUS_START_SCHEDULE_ID_MSB 31
|
||||
#define TX_FES_STATUS_START_SCHEDULE_ID_MASK 0x00000000ffffffff
|
||||
|
||||
#define TX_FES_STATUS_START_RESERVED_1A_OFFSET 0x0000000000000000
|
||||
#define TX_FES_STATUS_START_RESERVED_1A_LSB 32
|
||||
#define TX_FES_STATUS_START_RESERVED_1A_MSB 39
|
||||
#define TX_FES_STATUS_START_RESERVED_1A_MASK 0x000000ff00000000
|
||||
|
||||
#define TX_FES_STATUS_START_TRANSMIT_START_REASON_OFFSET 0x0000000000000000
|
||||
#define TX_FES_STATUS_START_TRANSMIT_START_REASON_LSB 40
|
||||
#define TX_FES_STATUS_START_TRANSMIT_START_REASON_MSB 42
|
||||
#define TX_FES_STATUS_START_TRANSMIT_START_REASON_MASK 0x0000070000000000
|
||||
|
||||
#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_36_32_OFFSET 0x0000000000000000
|
||||
#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_36_32_LSB 43
|
||||
#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_36_32_MSB 47
|
||||
#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_36_32_MASK 0x0000f80000000000
|
||||
|
||||
#define TX_FES_STATUS_START_SCHEDULE_CMD_RING_ID_OFFSET 0x0000000000000000
|
||||
#define TX_FES_STATUS_START_SCHEDULE_CMD_RING_ID_LSB 48
|
||||
#define TX_FES_STATUS_START_SCHEDULE_CMD_RING_ID_MSB 52
|
||||
#define TX_FES_STATUS_START_SCHEDULE_CMD_RING_ID_MASK 0x001f000000000000
|
||||
|
||||
#define TX_FES_STATUS_START_FES_CONTROL_MODE_OFFSET 0x0000000000000000
|
||||
#define TX_FES_STATUS_START_FES_CONTROL_MODE_LSB 53
|
||||
#define TX_FES_STATUS_START_FES_CONTROL_MODE_MSB 54
|
||||
#define TX_FES_STATUS_START_FES_CONTROL_MODE_MASK 0x0060000000000000
|
||||
|
||||
#define TX_FES_STATUS_START_SCHEDULE_TRY_OFFSET 0x0000000000000000
|
||||
#define TX_FES_STATUS_START_SCHEDULE_TRY_LSB 55
|
||||
#define TX_FES_STATUS_START_SCHEDULE_TRY_MSB 58
|
||||
#define TX_FES_STATUS_START_SCHEDULE_TRY_MASK 0x0780000000000000
|
||||
|
||||
#define TX_FES_STATUS_START_MEDIUM_PROT_TYPE_OFFSET 0x0000000000000000
|
||||
#define TX_FES_STATUS_START_MEDIUM_PROT_TYPE_LSB 59
|
||||
#define TX_FES_STATUS_START_MEDIUM_PROT_TYPE_MSB 61
|
||||
#define TX_FES_STATUS_START_MEDIUM_PROT_TYPE_MASK 0x3800000000000000
|
||||
|
||||
#define TX_FES_STATUS_START_RESERVED_1B_OFFSET 0x0000000000000000
|
||||
#define TX_FES_STATUS_START_RESERVED_1B_LSB 62
|
||||
#define TX_FES_STATUS_START_RESERVED_1B_MSB 63
|
||||
#define TX_FES_STATUS_START_RESERVED_1B_MASK 0xc000000000000000
|
||||
|
||||
#define TX_FES_STATUS_START_OPTIMAL_BW_TRY_COUNT_OFFSET 0x0000000000000008
|
||||
#define TX_FES_STATUS_START_OPTIMAL_BW_TRY_COUNT_LSB 0
|
||||
#define TX_FES_STATUS_START_OPTIMAL_BW_TRY_COUNT_MSB 3
|
||||
#define TX_FES_STATUS_START_OPTIMAL_BW_TRY_COUNT_MASK 0x000000000000000f
|
||||
|
||||
#define TX_FES_STATUS_START_NUMBER_OF_USERS_OFFSET 0x0000000000000008
|
||||
#define TX_FES_STATUS_START_NUMBER_OF_USERS_LSB 4
|
||||
#define TX_FES_STATUS_START_NUMBER_OF_USERS_MSB 10
|
||||
#define TX_FES_STATUS_START_NUMBER_OF_USERS_MASK 0x00000000000007f0
|
||||
|
||||
#define TX_FES_STATUS_START_COEX_NACK_COUNT_OFFSET 0x0000000000000008
|
||||
#define TX_FES_STATUS_START_COEX_NACK_COUNT_LSB 11
|
||||
#define TX_FES_STATUS_START_COEX_NACK_COUNT_MSB 15
|
||||
#define TX_FES_STATUS_START_COEX_NACK_COUNT_MASK 0x000000000000f800
|
||||
|
||||
#define TX_FES_STATUS_START_CCA_ED0_OFFSET 0x0000000000000008
|
||||
#define TX_FES_STATUS_START_CCA_ED0_LSB 16
|
||||
#define TX_FES_STATUS_START_CCA_ED0_MSB 31
|
||||
#define TX_FES_STATUS_START_CCA_ED0_MASK 0x00000000ffff0000
|
||||
|
||||
#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_31_0_OFFSET 0x0000000000000008
|
||||
#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_31_0_LSB 32
|
||||
#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_31_0_MSB 63
|
||||
#define TX_FES_STATUS_START_DISABLED_USER_BITMAP_31_0_MASK 0xffffffff00000000
|
||||
|
||||
#endif
|
||||
175
hw/kiwi/v2/tx_fes_status_start_ppdu.h
Normal file
175
hw/kiwi/v2/tx_fes_status_start_ppdu.h
Normal file
|
|
@ -0,0 +1,175 @@
|
|||
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
#ifndef _TX_FES_STATUS_START_PPDU_H_
|
||||
#define _TX_FES_STATUS_START_PPDU_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#define NUM_OF_DWORDS_TX_FES_STATUS_START_PPDU 4
|
||||
|
||||
#define NUM_OF_QWORDS_TX_FES_STATUS_START_PPDU 2
|
||||
|
||||
struct tx_fes_status_start_ppdu {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t ppdu_timestamp_lower_32 : 32;
|
||||
uint32_t ppdu_timestamp_upper_32 : 32;
|
||||
uint32_t subband_mask : 16,
|
||||
ndp_frame : 2,
|
||||
reserved_2b : 2,
|
||||
coex_based_tx_bw : 3,
|
||||
coex_based_ant_mask : 8,
|
||||
reserved_2c : 1;
|
||||
uint32_t coex_based_tx_pwr_shared_ant : 8,
|
||||
coex_based_tx_pwr_ant : 8,
|
||||
concurrent_bt_tx : 1,
|
||||
concurrent_wlan_tx : 1,
|
||||
concurrent_wan_tx : 1,
|
||||
concurrent_wan_rx : 1,
|
||||
coex_pwr_reduction_bt : 1,
|
||||
coex_pwr_reduction_wlan : 1,
|
||||
coex_pwr_reduction_wan : 1,
|
||||
coex_result_alt_based : 1,
|
||||
request_packet_bw : 3,
|
||||
response_type : 5;
|
||||
#else
|
||||
uint32_t ppdu_timestamp_lower_32 : 32;
|
||||
uint32_t ppdu_timestamp_upper_32 : 32;
|
||||
uint32_t reserved_2c : 1,
|
||||
coex_based_ant_mask : 8,
|
||||
coex_based_tx_bw : 3,
|
||||
reserved_2b : 2,
|
||||
ndp_frame : 2,
|
||||
subband_mask : 16;
|
||||
uint32_t response_type : 5,
|
||||
request_packet_bw : 3,
|
||||
coex_result_alt_based : 1,
|
||||
coex_pwr_reduction_wan : 1,
|
||||
coex_pwr_reduction_wlan : 1,
|
||||
coex_pwr_reduction_bt : 1,
|
||||
concurrent_wan_rx : 1,
|
||||
concurrent_wan_tx : 1,
|
||||
concurrent_wlan_tx : 1,
|
||||
concurrent_bt_tx : 1,
|
||||
coex_based_tx_pwr_ant : 8,
|
||||
coex_based_tx_pwr_shared_ant : 8;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_LOWER_32_OFFSET 0x0000000000000000
|
||||
#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_LOWER_32_LSB 0
|
||||
#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_LOWER_32_MSB 31
|
||||
#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_LOWER_32_MASK 0x00000000ffffffff
|
||||
|
||||
#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_UPPER_32_OFFSET 0x0000000000000000
|
||||
#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_UPPER_32_LSB 32
|
||||
#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_UPPER_32_MSB 63
|
||||
#define TX_FES_STATUS_START_PPDU_PPDU_TIMESTAMP_UPPER_32_MASK 0xffffffff00000000
|
||||
|
||||
#define TX_FES_STATUS_START_PPDU_SUBBAND_MASK_OFFSET 0x0000000000000008
|
||||
#define TX_FES_STATUS_START_PPDU_SUBBAND_MASK_LSB 0
|
||||
#define TX_FES_STATUS_START_PPDU_SUBBAND_MASK_MSB 15
|
||||
#define TX_FES_STATUS_START_PPDU_SUBBAND_MASK_MASK 0x000000000000ffff
|
||||
|
||||
#define TX_FES_STATUS_START_PPDU_NDP_FRAME_OFFSET 0x0000000000000008
|
||||
#define TX_FES_STATUS_START_PPDU_NDP_FRAME_LSB 16
|
||||
#define TX_FES_STATUS_START_PPDU_NDP_FRAME_MSB 17
|
||||
#define TX_FES_STATUS_START_PPDU_NDP_FRAME_MASK 0x0000000000030000
|
||||
|
||||
#define TX_FES_STATUS_START_PPDU_RESERVED_2B_OFFSET 0x0000000000000008
|
||||
#define TX_FES_STATUS_START_PPDU_RESERVED_2B_LSB 18
|
||||
#define TX_FES_STATUS_START_PPDU_RESERVED_2B_MSB 19
|
||||
#define TX_FES_STATUS_START_PPDU_RESERVED_2B_MASK 0x00000000000c0000
|
||||
|
||||
#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_BW_OFFSET 0x0000000000000008
|
||||
#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_BW_LSB 20
|
||||
#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_BW_MSB 22
|
||||
#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_BW_MASK 0x0000000000700000
|
||||
|
||||
#define TX_FES_STATUS_START_PPDU_COEX_BASED_ANT_MASK_OFFSET 0x0000000000000008
|
||||
#define TX_FES_STATUS_START_PPDU_COEX_BASED_ANT_MASK_LSB 23
|
||||
#define TX_FES_STATUS_START_PPDU_COEX_BASED_ANT_MASK_MSB 30
|
||||
#define TX_FES_STATUS_START_PPDU_COEX_BASED_ANT_MASK_MASK 0x000000007f800000
|
||||
|
||||
#define TX_FES_STATUS_START_PPDU_RESERVED_2C_OFFSET 0x0000000000000008
|
||||
#define TX_FES_STATUS_START_PPDU_RESERVED_2C_LSB 31
|
||||
#define TX_FES_STATUS_START_PPDU_RESERVED_2C_MSB 31
|
||||
#define TX_FES_STATUS_START_PPDU_RESERVED_2C_MASK 0x0000000080000000
|
||||
|
||||
#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_SHARED_ANT_OFFSET 0x0000000000000008
|
||||
#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_SHARED_ANT_LSB 32
|
||||
#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_SHARED_ANT_MSB 39
|
||||
#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_SHARED_ANT_MASK 0x000000ff00000000
|
||||
|
||||
#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_ANT_OFFSET 0x0000000000000008
|
||||
#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_ANT_LSB 40
|
||||
#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_ANT_MSB 47
|
||||
#define TX_FES_STATUS_START_PPDU_COEX_BASED_TX_PWR_ANT_MASK 0x0000ff0000000000
|
||||
|
||||
#define TX_FES_STATUS_START_PPDU_CONCURRENT_BT_TX_OFFSET 0x0000000000000008
|
||||
#define TX_FES_STATUS_START_PPDU_CONCURRENT_BT_TX_LSB 48
|
||||
#define TX_FES_STATUS_START_PPDU_CONCURRENT_BT_TX_MSB 48
|
||||
#define TX_FES_STATUS_START_PPDU_CONCURRENT_BT_TX_MASK 0x0001000000000000
|
||||
|
||||
#define TX_FES_STATUS_START_PPDU_CONCURRENT_WLAN_TX_OFFSET 0x0000000000000008
|
||||
#define TX_FES_STATUS_START_PPDU_CONCURRENT_WLAN_TX_LSB 49
|
||||
#define TX_FES_STATUS_START_PPDU_CONCURRENT_WLAN_TX_MSB 49
|
||||
#define TX_FES_STATUS_START_PPDU_CONCURRENT_WLAN_TX_MASK 0x0002000000000000
|
||||
|
||||
#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_TX_OFFSET 0x0000000000000008
|
||||
#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_TX_LSB 50
|
||||
#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_TX_MSB 50
|
||||
#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_TX_MASK 0x0004000000000000
|
||||
|
||||
#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_RX_OFFSET 0x0000000000000008
|
||||
#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_RX_LSB 51
|
||||
#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_RX_MSB 51
|
||||
#define TX_FES_STATUS_START_PPDU_CONCURRENT_WAN_RX_MASK 0x0008000000000000
|
||||
|
||||
#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_BT_OFFSET 0x0000000000000008
|
||||
#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_BT_LSB 52
|
||||
#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_BT_MSB 52
|
||||
#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_BT_MASK 0x0010000000000000
|
||||
|
||||
#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WLAN_OFFSET 0x0000000000000008
|
||||
#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WLAN_LSB 53
|
||||
#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WLAN_MSB 53
|
||||
#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WLAN_MASK 0x0020000000000000
|
||||
|
||||
#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WAN_OFFSET 0x0000000000000008
|
||||
#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WAN_LSB 54
|
||||
#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WAN_MSB 54
|
||||
#define TX_FES_STATUS_START_PPDU_COEX_PWR_REDUCTION_WAN_MASK 0x0040000000000000
|
||||
|
||||
#define TX_FES_STATUS_START_PPDU_COEX_RESULT_ALT_BASED_OFFSET 0x0000000000000008
|
||||
#define TX_FES_STATUS_START_PPDU_COEX_RESULT_ALT_BASED_LSB 55
|
||||
#define TX_FES_STATUS_START_PPDU_COEX_RESULT_ALT_BASED_MSB 55
|
||||
#define TX_FES_STATUS_START_PPDU_COEX_RESULT_ALT_BASED_MASK 0x0080000000000000
|
||||
|
||||
#define TX_FES_STATUS_START_PPDU_REQUEST_PACKET_BW_OFFSET 0x0000000000000008
|
||||
#define TX_FES_STATUS_START_PPDU_REQUEST_PACKET_BW_LSB 56
|
||||
#define TX_FES_STATUS_START_PPDU_REQUEST_PACKET_BW_MSB 58
|
||||
#define TX_FES_STATUS_START_PPDU_REQUEST_PACKET_BW_MASK 0x0700000000000000
|
||||
|
||||
#define TX_FES_STATUS_START_PPDU_RESPONSE_TYPE_OFFSET 0x0000000000000008
|
||||
#define TX_FES_STATUS_START_PPDU_RESPONSE_TYPE_LSB 59
|
||||
#define TX_FES_STATUS_START_PPDU_RESPONSE_TYPE_MSB 63
|
||||
#define TX_FES_STATUS_START_PPDU_RESPONSE_TYPE_MASK 0xf800000000000000
|
||||
|
||||
#endif
|
||||
168
hw/kiwi/v2/tx_fes_status_start_prot.h
Normal file
168
hw/kiwi/v2/tx_fes_status_start_prot.h
Normal file
|
|
@ -0,0 +1,168 @@
|
|||
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
#ifndef _TX_FES_STATUS_START_PROT_H_
|
||||
#define _TX_FES_STATUS_START_PROT_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#define NUM_OF_DWORDS_TX_FES_STATUS_START_PROT 4
|
||||
|
||||
#define NUM_OF_QWORDS_TX_FES_STATUS_START_PROT 2
|
||||
|
||||
struct tx_fes_status_start_prot {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t prot_timestamp_lower_32 : 32;
|
||||
uint32_t prot_timestamp_upper_32 : 32;
|
||||
uint32_t subband_mask : 16,
|
||||
reserved_2b : 4,
|
||||
prot_coex_based_tx_bw : 3,
|
||||
prot_coex_based_ant_mask : 8,
|
||||
prot_coex_result_alt_based : 1;
|
||||
uint32_t prot_coex_tx_pwr_shared_ant : 8,
|
||||
prot_coex_tx_pwr_ant : 8,
|
||||
prot_concurrent_bt_tx : 1,
|
||||
prot_concurrent_wlan_tx : 1,
|
||||
prot_concurrent_wan_tx : 1,
|
||||
prot_concurrent_wan_rx : 1,
|
||||
prot_coex_pwr_reduction_bt : 1,
|
||||
prot_coex_pwr_reduction_wlan : 1,
|
||||
prot_coex_pwr_reduction_wan : 1,
|
||||
prot_request_packet_bw : 3,
|
||||
response_type : 5,
|
||||
reserved_3a : 1;
|
||||
#else
|
||||
uint32_t prot_timestamp_lower_32 : 32;
|
||||
uint32_t prot_timestamp_upper_32 : 32;
|
||||
uint32_t prot_coex_result_alt_based : 1,
|
||||
prot_coex_based_ant_mask : 8,
|
||||
prot_coex_based_tx_bw : 3,
|
||||
reserved_2b : 4,
|
||||
subband_mask : 16;
|
||||
uint32_t reserved_3a : 1,
|
||||
response_type : 5,
|
||||
prot_request_packet_bw : 3,
|
||||
prot_coex_pwr_reduction_wan : 1,
|
||||
prot_coex_pwr_reduction_wlan : 1,
|
||||
prot_coex_pwr_reduction_bt : 1,
|
||||
prot_concurrent_wan_rx : 1,
|
||||
prot_concurrent_wan_tx : 1,
|
||||
prot_concurrent_wlan_tx : 1,
|
||||
prot_concurrent_bt_tx : 1,
|
||||
prot_coex_tx_pwr_ant : 8,
|
||||
prot_coex_tx_pwr_shared_ant : 8;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_LOWER_32_OFFSET 0x0000000000000000
|
||||
#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_LOWER_32_LSB 0
|
||||
#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_LOWER_32_MSB 31
|
||||
#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_LOWER_32_MASK 0x00000000ffffffff
|
||||
|
||||
#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_UPPER_32_OFFSET 0x0000000000000000
|
||||
#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_UPPER_32_LSB 32
|
||||
#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_UPPER_32_MSB 63
|
||||
#define TX_FES_STATUS_START_PROT_PROT_TIMESTAMP_UPPER_32_MASK 0xffffffff00000000
|
||||
|
||||
#define TX_FES_STATUS_START_PROT_SUBBAND_MASK_OFFSET 0x0000000000000008
|
||||
#define TX_FES_STATUS_START_PROT_SUBBAND_MASK_LSB 0
|
||||
#define TX_FES_STATUS_START_PROT_SUBBAND_MASK_MSB 15
|
||||
#define TX_FES_STATUS_START_PROT_SUBBAND_MASK_MASK 0x000000000000ffff
|
||||
|
||||
#define TX_FES_STATUS_START_PROT_RESERVED_2B_OFFSET 0x0000000000000008
|
||||
#define TX_FES_STATUS_START_PROT_RESERVED_2B_LSB 16
|
||||
#define TX_FES_STATUS_START_PROT_RESERVED_2B_MSB 19
|
||||
#define TX_FES_STATUS_START_PROT_RESERVED_2B_MASK 0x00000000000f0000
|
||||
|
||||
#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_TX_BW_OFFSET 0x0000000000000008
|
||||
#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_TX_BW_LSB 20
|
||||
#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_TX_BW_MSB 22
|
||||
#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_TX_BW_MASK 0x0000000000700000
|
||||
|
||||
#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_ANT_MASK_OFFSET 0x0000000000000008
|
||||
#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_ANT_MASK_LSB 23
|
||||
#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_ANT_MASK_MSB 30
|
||||
#define TX_FES_STATUS_START_PROT_PROT_COEX_BASED_ANT_MASK_MASK 0x000000007f800000
|
||||
|
||||
#define TX_FES_STATUS_START_PROT_PROT_COEX_RESULT_ALT_BASED_OFFSET 0x0000000000000008
|
||||
#define TX_FES_STATUS_START_PROT_PROT_COEX_RESULT_ALT_BASED_LSB 31
|
||||
#define TX_FES_STATUS_START_PROT_PROT_COEX_RESULT_ALT_BASED_MSB 31
|
||||
#define TX_FES_STATUS_START_PROT_PROT_COEX_RESULT_ALT_BASED_MASK 0x0000000080000000
|
||||
|
||||
#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_SHARED_ANT_OFFSET 0x0000000000000008
|
||||
#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_SHARED_ANT_LSB 32
|
||||
#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_SHARED_ANT_MSB 39
|
||||
#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_SHARED_ANT_MASK 0x000000ff00000000
|
||||
|
||||
#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_ANT_OFFSET 0x0000000000000008
|
||||
#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_ANT_LSB 40
|
||||
#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_ANT_MSB 47
|
||||
#define TX_FES_STATUS_START_PROT_PROT_COEX_TX_PWR_ANT_MASK 0x0000ff0000000000
|
||||
|
||||
#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_BT_TX_OFFSET 0x0000000000000008
|
||||
#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_BT_TX_LSB 48
|
||||
#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_BT_TX_MSB 48
|
||||
#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_BT_TX_MASK 0x0001000000000000
|
||||
|
||||
#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WLAN_TX_OFFSET 0x0000000000000008
|
||||
#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WLAN_TX_LSB 49
|
||||
#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WLAN_TX_MSB 49
|
||||
#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WLAN_TX_MASK 0x0002000000000000
|
||||
|
||||
#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_TX_OFFSET 0x0000000000000008
|
||||
#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_TX_LSB 50
|
||||
#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_TX_MSB 50
|
||||
#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_TX_MASK 0x0004000000000000
|
||||
|
||||
#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_RX_OFFSET 0x0000000000000008
|
||||
#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_RX_LSB 51
|
||||
#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_RX_MSB 51
|
||||
#define TX_FES_STATUS_START_PROT_PROT_CONCURRENT_WAN_RX_MASK 0x0008000000000000
|
||||
|
||||
#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_BT_OFFSET 0x0000000000000008
|
||||
#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_BT_LSB 52
|
||||
#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_BT_MSB 52
|
||||
#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_BT_MASK 0x0010000000000000
|
||||
|
||||
#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WLAN_OFFSET 0x0000000000000008
|
||||
#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WLAN_LSB 53
|
||||
#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WLAN_MSB 53
|
||||
#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WLAN_MASK 0x0020000000000000
|
||||
|
||||
#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WAN_OFFSET 0x0000000000000008
|
||||
#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WAN_LSB 54
|
||||
#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WAN_MSB 54
|
||||
#define TX_FES_STATUS_START_PROT_PROT_COEX_PWR_REDUCTION_WAN_MASK 0x0040000000000000
|
||||
|
||||
#define TX_FES_STATUS_START_PROT_PROT_REQUEST_PACKET_BW_OFFSET 0x0000000000000008
|
||||
#define TX_FES_STATUS_START_PROT_PROT_REQUEST_PACKET_BW_LSB 55
|
||||
#define TX_FES_STATUS_START_PROT_PROT_REQUEST_PACKET_BW_MSB 57
|
||||
#define TX_FES_STATUS_START_PROT_PROT_REQUEST_PACKET_BW_MASK 0x0380000000000000
|
||||
|
||||
#define TX_FES_STATUS_START_PROT_RESPONSE_TYPE_OFFSET 0x0000000000000008
|
||||
#define TX_FES_STATUS_START_PROT_RESPONSE_TYPE_LSB 58
|
||||
#define TX_FES_STATUS_START_PROT_RESPONSE_TYPE_MSB 62
|
||||
#define TX_FES_STATUS_START_PROT_RESPONSE_TYPE_MASK 0x7c00000000000000
|
||||
|
||||
#define TX_FES_STATUS_START_PROT_RESERVED_3A_OFFSET 0x0000000000000008
|
||||
#define TX_FES_STATUS_START_PROT_RESERVED_3A_LSB 63
|
||||
#define TX_FES_STATUS_START_PROT_RESERVED_3A_MSB 63
|
||||
#define TX_FES_STATUS_START_PROT_RESERVED_3A_MASK 0x8000000000000000
|
||||
|
||||
#endif
|
||||
210
hw/kiwi/v2/tx_fes_status_user_ppdu.h
Normal file
210
hw/kiwi/v2/tx_fes_status_user_ppdu.h
Normal file
|
|
@ -0,0 +1,210 @@
|
|||
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
#ifndef _TX_FES_STATUS_USER_PPDU_H_
|
||||
#define _TX_FES_STATUS_USER_PPDU_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#define NUM_OF_DWORDS_TX_FES_STATUS_USER_PPDU 6
|
||||
|
||||
#define NUM_OF_QWORDS_TX_FES_STATUS_USER_PPDU 3
|
||||
|
||||
struct tx_fes_status_user_ppdu {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t underflow_mpdu_count : 9,
|
||||
data_underflow_warning : 2,
|
||||
bw_drop_underflow_warning : 1,
|
||||
qc_eosp_setting : 1,
|
||||
fc_more_data_setting : 1,
|
||||
fc_pwr_mgt_setting : 1,
|
||||
mpdu_tx_count : 9,
|
||||
user_blocked : 1,
|
||||
pre_trig_response_delim_count : 7;
|
||||
uint32_t underflow_byte_count : 16,
|
||||
coex_abort_mpdu_count_valid : 1,
|
||||
coex_abort_mpdu_count : 9,
|
||||
transmitted_tid : 4,
|
||||
txdma_dropped_mpdu_warning : 1,
|
||||
reserved_1 : 1;
|
||||
uint32_t duration : 16,
|
||||
num_eof_delim_added : 16;
|
||||
uint32_t psdu_octet : 24,
|
||||
qos_buf_state : 8;
|
||||
uint32_t num_null_delim_added : 22,
|
||||
reserved_4a : 2,
|
||||
cv_corr_user_valid_in_phy : 1,
|
||||
nss : 3,
|
||||
mcs : 4;
|
||||
uint32_t ht_control : 32;
|
||||
#else
|
||||
uint32_t pre_trig_response_delim_count : 7,
|
||||
user_blocked : 1,
|
||||
mpdu_tx_count : 9,
|
||||
fc_pwr_mgt_setting : 1,
|
||||
fc_more_data_setting : 1,
|
||||
qc_eosp_setting : 1,
|
||||
bw_drop_underflow_warning : 1,
|
||||
data_underflow_warning : 2,
|
||||
underflow_mpdu_count : 9;
|
||||
uint32_t reserved_1 : 1,
|
||||
txdma_dropped_mpdu_warning : 1,
|
||||
transmitted_tid : 4,
|
||||
coex_abort_mpdu_count : 9,
|
||||
coex_abort_mpdu_count_valid : 1,
|
||||
underflow_byte_count : 16;
|
||||
uint32_t num_eof_delim_added : 16,
|
||||
duration : 16;
|
||||
uint32_t qos_buf_state : 8,
|
||||
psdu_octet : 24;
|
||||
uint32_t mcs : 4,
|
||||
nss : 3,
|
||||
cv_corr_user_valid_in_phy : 1,
|
||||
reserved_4a : 2,
|
||||
num_null_delim_added : 22;
|
||||
uint32_t ht_control : 32;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_MPDU_COUNT_OFFSET 0x0000000000000000
|
||||
#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_MPDU_COUNT_LSB 0
|
||||
#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_MPDU_COUNT_MSB 8
|
||||
#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_MPDU_COUNT_MASK 0x00000000000001ff
|
||||
|
||||
#define TX_FES_STATUS_USER_PPDU_DATA_UNDERFLOW_WARNING_OFFSET 0x0000000000000000
|
||||
#define TX_FES_STATUS_USER_PPDU_DATA_UNDERFLOW_WARNING_LSB 9
|
||||
#define TX_FES_STATUS_USER_PPDU_DATA_UNDERFLOW_WARNING_MSB 10
|
||||
#define TX_FES_STATUS_USER_PPDU_DATA_UNDERFLOW_WARNING_MASK 0x0000000000000600
|
||||
|
||||
#define TX_FES_STATUS_USER_PPDU_BW_DROP_UNDERFLOW_WARNING_OFFSET 0x0000000000000000
|
||||
#define TX_FES_STATUS_USER_PPDU_BW_DROP_UNDERFLOW_WARNING_LSB 11
|
||||
#define TX_FES_STATUS_USER_PPDU_BW_DROP_UNDERFLOW_WARNING_MSB 11
|
||||
#define TX_FES_STATUS_USER_PPDU_BW_DROP_UNDERFLOW_WARNING_MASK 0x0000000000000800
|
||||
|
||||
#define TX_FES_STATUS_USER_PPDU_QC_EOSP_SETTING_OFFSET 0x0000000000000000
|
||||
#define TX_FES_STATUS_USER_PPDU_QC_EOSP_SETTING_LSB 12
|
||||
#define TX_FES_STATUS_USER_PPDU_QC_EOSP_SETTING_MSB 12
|
||||
#define TX_FES_STATUS_USER_PPDU_QC_EOSP_SETTING_MASK 0x0000000000001000
|
||||
|
||||
#define TX_FES_STATUS_USER_PPDU_FC_MORE_DATA_SETTING_OFFSET 0x0000000000000000
|
||||
#define TX_FES_STATUS_USER_PPDU_FC_MORE_DATA_SETTING_LSB 13
|
||||
#define TX_FES_STATUS_USER_PPDU_FC_MORE_DATA_SETTING_MSB 13
|
||||
#define TX_FES_STATUS_USER_PPDU_FC_MORE_DATA_SETTING_MASK 0x0000000000002000
|
||||
|
||||
#define TX_FES_STATUS_USER_PPDU_FC_PWR_MGT_SETTING_OFFSET 0x0000000000000000
|
||||
#define TX_FES_STATUS_USER_PPDU_FC_PWR_MGT_SETTING_LSB 14
|
||||
#define TX_FES_STATUS_USER_PPDU_FC_PWR_MGT_SETTING_MSB 14
|
||||
#define TX_FES_STATUS_USER_PPDU_FC_PWR_MGT_SETTING_MASK 0x0000000000004000
|
||||
|
||||
#define TX_FES_STATUS_USER_PPDU_MPDU_TX_COUNT_OFFSET 0x0000000000000000
|
||||
#define TX_FES_STATUS_USER_PPDU_MPDU_TX_COUNT_LSB 15
|
||||
#define TX_FES_STATUS_USER_PPDU_MPDU_TX_COUNT_MSB 23
|
||||
#define TX_FES_STATUS_USER_PPDU_MPDU_TX_COUNT_MASK 0x0000000000ff8000
|
||||
|
||||
#define TX_FES_STATUS_USER_PPDU_USER_BLOCKED_OFFSET 0x0000000000000000
|
||||
#define TX_FES_STATUS_USER_PPDU_USER_BLOCKED_LSB 24
|
||||
#define TX_FES_STATUS_USER_PPDU_USER_BLOCKED_MSB 24
|
||||
#define TX_FES_STATUS_USER_PPDU_USER_BLOCKED_MASK 0x0000000001000000
|
||||
|
||||
#define TX_FES_STATUS_USER_PPDU_PRE_TRIG_RESPONSE_DELIM_COUNT_OFFSET 0x0000000000000000
|
||||
#define TX_FES_STATUS_USER_PPDU_PRE_TRIG_RESPONSE_DELIM_COUNT_LSB 25
|
||||
#define TX_FES_STATUS_USER_PPDU_PRE_TRIG_RESPONSE_DELIM_COUNT_MSB 31
|
||||
#define TX_FES_STATUS_USER_PPDU_PRE_TRIG_RESPONSE_DELIM_COUNT_MASK 0x00000000fe000000
|
||||
|
||||
#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_BYTE_COUNT_OFFSET 0x0000000000000000
|
||||
#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_BYTE_COUNT_LSB 32
|
||||
#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_BYTE_COUNT_MSB 47
|
||||
#define TX_FES_STATUS_USER_PPDU_UNDERFLOW_BYTE_COUNT_MASK 0x0000ffff00000000
|
||||
|
||||
#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_VALID_OFFSET 0x0000000000000000
|
||||
#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_VALID_LSB 48
|
||||
#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_VALID_MSB 48
|
||||
#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_VALID_MASK 0x0001000000000000
|
||||
|
||||
#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_OFFSET 0x0000000000000000
|
||||
#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_LSB 49
|
||||
#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_MSB 57
|
||||
#define TX_FES_STATUS_USER_PPDU_COEX_ABORT_MPDU_COUNT_MASK 0x03fe000000000000
|
||||
|
||||
#define TX_FES_STATUS_USER_PPDU_TRANSMITTED_TID_OFFSET 0x0000000000000000
|
||||
#define TX_FES_STATUS_USER_PPDU_TRANSMITTED_TID_LSB 58
|
||||
#define TX_FES_STATUS_USER_PPDU_TRANSMITTED_TID_MSB 61
|
||||
#define TX_FES_STATUS_USER_PPDU_TRANSMITTED_TID_MASK 0x3c00000000000000
|
||||
|
||||
#define TX_FES_STATUS_USER_PPDU_TXDMA_DROPPED_MPDU_WARNING_OFFSET 0x0000000000000000
|
||||
#define TX_FES_STATUS_USER_PPDU_TXDMA_DROPPED_MPDU_WARNING_LSB 62
|
||||
#define TX_FES_STATUS_USER_PPDU_TXDMA_DROPPED_MPDU_WARNING_MSB 62
|
||||
#define TX_FES_STATUS_USER_PPDU_TXDMA_DROPPED_MPDU_WARNING_MASK 0x4000000000000000
|
||||
|
||||
#define TX_FES_STATUS_USER_PPDU_RESERVED_1_OFFSET 0x0000000000000000
|
||||
#define TX_FES_STATUS_USER_PPDU_RESERVED_1_LSB 63
|
||||
#define TX_FES_STATUS_USER_PPDU_RESERVED_1_MSB 63
|
||||
#define TX_FES_STATUS_USER_PPDU_RESERVED_1_MASK 0x8000000000000000
|
||||
|
||||
#define TX_FES_STATUS_USER_PPDU_DURATION_OFFSET 0x0000000000000008
|
||||
#define TX_FES_STATUS_USER_PPDU_DURATION_LSB 0
|
||||
#define TX_FES_STATUS_USER_PPDU_DURATION_MSB 15
|
||||
#define TX_FES_STATUS_USER_PPDU_DURATION_MASK 0x000000000000ffff
|
||||
|
||||
#define TX_FES_STATUS_USER_PPDU_NUM_EOF_DELIM_ADDED_OFFSET 0x0000000000000008
|
||||
#define TX_FES_STATUS_USER_PPDU_NUM_EOF_DELIM_ADDED_LSB 16
|
||||
#define TX_FES_STATUS_USER_PPDU_NUM_EOF_DELIM_ADDED_MSB 31
|
||||
#define TX_FES_STATUS_USER_PPDU_NUM_EOF_DELIM_ADDED_MASK 0x00000000ffff0000
|
||||
|
||||
#define TX_FES_STATUS_USER_PPDU_PSDU_OCTET_OFFSET 0x0000000000000008
|
||||
#define TX_FES_STATUS_USER_PPDU_PSDU_OCTET_LSB 32
|
||||
#define TX_FES_STATUS_USER_PPDU_PSDU_OCTET_MSB 55
|
||||
#define TX_FES_STATUS_USER_PPDU_PSDU_OCTET_MASK 0x00ffffff00000000
|
||||
|
||||
#define TX_FES_STATUS_USER_PPDU_QOS_BUF_STATE_OFFSET 0x0000000000000008
|
||||
#define TX_FES_STATUS_USER_PPDU_QOS_BUF_STATE_LSB 56
|
||||
#define TX_FES_STATUS_USER_PPDU_QOS_BUF_STATE_MSB 63
|
||||
#define TX_FES_STATUS_USER_PPDU_QOS_BUF_STATE_MASK 0xff00000000000000
|
||||
|
||||
#define TX_FES_STATUS_USER_PPDU_NUM_NULL_DELIM_ADDED_OFFSET 0x0000000000000010
|
||||
#define TX_FES_STATUS_USER_PPDU_NUM_NULL_DELIM_ADDED_LSB 0
|
||||
#define TX_FES_STATUS_USER_PPDU_NUM_NULL_DELIM_ADDED_MSB 21
|
||||
#define TX_FES_STATUS_USER_PPDU_NUM_NULL_DELIM_ADDED_MASK 0x00000000003fffff
|
||||
|
||||
#define TX_FES_STATUS_USER_PPDU_RESERVED_4A_OFFSET 0x0000000000000010
|
||||
#define TX_FES_STATUS_USER_PPDU_RESERVED_4A_LSB 22
|
||||
#define TX_FES_STATUS_USER_PPDU_RESERVED_4A_MSB 23
|
||||
#define TX_FES_STATUS_USER_PPDU_RESERVED_4A_MASK 0x0000000000c00000
|
||||
|
||||
#define TX_FES_STATUS_USER_PPDU_CV_CORR_USER_VALID_IN_PHY_OFFSET 0x0000000000000010
|
||||
#define TX_FES_STATUS_USER_PPDU_CV_CORR_USER_VALID_IN_PHY_LSB 24
|
||||
#define TX_FES_STATUS_USER_PPDU_CV_CORR_USER_VALID_IN_PHY_MSB 24
|
||||
#define TX_FES_STATUS_USER_PPDU_CV_CORR_USER_VALID_IN_PHY_MASK 0x0000000001000000
|
||||
|
||||
#define TX_FES_STATUS_USER_PPDU_NSS_OFFSET 0x0000000000000010
|
||||
#define TX_FES_STATUS_USER_PPDU_NSS_LSB 25
|
||||
#define TX_FES_STATUS_USER_PPDU_NSS_MSB 27
|
||||
#define TX_FES_STATUS_USER_PPDU_NSS_MASK 0x000000000e000000
|
||||
|
||||
#define TX_FES_STATUS_USER_PPDU_MCS_OFFSET 0x0000000000000010
|
||||
#define TX_FES_STATUS_USER_PPDU_MCS_LSB 28
|
||||
#define TX_FES_STATUS_USER_PPDU_MCS_MSB 31
|
||||
#define TX_FES_STATUS_USER_PPDU_MCS_MASK 0x00000000f0000000
|
||||
|
||||
#define TX_FES_STATUS_USER_PPDU_HT_CONTROL_OFFSET 0x0000000000000010
|
||||
#define TX_FES_STATUS_USER_PPDU_HT_CONTROL_LSB 32
|
||||
#define TX_FES_STATUS_USER_PPDU_HT_CONTROL_MSB 63
|
||||
#define TX_FES_STATUS_USER_PPDU_HT_CONTROL_MASK 0xffffffff00000000
|
||||
|
||||
#endif
|
||||
74
hw/kiwi/v2/tx_fes_status_user_response.h
Normal file
74
hw/kiwi/v2/tx_fes_status_user_response.h
Normal file
|
|
@ -0,0 +1,74 @@
|
|||
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
#ifndef _TX_FES_STATUS_USER_RESPONSE_H_
|
||||
#define _TX_FES_STATUS_USER_RESPONSE_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#include "phytx_abort_request_info.h"
|
||||
#define NUM_OF_DWORDS_TX_FES_STATUS_USER_RESPONSE 2
|
||||
|
||||
#define NUM_OF_QWORDS_TX_FES_STATUS_USER_RESPONSE 1
|
||||
|
||||
struct tx_fes_status_user_response {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t fes_transmit_result : 4,
|
||||
reserved_0 : 28;
|
||||
struct phytx_abort_request_info phytx_abort_request_info_details;
|
||||
uint16_t reserved_after_struct16 : 16;
|
||||
#else
|
||||
uint32_t reserved_0 : 28,
|
||||
fes_transmit_result : 4;
|
||||
uint32_t reserved_after_struct16 : 16;
|
||||
struct phytx_abort_request_info phytx_abort_request_info_details;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define TX_FES_STATUS_USER_RESPONSE_FES_TRANSMIT_RESULT_OFFSET 0x0000000000000000
|
||||
#define TX_FES_STATUS_USER_RESPONSE_FES_TRANSMIT_RESULT_LSB 0
|
||||
#define TX_FES_STATUS_USER_RESPONSE_FES_TRANSMIT_RESULT_MSB 3
|
||||
#define TX_FES_STATUS_USER_RESPONSE_FES_TRANSMIT_RESULT_MASK 0x000000000000000f
|
||||
|
||||
#define TX_FES_STATUS_USER_RESPONSE_RESERVED_0_OFFSET 0x0000000000000000
|
||||
#define TX_FES_STATUS_USER_RESPONSE_RESERVED_0_LSB 4
|
||||
#define TX_FES_STATUS_USER_RESPONSE_RESERVED_0_MSB 31
|
||||
#define TX_FES_STATUS_USER_RESPONSE_RESERVED_0_MASK 0x00000000fffffff0
|
||||
|
||||
#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_OFFSET 0x0000000000000000
|
||||
#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_LSB 32
|
||||
#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MSB 39
|
||||
#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_PHYTX_ABORT_REASON_MASK 0x000000ff00000000
|
||||
|
||||
#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_OFFSET 0x0000000000000000
|
||||
#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_LSB 40
|
||||
#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MSB 45
|
||||
#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_USER_NUMBER_MASK 0x00003f0000000000
|
||||
|
||||
#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_OFFSET 0x0000000000000000
|
||||
#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_LSB 46
|
||||
#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MSB 47
|
||||
#define TX_FES_STATUS_USER_RESPONSE_PHYTX_ABORT_REQUEST_INFO_DETAILS_RESERVED_MASK 0x0000c00000000000
|
||||
|
||||
#define TX_FES_STATUS_USER_RESPONSE_RESERVED_AFTER_STRUCT16_OFFSET 0x0000000000000000
|
||||
#define TX_FES_STATUS_USER_RESPONSE_RESERVED_AFTER_STRUCT16_LSB 48
|
||||
#define TX_FES_STATUS_USER_RESPONSE_RESERVED_AFTER_STRUCT16_MSB 63
|
||||
#define TX_FES_STATUS_USER_RESPONSE_RESERVED_AFTER_STRUCT16_MASK 0xffff000000000000
|
||||
|
||||
#endif
|
||||
77
hw/kiwi/v2/tx_flush_req.h
Normal file
77
hw/kiwi/v2/tx_flush_req.h
Normal file
|
|
@ -0,0 +1,77 @@
|
|||
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
#ifndef _TX_FLUSH_REQ_H_
|
||||
#define _TX_FLUSH_REQ_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#define NUM_OF_DWORDS_TX_FLUSH_REQ 2
|
||||
|
||||
#define NUM_OF_QWORDS_TX_FLUSH_REQ 1
|
||||
|
||||
struct tx_flush_req {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t flush_req_reason : 8,
|
||||
phytx_abort_reason : 8,
|
||||
flush_req_user_number_or_link_id : 6,
|
||||
mlo_abort_reason : 5,
|
||||
reserved_0a : 5;
|
||||
uint32_t tlv64_padding : 32;
|
||||
#else
|
||||
uint32_t reserved_0a : 5,
|
||||
mlo_abort_reason : 5,
|
||||
flush_req_user_number_or_link_id : 6,
|
||||
phytx_abort_reason : 8,
|
||||
flush_req_reason : 8;
|
||||
uint32_t tlv64_padding : 32;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define TX_FLUSH_REQ_FLUSH_REQ_REASON_OFFSET 0x0000000000000000
|
||||
#define TX_FLUSH_REQ_FLUSH_REQ_REASON_LSB 0
|
||||
#define TX_FLUSH_REQ_FLUSH_REQ_REASON_MSB 7
|
||||
#define TX_FLUSH_REQ_FLUSH_REQ_REASON_MASK 0x00000000000000ff
|
||||
|
||||
#define TX_FLUSH_REQ_PHYTX_ABORT_REASON_OFFSET 0x0000000000000000
|
||||
#define TX_FLUSH_REQ_PHYTX_ABORT_REASON_LSB 8
|
||||
#define TX_FLUSH_REQ_PHYTX_ABORT_REASON_MSB 15
|
||||
#define TX_FLUSH_REQ_PHYTX_ABORT_REASON_MASK 0x000000000000ff00
|
||||
|
||||
#define TX_FLUSH_REQ_FLUSH_REQ_USER_NUMBER_OR_LINK_ID_OFFSET 0x0000000000000000
|
||||
#define TX_FLUSH_REQ_FLUSH_REQ_USER_NUMBER_OR_LINK_ID_LSB 16
|
||||
#define TX_FLUSH_REQ_FLUSH_REQ_USER_NUMBER_OR_LINK_ID_MSB 21
|
||||
#define TX_FLUSH_REQ_FLUSH_REQ_USER_NUMBER_OR_LINK_ID_MASK 0x00000000003f0000
|
||||
|
||||
#define TX_FLUSH_REQ_MLO_ABORT_REASON_OFFSET 0x0000000000000000
|
||||
#define TX_FLUSH_REQ_MLO_ABORT_REASON_LSB 22
|
||||
#define TX_FLUSH_REQ_MLO_ABORT_REASON_MSB 26
|
||||
#define TX_FLUSH_REQ_MLO_ABORT_REASON_MASK 0x0000000007c00000
|
||||
|
||||
#define TX_FLUSH_REQ_RESERVED_0A_OFFSET 0x0000000000000000
|
||||
#define TX_FLUSH_REQ_RESERVED_0A_LSB 27
|
||||
#define TX_FLUSH_REQ_RESERVED_0A_MSB 31
|
||||
#define TX_FLUSH_REQ_RESERVED_0A_MASK 0x00000000f8000000
|
||||
|
||||
#define TX_FLUSH_REQ_TLV64_PADDING_OFFSET 0x0000000000000000
|
||||
#define TX_FLUSH_REQ_TLV64_PADDING_LSB 32
|
||||
#define TX_FLUSH_REQ_TLV64_PADDING_MSB 63
|
||||
#define TX_FLUSH_REQ_TLV64_PADDING_MASK 0xffffffff00000000
|
||||
|
||||
#endif
|
||||
308
hw/kiwi/v2/tx_mpdu_start.h
Normal file
308
hw/kiwi/v2/tx_mpdu_start.h
Normal file
|
|
@ -0,0 +1,308 @@
|
|||
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
#ifndef _TX_MPDU_START_H_
|
||||
#define _TX_MPDU_START_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#define NUM_OF_DWORDS_TX_MPDU_START 10
|
||||
|
||||
#define NUM_OF_QWORDS_TX_MPDU_START 5
|
||||
|
||||
struct tx_mpdu_start {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t mpdu_length : 14,
|
||||
frame_not_from_tqm : 1,
|
||||
vht_control_present : 1,
|
||||
mpdu_header_length : 8,
|
||||
retry_count : 7,
|
||||
wds : 1;
|
||||
uint32_t pn_31_0 : 32;
|
||||
uint32_t pn_47_32 : 16,
|
||||
mpdu_sequence_number : 12,
|
||||
raw_already_encrypted : 1,
|
||||
frame_type : 2,
|
||||
txdma_dropped_mpdu_warning : 1;
|
||||
uint32_t iv_byte_0 : 8,
|
||||
iv_byte_1 : 8,
|
||||
iv_byte_2 : 8,
|
||||
iv_byte_3 : 8;
|
||||
uint32_t iv_byte_4 : 8,
|
||||
iv_byte_5 : 8,
|
||||
iv_byte_6 : 8,
|
||||
iv_byte_7 : 8;
|
||||
uint32_t iv_byte_8 : 8,
|
||||
iv_byte_9 : 8,
|
||||
iv_byte_10 : 8,
|
||||
iv_byte_11 : 8;
|
||||
uint32_t iv_byte_12 : 8,
|
||||
iv_byte_13 : 8,
|
||||
iv_byte_14 : 8,
|
||||
iv_byte_15 : 8;
|
||||
uint32_t iv_byte_16 : 8,
|
||||
iv_byte_17 : 8,
|
||||
iv_len : 5,
|
||||
icv_len : 5,
|
||||
vht_control_offset : 6;
|
||||
uint32_t mpdu_type : 1,
|
||||
transmit_bw_restriction : 1,
|
||||
allowed_transmit_bw : 4,
|
||||
tx_notify_frame : 3,
|
||||
reserved_8a : 23;
|
||||
uint32_t tlv64_padding : 32;
|
||||
#else
|
||||
uint32_t wds : 1,
|
||||
retry_count : 7,
|
||||
mpdu_header_length : 8,
|
||||
vht_control_present : 1,
|
||||
frame_not_from_tqm : 1,
|
||||
mpdu_length : 14;
|
||||
uint32_t pn_31_0 : 32;
|
||||
uint32_t txdma_dropped_mpdu_warning : 1,
|
||||
frame_type : 2,
|
||||
raw_already_encrypted : 1,
|
||||
mpdu_sequence_number : 12,
|
||||
pn_47_32 : 16;
|
||||
uint32_t iv_byte_3 : 8,
|
||||
iv_byte_2 : 8,
|
||||
iv_byte_1 : 8,
|
||||
iv_byte_0 : 8;
|
||||
uint32_t iv_byte_7 : 8,
|
||||
iv_byte_6 : 8,
|
||||
iv_byte_5 : 8,
|
||||
iv_byte_4 : 8;
|
||||
uint32_t iv_byte_11 : 8,
|
||||
iv_byte_10 : 8,
|
||||
iv_byte_9 : 8,
|
||||
iv_byte_8 : 8;
|
||||
uint32_t iv_byte_15 : 8,
|
||||
iv_byte_14 : 8,
|
||||
iv_byte_13 : 8,
|
||||
iv_byte_12 : 8;
|
||||
uint32_t vht_control_offset : 6,
|
||||
icv_len : 5,
|
||||
iv_len : 5,
|
||||
iv_byte_17 : 8,
|
||||
iv_byte_16 : 8;
|
||||
uint32_t reserved_8a : 23,
|
||||
tx_notify_frame : 3,
|
||||
allowed_transmit_bw : 4,
|
||||
transmit_bw_restriction : 1,
|
||||
mpdu_type : 1;
|
||||
uint32_t tlv64_padding : 32;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define TX_MPDU_START_MPDU_LENGTH_OFFSET 0x0000000000000000
|
||||
#define TX_MPDU_START_MPDU_LENGTH_LSB 0
|
||||
#define TX_MPDU_START_MPDU_LENGTH_MSB 13
|
||||
#define TX_MPDU_START_MPDU_LENGTH_MASK 0x0000000000003fff
|
||||
|
||||
#define TX_MPDU_START_FRAME_NOT_FROM_TQM_OFFSET 0x0000000000000000
|
||||
#define TX_MPDU_START_FRAME_NOT_FROM_TQM_LSB 14
|
||||
#define TX_MPDU_START_FRAME_NOT_FROM_TQM_MSB 14
|
||||
#define TX_MPDU_START_FRAME_NOT_FROM_TQM_MASK 0x0000000000004000
|
||||
|
||||
#define TX_MPDU_START_VHT_CONTROL_PRESENT_OFFSET 0x0000000000000000
|
||||
#define TX_MPDU_START_VHT_CONTROL_PRESENT_LSB 15
|
||||
#define TX_MPDU_START_VHT_CONTROL_PRESENT_MSB 15
|
||||
#define TX_MPDU_START_VHT_CONTROL_PRESENT_MASK 0x0000000000008000
|
||||
|
||||
#define TX_MPDU_START_MPDU_HEADER_LENGTH_OFFSET 0x0000000000000000
|
||||
#define TX_MPDU_START_MPDU_HEADER_LENGTH_LSB 16
|
||||
#define TX_MPDU_START_MPDU_HEADER_LENGTH_MSB 23
|
||||
#define TX_MPDU_START_MPDU_HEADER_LENGTH_MASK 0x0000000000ff0000
|
||||
|
||||
#define TX_MPDU_START_RETRY_COUNT_OFFSET 0x0000000000000000
|
||||
#define TX_MPDU_START_RETRY_COUNT_LSB 24
|
||||
#define TX_MPDU_START_RETRY_COUNT_MSB 30
|
||||
#define TX_MPDU_START_RETRY_COUNT_MASK 0x000000007f000000
|
||||
|
||||
#define TX_MPDU_START_WDS_OFFSET 0x0000000000000000
|
||||
#define TX_MPDU_START_WDS_LSB 31
|
||||
#define TX_MPDU_START_WDS_MSB 31
|
||||
#define TX_MPDU_START_WDS_MASK 0x0000000080000000
|
||||
|
||||
#define TX_MPDU_START_PN_31_0_OFFSET 0x0000000000000000
|
||||
#define TX_MPDU_START_PN_31_0_LSB 32
|
||||
#define TX_MPDU_START_PN_31_0_MSB 63
|
||||
#define TX_MPDU_START_PN_31_0_MASK 0xffffffff00000000
|
||||
|
||||
#define TX_MPDU_START_PN_47_32_OFFSET 0x0000000000000008
|
||||
#define TX_MPDU_START_PN_47_32_LSB 0
|
||||
#define TX_MPDU_START_PN_47_32_MSB 15
|
||||
#define TX_MPDU_START_PN_47_32_MASK 0x000000000000ffff
|
||||
|
||||
#define TX_MPDU_START_MPDU_SEQUENCE_NUMBER_OFFSET 0x0000000000000008
|
||||
#define TX_MPDU_START_MPDU_SEQUENCE_NUMBER_LSB 16
|
||||
#define TX_MPDU_START_MPDU_SEQUENCE_NUMBER_MSB 27
|
||||
#define TX_MPDU_START_MPDU_SEQUENCE_NUMBER_MASK 0x000000000fff0000
|
||||
|
||||
#define TX_MPDU_START_RAW_ALREADY_ENCRYPTED_OFFSET 0x0000000000000008
|
||||
#define TX_MPDU_START_RAW_ALREADY_ENCRYPTED_LSB 28
|
||||
#define TX_MPDU_START_RAW_ALREADY_ENCRYPTED_MSB 28
|
||||
#define TX_MPDU_START_RAW_ALREADY_ENCRYPTED_MASK 0x0000000010000000
|
||||
|
||||
#define TX_MPDU_START_FRAME_TYPE_OFFSET 0x0000000000000008
|
||||
#define TX_MPDU_START_FRAME_TYPE_LSB 29
|
||||
#define TX_MPDU_START_FRAME_TYPE_MSB 30
|
||||
#define TX_MPDU_START_FRAME_TYPE_MASK 0x0000000060000000
|
||||
|
||||
#define TX_MPDU_START_TXDMA_DROPPED_MPDU_WARNING_OFFSET 0x0000000000000008
|
||||
#define TX_MPDU_START_TXDMA_DROPPED_MPDU_WARNING_LSB 31
|
||||
#define TX_MPDU_START_TXDMA_DROPPED_MPDU_WARNING_MSB 31
|
||||
#define TX_MPDU_START_TXDMA_DROPPED_MPDU_WARNING_MASK 0x0000000080000000
|
||||
|
||||
#define TX_MPDU_START_IV_BYTE_0_OFFSET 0x0000000000000008
|
||||
#define TX_MPDU_START_IV_BYTE_0_LSB 32
|
||||
#define TX_MPDU_START_IV_BYTE_0_MSB 39
|
||||
#define TX_MPDU_START_IV_BYTE_0_MASK 0x000000ff00000000
|
||||
|
||||
#define TX_MPDU_START_IV_BYTE_1_OFFSET 0x0000000000000008
|
||||
#define TX_MPDU_START_IV_BYTE_1_LSB 40
|
||||
#define TX_MPDU_START_IV_BYTE_1_MSB 47
|
||||
#define TX_MPDU_START_IV_BYTE_1_MASK 0x0000ff0000000000
|
||||
|
||||
#define TX_MPDU_START_IV_BYTE_2_OFFSET 0x0000000000000008
|
||||
#define TX_MPDU_START_IV_BYTE_2_LSB 48
|
||||
#define TX_MPDU_START_IV_BYTE_2_MSB 55
|
||||
#define TX_MPDU_START_IV_BYTE_2_MASK 0x00ff000000000000
|
||||
|
||||
#define TX_MPDU_START_IV_BYTE_3_OFFSET 0x0000000000000008
|
||||
#define TX_MPDU_START_IV_BYTE_3_LSB 56
|
||||
#define TX_MPDU_START_IV_BYTE_3_MSB 63
|
||||
#define TX_MPDU_START_IV_BYTE_3_MASK 0xff00000000000000
|
||||
|
||||
#define TX_MPDU_START_IV_BYTE_4_OFFSET 0x0000000000000010
|
||||
#define TX_MPDU_START_IV_BYTE_4_LSB 0
|
||||
#define TX_MPDU_START_IV_BYTE_4_MSB 7
|
||||
#define TX_MPDU_START_IV_BYTE_4_MASK 0x00000000000000ff
|
||||
|
||||
#define TX_MPDU_START_IV_BYTE_5_OFFSET 0x0000000000000010
|
||||
#define TX_MPDU_START_IV_BYTE_5_LSB 8
|
||||
#define TX_MPDU_START_IV_BYTE_5_MSB 15
|
||||
#define TX_MPDU_START_IV_BYTE_5_MASK 0x000000000000ff00
|
||||
|
||||
#define TX_MPDU_START_IV_BYTE_6_OFFSET 0x0000000000000010
|
||||
#define TX_MPDU_START_IV_BYTE_6_LSB 16
|
||||
#define TX_MPDU_START_IV_BYTE_6_MSB 23
|
||||
#define TX_MPDU_START_IV_BYTE_6_MASK 0x0000000000ff0000
|
||||
|
||||
#define TX_MPDU_START_IV_BYTE_7_OFFSET 0x0000000000000010
|
||||
#define TX_MPDU_START_IV_BYTE_7_LSB 24
|
||||
#define TX_MPDU_START_IV_BYTE_7_MSB 31
|
||||
#define TX_MPDU_START_IV_BYTE_7_MASK 0x00000000ff000000
|
||||
|
||||
#define TX_MPDU_START_IV_BYTE_8_OFFSET 0x0000000000000010
|
||||
#define TX_MPDU_START_IV_BYTE_8_LSB 32
|
||||
#define TX_MPDU_START_IV_BYTE_8_MSB 39
|
||||
#define TX_MPDU_START_IV_BYTE_8_MASK 0x000000ff00000000
|
||||
|
||||
#define TX_MPDU_START_IV_BYTE_9_OFFSET 0x0000000000000010
|
||||
#define TX_MPDU_START_IV_BYTE_9_LSB 40
|
||||
#define TX_MPDU_START_IV_BYTE_9_MSB 47
|
||||
#define TX_MPDU_START_IV_BYTE_9_MASK 0x0000ff0000000000
|
||||
|
||||
#define TX_MPDU_START_IV_BYTE_10_OFFSET 0x0000000000000010
|
||||
#define TX_MPDU_START_IV_BYTE_10_LSB 48
|
||||
#define TX_MPDU_START_IV_BYTE_10_MSB 55
|
||||
#define TX_MPDU_START_IV_BYTE_10_MASK 0x00ff000000000000
|
||||
|
||||
#define TX_MPDU_START_IV_BYTE_11_OFFSET 0x0000000000000010
|
||||
#define TX_MPDU_START_IV_BYTE_11_LSB 56
|
||||
#define TX_MPDU_START_IV_BYTE_11_MSB 63
|
||||
#define TX_MPDU_START_IV_BYTE_11_MASK 0xff00000000000000
|
||||
|
||||
#define TX_MPDU_START_IV_BYTE_12_OFFSET 0x0000000000000018
|
||||
#define TX_MPDU_START_IV_BYTE_12_LSB 0
|
||||
#define TX_MPDU_START_IV_BYTE_12_MSB 7
|
||||
#define TX_MPDU_START_IV_BYTE_12_MASK 0x00000000000000ff
|
||||
|
||||
#define TX_MPDU_START_IV_BYTE_13_OFFSET 0x0000000000000018
|
||||
#define TX_MPDU_START_IV_BYTE_13_LSB 8
|
||||
#define TX_MPDU_START_IV_BYTE_13_MSB 15
|
||||
#define TX_MPDU_START_IV_BYTE_13_MASK 0x000000000000ff00
|
||||
|
||||
#define TX_MPDU_START_IV_BYTE_14_OFFSET 0x0000000000000018
|
||||
#define TX_MPDU_START_IV_BYTE_14_LSB 16
|
||||
#define TX_MPDU_START_IV_BYTE_14_MSB 23
|
||||
#define TX_MPDU_START_IV_BYTE_14_MASK 0x0000000000ff0000
|
||||
|
||||
#define TX_MPDU_START_IV_BYTE_15_OFFSET 0x0000000000000018
|
||||
#define TX_MPDU_START_IV_BYTE_15_LSB 24
|
||||
#define TX_MPDU_START_IV_BYTE_15_MSB 31
|
||||
#define TX_MPDU_START_IV_BYTE_15_MASK 0x00000000ff000000
|
||||
|
||||
#define TX_MPDU_START_IV_BYTE_16_OFFSET 0x0000000000000018
|
||||
#define TX_MPDU_START_IV_BYTE_16_LSB 32
|
||||
#define TX_MPDU_START_IV_BYTE_16_MSB 39
|
||||
#define TX_MPDU_START_IV_BYTE_16_MASK 0x000000ff00000000
|
||||
|
||||
#define TX_MPDU_START_IV_BYTE_17_OFFSET 0x0000000000000018
|
||||
#define TX_MPDU_START_IV_BYTE_17_LSB 40
|
||||
#define TX_MPDU_START_IV_BYTE_17_MSB 47
|
||||
#define TX_MPDU_START_IV_BYTE_17_MASK 0x0000ff0000000000
|
||||
|
||||
#define TX_MPDU_START_IV_LEN_OFFSET 0x0000000000000018
|
||||
#define TX_MPDU_START_IV_LEN_LSB 48
|
||||
#define TX_MPDU_START_IV_LEN_MSB 52
|
||||
#define TX_MPDU_START_IV_LEN_MASK 0x001f000000000000
|
||||
|
||||
#define TX_MPDU_START_ICV_LEN_OFFSET 0x0000000000000018
|
||||
#define TX_MPDU_START_ICV_LEN_LSB 53
|
||||
#define TX_MPDU_START_ICV_LEN_MSB 57
|
||||
#define TX_MPDU_START_ICV_LEN_MASK 0x03e0000000000000
|
||||
|
||||
#define TX_MPDU_START_VHT_CONTROL_OFFSET_OFFSET 0x0000000000000018
|
||||
#define TX_MPDU_START_VHT_CONTROL_OFFSET_LSB 58
|
||||
#define TX_MPDU_START_VHT_CONTROL_OFFSET_MSB 63
|
||||
#define TX_MPDU_START_VHT_CONTROL_OFFSET_MASK 0xfc00000000000000
|
||||
|
||||
#define TX_MPDU_START_MPDU_TYPE_OFFSET 0x0000000000000020
|
||||
#define TX_MPDU_START_MPDU_TYPE_LSB 0
|
||||
#define TX_MPDU_START_MPDU_TYPE_MSB 0
|
||||
#define TX_MPDU_START_MPDU_TYPE_MASK 0x0000000000000001
|
||||
|
||||
#define TX_MPDU_START_TRANSMIT_BW_RESTRICTION_OFFSET 0x0000000000000020
|
||||
#define TX_MPDU_START_TRANSMIT_BW_RESTRICTION_LSB 1
|
||||
#define TX_MPDU_START_TRANSMIT_BW_RESTRICTION_MSB 1
|
||||
#define TX_MPDU_START_TRANSMIT_BW_RESTRICTION_MASK 0x0000000000000002
|
||||
|
||||
#define TX_MPDU_START_ALLOWED_TRANSMIT_BW_OFFSET 0x0000000000000020
|
||||
#define TX_MPDU_START_ALLOWED_TRANSMIT_BW_LSB 2
|
||||
#define TX_MPDU_START_ALLOWED_TRANSMIT_BW_MSB 5
|
||||
#define TX_MPDU_START_ALLOWED_TRANSMIT_BW_MASK 0x000000000000003c
|
||||
|
||||
#define TX_MPDU_START_TX_NOTIFY_FRAME_OFFSET 0x0000000000000020
|
||||
#define TX_MPDU_START_TX_NOTIFY_FRAME_LSB 6
|
||||
#define TX_MPDU_START_TX_NOTIFY_FRAME_MSB 8
|
||||
#define TX_MPDU_START_TX_NOTIFY_FRAME_MASK 0x00000000000001c0
|
||||
|
||||
#define TX_MPDU_START_RESERVED_8A_OFFSET 0x0000000000000020
|
||||
#define TX_MPDU_START_RESERVED_8A_LSB 9
|
||||
#define TX_MPDU_START_RESERVED_8A_MSB 31
|
||||
#define TX_MPDU_START_RESERVED_8A_MASK 0x00000000fffffe00
|
||||
|
||||
#define TX_MPDU_START_TLV64_PADDING_OFFSET 0x0000000000000020
|
||||
#define TX_MPDU_START_TLV64_PADDING_LSB 32
|
||||
#define TX_MPDU_START_TLV64_PADDING_MSB 63
|
||||
#define TX_MPDU_START_TLV64_PADDING_MASK 0xffffffff00000000
|
||||
|
||||
#endif
|
||||
266
hw/kiwi/v2/tx_msdu_start.h
Normal file
266
hw/kiwi/v2/tx_msdu_start.h
Normal file
|
|
@ -0,0 +1,266 @@
|
|||
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
#ifndef _TX_MSDU_START_H_
|
||||
#define _TX_MSDU_START_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#define NUM_OF_DWORDS_TX_MSDU_START 8
|
||||
|
||||
#define NUM_OF_QWORDS_TX_MSDU_START 4
|
||||
|
||||
struct tx_msdu_start {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t msdu_len : 14,
|
||||
first_msdu : 1,
|
||||
last_msdu : 1,
|
||||
encap_type : 2,
|
||||
epd_en : 1,
|
||||
da_sa_present : 2,
|
||||
ipv4_checksum_en : 1,
|
||||
udp_over_ipv4_checksum_en : 1,
|
||||
udp_over_ipv6_checksum_en : 1,
|
||||
tcp_over_ipv4_checksum_en : 1,
|
||||
tcp_over_ipv6_checksum_en : 1,
|
||||
dummy_msdu_delimitation : 1,
|
||||
reserved_0a : 5;
|
||||
uint32_t tso_enable : 1,
|
||||
reserved_1a : 6,
|
||||
tcp_flag : 9,
|
||||
tcp_flag_mask : 9,
|
||||
mesh_enable : 1,
|
||||
reserved_1b : 6;
|
||||
uint32_t l2_length : 16,
|
||||
ip_length : 16;
|
||||
uint32_t tcp_seq_number : 32;
|
||||
uint32_t ip_identification : 16,
|
||||
checksum_offset : 13,
|
||||
partial_checksum_en : 1,
|
||||
reserved_4 : 2;
|
||||
uint32_t payload_start_offset : 14,
|
||||
reserved_5a : 2,
|
||||
payload_end_offset : 14,
|
||||
reserved_5b : 2;
|
||||
uint32_t udp_length : 16,
|
||||
reserved_6 : 16;
|
||||
uint32_t tlv64_padding : 32;
|
||||
#else
|
||||
uint32_t reserved_0a : 5,
|
||||
dummy_msdu_delimitation : 1,
|
||||
tcp_over_ipv6_checksum_en : 1,
|
||||
tcp_over_ipv4_checksum_en : 1,
|
||||
udp_over_ipv6_checksum_en : 1,
|
||||
udp_over_ipv4_checksum_en : 1,
|
||||
ipv4_checksum_en : 1,
|
||||
da_sa_present : 2,
|
||||
epd_en : 1,
|
||||
encap_type : 2,
|
||||
last_msdu : 1,
|
||||
first_msdu : 1,
|
||||
msdu_len : 14;
|
||||
uint32_t reserved_1b : 6,
|
||||
mesh_enable : 1,
|
||||
tcp_flag_mask : 9,
|
||||
tcp_flag : 9,
|
||||
reserved_1a : 6,
|
||||
tso_enable : 1;
|
||||
uint32_t ip_length : 16,
|
||||
l2_length : 16;
|
||||
uint32_t tcp_seq_number : 32;
|
||||
uint32_t reserved_4 : 2,
|
||||
partial_checksum_en : 1,
|
||||
checksum_offset : 13,
|
||||
ip_identification : 16;
|
||||
uint32_t reserved_5b : 2,
|
||||
payload_end_offset : 14,
|
||||
reserved_5a : 2,
|
||||
payload_start_offset : 14;
|
||||
uint32_t reserved_6 : 16,
|
||||
udp_length : 16;
|
||||
uint32_t tlv64_padding : 32;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define TX_MSDU_START_MSDU_LEN_OFFSET 0x0000000000000000
|
||||
#define TX_MSDU_START_MSDU_LEN_LSB 0
|
||||
#define TX_MSDU_START_MSDU_LEN_MSB 13
|
||||
#define TX_MSDU_START_MSDU_LEN_MASK 0x0000000000003fff
|
||||
|
||||
#define TX_MSDU_START_FIRST_MSDU_OFFSET 0x0000000000000000
|
||||
#define TX_MSDU_START_FIRST_MSDU_LSB 14
|
||||
#define TX_MSDU_START_FIRST_MSDU_MSB 14
|
||||
#define TX_MSDU_START_FIRST_MSDU_MASK 0x0000000000004000
|
||||
|
||||
#define TX_MSDU_START_LAST_MSDU_OFFSET 0x0000000000000000
|
||||
#define TX_MSDU_START_LAST_MSDU_LSB 15
|
||||
#define TX_MSDU_START_LAST_MSDU_MSB 15
|
||||
#define TX_MSDU_START_LAST_MSDU_MASK 0x0000000000008000
|
||||
|
||||
#define TX_MSDU_START_ENCAP_TYPE_OFFSET 0x0000000000000000
|
||||
#define TX_MSDU_START_ENCAP_TYPE_LSB 16
|
||||
#define TX_MSDU_START_ENCAP_TYPE_MSB 17
|
||||
#define TX_MSDU_START_ENCAP_TYPE_MASK 0x0000000000030000
|
||||
|
||||
#define TX_MSDU_START_EPD_EN_OFFSET 0x0000000000000000
|
||||
#define TX_MSDU_START_EPD_EN_LSB 18
|
||||
#define TX_MSDU_START_EPD_EN_MSB 18
|
||||
#define TX_MSDU_START_EPD_EN_MASK 0x0000000000040000
|
||||
|
||||
#define TX_MSDU_START_DA_SA_PRESENT_OFFSET 0x0000000000000000
|
||||
#define TX_MSDU_START_DA_SA_PRESENT_LSB 19
|
||||
#define TX_MSDU_START_DA_SA_PRESENT_MSB 20
|
||||
#define TX_MSDU_START_DA_SA_PRESENT_MASK 0x0000000000180000
|
||||
|
||||
#define TX_MSDU_START_IPV4_CHECKSUM_EN_OFFSET 0x0000000000000000
|
||||
#define TX_MSDU_START_IPV4_CHECKSUM_EN_LSB 21
|
||||
#define TX_MSDU_START_IPV4_CHECKSUM_EN_MSB 21
|
||||
#define TX_MSDU_START_IPV4_CHECKSUM_EN_MASK 0x0000000000200000
|
||||
|
||||
#define TX_MSDU_START_UDP_OVER_IPV4_CHECKSUM_EN_OFFSET 0x0000000000000000
|
||||
#define TX_MSDU_START_UDP_OVER_IPV4_CHECKSUM_EN_LSB 22
|
||||
#define TX_MSDU_START_UDP_OVER_IPV4_CHECKSUM_EN_MSB 22
|
||||
#define TX_MSDU_START_UDP_OVER_IPV4_CHECKSUM_EN_MASK 0x0000000000400000
|
||||
|
||||
#define TX_MSDU_START_UDP_OVER_IPV6_CHECKSUM_EN_OFFSET 0x0000000000000000
|
||||
#define TX_MSDU_START_UDP_OVER_IPV6_CHECKSUM_EN_LSB 23
|
||||
#define TX_MSDU_START_UDP_OVER_IPV6_CHECKSUM_EN_MSB 23
|
||||
#define TX_MSDU_START_UDP_OVER_IPV6_CHECKSUM_EN_MASK 0x0000000000800000
|
||||
|
||||
#define TX_MSDU_START_TCP_OVER_IPV4_CHECKSUM_EN_OFFSET 0x0000000000000000
|
||||
#define TX_MSDU_START_TCP_OVER_IPV4_CHECKSUM_EN_LSB 24
|
||||
#define TX_MSDU_START_TCP_OVER_IPV4_CHECKSUM_EN_MSB 24
|
||||
#define TX_MSDU_START_TCP_OVER_IPV4_CHECKSUM_EN_MASK 0x0000000001000000
|
||||
|
||||
#define TX_MSDU_START_TCP_OVER_IPV6_CHECKSUM_EN_OFFSET 0x0000000000000000
|
||||
#define TX_MSDU_START_TCP_OVER_IPV6_CHECKSUM_EN_LSB 25
|
||||
#define TX_MSDU_START_TCP_OVER_IPV6_CHECKSUM_EN_MSB 25
|
||||
#define TX_MSDU_START_TCP_OVER_IPV6_CHECKSUM_EN_MASK 0x0000000002000000
|
||||
|
||||
#define TX_MSDU_START_DUMMY_MSDU_DELIMITATION_OFFSET 0x0000000000000000
|
||||
#define TX_MSDU_START_DUMMY_MSDU_DELIMITATION_LSB 26
|
||||
#define TX_MSDU_START_DUMMY_MSDU_DELIMITATION_MSB 26
|
||||
#define TX_MSDU_START_DUMMY_MSDU_DELIMITATION_MASK 0x0000000004000000
|
||||
|
||||
#define TX_MSDU_START_RESERVED_0A_OFFSET 0x0000000000000000
|
||||
#define TX_MSDU_START_RESERVED_0A_LSB 27
|
||||
#define TX_MSDU_START_RESERVED_0A_MSB 31
|
||||
#define TX_MSDU_START_RESERVED_0A_MASK 0x00000000f8000000
|
||||
|
||||
#define TX_MSDU_START_TSO_ENABLE_OFFSET 0x0000000000000000
|
||||
#define TX_MSDU_START_TSO_ENABLE_LSB 32
|
||||
#define TX_MSDU_START_TSO_ENABLE_MSB 32
|
||||
#define TX_MSDU_START_TSO_ENABLE_MASK 0x0000000100000000
|
||||
|
||||
#define TX_MSDU_START_RESERVED_1A_OFFSET 0x0000000000000000
|
||||
#define TX_MSDU_START_RESERVED_1A_LSB 33
|
||||
#define TX_MSDU_START_RESERVED_1A_MSB 38
|
||||
#define TX_MSDU_START_RESERVED_1A_MASK 0x0000007e00000000
|
||||
|
||||
#define TX_MSDU_START_TCP_FLAG_OFFSET 0x0000000000000000
|
||||
#define TX_MSDU_START_TCP_FLAG_LSB 39
|
||||
#define TX_MSDU_START_TCP_FLAG_MSB 47
|
||||
#define TX_MSDU_START_TCP_FLAG_MASK 0x0000ff8000000000
|
||||
|
||||
#define TX_MSDU_START_TCP_FLAG_MASK_OFFSET 0x0000000000000000
|
||||
#define TX_MSDU_START_TCP_FLAG_MASK_LSB 48
|
||||
#define TX_MSDU_START_TCP_FLAG_MASK_MSB 56
|
||||
#define TX_MSDU_START_TCP_FLAG_MASK_MASK 0x01ff000000000000
|
||||
|
||||
#define TX_MSDU_START_MESH_ENABLE_OFFSET 0x0000000000000000
|
||||
#define TX_MSDU_START_MESH_ENABLE_LSB 57
|
||||
#define TX_MSDU_START_MESH_ENABLE_MSB 57
|
||||
#define TX_MSDU_START_MESH_ENABLE_MASK 0x0200000000000000
|
||||
|
||||
#define TX_MSDU_START_RESERVED_1B_OFFSET 0x0000000000000000
|
||||
#define TX_MSDU_START_RESERVED_1B_LSB 58
|
||||
#define TX_MSDU_START_RESERVED_1B_MSB 63
|
||||
#define TX_MSDU_START_RESERVED_1B_MASK 0xfc00000000000000
|
||||
|
||||
#define TX_MSDU_START_L2_LENGTH_OFFSET 0x0000000000000008
|
||||
#define TX_MSDU_START_L2_LENGTH_LSB 0
|
||||
#define TX_MSDU_START_L2_LENGTH_MSB 15
|
||||
#define TX_MSDU_START_L2_LENGTH_MASK 0x000000000000ffff
|
||||
|
||||
#define TX_MSDU_START_IP_LENGTH_OFFSET 0x0000000000000008
|
||||
#define TX_MSDU_START_IP_LENGTH_LSB 16
|
||||
#define TX_MSDU_START_IP_LENGTH_MSB 31
|
||||
#define TX_MSDU_START_IP_LENGTH_MASK 0x00000000ffff0000
|
||||
|
||||
#define TX_MSDU_START_TCP_SEQ_NUMBER_OFFSET 0x0000000000000008
|
||||
#define TX_MSDU_START_TCP_SEQ_NUMBER_LSB 32
|
||||
#define TX_MSDU_START_TCP_SEQ_NUMBER_MSB 63
|
||||
#define TX_MSDU_START_TCP_SEQ_NUMBER_MASK 0xffffffff00000000
|
||||
|
||||
#define TX_MSDU_START_IP_IDENTIFICATION_OFFSET 0x0000000000000010
|
||||
#define TX_MSDU_START_IP_IDENTIFICATION_LSB 0
|
||||
#define TX_MSDU_START_IP_IDENTIFICATION_MSB 15
|
||||
#define TX_MSDU_START_IP_IDENTIFICATION_MASK 0x000000000000ffff
|
||||
|
||||
#define TX_MSDU_START_CHECKSUM_OFFSET_OFFSET 0x0000000000000010
|
||||
#define TX_MSDU_START_CHECKSUM_OFFSET_LSB 16
|
||||
#define TX_MSDU_START_CHECKSUM_OFFSET_MSB 28
|
||||
#define TX_MSDU_START_CHECKSUM_OFFSET_MASK 0x000000001fff0000
|
||||
|
||||
#define TX_MSDU_START_PARTIAL_CHECKSUM_EN_OFFSET 0x0000000000000010
|
||||
#define TX_MSDU_START_PARTIAL_CHECKSUM_EN_LSB 29
|
||||
#define TX_MSDU_START_PARTIAL_CHECKSUM_EN_MSB 29
|
||||
#define TX_MSDU_START_PARTIAL_CHECKSUM_EN_MASK 0x0000000020000000
|
||||
|
||||
#define TX_MSDU_START_RESERVED_4_OFFSET 0x0000000000000010
|
||||
#define TX_MSDU_START_RESERVED_4_LSB 30
|
||||
#define TX_MSDU_START_RESERVED_4_MSB 31
|
||||
#define TX_MSDU_START_RESERVED_4_MASK 0x00000000c0000000
|
||||
|
||||
#define TX_MSDU_START_PAYLOAD_START_OFFSET_OFFSET 0x0000000000000010
|
||||
#define TX_MSDU_START_PAYLOAD_START_OFFSET_LSB 32
|
||||
#define TX_MSDU_START_PAYLOAD_START_OFFSET_MSB 45
|
||||
#define TX_MSDU_START_PAYLOAD_START_OFFSET_MASK 0x00003fff00000000
|
||||
|
||||
#define TX_MSDU_START_RESERVED_5A_OFFSET 0x0000000000000010
|
||||
#define TX_MSDU_START_RESERVED_5A_LSB 46
|
||||
#define TX_MSDU_START_RESERVED_5A_MSB 47
|
||||
#define TX_MSDU_START_RESERVED_5A_MASK 0x0000c00000000000
|
||||
|
||||
#define TX_MSDU_START_PAYLOAD_END_OFFSET_OFFSET 0x0000000000000010
|
||||
#define TX_MSDU_START_PAYLOAD_END_OFFSET_LSB 48
|
||||
#define TX_MSDU_START_PAYLOAD_END_OFFSET_MSB 61
|
||||
#define TX_MSDU_START_PAYLOAD_END_OFFSET_MASK 0x3fff000000000000
|
||||
|
||||
#define TX_MSDU_START_RESERVED_5B_OFFSET 0x0000000000000010
|
||||
#define TX_MSDU_START_RESERVED_5B_LSB 62
|
||||
#define TX_MSDU_START_RESERVED_5B_MSB 63
|
||||
#define TX_MSDU_START_RESERVED_5B_MASK 0xc000000000000000
|
||||
|
||||
#define TX_MSDU_START_UDP_LENGTH_OFFSET 0x0000000000000018
|
||||
#define TX_MSDU_START_UDP_LENGTH_LSB 0
|
||||
#define TX_MSDU_START_UDP_LENGTH_MSB 15
|
||||
#define TX_MSDU_START_UDP_LENGTH_MASK 0x000000000000ffff
|
||||
|
||||
#define TX_MSDU_START_RESERVED_6_OFFSET 0x0000000000000018
|
||||
#define TX_MSDU_START_RESERVED_6_LSB 16
|
||||
#define TX_MSDU_START_RESERVED_6_MSB 31
|
||||
#define TX_MSDU_START_RESERVED_6_MASK 0x00000000ffff0000
|
||||
|
||||
#define TX_MSDU_START_TLV64_PADDING_OFFSET 0x0000000000000018
|
||||
#define TX_MSDU_START_TLV64_PADDING_LSB 32
|
||||
#define TX_MSDU_START_TLV64_PADDING_MSB 63
|
||||
#define TX_MSDU_START_TLV64_PADDING_MASK 0xffffffff00000000
|
||||
|
||||
#endif
|
||||
295
hw/kiwi/v2/tx_peer_entry.h
Normal file
295
hw/kiwi/v2/tx_peer_entry.h
Normal file
|
|
@ -0,0 +1,295 @@
|
|||
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
#ifndef _TX_PEER_ENTRY_H_
|
||||
#define _TX_PEER_ENTRY_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#define NUM_OF_DWORDS_TX_PEER_ENTRY 18
|
||||
|
||||
#define NUM_OF_QWORDS_TX_PEER_ENTRY 9
|
||||
|
||||
struct tx_peer_entry {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t mac_addr_a_31_0 : 32;
|
||||
uint32_t mac_addr_a_47_32 : 16,
|
||||
mac_addr_b_15_0 : 16;
|
||||
uint32_t mac_addr_b_47_16 : 32;
|
||||
uint32_t use_ad_b : 1,
|
||||
strip_insert_vlan_inner : 1,
|
||||
strip_insert_vlan_outer : 1,
|
||||
vlan_llc_mode : 1,
|
||||
key_type : 4,
|
||||
a_msdu_wds_ad3_ad4 : 3,
|
||||
ignore_hard_filters : 1,
|
||||
ignore_soft_filters : 1,
|
||||
epd_output : 1,
|
||||
wds : 1,
|
||||
insert_or_strip : 1,
|
||||
sw_filter_id : 16;
|
||||
uint32_t temporal_key_31_0 : 32;
|
||||
uint32_t temporal_key_63_32 : 32;
|
||||
uint32_t temporal_key_95_64 : 32;
|
||||
uint32_t temporal_key_127_96 : 32;
|
||||
uint32_t temporal_key_159_128 : 32;
|
||||
uint32_t temporal_key_191_160 : 32;
|
||||
uint32_t temporal_key_223_192 : 32;
|
||||
uint32_t temporal_key_255_224 : 32;
|
||||
uint32_t sta_partial_aid : 11,
|
||||
transmit_vif : 4,
|
||||
block_this_user : 1,
|
||||
mesh_amsdu_mode : 2,
|
||||
use_qos_alt_mute_mask : 1,
|
||||
dl_ul_direction : 1,
|
||||
reserved_12 : 12;
|
||||
uint32_t insert_vlan_outer_tci : 16,
|
||||
insert_vlan_inner_tci : 16;
|
||||
uint32_t __reserved_g_0007 : 32;
|
||||
uint32_t __reserved_g_0008 : 16,
|
||||
__reserved_g_0009 : 16;
|
||||
uint32_t __reserved_g_0010 : 32;
|
||||
uint32_t multi_link_addr_crypto_enable : 1,
|
||||
reserved_17a : 15,
|
||||
sw_peer_id : 16;
|
||||
#else
|
||||
uint32_t mac_addr_a_31_0 : 32;
|
||||
uint32_t mac_addr_b_15_0 : 16,
|
||||
mac_addr_a_47_32 : 16;
|
||||
uint32_t mac_addr_b_47_16 : 32;
|
||||
uint32_t sw_filter_id : 16,
|
||||
insert_or_strip : 1,
|
||||
wds : 1,
|
||||
epd_output : 1,
|
||||
ignore_soft_filters : 1,
|
||||
ignore_hard_filters : 1,
|
||||
a_msdu_wds_ad3_ad4 : 3,
|
||||
key_type : 4,
|
||||
vlan_llc_mode : 1,
|
||||
strip_insert_vlan_outer : 1,
|
||||
strip_insert_vlan_inner : 1,
|
||||
use_ad_b : 1;
|
||||
uint32_t temporal_key_31_0 : 32;
|
||||
uint32_t temporal_key_63_32 : 32;
|
||||
uint32_t temporal_key_95_64 : 32;
|
||||
uint32_t temporal_key_127_96 : 32;
|
||||
uint32_t temporal_key_159_128 : 32;
|
||||
uint32_t temporal_key_191_160 : 32;
|
||||
uint32_t temporal_key_223_192 : 32;
|
||||
uint32_t temporal_key_255_224 : 32;
|
||||
uint32_t reserved_12 : 12,
|
||||
dl_ul_direction : 1,
|
||||
use_qos_alt_mute_mask : 1,
|
||||
mesh_amsdu_mode : 2,
|
||||
block_this_user : 1,
|
||||
transmit_vif : 4,
|
||||
sta_partial_aid : 11;
|
||||
uint32_t insert_vlan_inner_tci : 16,
|
||||
insert_vlan_outer_tci : 16;
|
||||
uint32_t __reserved_g_0007 : 32;
|
||||
uint32_t __reserved_g_0009 : 16,
|
||||
__reserved_g_0008 : 16;
|
||||
uint32_t __reserved_g_0010 : 32;
|
||||
uint32_t sw_peer_id : 16,
|
||||
reserved_17a : 15,
|
||||
multi_link_addr_crypto_enable : 1;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define TX_PEER_ENTRY_MAC_ADDR_A_31_0_OFFSET 0x0000000000000000
|
||||
#define TX_PEER_ENTRY_MAC_ADDR_A_31_0_LSB 0
|
||||
#define TX_PEER_ENTRY_MAC_ADDR_A_31_0_MSB 31
|
||||
#define TX_PEER_ENTRY_MAC_ADDR_A_31_0_MASK 0x00000000ffffffff
|
||||
|
||||
#define TX_PEER_ENTRY_MAC_ADDR_A_47_32_OFFSET 0x0000000000000000
|
||||
#define TX_PEER_ENTRY_MAC_ADDR_A_47_32_LSB 32
|
||||
#define TX_PEER_ENTRY_MAC_ADDR_A_47_32_MSB 47
|
||||
#define TX_PEER_ENTRY_MAC_ADDR_A_47_32_MASK 0x0000ffff00000000
|
||||
|
||||
#define TX_PEER_ENTRY_MAC_ADDR_B_15_0_OFFSET 0x0000000000000000
|
||||
#define TX_PEER_ENTRY_MAC_ADDR_B_15_0_LSB 48
|
||||
#define TX_PEER_ENTRY_MAC_ADDR_B_15_0_MSB 63
|
||||
#define TX_PEER_ENTRY_MAC_ADDR_B_15_0_MASK 0xffff000000000000
|
||||
|
||||
#define TX_PEER_ENTRY_MAC_ADDR_B_47_16_OFFSET 0x0000000000000008
|
||||
#define TX_PEER_ENTRY_MAC_ADDR_B_47_16_LSB 0
|
||||
#define TX_PEER_ENTRY_MAC_ADDR_B_47_16_MSB 31
|
||||
#define TX_PEER_ENTRY_MAC_ADDR_B_47_16_MASK 0x00000000ffffffff
|
||||
|
||||
#define TX_PEER_ENTRY_USE_AD_B_OFFSET 0x0000000000000008
|
||||
#define TX_PEER_ENTRY_USE_AD_B_LSB 32
|
||||
#define TX_PEER_ENTRY_USE_AD_B_MSB 32
|
||||
#define TX_PEER_ENTRY_USE_AD_B_MASK 0x0000000100000000
|
||||
|
||||
#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_INNER_OFFSET 0x0000000000000008
|
||||
#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_INNER_LSB 33
|
||||
#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_INNER_MSB 33
|
||||
#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_INNER_MASK 0x0000000200000000
|
||||
|
||||
#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_OUTER_OFFSET 0x0000000000000008
|
||||
#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_OUTER_LSB 34
|
||||
#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_OUTER_MSB 34
|
||||
#define TX_PEER_ENTRY_STRIP_INSERT_VLAN_OUTER_MASK 0x0000000400000000
|
||||
|
||||
#define TX_PEER_ENTRY_VLAN_LLC_MODE_OFFSET 0x0000000000000008
|
||||
#define TX_PEER_ENTRY_VLAN_LLC_MODE_LSB 35
|
||||
#define TX_PEER_ENTRY_VLAN_LLC_MODE_MSB 35
|
||||
#define TX_PEER_ENTRY_VLAN_LLC_MODE_MASK 0x0000000800000000
|
||||
|
||||
#define TX_PEER_ENTRY_KEY_TYPE_OFFSET 0x0000000000000008
|
||||
#define TX_PEER_ENTRY_KEY_TYPE_LSB 36
|
||||
#define TX_PEER_ENTRY_KEY_TYPE_MSB 39
|
||||
#define TX_PEER_ENTRY_KEY_TYPE_MASK 0x000000f000000000
|
||||
|
||||
#define TX_PEER_ENTRY_A_MSDU_WDS_AD3_AD4_OFFSET 0x0000000000000008
|
||||
#define TX_PEER_ENTRY_A_MSDU_WDS_AD3_AD4_LSB 40
|
||||
#define TX_PEER_ENTRY_A_MSDU_WDS_AD3_AD4_MSB 42
|
||||
#define TX_PEER_ENTRY_A_MSDU_WDS_AD3_AD4_MASK 0x0000070000000000
|
||||
|
||||
#define TX_PEER_ENTRY_IGNORE_HARD_FILTERS_OFFSET 0x0000000000000008
|
||||
#define TX_PEER_ENTRY_IGNORE_HARD_FILTERS_LSB 43
|
||||
#define TX_PEER_ENTRY_IGNORE_HARD_FILTERS_MSB 43
|
||||
#define TX_PEER_ENTRY_IGNORE_HARD_FILTERS_MASK 0x0000080000000000
|
||||
|
||||
#define TX_PEER_ENTRY_IGNORE_SOFT_FILTERS_OFFSET 0x0000000000000008
|
||||
#define TX_PEER_ENTRY_IGNORE_SOFT_FILTERS_LSB 44
|
||||
#define TX_PEER_ENTRY_IGNORE_SOFT_FILTERS_MSB 44
|
||||
#define TX_PEER_ENTRY_IGNORE_SOFT_FILTERS_MASK 0x0000100000000000
|
||||
|
||||
#define TX_PEER_ENTRY_EPD_OUTPUT_OFFSET 0x0000000000000008
|
||||
#define TX_PEER_ENTRY_EPD_OUTPUT_LSB 45
|
||||
#define TX_PEER_ENTRY_EPD_OUTPUT_MSB 45
|
||||
#define TX_PEER_ENTRY_EPD_OUTPUT_MASK 0x0000200000000000
|
||||
|
||||
#define TX_PEER_ENTRY_WDS_OFFSET 0x0000000000000008
|
||||
#define TX_PEER_ENTRY_WDS_LSB 46
|
||||
#define TX_PEER_ENTRY_WDS_MSB 46
|
||||
#define TX_PEER_ENTRY_WDS_MASK 0x0000400000000000
|
||||
|
||||
#define TX_PEER_ENTRY_INSERT_OR_STRIP_OFFSET 0x0000000000000008
|
||||
#define TX_PEER_ENTRY_INSERT_OR_STRIP_LSB 47
|
||||
#define TX_PEER_ENTRY_INSERT_OR_STRIP_MSB 47
|
||||
#define TX_PEER_ENTRY_INSERT_OR_STRIP_MASK 0x0000800000000000
|
||||
|
||||
#define TX_PEER_ENTRY_SW_FILTER_ID_OFFSET 0x0000000000000008
|
||||
#define TX_PEER_ENTRY_SW_FILTER_ID_LSB 48
|
||||
#define TX_PEER_ENTRY_SW_FILTER_ID_MSB 63
|
||||
#define TX_PEER_ENTRY_SW_FILTER_ID_MASK 0xffff000000000000
|
||||
|
||||
#define TX_PEER_ENTRY_TEMPORAL_KEY_31_0_OFFSET 0x0000000000000010
|
||||
#define TX_PEER_ENTRY_TEMPORAL_KEY_31_0_LSB 0
|
||||
#define TX_PEER_ENTRY_TEMPORAL_KEY_31_0_MSB 31
|
||||
#define TX_PEER_ENTRY_TEMPORAL_KEY_31_0_MASK 0x00000000ffffffff
|
||||
|
||||
#define TX_PEER_ENTRY_TEMPORAL_KEY_63_32_OFFSET 0x0000000000000010
|
||||
#define TX_PEER_ENTRY_TEMPORAL_KEY_63_32_LSB 32
|
||||
#define TX_PEER_ENTRY_TEMPORAL_KEY_63_32_MSB 63
|
||||
#define TX_PEER_ENTRY_TEMPORAL_KEY_63_32_MASK 0xffffffff00000000
|
||||
|
||||
#define TX_PEER_ENTRY_TEMPORAL_KEY_95_64_OFFSET 0x0000000000000018
|
||||
#define TX_PEER_ENTRY_TEMPORAL_KEY_95_64_LSB 0
|
||||
#define TX_PEER_ENTRY_TEMPORAL_KEY_95_64_MSB 31
|
||||
#define TX_PEER_ENTRY_TEMPORAL_KEY_95_64_MASK 0x00000000ffffffff
|
||||
|
||||
#define TX_PEER_ENTRY_TEMPORAL_KEY_127_96_OFFSET 0x0000000000000018
|
||||
#define TX_PEER_ENTRY_TEMPORAL_KEY_127_96_LSB 32
|
||||
#define TX_PEER_ENTRY_TEMPORAL_KEY_127_96_MSB 63
|
||||
#define TX_PEER_ENTRY_TEMPORAL_KEY_127_96_MASK 0xffffffff00000000
|
||||
|
||||
#define TX_PEER_ENTRY_TEMPORAL_KEY_159_128_OFFSET 0x0000000000000020
|
||||
#define TX_PEER_ENTRY_TEMPORAL_KEY_159_128_LSB 0
|
||||
#define TX_PEER_ENTRY_TEMPORAL_KEY_159_128_MSB 31
|
||||
#define TX_PEER_ENTRY_TEMPORAL_KEY_159_128_MASK 0x00000000ffffffff
|
||||
|
||||
#define TX_PEER_ENTRY_TEMPORAL_KEY_191_160_OFFSET 0x0000000000000020
|
||||
#define TX_PEER_ENTRY_TEMPORAL_KEY_191_160_LSB 32
|
||||
#define TX_PEER_ENTRY_TEMPORAL_KEY_191_160_MSB 63
|
||||
#define TX_PEER_ENTRY_TEMPORAL_KEY_191_160_MASK 0xffffffff00000000
|
||||
|
||||
#define TX_PEER_ENTRY_TEMPORAL_KEY_223_192_OFFSET 0x0000000000000028
|
||||
#define TX_PEER_ENTRY_TEMPORAL_KEY_223_192_LSB 0
|
||||
#define TX_PEER_ENTRY_TEMPORAL_KEY_223_192_MSB 31
|
||||
#define TX_PEER_ENTRY_TEMPORAL_KEY_223_192_MASK 0x00000000ffffffff
|
||||
|
||||
#define TX_PEER_ENTRY_TEMPORAL_KEY_255_224_OFFSET 0x0000000000000028
|
||||
#define TX_PEER_ENTRY_TEMPORAL_KEY_255_224_LSB 32
|
||||
#define TX_PEER_ENTRY_TEMPORAL_KEY_255_224_MSB 63
|
||||
#define TX_PEER_ENTRY_TEMPORAL_KEY_255_224_MASK 0xffffffff00000000
|
||||
|
||||
#define TX_PEER_ENTRY_STA_PARTIAL_AID_OFFSET 0x0000000000000030
|
||||
#define TX_PEER_ENTRY_STA_PARTIAL_AID_LSB 0
|
||||
#define TX_PEER_ENTRY_STA_PARTIAL_AID_MSB 10
|
||||
#define TX_PEER_ENTRY_STA_PARTIAL_AID_MASK 0x00000000000007ff
|
||||
|
||||
#define TX_PEER_ENTRY_TRANSMIT_VIF_OFFSET 0x0000000000000030
|
||||
#define TX_PEER_ENTRY_TRANSMIT_VIF_LSB 11
|
||||
#define TX_PEER_ENTRY_TRANSMIT_VIF_MSB 14
|
||||
#define TX_PEER_ENTRY_TRANSMIT_VIF_MASK 0x0000000000007800
|
||||
|
||||
#define TX_PEER_ENTRY_BLOCK_THIS_USER_OFFSET 0x0000000000000030
|
||||
#define TX_PEER_ENTRY_BLOCK_THIS_USER_LSB 15
|
||||
#define TX_PEER_ENTRY_BLOCK_THIS_USER_MSB 15
|
||||
#define TX_PEER_ENTRY_BLOCK_THIS_USER_MASK 0x0000000000008000
|
||||
|
||||
#define TX_PEER_ENTRY_MESH_AMSDU_MODE_OFFSET 0x0000000000000030
|
||||
#define TX_PEER_ENTRY_MESH_AMSDU_MODE_LSB 16
|
||||
#define TX_PEER_ENTRY_MESH_AMSDU_MODE_MSB 17
|
||||
#define TX_PEER_ENTRY_MESH_AMSDU_MODE_MASK 0x0000000000030000
|
||||
|
||||
#define TX_PEER_ENTRY_USE_QOS_ALT_MUTE_MASK_OFFSET 0x0000000000000030
|
||||
#define TX_PEER_ENTRY_USE_QOS_ALT_MUTE_MASK_LSB 18
|
||||
#define TX_PEER_ENTRY_USE_QOS_ALT_MUTE_MASK_MSB 18
|
||||
#define TX_PEER_ENTRY_USE_QOS_ALT_MUTE_MASK_MASK 0x0000000000040000
|
||||
|
||||
#define TX_PEER_ENTRY_DL_UL_DIRECTION_OFFSET 0x0000000000000030
|
||||
#define TX_PEER_ENTRY_DL_UL_DIRECTION_LSB 19
|
||||
#define TX_PEER_ENTRY_DL_UL_DIRECTION_MSB 19
|
||||
#define TX_PEER_ENTRY_DL_UL_DIRECTION_MASK 0x0000000000080000
|
||||
|
||||
#define TX_PEER_ENTRY_RESERVED_12_OFFSET 0x0000000000000030
|
||||
#define TX_PEER_ENTRY_RESERVED_12_LSB 20
|
||||
#define TX_PEER_ENTRY_RESERVED_12_MSB 31
|
||||
#define TX_PEER_ENTRY_RESERVED_12_MASK 0x00000000fff00000
|
||||
|
||||
#define TX_PEER_ENTRY_INSERT_VLAN_OUTER_TCI_OFFSET 0x0000000000000030
|
||||
#define TX_PEER_ENTRY_INSERT_VLAN_OUTER_TCI_LSB 32
|
||||
#define TX_PEER_ENTRY_INSERT_VLAN_OUTER_TCI_MSB 47
|
||||
#define TX_PEER_ENTRY_INSERT_VLAN_OUTER_TCI_MASK 0x0000ffff00000000
|
||||
|
||||
#define TX_PEER_ENTRY_INSERT_VLAN_INNER_TCI_OFFSET 0x0000000000000030
|
||||
#define TX_PEER_ENTRY_INSERT_VLAN_INNER_TCI_LSB 48
|
||||
#define TX_PEER_ENTRY_INSERT_VLAN_INNER_TCI_MSB 63
|
||||
#define TX_PEER_ENTRY_INSERT_VLAN_INNER_TCI_MASK 0xffff000000000000
|
||||
|
||||
#define TX_PEER_ENTRY_MULTI_LINK_ADDR_CRYPTO_ENABLE_OFFSET 0x0000000000000040
|
||||
#define TX_PEER_ENTRY_MULTI_LINK_ADDR_CRYPTO_ENABLE_LSB 32
|
||||
#define TX_PEER_ENTRY_MULTI_LINK_ADDR_CRYPTO_ENABLE_MSB 32
|
||||
#define TX_PEER_ENTRY_MULTI_LINK_ADDR_CRYPTO_ENABLE_MASK 0x0000000100000000
|
||||
|
||||
#define TX_PEER_ENTRY_RESERVED_17A_OFFSET 0x0000000000000040
|
||||
#define TX_PEER_ENTRY_RESERVED_17A_LSB 33
|
||||
#define TX_PEER_ENTRY_RESERVED_17A_MSB 47
|
||||
#define TX_PEER_ENTRY_RESERVED_17A_MASK 0x0000fffe00000000
|
||||
|
||||
#define TX_PEER_ENTRY_SW_PEER_ID_OFFSET 0x0000000000000040
|
||||
#define TX_PEER_ENTRY_SW_PEER_ID_LSB 48
|
||||
#define TX_PEER_ENTRY_SW_PEER_ID_MSB 63
|
||||
#define TX_PEER_ENTRY_SW_PEER_ID_MASK 0xffff000000000000
|
||||
|
||||
#endif
|
||||
322
hw/kiwi/v2/tx_queue_extension.h
Normal file
322
hw/kiwi/v2/tx_queue_extension.h
Normal file
|
|
@ -0,0 +1,322 @@
|
|||
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
#ifndef _TX_QUEUE_EXTENSION_H_
|
||||
#define _TX_QUEUE_EXTENSION_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#define NUM_OF_DWORDS_TX_QUEUE_EXTENSION 14
|
||||
|
||||
#define NUM_OF_QWORDS_TX_QUEUE_EXTENSION 7
|
||||
|
||||
struct tx_queue_extension {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t frame_ctl : 16,
|
||||
qos_ctl : 16;
|
||||
uint32_t ampdu_flag : 1,
|
||||
tx_notify_no_htc_override : 1,
|
||||
reserved_1a : 7,
|
||||
checksum_tso_disable_for_frag : 1,
|
||||
key_id : 8,
|
||||
qos_buf_state_overwrite : 1,
|
||||
buf_state_sta_id : 1,
|
||||
buf_state_source : 1,
|
||||
ht_control_overwrite_enable : 1,
|
||||
ht_control_overwrite_source : 4,
|
||||
reserved_1b : 6;
|
||||
uint32_t ul_headroom_insertion_enable : 1,
|
||||
ul_headroom_offset : 5,
|
||||
bqrp_insertion_enable : 1,
|
||||
bqrp_offset : 5,
|
||||
ul_headroom_rsvd_7_6 : 2,
|
||||
bqr_rsvd_9_8 : 2,
|
||||
base_pn_63_48 : 16;
|
||||
uint32_t base_pn_95_64 : 32;
|
||||
uint32_t base_pn_127_96 : 32;
|
||||
uint32_t ht_control_field_bw20 : 32;
|
||||
uint32_t ht_control_field_bw40 : 32;
|
||||
uint32_t ht_control_field_bw80 : 32;
|
||||
uint32_t ht_control_field_bw160 : 32;
|
||||
uint32_t ht_control_overwrite_mask : 32;
|
||||
uint32_t cas_control_info : 8,
|
||||
cas_offset : 5,
|
||||
cas_insertion_enable : 1,
|
||||
reserved_10a : 2,
|
||||
ht_control_overwrite_source_for_srp : 4,
|
||||
ht_control_overwrite_source_for_bsrp : 4,
|
||||
reserved_10b : 6,
|
||||
mpdu_hdr_len_override_en : 1,
|
||||
bar_ssn_overwrite_enable : 1;
|
||||
uint32_t bar_ssn_offset : 12,
|
||||
mpdu_hdr_len_override_val : 9,
|
||||
reserved_11a : 11;
|
||||
uint32_t ht_control_field_bw320 : 32;
|
||||
uint32_t fw2sw_info : 32;
|
||||
#else
|
||||
uint32_t qos_ctl : 16,
|
||||
frame_ctl : 16;
|
||||
uint32_t reserved_1b : 6,
|
||||
ht_control_overwrite_source : 4,
|
||||
ht_control_overwrite_enable : 1,
|
||||
buf_state_source : 1,
|
||||
buf_state_sta_id : 1,
|
||||
qos_buf_state_overwrite : 1,
|
||||
key_id : 8,
|
||||
checksum_tso_disable_for_frag : 1,
|
||||
reserved_1a : 7,
|
||||
tx_notify_no_htc_override : 1,
|
||||
ampdu_flag : 1;
|
||||
uint32_t base_pn_63_48 : 16,
|
||||
bqr_rsvd_9_8 : 2,
|
||||
ul_headroom_rsvd_7_6 : 2,
|
||||
bqrp_offset : 5,
|
||||
bqrp_insertion_enable : 1,
|
||||
ul_headroom_offset : 5,
|
||||
ul_headroom_insertion_enable : 1;
|
||||
uint32_t base_pn_95_64 : 32;
|
||||
uint32_t base_pn_127_96 : 32;
|
||||
uint32_t ht_control_field_bw20 : 32;
|
||||
uint32_t ht_control_field_bw40 : 32;
|
||||
uint32_t ht_control_field_bw80 : 32;
|
||||
uint32_t ht_control_field_bw160 : 32;
|
||||
uint32_t ht_control_overwrite_mask : 32;
|
||||
uint32_t bar_ssn_overwrite_enable : 1,
|
||||
mpdu_hdr_len_override_en : 1,
|
||||
reserved_10b : 6,
|
||||
ht_control_overwrite_source_for_bsrp : 4,
|
||||
ht_control_overwrite_source_for_srp : 4,
|
||||
reserved_10a : 2,
|
||||
cas_insertion_enable : 1,
|
||||
cas_offset : 5,
|
||||
cas_control_info : 8;
|
||||
uint32_t reserved_11a : 11,
|
||||
mpdu_hdr_len_override_val : 9,
|
||||
bar_ssn_offset : 12;
|
||||
uint32_t ht_control_field_bw320 : 32;
|
||||
uint32_t fw2sw_info : 32;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define TX_QUEUE_EXTENSION_FRAME_CTL_OFFSET 0x0000000000000000
|
||||
#define TX_QUEUE_EXTENSION_FRAME_CTL_LSB 0
|
||||
#define TX_QUEUE_EXTENSION_FRAME_CTL_MSB 15
|
||||
#define TX_QUEUE_EXTENSION_FRAME_CTL_MASK 0x000000000000ffff
|
||||
|
||||
#define TX_QUEUE_EXTENSION_QOS_CTL_OFFSET 0x0000000000000000
|
||||
#define TX_QUEUE_EXTENSION_QOS_CTL_LSB 16
|
||||
#define TX_QUEUE_EXTENSION_QOS_CTL_MSB 31
|
||||
#define TX_QUEUE_EXTENSION_QOS_CTL_MASK 0x00000000ffff0000
|
||||
|
||||
#define TX_QUEUE_EXTENSION_AMPDU_FLAG_OFFSET 0x0000000000000000
|
||||
#define TX_QUEUE_EXTENSION_AMPDU_FLAG_LSB 32
|
||||
#define TX_QUEUE_EXTENSION_AMPDU_FLAG_MSB 32
|
||||
#define TX_QUEUE_EXTENSION_AMPDU_FLAG_MASK 0x0000000100000000
|
||||
|
||||
#define TX_QUEUE_EXTENSION_TX_NOTIFY_NO_HTC_OVERRIDE_OFFSET 0x0000000000000000
|
||||
#define TX_QUEUE_EXTENSION_TX_NOTIFY_NO_HTC_OVERRIDE_LSB 33
|
||||
#define TX_QUEUE_EXTENSION_TX_NOTIFY_NO_HTC_OVERRIDE_MSB 33
|
||||
#define TX_QUEUE_EXTENSION_TX_NOTIFY_NO_HTC_OVERRIDE_MASK 0x0000000200000000
|
||||
|
||||
#define TX_QUEUE_EXTENSION_RESERVED_1A_OFFSET 0x0000000000000000
|
||||
#define TX_QUEUE_EXTENSION_RESERVED_1A_LSB 34
|
||||
#define TX_QUEUE_EXTENSION_RESERVED_1A_MSB 40
|
||||
#define TX_QUEUE_EXTENSION_RESERVED_1A_MASK 0x000001fc00000000
|
||||
|
||||
#define TX_QUEUE_EXTENSION_CHECKSUM_TSO_DISABLE_FOR_FRAG_OFFSET 0x0000000000000000
|
||||
#define TX_QUEUE_EXTENSION_CHECKSUM_TSO_DISABLE_FOR_FRAG_LSB 41
|
||||
#define TX_QUEUE_EXTENSION_CHECKSUM_TSO_DISABLE_FOR_FRAG_MSB 41
|
||||
#define TX_QUEUE_EXTENSION_CHECKSUM_TSO_DISABLE_FOR_FRAG_MASK 0x0000020000000000
|
||||
|
||||
#define TX_QUEUE_EXTENSION_KEY_ID_OFFSET 0x0000000000000000
|
||||
#define TX_QUEUE_EXTENSION_KEY_ID_LSB 42
|
||||
#define TX_QUEUE_EXTENSION_KEY_ID_MSB 49
|
||||
#define TX_QUEUE_EXTENSION_KEY_ID_MASK 0x0003fc0000000000
|
||||
|
||||
#define TX_QUEUE_EXTENSION_QOS_BUF_STATE_OVERWRITE_OFFSET 0x0000000000000000
|
||||
#define TX_QUEUE_EXTENSION_QOS_BUF_STATE_OVERWRITE_LSB 50
|
||||
#define TX_QUEUE_EXTENSION_QOS_BUF_STATE_OVERWRITE_MSB 50
|
||||
#define TX_QUEUE_EXTENSION_QOS_BUF_STATE_OVERWRITE_MASK 0x0004000000000000
|
||||
|
||||
#define TX_QUEUE_EXTENSION_BUF_STATE_STA_ID_OFFSET 0x0000000000000000
|
||||
#define TX_QUEUE_EXTENSION_BUF_STATE_STA_ID_LSB 51
|
||||
#define TX_QUEUE_EXTENSION_BUF_STATE_STA_ID_MSB 51
|
||||
#define TX_QUEUE_EXTENSION_BUF_STATE_STA_ID_MASK 0x0008000000000000
|
||||
|
||||
#define TX_QUEUE_EXTENSION_BUF_STATE_SOURCE_OFFSET 0x0000000000000000
|
||||
#define TX_QUEUE_EXTENSION_BUF_STATE_SOURCE_LSB 52
|
||||
#define TX_QUEUE_EXTENSION_BUF_STATE_SOURCE_MSB 52
|
||||
#define TX_QUEUE_EXTENSION_BUF_STATE_SOURCE_MASK 0x0010000000000000
|
||||
|
||||
#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_ENABLE_OFFSET 0x0000000000000000
|
||||
#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_ENABLE_LSB 53
|
||||
#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_ENABLE_MSB 53
|
||||
#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_ENABLE_MASK 0x0020000000000000
|
||||
|
||||
#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_OFFSET 0x0000000000000000
|
||||
#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_LSB 54
|
||||
#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_MSB 57
|
||||
#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_MASK 0x03c0000000000000
|
||||
|
||||
#define TX_QUEUE_EXTENSION_RESERVED_1B_OFFSET 0x0000000000000000
|
||||
#define TX_QUEUE_EXTENSION_RESERVED_1B_LSB 58
|
||||
#define TX_QUEUE_EXTENSION_RESERVED_1B_MSB 63
|
||||
#define TX_QUEUE_EXTENSION_RESERVED_1B_MASK 0xfc00000000000000
|
||||
|
||||
#define TX_QUEUE_EXTENSION_UL_HEADROOM_INSERTION_ENABLE_OFFSET 0x0000000000000008
|
||||
#define TX_QUEUE_EXTENSION_UL_HEADROOM_INSERTION_ENABLE_LSB 0
|
||||
#define TX_QUEUE_EXTENSION_UL_HEADROOM_INSERTION_ENABLE_MSB 0
|
||||
#define TX_QUEUE_EXTENSION_UL_HEADROOM_INSERTION_ENABLE_MASK 0x0000000000000001
|
||||
|
||||
#define TX_QUEUE_EXTENSION_UL_HEADROOM_OFFSET_OFFSET 0x0000000000000008
|
||||
#define TX_QUEUE_EXTENSION_UL_HEADROOM_OFFSET_LSB 1
|
||||
#define TX_QUEUE_EXTENSION_UL_HEADROOM_OFFSET_MSB 5
|
||||
#define TX_QUEUE_EXTENSION_UL_HEADROOM_OFFSET_MASK 0x000000000000003e
|
||||
|
||||
#define TX_QUEUE_EXTENSION_BQRP_INSERTION_ENABLE_OFFSET 0x0000000000000008
|
||||
#define TX_QUEUE_EXTENSION_BQRP_INSERTION_ENABLE_LSB 6
|
||||
#define TX_QUEUE_EXTENSION_BQRP_INSERTION_ENABLE_MSB 6
|
||||
#define TX_QUEUE_EXTENSION_BQRP_INSERTION_ENABLE_MASK 0x0000000000000040
|
||||
|
||||
#define TX_QUEUE_EXTENSION_BQRP_OFFSET_OFFSET 0x0000000000000008
|
||||
#define TX_QUEUE_EXTENSION_BQRP_OFFSET_LSB 7
|
||||
#define TX_QUEUE_EXTENSION_BQRP_OFFSET_MSB 11
|
||||
#define TX_QUEUE_EXTENSION_BQRP_OFFSET_MASK 0x0000000000000f80
|
||||
|
||||
#define TX_QUEUE_EXTENSION_UL_HEADROOM_RSVD_7_6_OFFSET 0x0000000000000008
|
||||
#define TX_QUEUE_EXTENSION_UL_HEADROOM_RSVD_7_6_LSB 12
|
||||
#define TX_QUEUE_EXTENSION_UL_HEADROOM_RSVD_7_6_MSB 13
|
||||
#define TX_QUEUE_EXTENSION_UL_HEADROOM_RSVD_7_6_MASK 0x0000000000003000
|
||||
|
||||
#define TX_QUEUE_EXTENSION_BQR_RSVD_9_8_OFFSET 0x0000000000000008
|
||||
#define TX_QUEUE_EXTENSION_BQR_RSVD_9_8_LSB 14
|
||||
#define TX_QUEUE_EXTENSION_BQR_RSVD_9_8_MSB 15
|
||||
#define TX_QUEUE_EXTENSION_BQR_RSVD_9_8_MASK 0x000000000000c000
|
||||
|
||||
#define TX_QUEUE_EXTENSION_BASE_PN_63_48_OFFSET 0x0000000000000008
|
||||
#define TX_QUEUE_EXTENSION_BASE_PN_63_48_LSB 16
|
||||
#define TX_QUEUE_EXTENSION_BASE_PN_63_48_MSB 31
|
||||
#define TX_QUEUE_EXTENSION_BASE_PN_63_48_MASK 0x00000000ffff0000
|
||||
|
||||
#define TX_QUEUE_EXTENSION_BASE_PN_95_64_OFFSET 0x0000000000000008
|
||||
#define TX_QUEUE_EXTENSION_BASE_PN_95_64_LSB 32
|
||||
#define TX_QUEUE_EXTENSION_BASE_PN_95_64_MSB 63
|
||||
#define TX_QUEUE_EXTENSION_BASE_PN_95_64_MASK 0xffffffff00000000
|
||||
|
||||
#define TX_QUEUE_EXTENSION_BASE_PN_127_96_OFFSET 0x0000000000000010
|
||||
#define TX_QUEUE_EXTENSION_BASE_PN_127_96_LSB 0
|
||||
#define TX_QUEUE_EXTENSION_BASE_PN_127_96_MSB 31
|
||||
#define TX_QUEUE_EXTENSION_BASE_PN_127_96_MASK 0x00000000ffffffff
|
||||
|
||||
#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW20_OFFSET 0x0000000000000010
|
||||
#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW20_LSB 32
|
||||
#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW20_MSB 63
|
||||
#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW20_MASK 0xffffffff00000000
|
||||
|
||||
#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW40_OFFSET 0x0000000000000018
|
||||
#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW40_LSB 0
|
||||
#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW40_MSB 31
|
||||
#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW40_MASK 0x00000000ffffffff
|
||||
|
||||
#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW80_OFFSET 0x0000000000000018
|
||||
#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW80_LSB 32
|
||||
#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW80_MSB 63
|
||||
#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW80_MASK 0xffffffff00000000
|
||||
|
||||
#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW160_OFFSET 0x0000000000000020
|
||||
#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW160_LSB 0
|
||||
#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW160_MSB 31
|
||||
#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW160_MASK 0x00000000ffffffff
|
||||
|
||||
#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_MASK_OFFSET 0x0000000000000020
|
||||
#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_MASK_LSB 32
|
||||
#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_MASK_MSB 63
|
||||
#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_MASK_MASK 0xffffffff00000000
|
||||
|
||||
#define TX_QUEUE_EXTENSION_CAS_CONTROL_INFO_OFFSET 0x0000000000000028
|
||||
#define TX_QUEUE_EXTENSION_CAS_CONTROL_INFO_LSB 0
|
||||
#define TX_QUEUE_EXTENSION_CAS_CONTROL_INFO_MSB 7
|
||||
#define TX_QUEUE_EXTENSION_CAS_CONTROL_INFO_MASK 0x00000000000000ff
|
||||
|
||||
#define TX_QUEUE_EXTENSION_CAS_OFFSET_OFFSET 0x0000000000000028
|
||||
#define TX_QUEUE_EXTENSION_CAS_OFFSET_LSB 8
|
||||
#define TX_QUEUE_EXTENSION_CAS_OFFSET_MSB 12
|
||||
#define TX_QUEUE_EXTENSION_CAS_OFFSET_MASK 0x0000000000001f00
|
||||
|
||||
#define TX_QUEUE_EXTENSION_CAS_INSERTION_ENABLE_OFFSET 0x0000000000000028
|
||||
#define TX_QUEUE_EXTENSION_CAS_INSERTION_ENABLE_LSB 13
|
||||
#define TX_QUEUE_EXTENSION_CAS_INSERTION_ENABLE_MSB 13
|
||||
#define TX_QUEUE_EXTENSION_CAS_INSERTION_ENABLE_MASK 0x0000000000002000
|
||||
|
||||
#define TX_QUEUE_EXTENSION_RESERVED_10A_OFFSET 0x0000000000000028
|
||||
#define TX_QUEUE_EXTENSION_RESERVED_10A_LSB 14
|
||||
#define TX_QUEUE_EXTENSION_RESERVED_10A_MSB 15
|
||||
#define TX_QUEUE_EXTENSION_RESERVED_10A_MASK 0x000000000000c000
|
||||
|
||||
#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_SRP_OFFSET 0x0000000000000028
|
||||
#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_SRP_LSB 16
|
||||
#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_SRP_MSB 19
|
||||
#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_SRP_MASK 0x00000000000f0000
|
||||
|
||||
#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_BSRP_OFFSET 0x0000000000000028
|
||||
#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_BSRP_LSB 20
|
||||
#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_BSRP_MSB 23
|
||||
#define TX_QUEUE_EXTENSION_HT_CONTROL_OVERWRITE_SOURCE_FOR_BSRP_MASK 0x0000000000f00000
|
||||
|
||||
#define TX_QUEUE_EXTENSION_RESERVED_10B_OFFSET 0x0000000000000028
|
||||
#define TX_QUEUE_EXTENSION_RESERVED_10B_LSB 24
|
||||
#define TX_QUEUE_EXTENSION_RESERVED_10B_MSB 29
|
||||
#define TX_QUEUE_EXTENSION_RESERVED_10B_MASK 0x000000003f000000
|
||||
|
||||
#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_EN_OFFSET 0x0000000000000028
|
||||
#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_EN_LSB 30
|
||||
#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_EN_MSB 30
|
||||
#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_EN_MASK 0x0000000040000000
|
||||
|
||||
#define TX_QUEUE_EXTENSION_BAR_SSN_OVERWRITE_ENABLE_OFFSET 0x0000000000000028
|
||||
#define TX_QUEUE_EXTENSION_BAR_SSN_OVERWRITE_ENABLE_LSB 31
|
||||
#define TX_QUEUE_EXTENSION_BAR_SSN_OVERWRITE_ENABLE_MSB 31
|
||||
#define TX_QUEUE_EXTENSION_BAR_SSN_OVERWRITE_ENABLE_MASK 0x0000000080000000
|
||||
|
||||
#define TX_QUEUE_EXTENSION_BAR_SSN_OFFSET_OFFSET 0x0000000000000028
|
||||
#define TX_QUEUE_EXTENSION_BAR_SSN_OFFSET_LSB 32
|
||||
#define TX_QUEUE_EXTENSION_BAR_SSN_OFFSET_MSB 43
|
||||
#define TX_QUEUE_EXTENSION_BAR_SSN_OFFSET_MASK 0x00000fff00000000
|
||||
|
||||
#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_VAL_OFFSET 0x0000000000000028
|
||||
#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_VAL_LSB 44
|
||||
#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_VAL_MSB 52
|
||||
#define TX_QUEUE_EXTENSION_MPDU_HDR_LEN_OVERRIDE_VAL_MASK 0x001ff00000000000
|
||||
|
||||
#define TX_QUEUE_EXTENSION_RESERVED_11A_OFFSET 0x0000000000000028
|
||||
#define TX_QUEUE_EXTENSION_RESERVED_11A_LSB 53
|
||||
#define TX_QUEUE_EXTENSION_RESERVED_11A_MSB 63
|
||||
#define TX_QUEUE_EXTENSION_RESERVED_11A_MASK 0xffe0000000000000
|
||||
|
||||
#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW320_OFFSET 0x0000000000000030
|
||||
#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW320_LSB 0
|
||||
#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW320_MSB 31
|
||||
#define TX_QUEUE_EXTENSION_HT_CONTROL_FIELD_BW320_MASK 0x00000000ffffffff
|
||||
|
||||
#define TX_QUEUE_EXTENSION_FW2SW_INFO_OFFSET 0x0000000000000030
|
||||
#define TX_QUEUE_EXTENSION_FW2SW_INFO_LSB 32
|
||||
#define TX_QUEUE_EXTENSION_FW2SW_INFO_MSB 63
|
||||
#define TX_QUEUE_EXTENSION_FW2SW_INFO_MASK 0xffffffff00000000
|
||||
|
||||
#endif
|
||||
280
hw/kiwi/v2/tx_raw_or_native_frame_setup.h
Normal file
280
hw/kiwi/v2/tx_raw_or_native_frame_setup.h
Normal file
|
|
@ -0,0 +1,280 @@
|
|||
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
#ifndef _TX_RAW_OR_NATIVE_FRAME_SETUP_H_
|
||||
#define _TX_RAW_OR_NATIVE_FRAME_SETUP_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#define NUM_OF_DWORDS_TX_RAW_OR_NATIVE_FRAME_SETUP 2
|
||||
|
||||
#define NUM_OF_QWORDS_TX_RAW_OR_NATIVE_FRAME_SETUP 1
|
||||
|
||||
struct tx_raw_or_native_frame_setup {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t fc_to_ds_mask : 1,
|
||||
fc_from_ds_mask : 1,
|
||||
fc_more_frag_mask : 1,
|
||||
fc_retry_mask : 1,
|
||||
fc_pwr_mgt_mask : 1,
|
||||
fc_more_data_mask : 1,
|
||||
fc_prot_frame_mask : 1,
|
||||
fc_order_mask : 1,
|
||||
duration_field_mask : 1,
|
||||
sequence_control_mask : 1,
|
||||
qc_tid_mask : 1,
|
||||
qc_eosp_mask : 1,
|
||||
qc_ack_policy_mask : 1,
|
||||
qc_amsdu_mask : 1,
|
||||
reserved_0a : 1,
|
||||
qc_15to8_mask : 1,
|
||||
iv_mask : 1,
|
||||
fc_to_ds_setting : 1,
|
||||
fc_from_ds_setting : 1,
|
||||
fc_more_frag_setting : 1,
|
||||
fc_retry_setting : 2,
|
||||
fc_pwr_mgt_setting : 1,
|
||||
fc_more_data_setting : 2,
|
||||
fc_prot_frame_setting : 2,
|
||||
fc_order_setting : 1,
|
||||
qc_tid_setting : 4;
|
||||
uint32_t qc_eosp_setting : 2,
|
||||
qc_ack_policy_setting : 2,
|
||||
qc_amsdu_setting : 1,
|
||||
qc_15to8_setting : 8,
|
||||
mlo_addr_override : 1,
|
||||
mlo_ignore_addr3_override : 1,
|
||||
sequence_control_source : 1,
|
||||
fragment_number : 4,
|
||||
sequence_number : 12;
|
||||
#else
|
||||
uint32_t qc_tid_setting : 4,
|
||||
fc_order_setting : 1,
|
||||
fc_prot_frame_setting : 2,
|
||||
fc_more_data_setting : 2,
|
||||
fc_pwr_mgt_setting : 1,
|
||||
fc_retry_setting : 2,
|
||||
fc_more_frag_setting : 1,
|
||||
fc_from_ds_setting : 1,
|
||||
fc_to_ds_setting : 1,
|
||||
iv_mask : 1,
|
||||
qc_15to8_mask : 1,
|
||||
reserved_0a : 1,
|
||||
qc_amsdu_mask : 1,
|
||||
qc_ack_policy_mask : 1,
|
||||
qc_eosp_mask : 1,
|
||||
qc_tid_mask : 1,
|
||||
sequence_control_mask : 1,
|
||||
duration_field_mask : 1,
|
||||
fc_order_mask : 1,
|
||||
fc_prot_frame_mask : 1,
|
||||
fc_more_data_mask : 1,
|
||||
fc_pwr_mgt_mask : 1,
|
||||
fc_retry_mask : 1,
|
||||
fc_more_frag_mask : 1,
|
||||
fc_from_ds_mask : 1,
|
||||
fc_to_ds_mask : 1;
|
||||
uint32_t sequence_number : 12,
|
||||
fragment_number : 4,
|
||||
sequence_control_source : 1,
|
||||
mlo_ignore_addr3_override : 1,
|
||||
mlo_addr_override : 1,
|
||||
qc_15to8_setting : 8,
|
||||
qc_amsdu_setting : 1,
|
||||
qc_ack_policy_setting : 2,
|
||||
qc_eosp_setting : 2;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_MASK_OFFSET 0x0000000000000000
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_MASK_LSB 0
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_MASK_MSB 0
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_MASK_MASK 0x0000000000000001
|
||||
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_MASK_OFFSET 0x0000000000000000
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_MASK_LSB 1
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_MASK_MSB 1
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_MASK_MASK 0x0000000000000002
|
||||
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_MASK_OFFSET 0x0000000000000000
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_MASK_LSB 2
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_MASK_MSB 2
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_MASK_MASK 0x0000000000000004
|
||||
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_MASK_OFFSET 0x0000000000000000
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_MASK_LSB 3
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_MASK_MSB 3
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_MASK_MASK 0x0000000000000008
|
||||
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_MASK_OFFSET 0x0000000000000000
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_MASK_LSB 4
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_MASK_MSB 4
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_MASK_MASK 0x0000000000000010
|
||||
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_MASK_OFFSET 0x0000000000000000
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_MASK_LSB 5
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_MASK_MSB 5
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_MASK_MASK 0x0000000000000020
|
||||
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_MASK_OFFSET 0x0000000000000000
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_MASK_LSB 6
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_MASK_MSB 6
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_MASK_MASK 0x0000000000000040
|
||||
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_MASK_OFFSET 0x0000000000000000
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_MASK_LSB 7
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_MASK_MSB 7
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_MASK_MASK 0x0000000000000080
|
||||
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_DURATION_FIELD_MASK_OFFSET 0x0000000000000000
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_DURATION_FIELD_MASK_LSB 8
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_DURATION_FIELD_MASK_MSB 8
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_DURATION_FIELD_MASK_MASK 0x0000000000000100
|
||||
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_MASK_OFFSET 0x0000000000000000
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_MASK_LSB 9
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_MASK_MSB 9
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_MASK_MASK 0x0000000000000200
|
||||
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_MASK_OFFSET 0x0000000000000000
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_MASK_LSB 10
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_MASK_MSB 10
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_MASK_MASK 0x0000000000000400
|
||||
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_MASK_OFFSET 0x0000000000000000
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_MASK_LSB 11
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_MASK_MSB 11
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_MASK_MASK 0x0000000000000800
|
||||
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_MASK_OFFSET 0x0000000000000000
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_MASK_LSB 12
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_MASK_MSB 12
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_MASK_MASK 0x0000000000001000
|
||||
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_MASK_OFFSET 0x0000000000000000
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_MASK_LSB 13
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_MASK_MSB 13
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_MASK_MASK 0x0000000000002000
|
||||
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_RESERVED_0A_OFFSET 0x0000000000000000
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_RESERVED_0A_LSB 14
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_RESERVED_0A_MSB 14
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_RESERVED_0A_MASK 0x0000000000004000
|
||||
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_MASK_OFFSET 0x0000000000000000
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_MASK_LSB 15
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_MASK_MSB 15
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_MASK_MASK 0x0000000000008000
|
||||
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_IV_MASK_OFFSET 0x0000000000000000
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_IV_MASK_LSB 16
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_IV_MASK_MSB 16
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_IV_MASK_MASK 0x0000000000010000
|
||||
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_SETTING_OFFSET 0x0000000000000000
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_SETTING_LSB 17
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_SETTING_MSB 17
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_TO_DS_SETTING_MASK 0x0000000000020000
|
||||
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_SETTING_OFFSET 0x0000000000000000
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_SETTING_LSB 18
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_SETTING_MSB 18
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_FROM_DS_SETTING_MASK 0x0000000000040000
|
||||
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_SETTING_OFFSET 0x0000000000000000
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_SETTING_LSB 19
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_SETTING_MSB 19
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_FRAG_SETTING_MASK 0x0000000000080000
|
||||
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_SETTING_OFFSET 0x0000000000000000
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_SETTING_LSB 20
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_SETTING_MSB 21
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_RETRY_SETTING_MASK 0x0000000000300000
|
||||
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_SETTING_OFFSET 0x0000000000000000
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_SETTING_LSB 22
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_SETTING_MSB 22
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PWR_MGT_SETTING_MASK 0x0000000000400000
|
||||
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_SETTING_OFFSET 0x0000000000000000
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_SETTING_LSB 23
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_SETTING_MSB 24
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_MORE_DATA_SETTING_MASK 0x0000000001800000
|
||||
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_SETTING_OFFSET 0x0000000000000000
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_SETTING_LSB 25
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_SETTING_MSB 26
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_PROT_FRAME_SETTING_MASK 0x0000000006000000
|
||||
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_SETTING_OFFSET 0x0000000000000000
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_SETTING_LSB 27
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_SETTING_MSB 27
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_FC_ORDER_SETTING_MASK 0x0000000008000000
|
||||
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_SETTING_OFFSET 0x0000000000000000
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_SETTING_LSB 28
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_SETTING_MSB 31
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_TID_SETTING_MASK 0x00000000f0000000
|
||||
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_SETTING_OFFSET 0x0000000000000000
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_SETTING_LSB 32
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_SETTING_MSB 33
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_EOSP_SETTING_MASK 0x0000000300000000
|
||||
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_SETTING_OFFSET 0x0000000000000000
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_SETTING_LSB 34
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_SETTING_MSB 35
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_ACK_POLICY_SETTING_MASK 0x0000000c00000000
|
||||
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_SETTING_OFFSET 0x0000000000000000
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_SETTING_LSB 36
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_SETTING_MSB 36
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_AMSDU_SETTING_MASK 0x0000001000000000
|
||||
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_SETTING_OFFSET 0x0000000000000000
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_SETTING_LSB 37
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_SETTING_MSB 44
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_QC_15TO8_SETTING_MASK 0x00001fe000000000
|
||||
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_ADDR_OVERRIDE_OFFSET 0x0000000000000000
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_ADDR_OVERRIDE_LSB 45
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_ADDR_OVERRIDE_MSB 45
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_ADDR_OVERRIDE_MASK 0x0000200000000000
|
||||
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_IGNORE_ADDR3_OVERRIDE_OFFSET 0x0000000000000000
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_IGNORE_ADDR3_OVERRIDE_LSB 46
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_IGNORE_ADDR3_OVERRIDE_MSB 46
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_MLO_IGNORE_ADDR3_OVERRIDE_MASK 0x0000400000000000
|
||||
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_SOURCE_OFFSET 0x0000000000000000
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_SOURCE_LSB 47
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_SOURCE_MSB 47
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_CONTROL_SOURCE_MASK 0x0000800000000000
|
||||
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_FRAGMENT_NUMBER_OFFSET 0x0000000000000000
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_FRAGMENT_NUMBER_LSB 48
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_FRAGMENT_NUMBER_MSB 51
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_FRAGMENT_NUMBER_MASK 0x000f000000000000
|
||||
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_NUMBER_OFFSET 0x0000000000000000
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_NUMBER_LSB 52
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_NUMBER_MSB 63
|
||||
#define TX_RAW_OR_NATIVE_FRAME_SETUP_SEQUENCE_NUMBER_MASK 0xfff0000000000000
|
||||
|
||||
#endif
|
||||
54
hw/kiwi/v2/txpcu_buffer_basics.h
Normal file
54
hw/kiwi/v2/txpcu_buffer_basics.h
Normal file
|
|
@ -0,0 +1,54 @@
|
|||
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
#ifndef _TXPCU_BUFFER_BASICS_H_
|
||||
#define _TXPCU_BUFFER_BASICS_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#define NUM_OF_DWORDS_TXPCU_BUFFER_BASICS 1
|
||||
|
||||
struct txpcu_buffer_basics {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t available_memory : 8,
|
||||
partial_tx_data_tlv_count : 8,
|
||||
tx_data_tlv_count : 16;
|
||||
#else
|
||||
uint32_t tx_data_tlv_count : 16,
|
||||
partial_tx_data_tlv_count : 8,
|
||||
available_memory : 8;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define TXPCU_BUFFER_BASICS_AVAILABLE_MEMORY_OFFSET 0x00000000
|
||||
#define TXPCU_BUFFER_BASICS_AVAILABLE_MEMORY_LSB 0
|
||||
#define TXPCU_BUFFER_BASICS_AVAILABLE_MEMORY_MSB 7
|
||||
#define TXPCU_BUFFER_BASICS_AVAILABLE_MEMORY_MASK 0x000000ff
|
||||
|
||||
#define TXPCU_BUFFER_BASICS_PARTIAL_TX_DATA_TLV_COUNT_OFFSET 0x00000000
|
||||
#define TXPCU_BUFFER_BASICS_PARTIAL_TX_DATA_TLV_COUNT_LSB 8
|
||||
#define TXPCU_BUFFER_BASICS_PARTIAL_TX_DATA_TLV_COUNT_MSB 15
|
||||
#define TXPCU_BUFFER_BASICS_PARTIAL_TX_DATA_TLV_COUNT_MASK 0x0000ff00
|
||||
|
||||
#define TXPCU_BUFFER_BASICS_TX_DATA_TLV_COUNT_OFFSET 0x00000000
|
||||
#define TXPCU_BUFFER_BASICS_TX_DATA_TLV_COUNT_LSB 16
|
||||
#define TXPCU_BUFFER_BASICS_TX_DATA_TLV_COUNT_MSB 31
|
||||
#define TXPCU_BUFFER_BASICS_TX_DATA_TLV_COUNT_MASK 0xffff0000
|
||||
|
||||
#endif
|
||||
74
hw/kiwi/v2/txpcu_buffer_status.h
Normal file
74
hw/kiwi/v2/txpcu_buffer_status.h
Normal file
|
|
@ -0,0 +1,74 @@
|
|||
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
#ifndef _TXPCU_BUFFER_STATUS_H_
|
||||
#define _TXPCU_BUFFER_STATUS_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#include "txpcu_buffer_basics.h"
|
||||
#define NUM_OF_DWORDS_TXPCU_BUFFER_STATUS 2
|
||||
|
||||
#define NUM_OF_QWORDS_TXPCU_BUFFER_STATUS 1
|
||||
|
||||
struct txpcu_buffer_status {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
struct txpcu_buffer_basics txpcu_basix_buffer_info;
|
||||
uint32_t reserved : 15,
|
||||
msdu_end : 1,
|
||||
tx_data_sync_value : 16;
|
||||
#else
|
||||
struct txpcu_buffer_basics txpcu_basix_buffer_info;
|
||||
uint32_t tx_data_sync_value : 16,
|
||||
msdu_end : 1,
|
||||
reserved : 15;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_AVAILABLE_MEMORY_OFFSET 0x0000000000000000
|
||||
#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_AVAILABLE_MEMORY_LSB 0
|
||||
#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_AVAILABLE_MEMORY_MSB 7
|
||||
#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_AVAILABLE_MEMORY_MASK 0x00000000000000ff
|
||||
|
||||
#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_OFFSET 0x0000000000000000
|
||||
#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_LSB 8
|
||||
#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_MSB 15
|
||||
#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_MASK 0x000000000000ff00
|
||||
|
||||
#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_TX_DATA_TLV_COUNT_OFFSET 0x0000000000000000
|
||||
#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_TX_DATA_TLV_COUNT_LSB 16
|
||||
#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_TX_DATA_TLV_COUNT_MSB 31
|
||||
#define TXPCU_BUFFER_STATUS_TXPCU_BASIX_BUFFER_INFO_TX_DATA_TLV_COUNT_MASK 0x00000000ffff0000
|
||||
|
||||
#define TXPCU_BUFFER_STATUS_RESERVED_OFFSET 0x0000000000000000
|
||||
#define TXPCU_BUFFER_STATUS_RESERVED_LSB 32
|
||||
#define TXPCU_BUFFER_STATUS_RESERVED_MSB 46
|
||||
#define TXPCU_BUFFER_STATUS_RESERVED_MASK 0x00007fff00000000
|
||||
|
||||
#define TXPCU_BUFFER_STATUS_MSDU_END_OFFSET 0x0000000000000000
|
||||
#define TXPCU_BUFFER_STATUS_MSDU_END_LSB 47
|
||||
#define TXPCU_BUFFER_STATUS_MSDU_END_MSB 47
|
||||
#define TXPCU_BUFFER_STATUS_MSDU_END_MASK 0x0000800000000000
|
||||
|
||||
#define TXPCU_BUFFER_STATUS_TX_DATA_SYNC_VALUE_OFFSET 0x0000000000000000
|
||||
#define TXPCU_BUFFER_STATUS_TX_DATA_SYNC_VALUE_LSB 48
|
||||
#define TXPCU_BUFFER_STATUS_TX_DATA_SYNC_VALUE_MSB 63
|
||||
#define TXPCU_BUFFER_STATUS_TX_DATA_SYNC_VALUE_MASK 0xffff000000000000
|
||||
|
||||
#endif
|
||||
81
hw/kiwi/v2/txpcu_user_buffer_status.h
Normal file
81
hw/kiwi/v2/txpcu_user_buffer_status.h
Normal file
|
|
@ -0,0 +1,81 @@
|
|||
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
#ifndef _TXPCU_USER_BUFFER_STATUS_H_
|
||||
#define _TXPCU_USER_BUFFER_STATUS_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#include "txpcu_buffer_basics.h"
|
||||
#define NUM_OF_DWORDS_TXPCU_USER_BUFFER_STATUS 2
|
||||
|
||||
#define NUM_OF_QWORDS_TXPCU_USER_BUFFER_STATUS 1
|
||||
|
||||
struct txpcu_user_buffer_status {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
struct txpcu_buffer_basics txpcu_basic_buffer_info;
|
||||
uint32_t stored_word_count_user : 14,
|
||||
reserved_1a : 1,
|
||||
msdu_end : 1,
|
||||
tx_data_sync_value : 16;
|
||||
#else
|
||||
struct txpcu_buffer_basics txpcu_basic_buffer_info;
|
||||
uint32_t tx_data_sync_value : 16,
|
||||
msdu_end : 1,
|
||||
reserved_1a : 1,
|
||||
stored_word_count_user : 14;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_AVAILABLE_MEMORY_OFFSET 0x0000000000000000
|
||||
#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_AVAILABLE_MEMORY_LSB 0
|
||||
#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_AVAILABLE_MEMORY_MSB 7
|
||||
#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_AVAILABLE_MEMORY_MASK 0x00000000000000ff
|
||||
|
||||
#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_OFFSET 0x0000000000000000
|
||||
#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_LSB 8
|
||||
#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_MSB 15
|
||||
#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_PARTIAL_TX_DATA_TLV_COUNT_MASK 0x000000000000ff00
|
||||
|
||||
#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_TX_DATA_TLV_COUNT_OFFSET 0x0000000000000000
|
||||
#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_TX_DATA_TLV_COUNT_LSB 16
|
||||
#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_TX_DATA_TLV_COUNT_MSB 31
|
||||
#define TXPCU_USER_BUFFER_STATUS_TXPCU_BASIC_BUFFER_INFO_TX_DATA_TLV_COUNT_MASK 0x00000000ffff0000
|
||||
|
||||
#define TXPCU_USER_BUFFER_STATUS_STORED_WORD_COUNT_USER_OFFSET 0x0000000000000000
|
||||
#define TXPCU_USER_BUFFER_STATUS_STORED_WORD_COUNT_USER_LSB 32
|
||||
#define TXPCU_USER_BUFFER_STATUS_STORED_WORD_COUNT_USER_MSB 45
|
||||
#define TXPCU_USER_BUFFER_STATUS_STORED_WORD_COUNT_USER_MASK 0x00003fff00000000
|
||||
|
||||
#define TXPCU_USER_BUFFER_STATUS_RESERVED_1A_OFFSET 0x0000000000000000
|
||||
#define TXPCU_USER_BUFFER_STATUS_RESERVED_1A_LSB 46
|
||||
#define TXPCU_USER_BUFFER_STATUS_RESERVED_1A_MSB 46
|
||||
#define TXPCU_USER_BUFFER_STATUS_RESERVED_1A_MASK 0x0000400000000000
|
||||
|
||||
#define TXPCU_USER_BUFFER_STATUS_MSDU_END_OFFSET 0x0000000000000000
|
||||
#define TXPCU_USER_BUFFER_STATUS_MSDU_END_LSB 47
|
||||
#define TXPCU_USER_BUFFER_STATUS_MSDU_END_MSB 47
|
||||
#define TXPCU_USER_BUFFER_STATUS_MSDU_END_MASK 0x0000800000000000
|
||||
|
||||
#define TXPCU_USER_BUFFER_STATUS_TX_DATA_SYNC_VALUE_OFFSET 0x0000000000000000
|
||||
#define TXPCU_USER_BUFFER_STATUS_TX_DATA_SYNC_VALUE_LSB 48
|
||||
#define TXPCU_USER_BUFFER_STATUS_TX_DATA_SYNC_VALUE_MSB 63
|
||||
#define TXPCU_USER_BUFFER_STATUS_TX_DATA_SYNC_VALUE_MASK 0xffff000000000000
|
||||
|
||||
#endif
|
||||
173
hw/kiwi/v2/u_sig_eht_su_mu_info.h
Normal file
173
hw/kiwi/v2/u_sig_eht_su_mu_info.h
Normal file
|
|
@ -0,0 +1,173 @@
|
|||
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
#ifndef _U_SIG_EHT_SU_MU_INFO_H_
|
||||
#define _U_SIG_EHT_SU_MU_INFO_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#define NUM_OF_DWORDS_U_SIG_EHT_SU_MU_INFO 2
|
||||
|
||||
struct u_sig_eht_su_mu_info {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t phy_version : 3,
|
||||
transmit_bw : 3,
|
||||
dl_ul_flag : 1,
|
||||
bss_color_id : 6,
|
||||
txop_duration : 7,
|
||||
disregard_0a : 5,
|
||||
validate_0b : 1,
|
||||
reserved_0c : 6;
|
||||
uint32_t eht_ppdu_sig_cmn_type : 2,
|
||||
validate_1a : 1,
|
||||
punctured_channel_information : 5,
|
||||
validate_1b : 1,
|
||||
mcs_of_eht_sig : 2,
|
||||
num_eht_sig_symbols : 5,
|
||||
crc : 4,
|
||||
tail : 6,
|
||||
dot11ax_su_extended : 1,
|
||||
reserved_1d : 3,
|
||||
rx_ndp : 1,
|
||||
rx_integrity_check_passed : 1;
|
||||
#else
|
||||
uint32_t reserved_0c : 6,
|
||||
validate_0b : 1,
|
||||
disregard_0a : 5,
|
||||
txop_duration : 7,
|
||||
bss_color_id : 6,
|
||||
dl_ul_flag : 1,
|
||||
transmit_bw : 3,
|
||||
phy_version : 3;
|
||||
uint32_t rx_integrity_check_passed : 1,
|
||||
rx_ndp : 1,
|
||||
reserved_1d : 3,
|
||||
dot11ax_su_extended : 1,
|
||||
tail : 6,
|
||||
crc : 4,
|
||||
num_eht_sig_symbols : 5,
|
||||
mcs_of_eht_sig : 2,
|
||||
validate_1b : 1,
|
||||
punctured_channel_information : 5,
|
||||
validate_1a : 1,
|
||||
eht_ppdu_sig_cmn_type : 2;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define U_SIG_EHT_SU_MU_INFO_PHY_VERSION_OFFSET 0x00000000
|
||||
#define U_SIG_EHT_SU_MU_INFO_PHY_VERSION_LSB 0
|
||||
#define U_SIG_EHT_SU_MU_INFO_PHY_VERSION_MSB 2
|
||||
#define U_SIG_EHT_SU_MU_INFO_PHY_VERSION_MASK 0x00000007
|
||||
|
||||
#define U_SIG_EHT_SU_MU_INFO_TRANSMIT_BW_OFFSET 0x00000000
|
||||
#define U_SIG_EHT_SU_MU_INFO_TRANSMIT_BW_LSB 3
|
||||
#define U_SIG_EHT_SU_MU_INFO_TRANSMIT_BW_MSB 5
|
||||
#define U_SIG_EHT_SU_MU_INFO_TRANSMIT_BW_MASK 0x00000038
|
||||
|
||||
#define U_SIG_EHT_SU_MU_INFO_DL_UL_FLAG_OFFSET 0x00000000
|
||||
#define U_SIG_EHT_SU_MU_INFO_DL_UL_FLAG_LSB 6
|
||||
#define U_SIG_EHT_SU_MU_INFO_DL_UL_FLAG_MSB 6
|
||||
#define U_SIG_EHT_SU_MU_INFO_DL_UL_FLAG_MASK 0x00000040
|
||||
|
||||
#define U_SIG_EHT_SU_MU_INFO_BSS_COLOR_ID_OFFSET 0x00000000
|
||||
#define U_SIG_EHT_SU_MU_INFO_BSS_COLOR_ID_LSB 7
|
||||
#define U_SIG_EHT_SU_MU_INFO_BSS_COLOR_ID_MSB 12
|
||||
#define U_SIG_EHT_SU_MU_INFO_BSS_COLOR_ID_MASK 0x00001f80
|
||||
|
||||
#define U_SIG_EHT_SU_MU_INFO_TXOP_DURATION_OFFSET 0x00000000
|
||||
#define U_SIG_EHT_SU_MU_INFO_TXOP_DURATION_LSB 13
|
||||
#define U_SIG_EHT_SU_MU_INFO_TXOP_DURATION_MSB 19
|
||||
#define U_SIG_EHT_SU_MU_INFO_TXOP_DURATION_MASK 0x000fe000
|
||||
|
||||
#define U_SIG_EHT_SU_MU_INFO_DISREGARD_0A_OFFSET 0x00000000
|
||||
#define U_SIG_EHT_SU_MU_INFO_DISREGARD_0A_LSB 20
|
||||
#define U_SIG_EHT_SU_MU_INFO_DISREGARD_0A_MSB 24
|
||||
#define U_SIG_EHT_SU_MU_INFO_DISREGARD_0A_MASK 0x01f00000
|
||||
|
||||
#define U_SIG_EHT_SU_MU_INFO_VALIDATE_0B_OFFSET 0x00000000
|
||||
#define U_SIG_EHT_SU_MU_INFO_VALIDATE_0B_LSB 25
|
||||
#define U_SIG_EHT_SU_MU_INFO_VALIDATE_0B_MSB 25
|
||||
#define U_SIG_EHT_SU_MU_INFO_VALIDATE_0B_MASK 0x02000000
|
||||
|
||||
#define U_SIG_EHT_SU_MU_INFO_RESERVED_0C_OFFSET 0x00000000
|
||||
#define U_SIG_EHT_SU_MU_INFO_RESERVED_0C_LSB 26
|
||||
#define U_SIG_EHT_SU_MU_INFO_RESERVED_0C_MSB 31
|
||||
#define U_SIG_EHT_SU_MU_INFO_RESERVED_0C_MASK 0xfc000000
|
||||
|
||||
#define U_SIG_EHT_SU_MU_INFO_EHT_PPDU_SIG_CMN_TYPE_OFFSET 0x00000004
|
||||
#define U_SIG_EHT_SU_MU_INFO_EHT_PPDU_SIG_CMN_TYPE_LSB 0
|
||||
#define U_SIG_EHT_SU_MU_INFO_EHT_PPDU_SIG_CMN_TYPE_MSB 1
|
||||
#define U_SIG_EHT_SU_MU_INFO_EHT_PPDU_SIG_CMN_TYPE_MASK 0x00000003
|
||||
|
||||
#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1A_OFFSET 0x00000004
|
||||
#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1A_LSB 2
|
||||
#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1A_MSB 2
|
||||
#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1A_MASK 0x00000004
|
||||
|
||||
#define U_SIG_EHT_SU_MU_INFO_PUNCTURED_CHANNEL_INFORMATION_OFFSET 0x00000004
|
||||
#define U_SIG_EHT_SU_MU_INFO_PUNCTURED_CHANNEL_INFORMATION_LSB 3
|
||||
#define U_SIG_EHT_SU_MU_INFO_PUNCTURED_CHANNEL_INFORMATION_MSB 7
|
||||
#define U_SIG_EHT_SU_MU_INFO_PUNCTURED_CHANNEL_INFORMATION_MASK 0x000000f8
|
||||
|
||||
#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1B_OFFSET 0x00000004
|
||||
#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1B_LSB 8
|
||||
#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1B_MSB 8
|
||||
#define U_SIG_EHT_SU_MU_INFO_VALIDATE_1B_MASK 0x00000100
|
||||
|
||||
#define U_SIG_EHT_SU_MU_INFO_MCS_OF_EHT_SIG_OFFSET 0x00000004
|
||||
#define U_SIG_EHT_SU_MU_INFO_MCS_OF_EHT_SIG_LSB 9
|
||||
#define U_SIG_EHT_SU_MU_INFO_MCS_OF_EHT_SIG_MSB 10
|
||||
#define U_SIG_EHT_SU_MU_INFO_MCS_OF_EHT_SIG_MASK 0x00000600
|
||||
|
||||
#define U_SIG_EHT_SU_MU_INFO_NUM_EHT_SIG_SYMBOLS_OFFSET 0x00000004
|
||||
#define U_SIG_EHT_SU_MU_INFO_NUM_EHT_SIG_SYMBOLS_LSB 11
|
||||
#define U_SIG_EHT_SU_MU_INFO_NUM_EHT_SIG_SYMBOLS_MSB 15
|
||||
#define U_SIG_EHT_SU_MU_INFO_NUM_EHT_SIG_SYMBOLS_MASK 0x0000f800
|
||||
|
||||
#define U_SIG_EHT_SU_MU_INFO_CRC_OFFSET 0x00000004
|
||||
#define U_SIG_EHT_SU_MU_INFO_CRC_LSB 16
|
||||
#define U_SIG_EHT_SU_MU_INFO_CRC_MSB 19
|
||||
#define U_SIG_EHT_SU_MU_INFO_CRC_MASK 0x000f0000
|
||||
|
||||
#define U_SIG_EHT_SU_MU_INFO_TAIL_OFFSET 0x00000004
|
||||
#define U_SIG_EHT_SU_MU_INFO_TAIL_LSB 20
|
||||
#define U_SIG_EHT_SU_MU_INFO_TAIL_MSB 25
|
||||
#define U_SIG_EHT_SU_MU_INFO_TAIL_MASK 0x03f00000
|
||||
|
||||
#define U_SIG_EHT_SU_MU_INFO_DOT11AX_SU_EXTENDED_OFFSET 0x00000004
|
||||
#define U_SIG_EHT_SU_MU_INFO_DOT11AX_SU_EXTENDED_LSB 26
|
||||
#define U_SIG_EHT_SU_MU_INFO_DOT11AX_SU_EXTENDED_MSB 26
|
||||
#define U_SIG_EHT_SU_MU_INFO_DOT11AX_SU_EXTENDED_MASK 0x04000000
|
||||
|
||||
#define U_SIG_EHT_SU_MU_INFO_RESERVED_1D_OFFSET 0x00000004
|
||||
#define U_SIG_EHT_SU_MU_INFO_RESERVED_1D_LSB 27
|
||||
#define U_SIG_EHT_SU_MU_INFO_RESERVED_1D_MSB 29
|
||||
#define U_SIG_EHT_SU_MU_INFO_RESERVED_1D_MASK 0x38000000
|
||||
|
||||
#define U_SIG_EHT_SU_MU_INFO_RX_NDP_OFFSET 0x00000004
|
||||
#define U_SIG_EHT_SU_MU_INFO_RX_NDP_LSB 30
|
||||
#define U_SIG_EHT_SU_MU_INFO_RX_NDP_MSB 30
|
||||
#define U_SIG_EHT_SU_MU_INFO_RX_NDP_MASK 0x40000000
|
||||
|
||||
#define U_SIG_EHT_SU_MU_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004
|
||||
#define U_SIG_EHT_SU_MU_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31
|
||||
#define U_SIG_EHT_SU_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31
|
||||
#define U_SIG_EHT_SU_MU_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
|
||||
|
||||
#endif
|
||||
138
hw/kiwi/v2/u_sig_eht_tb_info.h
Normal file
138
hw/kiwi/v2/u_sig_eht_tb_info.h
Normal file
|
|
@ -0,0 +1,138 @@
|
|||
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
#ifndef _U_SIG_EHT_TB_INFO_H_
|
||||
#define _U_SIG_EHT_TB_INFO_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#define NUM_OF_DWORDS_U_SIG_EHT_TB_INFO 2
|
||||
|
||||
struct u_sig_eht_tb_info {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t phy_version : 3,
|
||||
transmit_bw : 3,
|
||||
dl_ul_flag : 1,
|
||||
bss_color_id : 6,
|
||||
txop_duration : 7,
|
||||
disregard_0a : 6,
|
||||
reserved_0c : 6;
|
||||
uint32_t eht_ppdu_sig_cmn_type : 2,
|
||||
validate_1a : 1,
|
||||
spatial_reuse : 8,
|
||||
disregard_1b : 5,
|
||||
crc : 4,
|
||||
tail : 6,
|
||||
reserved_1c : 5,
|
||||
rx_integrity_check_passed : 1;
|
||||
#else
|
||||
uint32_t reserved_0c : 6,
|
||||
disregard_0a : 6,
|
||||
txop_duration : 7,
|
||||
bss_color_id : 6,
|
||||
dl_ul_flag : 1,
|
||||
transmit_bw : 3,
|
||||
phy_version : 3;
|
||||
uint32_t rx_integrity_check_passed : 1,
|
||||
reserved_1c : 5,
|
||||
tail : 6,
|
||||
crc : 4,
|
||||
disregard_1b : 5,
|
||||
spatial_reuse : 8,
|
||||
validate_1a : 1,
|
||||
eht_ppdu_sig_cmn_type : 2;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define U_SIG_EHT_TB_INFO_PHY_VERSION_OFFSET 0x00000000
|
||||
#define U_SIG_EHT_TB_INFO_PHY_VERSION_LSB 0
|
||||
#define U_SIG_EHT_TB_INFO_PHY_VERSION_MSB 2
|
||||
#define U_SIG_EHT_TB_INFO_PHY_VERSION_MASK 0x00000007
|
||||
|
||||
#define U_SIG_EHT_TB_INFO_TRANSMIT_BW_OFFSET 0x00000000
|
||||
#define U_SIG_EHT_TB_INFO_TRANSMIT_BW_LSB 3
|
||||
#define U_SIG_EHT_TB_INFO_TRANSMIT_BW_MSB 5
|
||||
#define U_SIG_EHT_TB_INFO_TRANSMIT_BW_MASK 0x00000038
|
||||
|
||||
#define U_SIG_EHT_TB_INFO_DL_UL_FLAG_OFFSET 0x00000000
|
||||
#define U_SIG_EHT_TB_INFO_DL_UL_FLAG_LSB 6
|
||||
#define U_SIG_EHT_TB_INFO_DL_UL_FLAG_MSB 6
|
||||
#define U_SIG_EHT_TB_INFO_DL_UL_FLAG_MASK 0x00000040
|
||||
|
||||
#define U_SIG_EHT_TB_INFO_BSS_COLOR_ID_OFFSET 0x00000000
|
||||
#define U_SIG_EHT_TB_INFO_BSS_COLOR_ID_LSB 7
|
||||
#define U_SIG_EHT_TB_INFO_BSS_COLOR_ID_MSB 12
|
||||
#define U_SIG_EHT_TB_INFO_BSS_COLOR_ID_MASK 0x00001f80
|
||||
|
||||
#define U_SIG_EHT_TB_INFO_TXOP_DURATION_OFFSET 0x00000000
|
||||
#define U_SIG_EHT_TB_INFO_TXOP_DURATION_LSB 13
|
||||
#define U_SIG_EHT_TB_INFO_TXOP_DURATION_MSB 19
|
||||
#define U_SIG_EHT_TB_INFO_TXOP_DURATION_MASK 0x000fe000
|
||||
|
||||
#define U_SIG_EHT_TB_INFO_DISREGARD_0A_OFFSET 0x00000000
|
||||
#define U_SIG_EHT_TB_INFO_DISREGARD_0A_LSB 20
|
||||
#define U_SIG_EHT_TB_INFO_DISREGARD_0A_MSB 25
|
||||
#define U_SIG_EHT_TB_INFO_DISREGARD_0A_MASK 0x03f00000
|
||||
|
||||
#define U_SIG_EHT_TB_INFO_RESERVED_0C_OFFSET 0x00000000
|
||||
#define U_SIG_EHT_TB_INFO_RESERVED_0C_LSB 26
|
||||
#define U_SIG_EHT_TB_INFO_RESERVED_0C_MSB 31
|
||||
#define U_SIG_EHT_TB_INFO_RESERVED_0C_MASK 0xfc000000
|
||||
|
||||
#define U_SIG_EHT_TB_INFO_EHT_PPDU_SIG_CMN_TYPE_OFFSET 0x00000004
|
||||
#define U_SIG_EHT_TB_INFO_EHT_PPDU_SIG_CMN_TYPE_LSB 0
|
||||
#define U_SIG_EHT_TB_INFO_EHT_PPDU_SIG_CMN_TYPE_MSB 1
|
||||
#define U_SIG_EHT_TB_INFO_EHT_PPDU_SIG_CMN_TYPE_MASK 0x00000003
|
||||
|
||||
#define U_SIG_EHT_TB_INFO_VALIDATE_1A_OFFSET 0x00000004
|
||||
#define U_SIG_EHT_TB_INFO_VALIDATE_1A_LSB 2
|
||||
#define U_SIG_EHT_TB_INFO_VALIDATE_1A_MSB 2
|
||||
#define U_SIG_EHT_TB_INFO_VALIDATE_1A_MASK 0x00000004
|
||||
|
||||
#define U_SIG_EHT_TB_INFO_SPATIAL_REUSE_OFFSET 0x00000004
|
||||
#define U_SIG_EHT_TB_INFO_SPATIAL_REUSE_LSB 3
|
||||
#define U_SIG_EHT_TB_INFO_SPATIAL_REUSE_MSB 10
|
||||
#define U_SIG_EHT_TB_INFO_SPATIAL_REUSE_MASK 0x000007f8
|
||||
|
||||
#define U_SIG_EHT_TB_INFO_DISREGARD_1B_OFFSET 0x00000004
|
||||
#define U_SIG_EHT_TB_INFO_DISREGARD_1B_LSB 11
|
||||
#define U_SIG_EHT_TB_INFO_DISREGARD_1B_MSB 15
|
||||
#define U_SIG_EHT_TB_INFO_DISREGARD_1B_MASK 0x0000f800
|
||||
|
||||
#define U_SIG_EHT_TB_INFO_CRC_OFFSET 0x00000004
|
||||
#define U_SIG_EHT_TB_INFO_CRC_LSB 16
|
||||
#define U_SIG_EHT_TB_INFO_CRC_MSB 19
|
||||
#define U_SIG_EHT_TB_INFO_CRC_MASK 0x000f0000
|
||||
|
||||
#define U_SIG_EHT_TB_INFO_TAIL_OFFSET 0x00000004
|
||||
#define U_SIG_EHT_TB_INFO_TAIL_LSB 20
|
||||
#define U_SIG_EHT_TB_INFO_TAIL_MSB 25
|
||||
#define U_SIG_EHT_TB_INFO_TAIL_MASK 0x03f00000
|
||||
|
||||
#define U_SIG_EHT_TB_INFO_RESERVED_1C_OFFSET 0x00000004
|
||||
#define U_SIG_EHT_TB_INFO_RESERVED_1C_LSB 26
|
||||
#define U_SIG_EHT_TB_INFO_RESERVED_1C_MSB 30
|
||||
#define U_SIG_EHT_TB_INFO_RESERVED_1C_MASK 0x7c000000
|
||||
|
||||
#define U_SIG_EHT_TB_INFO_RX_INTEGRITY_CHECK_PASSED_OFFSET 0x00000004
|
||||
#define U_SIG_EHT_TB_INFO_RX_INTEGRITY_CHECK_PASSED_LSB 31
|
||||
#define U_SIG_EHT_TB_INFO_RX_INTEGRITY_CHECK_PASSED_MSB 31
|
||||
#define U_SIG_EHT_TB_INFO_RX_INTEGRITY_CHECK_PASSED_MASK 0x80000000
|
||||
|
||||
#endif
|
||||
61
hw/kiwi/v2/unallocated_ru_160_info.h
Normal file
61
hw/kiwi/v2/unallocated_ru_160_info.h
Normal file
|
|
@ -0,0 +1,61 @@
|
|||
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
#ifndef _UNALLOCATED_RU_160_INFO_H_
|
||||
#define _UNALLOCATED_RU_160_INFO_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#define NUM_OF_DWORDS_UNALLOCATED_RU_160_INFO 1
|
||||
|
||||
struct unallocated_ru_160_info {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t subband80_0_cc0 : 8,
|
||||
subband80_0_cc1 : 8,
|
||||
subband80_1_cc0 : 8,
|
||||
subband80_1_cc1 : 8;
|
||||
#else
|
||||
uint32_t subband80_1_cc1 : 8,
|
||||
subband80_1_cc0 : 8,
|
||||
subband80_0_cc1 : 8,
|
||||
subband80_0_cc0 : 8;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC0_OFFSET 0x00000000
|
||||
#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC0_LSB 0
|
||||
#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC0_MSB 7
|
||||
#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC0_MASK 0x000000ff
|
||||
|
||||
#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC1_OFFSET 0x00000000
|
||||
#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC1_LSB 8
|
||||
#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC1_MSB 15
|
||||
#define UNALLOCATED_RU_160_INFO_SUBBAND80_0_CC1_MASK 0x0000ff00
|
||||
|
||||
#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC0_OFFSET 0x00000000
|
||||
#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC0_LSB 16
|
||||
#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC0_MSB 23
|
||||
#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC0_MASK 0x00ff0000
|
||||
|
||||
#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC1_OFFSET 0x00000000
|
||||
#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC1_LSB 24
|
||||
#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC1_MSB 31
|
||||
#define UNALLOCATED_RU_160_INFO_SUBBAND80_1_CC1_MASK 0xff000000
|
||||
|
||||
#endif
|
||||
257
hw/kiwi/v2/vht_sig_b_mu160_info.h
Normal file
257
hw/kiwi/v2/vht_sig_b_mu160_info.h
Normal file
|
|
@ -0,0 +1,257 @@
|
|||
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
#ifndef _VHT_SIG_B_MU160_INFO_H_
|
||||
#define _VHT_SIG_B_MU160_INFO_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#define NUM_OF_DWORDS_VHT_SIG_B_MU160_INFO 8
|
||||
|
||||
struct vht_sig_b_mu160_info {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t length : 19,
|
||||
mcs : 4,
|
||||
tail : 6,
|
||||
reserved_0 : 3;
|
||||
uint32_t length_copy_a : 19,
|
||||
mcs_copy_a : 4,
|
||||
tail_copy_a : 6,
|
||||
reserved_1 : 3;
|
||||
uint32_t length_copy_b : 19,
|
||||
mcs_copy_b : 4,
|
||||
tail_copy_b : 6,
|
||||
reserved_2 : 3;
|
||||
uint32_t length_copy_c : 19,
|
||||
mcs_copy_c : 4,
|
||||
tail_copy_c : 6,
|
||||
reserved_3 : 3;
|
||||
uint32_t length_copy_d : 19,
|
||||
mcs_copy_d : 4,
|
||||
tail_copy_d : 6,
|
||||
reserved_4 : 3;
|
||||
uint32_t length_copy_e : 19,
|
||||
mcs_copy_e : 4,
|
||||
tail_copy_e : 6,
|
||||
reserved_5 : 3;
|
||||
uint32_t length_copy_f : 19,
|
||||
mcs_copy_f : 4,
|
||||
tail_copy_f : 6,
|
||||
mu_user_number : 3;
|
||||
uint32_t length_copy_g : 19,
|
||||
mcs_copy_g : 4,
|
||||
tail_copy_g : 6,
|
||||
reserved_7 : 3;
|
||||
#else
|
||||
uint32_t reserved_0 : 3,
|
||||
tail : 6,
|
||||
mcs : 4,
|
||||
length : 19;
|
||||
uint32_t reserved_1 : 3,
|
||||
tail_copy_a : 6,
|
||||
mcs_copy_a : 4,
|
||||
length_copy_a : 19;
|
||||
uint32_t reserved_2 : 3,
|
||||
tail_copy_b : 6,
|
||||
mcs_copy_b : 4,
|
||||
length_copy_b : 19;
|
||||
uint32_t reserved_3 : 3,
|
||||
tail_copy_c : 6,
|
||||
mcs_copy_c : 4,
|
||||
length_copy_c : 19;
|
||||
uint32_t reserved_4 : 3,
|
||||
tail_copy_d : 6,
|
||||
mcs_copy_d : 4,
|
||||
length_copy_d : 19;
|
||||
uint32_t reserved_5 : 3,
|
||||
tail_copy_e : 6,
|
||||
mcs_copy_e : 4,
|
||||
length_copy_e : 19;
|
||||
uint32_t mu_user_number : 3,
|
||||
tail_copy_f : 6,
|
||||
mcs_copy_f : 4,
|
||||
length_copy_f : 19;
|
||||
uint32_t reserved_7 : 3,
|
||||
tail_copy_g : 6,
|
||||
mcs_copy_g : 4,
|
||||
length_copy_g : 19;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define VHT_SIG_B_MU160_INFO_LENGTH_OFFSET 0x00000000
|
||||
#define VHT_SIG_B_MU160_INFO_LENGTH_LSB 0
|
||||
#define VHT_SIG_B_MU160_INFO_LENGTH_MSB 18
|
||||
#define VHT_SIG_B_MU160_INFO_LENGTH_MASK 0x0007ffff
|
||||
|
||||
#define VHT_SIG_B_MU160_INFO_MCS_OFFSET 0x00000000
|
||||
#define VHT_SIG_B_MU160_INFO_MCS_LSB 19
|
||||
#define VHT_SIG_B_MU160_INFO_MCS_MSB 22
|
||||
#define VHT_SIG_B_MU160_INFO_MCS_MASK 0x00780000
|
||||
|
||||
#define VHT_SIG_B_MU160_INFO_TAIL_OFFSET 0x00000000
|
||||
#define VHT_SIG_B_MU160_INFO_TAIL_LSB 23
|
||||
#define VHT_SIG_B_MU160_INFO_TAIL_MSB 28
|
||||
#define VHT_SIG_B_MU160_INFO_TAIL_MASK 0x1f800000
|
||||
|
||||
#define VHT_SIG_B_MU160_INFO_RESERVED_0_OFFSET 0x00000000
|
||||
#define VHT_SIG_B_MU160_INFO_RESERVED_0_LSB 29
|
||||
#define VHT_SIG_B_MU160_INFO_RESERVED_0_MSB 31
|
||||
#define VHT_SIG_B_MU160_INFO_RESERVED_0_MASK 0xe0000000
|
||||
|
||||
#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_A_OFFSET 0x00000004
|
||||
#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_A_LSB 0
|
||||
#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_A_MSB 18
|
||||
#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_A_MASK 0x0007ffff
|
||||
|
||||
#define VHT_SIG_B_MU160_INFO_MCS_COPY_A_OFFSET 0x00000004
|
||||
#define VHT_SIG_B_MU160_INFO_MCS_COPY_A_LSB 19
|
||||
#define VHT_SIG_B_MU160_INFO_MCS_COPY_A_MSB 22
|
||||
#define VHT_SIG_B_MU160_INFO_MCS_COPY_A_MASK 0x00780000
|
||||
|
||||
#define VHT_SIG_B_MU160_INFO_TAIL_COPY_A_OFFSET 0x00000004
|
||||
#define VHT_SIG_B_MU160_INFO_TAIL_COPY_A_LSB 23
|
||||
#define VHT_SIG_B_MU160_INFO_TAIL_COPY_A_MSB 28
|
||||
#define VHT_SIG_B_MU160_INFO_TAIL_COPY_A_MASK 0x1f800000
|
||||
|
||||
#define VHT_SIG_B_MU160_INFO_RESERVED_1_OFFSET 0x00000004
|
||||
#define VHT_SIG_B_MU160_INFO_RESERVED_1_LSB 29
|
||||
#define VHT_SIG_B_MU160_INFO_RESERVED_1_MSB 31
|
||||
#define VHT_SIG_B_MU160_INFO_RESERVED_1_MASK 0xe0000000
|
||||
|
||||
#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_B_OFFSET 0x00000008
|
||||
#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_B_LSB 0
|
||||
#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_B_MSB 18
|
||||
#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_B_MASK 0x0007ffff
|
||||
|
||||
#define VHT_SIG_B_MU160_INFO_MCS_COPY_B_OFFSET 0x00000008
|
||||
#define VHT_SIG_B_MU160_INFO_MCS_COPY_B_LSB 19
|
||||
#define VHT_SIG_B_MU160_INFO_MCS_COPY_B_MSB 22
|
||||
#define VHT_SIG_B_MU160_INFO_MCS_COPY_B_MASK 0x00780000
|
||||
|
||||
#define VHT_SIG_B_MU160_INFO_TAIL_COPY_B_OFFSET 0x00000008
|
||||
#define VHT_SIG_B_MU160_INFO_TAIL_COPY_B_LSB 23
|
||||
#define VHT_SIG_B_MU160_INFO_TAIL_COPY_B_MSB 28
|
||||
#define VHT_SIG_B_MU160_INFO_TAIL_COPY_B_MASK 0x1f800000
|
||||
|
||||
#define VHT_SIG_B_MU160_INFO_RESERVED_2_OFFSET 0x00000008
|
||||
#define VHT_SIG_B_MU160_INFO_RESERVED_2_LSB 29
|
||||
#define VHT_SIG_B_MU160_INFO_RESERVED_2_MSB 31
|
||||
#define VHT_SIG_B_MU160_INFO_RESERVED_2_MASK 0xe0000000
|
||||
|
||||
#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_C_OFFSET 0x0000000c
|
||||
#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_C_LSB 0
|
||||
#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_C_MSB 18
|
||||
#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_C_MASK 0x0007ffff
|
||||
|
||||
#define VHT_SIG_B_MU160_INFO_MCS_COPY_C_OFFSET 0x0000000c
|
||||
#define VHT_SIG_B_MU160_INFO_MCS_COPY_C_LSB 19
|
||||
#define VHT_SIG_B_MU160_INFO_MCS_COPY_C_MSB 22
|
||||
#define VHT_SIG_B_MU160_INFO_MCS_COPY_C_MASK 0x00780000
|
||||
|
||||
#define VHT_SIG_B_MU160_INFO_TAIL_COPY_C_OFFSET 0x0000000c
|
||||
#define VHT_SIG_B_MU160_INFO_TAIL_COPY_C_LSB 23
|
||||
#define VHT_SIG_B_MU160_INFO_TAIL_COPY_C_MSB 28
|
||||
#define VHT_SIG_B_MU160_INFO_TAIL_COPY_C_MASK 0x1f800000
|
||||
|
||||
#define VHT_SIG_B_MU160_INFO_RESERVED_3_OFFSET 0x0000000c
|
||||
#define VHT_SIG_B_MU160_INFO_RESERVED_3_LSB 29
|
||||
#define VHT_SIG_B_MU160_INFO_RESERVED_3_MSB 31
|
||||
#define VHT_SIG_B_MU160_INFO_RESERVED_3_MASK 0xe0000000
|
||||
|
||||
#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_D_OFFSET 0x00000010
|
||||
#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_D_LSB 0
|
||||
#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_D_MSB 18
|
||||
#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_D_MASK 0x0007ffff
|
||||
|
||||
#define VHT_SIG_B_MU160_INFO_MCS_COPY_D_OFFSET 0x00000010
|
||||
#define VHT_SIG_B_MU160_INFO_MCS_COPY_D_LSB 19
|
||||
#define VHT_SIG_B_MU160_INFO_MCS_COPY_D_MSB 22
|
||||
#define VHT_SIG_B_MU160_INFO_MCS_COPY_D_MASK 0x00780000
|
||||
|
||||
#define VHT_SIG_B_MU160_INFO_TAIL_COPY_D_OFFSET 0x00000010
|
||||
#define VHT_SIG_B_MU160_INFO_TAIL_COPY_D_LSB 23
|
||||
#define VHT_SIG_B_MU160_INFO_TAIL_COPY_D_MSB 28
|
||||
#define VHT_SIG_B_MU160_INFO_TAIL_COPY_D_MASK 0x1f800000
|
||||
|
||||
#define VHT_SIG_B_MU160_INFO_RESERVED_4_OFFSET 0x00000010
|
||||
#define VHT_SIG_B_MU160_INFO_RESERVED_4_LSB 29
|
||||
#define VHT_SIG_B_MU160_INFO_RESERVED_4_MSB 31
|
||||
#define VHT_SIG_B_MU160_INFO_RESERVED_4_MASK 0xe0000000
|
||||
|
||||
#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_E_OFFSET 0x00000014
|
||||
#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_E_LSB 0
|
||||
#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_E_MSB 18
|
||||
#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_E_MASK 0x0007ffff
|
||||
|
||||
#define VHT_SIG_B_MU160_INFO_MCS_COPY_E_OFFSET 0x00000014
|
||||
#define VHT_SIG_B_MU160_INFO_MCS_COPY_E_LSB 19
|
||||
#define VHT_SIG_B_MU160_INFO_MCS_COPY_E_MSB 22
|
||||
#define VHT_SIG_B_MU160_INFO_MCS_COPY_E_MASK 0x00780000
|
||||
|
||||
#define VHT_SIG_B_MU160_INFO_TAIL_COPY_E_OFFSET 0x00000014
|
||||
#define VHT_SIG_B_MU160_INFO_TAIL_COPY_E_LSB 23
|
||||
#define VHT_SIG_B_MU160_INFO_TAIL_COPY_E_MSB 28
|
||||
#define VHT_SIG_B_MU160_INFO_TAIL_COPY_E_MASK 0x1f800000
|
||||
|
||||
#define VHT_SIG_B_MU160_INFO_RESERVED_5_OFFSET 0x00000014
|
||||
#define VHT_SIG_B_MU160_INFO_RESERVED_5_LSB 29
|
||||
#define VHT_SIG_B_MU160_INFO_RESERVED_5_MSB 31
|
||||
#define VHT_SIG_B_MU160_INFO_RESERVED_5_MASK 0xe0000000
|
||||
|
||||
#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_F_OFFSET 0x00000018
|
||||
#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_F_LSB 0
|
||||
#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_F_MSB 18
|
||||
#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_F_MASK 0x0007ffff
|
||||
|
||||
#define VHT_SIG_B_MU160_INFO_MCS_COPY_F_OFFSET 0x00000018
|
||||
#define VHT_SIG_B_MU160_INFO_MCS_COPY_F_LSB 19
|
||||
#define VHT_SIG_B_MU160_INFO_MCS_COPY_F_MSB 22
|
||||
#define VHT_SIG_B_MU160_INFO_MCS_COPY_F_MASK 0x00780000
|
||||
|
||||
#define VHT_SIG_B_MU160_INFO_TAIL_COPY_F_OFFSET 0x00000018
|
||||
#define VHT_SIG_B_MU160_INFO_TAIL_COPY_F_LSB 23
|
||||
#define VHT_SIG_B_MU160_INFO_TAIL_COPY_F_MSB 28
|
||||
#define VHT_SIG_B_MU160_INFO_TAIL_COPY_F_MASK 0x1f800000
|
||||
|
||||
#define VHT_SIG_B_MU160_INFO_MU_USER_NUMBER_OFFSET 0x00000018
|
||||
#define VHT_SIG_B_MU160_INFO_MU_USER_NUMBER_LSB 29
|
||||
#define VHT_SIG_B_MU160_INFO_MU_USER_NUMBER_MSB 31
|
||||
#define VHT_SIG_B_MU160_INFO_MU_USER_NUMBER_MASK 0xe0000000
|
||||
|
||||
#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_G_OFFSET 0x0000001c
|
||||
#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_G_LSB 0
|
||||
#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_G_MSB 18
|
||||
#define VHT_SIG_B_MU160_INFO_LENGTH_COPY_G_MASK 0x0007ffff
|
||||
|
||||
#define VHT_SIG_B_MU160_INFO_MCS_COPY_G_OFFSET 0x0000001c
|
||||
#define VHT_SIG_B_MU160_INFO_MCS_COPY_G_LSB 19
|
||||
#define VHT_SIG_B_MU160_INFO_MCS_COPY_G_MSB 22
|
||||
#define VHT_SIG_B_MU160_INFO_MCS_COPY_G_MASK 0x00780000
|
||||
|
||||
#define VHT_SIG_B_MU160_INFO_TAIL_COPY_G_OFFSET 0x0000001c
|
||||
#define VHT_SIG_B_MU160_INFO_TAIL_COPY_G_LSB 23
|
||||
#define VHT_SIG_B_MU160_INFO_TAIL_COPY_G_MSB 28
|
||||
#define VHT_SIG_B_MU160_INFO_TAIL_COPY_G_MASK 0x1f800000
|
||||
|
||||
#define VHT_SIG_B_MU160_INFO_RESERVED_7_OFFSET 0x0000001c
|
||||
#define VHT_SIG_B_MU160_INFO_RESERVED_7_LSB 29
|
||||
#define VHT_SIG_B_MU160_INFO_RESERVED_7_MSB 31
|
||||
#define VHT_SIG_B_MU160_INFO_RESERVED_7_MASK 0xe0000000
|
||||
|
||||
#endif
|
||||
68
hw/kiwi/v2/vht_sig_b_mu20_info.h
Normal file
68
hw/kiwi/v2/vht_sig_b_mu20_info.h
Normal file
|
|
@ -0,0 +1,68 @@
|
|||
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
#ifndef _VHT_SIG_B_MU20_INFO_H_
|
||||
#define _VHT_SIG_B_MU20_INFO_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#define NUM_OF_DWORDS_VHT_SIG_B_MU20_INFO 1
|
||||
|
||||
struct vht_sig_b_mu20_info {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t length : 16,
|
||||
mcs : 4,
|
||||
tail : 6,
|
||||
mu_user_number : 3,
|
||||
reserved_0 : 3;
|
||||
#else
|
||||
uint32_t reserved_0 : 3,
|
||||
mu_user_number : 3,
|
||||
tail : 6,
|
||||
mcs : 4,
|
||||
length : 16;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define VHT_SIG_B_MU20_INFO_LENGTH_OFFSET 0x00000000
|
||||
#define VHT_SIG_B_MU20_INFO_LENGTH_LSB 0
|
||||
#define VHT_SIG_B_MU20_INFO_LENGTH_MSB 15
|
||||
#define VHT_SIG_B_MU20_INFO_LENGTH_MASK 0x0000ffff
|
||||
|
||||
#define VHT_SIG_B_MU20_INFO_MCS_OFFSET 0x00000000
|
||||
#define VHT_SIG_B_MU20_INFO_MCS_LSB 16
|
||||
#define VHT_SIG_B_MU20_INFO_MCS_MSB 19
|
||||
#define VHT_SIG_B_MU20_INFO_MCS_MASK 0x000f0000
|
||||
|
||||
#define VHT_SIG_B_MU20_INFO_TAIL_OFFSET 0x00000000
|
||||
#define VHT_SIG_B_MU20_INFO_TAIL_LSB 20
|
||||
#define VHT_SIG_B_MU20_INFO_TAIL_MSB 25
|
||||
#define VHT_SIG_B_MU20_INFO_TAIL_MASK 0x03f00000
|
||||
|
||||
#define VHT_SIG_B_MU20_INFO_MU_USER_NUMBER_OFFSET 0x00000000
|
||||
#define VHT_SIG_B_MU20_INFO_MU_USER_NUMBER_LSB 26
|
||||
#define VHT_SIG_B_MU20_INFO_MU_USER_NUMBER_MSB 28
|
||||
#define VHT_SIG_B_MU20_INFO_MU_USER_NUMBER_MASK 0x1c000000
|
||||
|
||||
#define VHT_SIG_B_MU20_INFO_RESERVED_0_OFFSET 0x00000000
|
||||
#define VHT_SIG_B_MU20_INFO_RESERVED_0_LSB 29
|
||||
#define VHT_SIG_B_MU20_INFO_RESERVED_0_MSB 31
|
||||
#define VHT_SIG_B_MU20_INFO_RESERVED_0_MASK 0xe0000000
|
||||
|
||||
#endif
|
||||
96
hw/kiwi/v2/vht_sig_b_mu40_info.h
Normal file
96
hw/kiwi/v2/vht_sig_b_mu40_info.h
Normal file
|
|
@ -0,0 +1,96 @@
|
|||
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
#ifndef _VHT_SIG_B_MU40_INFO_H_
|
||||
#define _VHT_SIG_B_MU40_INFO_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#define NUM_OF_DWORDS_VHT_SIG_B_MU40_INFO 2
|
||||
|
||||
struct vht_sig_b_mu40_info {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t length : 17,
|
||||
mcs : 4,
|
||||
tail : 6,
|
||||
reserved_0 : 2,
|
||||
mu_user_number : 3;
|
||||
uint32_t length_copy : 17,
|
||||
mcs_copy : 4,
|
||||
tail_copy : 6,
|
||||
reserved_1 : 5;
|
||||
#else
|
||||
uint32_t mu_user_number : 3,
|
||||
reserved_0 : 2,
|
||||
tail : 6,
|
||||
mcs : 4,
|
||||
length : 17;
|
||||
uint32_t reserved_1 : 5,
|
||||
tail_copy : 6,
|
||||
mcs_copy : 4,
|
||||
length_copy : 17;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define VHT_SIG_B_MU40_INFO_LENGTH_OFFSET 0x00000000
|
||||
#define VHT_SIG_B_MU40_INFO_LENGTH_LSB 0
|
||||
#define VHT_SIG_B_MU40_INFO_LENGTH_MSB 16
|
||||
#define VHT_SIG_B_MU40_INFO_LENGTH_MASK 0x0001ffff
|
||||
|
||||
#define VHT_SIG_B_MU40_INFO_MCS_OFFSET 0x00000000
|
||||
#define VHT_SIG_B_MU40_INFO_MCS_LSB 17
|
||||
#define VHT_SIG_B_MU40_INFO_MCS_MSB 20
|
||||
#define VHT_SIG_B_MU40_INFO_MCS_MASK 0x001e0000
|
||||
|
||||
#define VHT_SIG_B_MU40_INFO_TAIL_OFFSET 0x00000000
|
||||
#define VHT_SIG_B_MU40_INFO_TAIL_LSB 21
|
||||
#define VHT_SIG_B_MU40_INFO_TAIL_MSB 26
|
||||
#define VHT_SIG_B_MU40_INFO_TAIL_MASK 0x07e00000
|
||||
|
||||
#define VHT_SIG_B_MU40_INFO_RESERVED_0_OFFSET 0x00000000
|
||||
#define VHT_SIG_B_MU40_INFO_RESERVED_0_LSB 27
|
||||
#define VHT_SIG_B_MU40_INFO_RESERVED_0_MSB 28
|
||||
#define VHT_SIG_B_MU40_INFO_RESERVED_0_MASK 0x18000000
|
||||
|
||||
#define VHT_SIG_B_MU40_INFO_MU_USER_NUMBER_OFFSET 0x00000000
|
||||
#define VHT_SIG_B_MU40_INFO_MU_USER_NUMBER_LSB 29
|
||||
#define VHT_SIG_B_MU40_INFO_MU_USER_NUMBER_MSB 31
|
||||
#define VHT_SIG_B_MU40_INFO_MU_USER_NUMBER_MASK 0xe0000000
|
||||
|
||||
#define VHT_SIG_B_MU40_INFO_LENGTH_COPY_OFFSET 0x00000004
|
||||
#define VHT_SIG_B_MU40_INFO_LENGTH_COPY_LSB 0
|
||||
#define VHT_SIG_B_MU40_INFO_LENGTH_COPY_MSB 16
|
||||
#define VHT_SIG_B_MU40_INFO_LENGTH_COPY_MASK 0x0001ffff
|
||||
|
||||
#define VHT_SIG_B_MU40_INFO_MCS_COPY_OFFSET 0x00000004
|
||||
#define VHT_SIG_B_MU40_INFO_MCS_COPY_LSB 17
|
||||
#define VHT_SIG_B_MU40_INFO_MCS_COPY_MSB 20
|
||||
#define VHT_SIG_B_MU40_INFO_MCS_COPY_MASK 0x001e0000
|
||||
|
||||
#define VHT_SIG_B_MU40_INFO_TAIL_COPY_OFFSET 0x00000004
|
||||
#define VHT_SIG_B_MU40_INFO_TAIL_COPY_LSB 21
|
||||
#define VHT_SIG_B_MU40_INFO_TAIL_COPY_MSB 26
|
||||
#define VHT_SIG_B_MU40_INFO_TAIL_COPY_MASK 0x07e00000
|
||||
|
||||
#define VHT_SIG_B_MU40_INFO_RESERVED_1_OFFSET 0x00000004
|
||||
#define VHT_SIG_B_MU40_INFO_RESERVED_1_LSB 27
|
||||
#define VHT_SIG_B_MU40_INFO_RESERVED_1_MSB 31
|
||||
#define VHT_SIG_B_MU40_INFO_RESERVED_1_MASK 0xf8000000
|
||||
|
||||
#endif
|
||||
145
hw/kiwi/v2/vht_sig_b_mu80_info.h
Normal file
145
hw/kiwi/v2/vht_sig_b_mu80_info.h
Normal file
|
|
@ -0,0 +1,145 @@
|
|||
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
#ifndef _VHT_SIG_B_MU80_INFO_H_
|
||||
#define _VHT_SIG_B_MU80_INFO_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#define NUM_OF_DWORDS_VHT_SIG_B_MU80_INFO 4
|
||||
|
||||
struct vht_sig_b_mu80_info {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t length : 19,
|
||||
mcs : 4,
|
||||
tail : 6,
|
||||
reserved_0 : 3;
|
||||
uint32_t length_copy_a : 19,
|
||||
mcs_copy_a : 4,
|
||||
tail_copy_a : 6,
|
||||
reserved_1 : 3;
|
||||
uint32_t length_copy_b : 19,
|
||||
mcs_copy_b : 4,
|
||||
tail_copy_b : 6,
|
||||
mu_user_number : 3;
|
||||
uint32_t length_copy_c : 19,
|
||||
mcs_copy_c : 4,
|
||||
tail_copy_c : 6,
|
||||
reserved_3 : 3;
|
||||
#else
|
||||
uint32_t reserved_0 : 3,
|
||||
tail : 6,
|
||||
mcs : 4,
|
||||
length : 19;
|
||||
uint32_t reserved_1 : 3,
|
||||
tail_copy_a : 6,
|
||||
mcs_copy_a : 4,
|
||||
length_copy_a : 19;
|
||||
uint32_t mu_user_number : 3,
|
||||
tail_copy_b : 6,
|
||||
mcs_copy_b : 4,
|
||||
length_copy_b : 19;
|
||||
uint32_t reserved_3 : 3,
|
||||
tail_copy_c : 6,
|
||||
mcs_copy_c : 4,
|
||||
length_copy_c : 19;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define VHT_SIG_B_MU80_INFO_LENGTH_OFFSET 0x00000000
|
||||
#define VHT_SIG_B_MU80_INFO_LENGTH_LSB 0
|
||||
#define VHT_SIG_B_MU80_INFO_LENGTH_MSB 18
|
||||
#define VHT_SIG_B_MU80_INFO_LENGTH_MASK 0x0007ffff
|
||||
|
||||
#define VHT_SIG_B_MU80_INFO_MCS_OFFSET 0x00000000
|
||||
#define VHT_SIG_B_MU80_INFO_MCS_LSB 19
|
||||
#define VHT_SIG_B_MU80_INFO_MCS_MSB 22
|
||||
#define VHT_SIG_B_MU80_INFO_MCS_MASK 0x00780000
|
||||
|
||||
#define VHT_SIG_B_MU80_INFO_TAIL_OFFSET 0x00000000
|
||||
#define VHT_SIG_B_MU80_INFO_TAIL_LSB 23
|
||||
#define VHT_SIG_B_MU80_INFO_TAIL_MSB 28
|
||||
#define VHT_SIG_B_MU80_INFO_TAIL_MASK 0x1f800000
|
||||
|
||||
#define VHT_SIG_B_MU80_INFO_RESERVED_0_OFFSET 0x00000000
|
||||
#define VHT_SIG_B_MU80_INFO_RESERVED_0_LSB 29
|
||||
#define VHT_SIG_B_MU80_INFO_RESERVED_0_MSB 31
|
||||
#define VHT_SIG_B_MU80_INFO_RESERVED_0_MASK 0xe0000000
|
||||
|
||||
#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_A_OFFSET 0x00000004
|
||||
#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_A_LSB 0
|
||||
#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_A_MSB 18
|
||||
#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_A_MASK 0x0007ffff
|
||||
|
||||
#define VHT_SIG_B_MU80_INFO_MCS_COPY_A_OFFSET 0x00000004
|
||||
#define VHT_SIG_B_MU80_INFO_MCS_COPY_A_LSB 19
|
||||
#define VHT_SIG_B_MU80_INFO_MCS_COPY_A_MSB 22
|
||||
#define VHT_SIG_B_MU80_INFO_MCS_COPY_A_MASK 0x00780000
|
||||
|
||||
#define VHT_SIG_B_MU80_INFO_TAIL_COPY_A_OFFSET 0x00000004
|
||||
#define VHT_SIG_B_MU80_INFO_TAIL_COPY_A_LSB 23
|
||||
#define VHT_SIG_B_MU80_INFO_TAIL_COPY_A_MSB 28
|
||||
#define VHT_SIG_B_MU80_INFO_TAIL_COPY_A_MASK 0x1f800000
|
||||
|
||||
#define VHT_SIG_B_MU80_INFO_RESERVED_1_OFFSET 0x00000004
|
||||
#define VHT_SIG_B_MU80_INFO_RESERVED_1_LSB 29
|
||||
#define VHT_SIG_B_MU80_INFO_RESERVED_1_MSB 31
|
||||
#define VHT_SIG_B_MU80_INFO_RESERVED_1_MASK 0xe0000000
|
||||
|
||||
#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_B_OFFSET 0x00000008
|
||||
#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_B_LSB 0
|
||||
#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_B_MSB 18
|
||||
#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_B_MASK 0x0007ffff
|
||||
|
||||
#define VHT_SIG_B_MU80_INFO_MCS_COPY_B_OFFSET 0x00000008
|
||||
#define VHT_SIG_B_MU80_INFO_MCS_COPY_B_LSB 19
|
||||
#define VHT_SIG_B_MU80_INFO_MCS_COPY_B_MSB 22
|
||||
#define VHT_SIG_B_MU80_INFO_MCS_COPY_B_MASK 0x00780000
|
||||
|
||||
#define VHT_SIG_B_MU80_INFO_TAIL_COPY_B_OFFSET 0x00000008
|
||||
#define VHT_SIG_B_MU80_INFO_TAIL_COPY_B_LSB 23
|
||||
#define VHT_SIG_B_MU80_INFO_TAIL_COPY_B_MSB 28
|
||||
#define VHT_SIG_B_MU80_INFO_TAIL_COPY_B_MASK 0x1f800000
|
||||
|
||||
#define VHT_SIG_B_MU80_INFO_MU_USER_NUMBER_OFFSET 0x00000008
|
||||
#define VHT_SIG_B_MU80_INFO_MU_USER_NUMBER_LSB 29
|
||||
#define VHT_SIG_B_MU80_INFO_MU_USER_NUMBER_MSB 31
|
||||
#define VHT_SIG_B_MU80_INFO_MU_USER_NUMBER_MASK 0xe0000000
|
||||
|
||||
#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_C_OFFSET 0x0000000c
|
||||
#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_C_LSB 0
|
||||
#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_C_MSB 18
|
||||
#define VHT_SIG_B_MU80_INFO_LENGTH_COPY_C_MASK 0x0007ffff
|
||||
|
||||
#define VHT_SIG_B_MU80_INFO_MCS_COPY_C_OFFSET 0x0000000c
|
||||
#define VHT_SIG_B_MU80_INFO_MCS_COPY_C_LSB 19
|
||||
#define VHT_SIG_B_MU80_INFO_MCS_COPY_C_MSB 22
|
||||
#define VHT_SIG_B_MU80_INFO_MCS_COPY_C_MASK 0x00780000
|
||||
|
||||
#define VHT_SIG_B_MU80_INFO_TAIL_COPY_C_OFFSET 0x0000000c
|
||||
#define VHT_SIG_B_MU80_INFO_TAIL_COPY_C_LSB 23
|
||||
#define VHT_SIG_B_MU80_INFO_TAIL_COPY_C_MSB 28
|
||||
#define VHT_SIG_B_MU80_INFO_TAIL_COPY_C_MASK 0x1f800000
|
||||
|
||||
#define VHT_SIG_B_MU80_INFO_RESERVED_3_OFFSET 0x0000000c
|
||||
#define VHT_SIG_B_MU80_INFO_RESERVED_3_LSB 29
|
||||
#define VHT_SIG_B_MU80_INFO_RESERVED_3_MSB 31
|
||||
#define VHT_SIG_B_MU80_INFO_RESERVED_3_MASK 0xe0000000
|
||||
|
||||
#endif
|
||||
313
hw/kiwi/v2/vht_sig_b_su160_info.h
Normal file
313
hw/kiwi/v2/vht_sig_b_su160_info.h
Normal file
|
|
@ -0,0 +1,313 @@
|
|||
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
#ifndef _VHT_SIG_B_SU160_INFO_H_
|
||||
#define _VHT_SIG_B_SU160_INFO_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#define NUM_OF_DWORDS_VHT_SIG_B_SU160_INFO 8
|
||||
|
||||
struct vht_sig_b_su160_info {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t length : 21,
|
||||
vhtb_reserved : 2,
|
||||
tail : 6,
|
||||
reserved_0 : 2,
|
||||
rx_ndp : 1;
|
||||
uint32_t length_copy_a : 21,
|
||||
vhtb_reserved_copy_a : 2,
|
||||
tail_copy_a : 6,
|
||||
reserved_1 : 2,
|
||||
rx_ndp_copy_a : 1;
|
||||
uint32_t length_copy_b : 21,
|
||||
vhtb_reserved_copy_b : 2,
|
||||
tail_copy_b : 6,
|
||||
reserved_2 : 2,
|
||||
rx_ndp_copy_b : 1;
|
||||
uint32_t length_copy_c : 21,
|
||||
vhtb_reserved_copy_c : 2,
|
||||
tail_copy_c : 6,
|
||||
reserved_3 : 2,
|
||||
rx_ndp_copy_c : 1;
|
||||
uint32_t length_copy_d : 21,
|
||||
vhtb_reserved_copy_d : 2,
|
||||
tail_copy_d : 6,
|
||||
reserved_4 : 2,
|
||||
rx_ndp_copy_d : 1;
|
||||
uint32_t length_copy_e : 21,
|
||||
vhtb_reserved_copy_e : 2,
|
||||
tail_copy_e : 6,
|
||||
reserved_5 : 2,
|
||||
rx_ndp_copy_e : 1;
|
||||
uint32_t length_copy_f : 21,
|
||||
vhtb_reserved_copy_f : 2,
|
||||
tail_copy_f : 6,
|
||||
reserved_6 : 2,
|
||||
rx_ndp_copy_f : 1;
|
||||
uint32_t length_copy_g : 21,
|
||||
vhtb_reserved_copy_g : 2,
|
||||
tail_copy_g : 6,
|
||||
reserved_7 : 2,
|
||||
rx_ndp_copy_g : 1;
|
||||
#else
|
||||
uint32_t rx_ndp : 1,
|
||||
reserved_0 : 2,
|
||||
tail : 6,
|
||||
vhtb_reserved : 2,
|
||||
length : 21;
|
||||
uint32_t rx_ndp_copy_a : 1,
|
||||
reserved_1 : 2,
|
||||
tail_copy_a : 6,
|
||||
vhtb_reserved_copy_a : 2,
|
||||
length_copy_a : 21;
|
||||
uint32_t rx_ndp_copy_b : 1,
|
||||
reserved_2 : 2,
|
||||
tail_copy_b : 6,
|
||||
vhtb_reserved_copy_b : 2,
|
||||
length_copy_b : 21;
|
||||
uint32_t rx_ndp_copy_c : 1,
|
||||
reserved_3 : 2,
|
||||
tail_copy_c : 6,
|
||||
vhtb_reserved_copy_c : 2,
|
||||
length_copy_c : 21;
|
||||
uint32_t rx_ndp_copy_d : 1,
|
||||
reserved_4 : 2,
|
||||
tail_copy_d : 6,
|
||||
vhtb_reserved_copy_d : 2,
|
||||
length_copy_d : 21;
|
||||
uint32_t rx_ndp_copy_e : 1,
|
||||
reserved_5 : 2,
|
||||
tail_copy_e : 6,
|
||||
vhtb_reserved_copy_e : 2,
|
||||
length_copy_e : 21;
|
||||
uint32_t rx_ndp_copy_f : 1,
|
||||
reserved_6 : 2,
|
||||
tail_copy_f : 6,
|
||||
vhtb_reserved_copy_f : 2,
|
||||
length_copy_f : 21;
|
||||
uint32_t rx_ndp_copy_g : 1,
|
||||
reserved_7 : 2,
|
||||
tail_copy_g : 6,
|
||||
vhtb_reserved_copy_g : 2,
|
||||
length_copy_g : 21;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define VHT_SIG_B_SU160_INFO_LENGTH_OFFSET 0x00000000
|
||||
#define VHT_SIG_B_SU160_INFO_LENGTH_LSB 0
|
||||
#define VHT_SIG_B_SU160_INFO_LENGTH_MSB 20
|
||||
#define VHT_SIG_B_SU160_INFO_LENGTH_MASK 0x001fffff
|
||||
|
||||
#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_OFFSET 0x00000000
|
||||
#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_LSB 21
|
||||
#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_MSB 22
|
||||
#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_MASK 0x00600000
|
||||
|
||||
#define VHT_SIG_B_SU160_INFO_TAIL_OFFSET 0x00000000
|
||||
#define VHT_SIG_B_SU160_INFO_TAIL_LSB 23
|
||||
#define VHT_SIG_B_SU160_INFO_TAIL_MSB 28
|
||||
#define VHT_SIG_B_SU160_INFO_TAIL_MASK 0x1f800000
|
||||
|
||||
#define VHT_SIG_B_SU160_INFO_RESERVED_0_OFFSET 0x00000000
|
||||
#define VHT_SIG_B_SU160_INFO_RESERVED_0_LSB 29
|
||||
#define VHT_SIG_B_SU160_INFO_RESERVED_0_MSB 30
|
||||
#define VHT_SIG_B_SU160_INFO_RESERVED_0_MASK 0x60000000
|
||||
|
||||
#define VHT_SIG_B_SU160_INFO_RX_NDP_OFFSET 0x00000000
|
||||
#define VHT_SIG_B_SU160_INFO_RX_NDP_LSB 31
|
||||
#define VHT_SIG_B_SU160_INFO_RX_NDP_MSB 31
|
||||
#define VHT_SIG_B_SU160_INFO_RX_NDP_MASK 0x80000000
|
||||
|
||||
#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_A_OFFSET 0x00000004
|
||||
#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_A_LSB 0
|
||||
#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_A_MSB 20
|
||||
#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_A_MASK 0x001fffff
|
||||
|
||||
#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_A_OFFSET 0x00000004
|
||||
#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_A_LSB 21
|
||||
#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_A_MSB 22
|
||||
#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_A_MASK 0x00600000
|
||||
|
||||
#define VHT_SIG_B_SU160_INFO_TAIL_COPY_A_OFFSET 0x00000004
|
||||
#define VHT_SIG_B_SU160_INFO_TAIL_COPY_A_LSB 23
|
||||
#define VHT_SIG_B_SU160_INFO_TAIL_COPY_A_MSB 28
|
||||
#define VHT_SIG_B_SU160_INFO_TAIL_COPY_A_MASK 0x1f800000
|
||||
|
||||
#define VHT_SIG_B_SU160_INFO_RESERVED_1_OFFSET 0x00000004
|
||||
#define VHT_SIG_B_SU160_INFO_RESERVED_1_LSB 29
|
||||
#define VHT_SIG_B_SU160_INFO_RESERVED_1_MSB 30
|
||||
#define VHT_SIG_B_SU160_INFO_RESERVED_1_MASK 0x60000000
|
||||
|
||||
#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_A_OFFSET 0x00000004
|
||||
#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_A_LSB 31
|
||||
#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_A_MSB 31
|
||||
#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_A_MASK 0x80000000
|
||||
|
||||
#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_B_OFFSET 0x00000008
|
||||
#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_B_LSB 0
|
||||
#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_B_MSB 20
|
||||
#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_B_MASK 0x001fffff
|
||||
|
||||
#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_B_OFFSET 0x00000008
|
||||
#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_B_LSB 21
|
||||
#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_B_MSB 22
|
||||
#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_B_MASK 0x00600000
|
||||
|
||||
#define VHT_SIG_B_SU160_INFO_TAIL_COPY_B_OFFSET 0x00000008
|
||||
#define VHT_SIG_B_SU160_INFO_TAIL_COPY_B_LSB 23
|
||||
#define VHT_SIG_B_SU160_INFO_TAIL_COPY_B_MSB 28
|
||||
#define VHT_SIG_B_SU160_INFO_TAIL_COPY_B_MASK 0x1f800000
|
||||
|
||||
#define VHT_SIG_B_SU160_INFO_RESERVED_2_OFFSET 0x00000008
|
||||
#define VHT_SIG_B_SU160_INFO_RESERVED_2_LSB 29
|
||||
#define VHT_SIG_B_SU160_INFO_RESERVED_2_MSB 30
|
||||
#define VHT_SIG_B_SU160_INFO_RESERVED_2_MASK 0x60000000
|
||||
|
||||
#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_B_OFFSET 0x00000008
|
||||
#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_B_LSB 31
|
||||
#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_B_MSB 31
|
||||
#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_B_MASK 0x80000000
|
||||
|
||||
#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_C_OFFSET 0x0000000c
|
||||
#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_C_LSB 0
|
||||
#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_C_MSB 20
|
||||
#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_C_MASK 0x001fffff
|
||||
|
||||
#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_C_OFFSET 0x0000000c
|
||||
#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_C_LSB 21
|
||||
#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_C_MSB 22
|
||||
#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_C_MASK 0x00600000
|
||||
|
||||
#define VHT_SIG_B_SU160_INFO_TAIL_COPY_C_OFFSET 0x0000000c
|
||||
#define VHT_SIG_B_SU160_INFO_TAIL_COPY_C_LSB 23
|
||||
#define VHT_SIG_B_SU160_INFO_TAIL_COPY_C_MSB 28
|
||||
#define VHT_SIG_B_SU160_INFO_TAIL_COPY_C_MASK 0x1f800000
|
||||
|
||||
#define VHT_SIG_B_SU160_INFO_RESERVED_3_OFFSET 0x0000000c
|
||||
#define VHT_SIG_B_SU160_INFO_RESERVED_3_LSB 29
|
||||
#define VHT_SIG_B_SU160_INFO_RESERVED_3_MSB 30
|
||||
#define VHT_SIG_B_SU160_INFO_RESERVED_3_MASK 0x60000000
|
||||
|
||||
#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_C_OFFSET 0x0000000c
|
||||
#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_C_LSB 31
|
||||
#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_C_MSB 31
|
||||
#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_C_MASK 0x80000000
|
||||
|
||||
#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_D_OFFSET 0x00000010
|
||||
#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_D_LSB 0
|
||||
#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_D_MSB 20
|
||||
#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_D_MASK 0x001fffff
|
||||
|
||||
#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_D_OFFSET 0x00000010
|
||||
#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_D_LSB 21
|
||||
#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_D_MSB 22
|
||||
#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_D_MASK 0x00600000
|
||||
|
||||
#define VHT_SIG_B_SU160_INFO_TAIL_COPY_D_OFFSET 0x00000010
|
||||
#define VHT_SIG_B_SU160_INFO_TAIL_COPY_D_LSB 23
|
||||
#define VHT_SIG_B_SU160_INFO_TAIL_COPY_D_MSB 28
|
||||
#define VHT_SIG_B_SU160_INFO_TAIL_COPY_D_MASK 0x1f800000
|
||||
|
||||
#define VHT_SIG_B_SU160_INFO_RESERVED_4_OFFSET 0x00000010
|
||||
#define VHT_SIG_B_SU160_INFO_RESERVED_4_LSB 29
|
||||
#define VHT_SIG_B_SU160_INFO_RESERVED_4_MSB 30
|
||||
#define VHT_SIG_B_SU160_INFO_RESERVED_4_MASK 0x60000000
|
||||
|
||||
#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_D_OFFSET 0x00000010
|
||||
#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_D_LSB 31
|
||||
#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_D_MSB 31
|
||||
#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_D_MASK 0x80000000
|
||||
|
||||
#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_E_OFFSET 0x00000014
|
||||
#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_E_LSB 0
|
||||
#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_E_MSB 20
|
||||
#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_E_MASK 0x001fffff
|
||||
|
||||
#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_E_OFFSET 0x00000014
|
||||
#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_E_LSB 21
|
||||
#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_E_MSB 22
|
||||
#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_E_MASK 0x00600000
|
||||
|
||||
#define VHT_SIG_B_SU160_INFO_TAIL_COPY_E_OFFSET 0x00000014
|
||||
#define VHT_SIG_B_SU160_INFO_TAIL_COPY_E_LSB 23
|
||||
#define VHT_SIG_B_SU160_INFO_TAIL_COPY_E_MSB 28
|
||||
#define VHT_SIG_B_SU160_INFO_TAIL_COPY_E_MASK 0x1f800000
|
||||
|
||||
#define VHT_SIG_B_SU160_INFO_RESERVED_5_OFFSET 0x00000014
|
||||
#define VHT_SIG_B_SU160_INFO_RESERVED_5_LSB 29
|
||||
#define VHT_SIG_B_SU160_INFO_RESERVED_5_MSB 30
|
||||
#define VHT_SIG_B_SU160_INFO_RESERVED_5_MASK 0x60000000
|
||||
|
||||
#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_E_OFFSET 0x00000014
|
||||
#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_E_LSB 31
|
||||
#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_E_MSB 31
|
||||
#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_E_MASK 0x80000000
|
||||
|
||||
#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_F_OFFSET 0x00000018
|
||||
#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_F_LSB 0
|
||||
#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_F_MSB 20
|
||||
#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_F_MASK 0x001fffff
|
||||
|
||||
#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_F_OFFSET 0x00000018
|
||||
#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_F_LSB 21
|
||||
#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_F_MSB 22
|
||||
#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_F_MASK 0x00600000
|
||||
|
||||
#define VHT_SIG_B_SU160_INFO_TAIL_COPY_F_OFFSET 0x00000018
|
||||
#define VHT_SIG_B_SU160_INFO_TAIL_COPY_F_LSB 23
|
||||
#define VHT_SIG_B_SU160_INFO_TAIL_COPY_F_MSB 28
|
||||
#define VHT_SIG_B_SU160_INFO_TAIL_COPY_F_MASK 0x1f800000
|
||||
|
||||
#define VHT_SIG_B_SU160_INFO_RESERVED_6_OFFSET 0x00000018
|
||||
#define VHT_SIG_B_SU160_INFO_RESERVED_6_LSB 29
|
||||
#define VHT_SIG_B_SU160_INFO_RESERVED_6_MSB 30
|
||||
#define VHT_SIG_B_SU160_INFO_RESERVED_6_MASK 0x60000000
|
||||
|
||||
#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_F_OFFSET 0x00000018
|
||||
#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_F_LSB 31
|
||||
#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_F_MSB 31
|
||||
#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_F_MASK 0x80000000
|
||||
|
||||
#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_G_OFFSET 0x0000001c
|
||||
#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_G_LSB 0
|
||||
#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_G_MSB 20
|
||||
#define VHT_SIG_B_SU160_INFO_LENGTH_COPY_G_MASK 0x001fffff
|
||||
|
||||
#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_G_OFFSET 0x0000001c
|
||||
#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_G_LSB 21
|
||||
#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_G_MSB 22
|
||||
#define VHT_SIG_B_SU160_INFO_VHTB_RESERVED_COPY_G_MASK 0x00600000
|
||||
|
||||
#define VHT_SIG_B_SU160_INFO_TAIL_COPY_G_OFFSET 0x0000001c
|
||||
#define VHT_SIG_B_SU160_INFO_TAIL_COPY_G_LSB 23
|
||||
#define VHT_SIG_B_SU160_INFO_TAIL_COPY_G_MSB 28
|
||||
#define VHT_SIG_B_SU160_INFO_TAIL_COPY_G_MASK 0x1f800000
|
||||
|
||||
#define VHT_SIG_B_SU160_INFO_RESERVED_7_OFFSET 0x0000001c
|
||||
#define VHT_SIG_B_SU160_INFO_RESERVED_7_LSB 29
|
||||
#define VHT_SIG_B_SU160_INFO_RESERVED_7_MSB 30
|
||||
#define VHT_SIG_B_SU160_INFO_RESERVED_7_MASK 0x60000000
|
||||
|
||||
#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_G_OFFSET 0x0000001c
|
||||
#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_G_LSB 31
|
||||
#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_G_MSB 31
|
||||
#define VHT_SIG_B_SU160_INFO_RX_NDP_COPY_G_MASK 0x80000000
|
||||
|
||||
#endif
|
||||
68
hw/kiwi/v2/vht_sig_b_su20_info.h
Normal file
68
hw/kiwi/v2/vht_sig_b_su20_info.h
Normal file
|
|
@ -0,0 +1,68 @@
|
|||
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
#ifndef _VHT_SIG_B_SU20_INFO_H_
|
||||
#define _VHT_SIG_B_SU20_INFO_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#define NUM_OF_DWORDS_VHT_SIG_B_SU20_INFO 1
|
||||
|
||||
struct vht_sig_b_su20_info {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t length : 17,
|
||||
vhtb_reserved : 3,
|
||||
tail : 6,
|
||||
reserved : 5,
|
||||
rx_ndp : 1;
|
||||
#else
|
||||
uint32_t rx_ndp : 1,
|
||||
reserved : 5,
|
||||
tail : 6,
|
||||
vhtb_reserved : 3,
|
||||
length : 17;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define VHT_SIG_B_SU20_INFO_LENGTH_OFFSET 0x00000000
|
||||
#define VHT_SIG_B_SU20_INFO_LENGTH_LSB 0
|
||||
#define VHT_SIG_B_SU20_INFO_LENGTH_MSB 16
|
||||
#define VHT_SIG_B_SU20_INFO_LENGTH_MASK 0x0001ffff
|
||||
|
||||
#define VHT_SIG_B_SU20_INFO_VHTB_RESERVED_OFFSET 0x00000000
|
||||
#define VHT_SIG_B_SU20_INFO_VHTB_RESERVED_LSB 17
|
||||
#define VHT_SIG_B_SU20_INFO_VHTB_RESERVED_MSB 19
|
||||
#define VHT_SIG_B_SU20_INFO_VHTB_RESERVED_MASK 0x000e0000
|
||||
|
||||
#define VHT_SIG_B_SU20_INFO_TAIL_OFFSET 0x00000000
|
||||
#define VHT_SIG_B_SU20_INFO_TAIL_LSB 20
|
||||
#define VHT_SIG_B_SU20_INFO_TAIL_MSB 25
|
||||
#define VHT_SIG_B_SU20_INFO_TAIL_MASK 0x03f00000
|
||||
|
||||
#define VHT_SIG_B_SU20_INFO_RESERVED_OFFSET 0x00000000
|
||||
#define VHT_SIG_B_SU20_INFO_RESERVED_LSB 26
|
||||
#define VHT_SIG_B_SU20_INFO_RESERVED_MSB 30
|
||||
#define VHT_SIG_B_SU20_INFO_RESERVED_MASK 0x7c000000
|
||||
|
||||
#define VHT_SIG_B_SU20_INFO_RX_NDP_OFFSET 0x00000000
|
||||
#define VHT_SIG_B_SU20_INFO_RX_NDP_LSB 31
|
||||
#define VHT_SIG_B_SU20_INFO_RX_NDP_MSB 31
|
||||
#define VHT_SIG_B_SU20_INFO_RX_NDP_MASK 0x80000000
|
||||
|
||||
#endif
|
||||
103
hw/kiwi/v2/vht_sig_b_su40_info.h
Normal file
103
hw/kiwi/v2/vht_sig_b_su40_info.h
Normal file
|
|
@ -0,0 +1,103 @@
|
|||
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
#ifndef _VHT_SIG_B_SU40_INFO_H_
|
||||
#define _VHT_SIG_B_SU40_INFO_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#define NUM_OF_DWORDS_VHT_SIG_B_SU40_INFO 2
|
||||
|
||||
struct vht_sig_b_su40_info {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t length : 19,
|
||||
vhtb_reserved : 2,
|
||||
tail : 6,
|
||||
reserved : 4,
|
||||
rx_ndp : 1;
|
||||
uint32_t length_copy : 19,
|
||||
vhtb_reserved_copy : 2,
|
||||
tail_copy : 6,
|
||||
reserved_copy : 4,
|
||||
rx_ndp_copy : 1;
|
||||
#else
|
||||
uint32_t rx_ndp : 1,
|
||||
reserved : 4,
|
||||
tail : 6,
|
||||
vhtb_reserved : 2,
|
||||
length : 19;
|
||||
uint32_t rx_ndp_copy : 1,
|
||||
reserved_copy : 4,
|
||||
tail_copy : 6,
|
||||
vhtb_reserved_copy : 2,
|
||||
length_copy : 19;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define VHT_SIG_B_SU40_INFO_LENGTH_OFFSET 0x00000000
|
||||
#define VHT_SIG_B_SU40_INFO_LENGTH_LSB 0
|
||||
#define VHT_SIG_B_SU40_INFO_LENGTH_MSB 18
|
||||
#define VHT_SIG_B_SU40_INFO_LENGTH_MASK 0x0007ffff
|
||||
|
||||
#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_OFFSET 0x00000000
|
||||
#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_LSB 19
|
||||
#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_MSB 20
|
||||
#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_MASK 0x00180000
|
||||
|
||||
#define VHT_SIG_B_SU40_INFO_TAIL_OFFSET 0x00000000
|
||||
#define VHT_SIG_B_SU40_INFO_TAIL_LSB 21
|
||||
#define VHT_SIG_B_SU40_INFO_TAIL_MSB 26
|
||||
#define VHT_SIG_B_SU40_INFO_TAIL_MASK 0x07e00000
|
||||
|
||||
#define VHT_SIG_B_SU40_INFO_RESERVED_OFFSET 0x00000000
|
||||
#define VHT_SIG_B_SU40_INFO_RESERVED_LSB 27
|
||||
#define VHT_SIG_B_SU40_INFO_RESERVED_MSB 30
|
||||
#define VHT_SIG_B_SU40_INFO_RESERVED_MASK 0x78000000
|
||||
|
||||
#define VHT_SIG_B_SU40_INFO_RX_NDP_OFFSET 0x00000000
|
||||
#define VHT_SIG_B_SU40_INFO_RX_NDP_LSB 31
|
||||
#define VHT_SIG_B_SU40_INFO_RX_NDP_MSB 31
|
||||
#define VHT_SIG_B_SU40_INFO_RX_NDP_MASK 0x80000000
|
||||
|
||||
#define VHT_SIG_B_SU40_INFO_LENGTH_COPY_OFFSET 0x00000004
|
||||
#define VHT_SIG_B_SU40_INFO_LENGTH_COPY_LSB 0
|
||||
#define VHT_SIG_B_SU40_INFO_LENGTH_COPY_MSB 18
|
||||
#define VHT_SIG_B_SU40_INFO_LENGTH_COPY_MASK 0x0007ffff
|
||||
|
||||
#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_COPY_OFFSET 0x00000004
|
||||
#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_COPY_LSB 19
|
||||
#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_COPY_MSB 20
|
||||
#define VHT_SIG_B_SU40_INFO_VHTB_RESERVED_COPY_MASK 0x00180000
|
||||
|
||||
#define VHT_SIG_B_SU40_INFO_TAIL_COPY_OFFSET 0x00000004
|
||||
#define VHT_SIG_B_SU40_INFO_TAIL_COPY_LSB 21
|
||||
#define VHT_SIG_B_SU40_INFO_TAIL_COPY_MSB 26
|
||||
#define VHT_SIG_B_SU40_INFO_TAIL_COPY_MASK 0x07e00000
|
||||
|
||||
#define VHT_SIG_B_SU40_INFO_RESERVED_COPY_OFFSET 0x00000004
|
||||
#define VHT_SIG_B_SU40_INFO_RESERVED_COPY_LSB 27
|
||||
#define VHT_SIG_B_SU40_INFO_RESERVED_COPY_MSB 30
|
||||
#define VHT_SIG_B_SU40_INFO_RESERVED_COPY_MASK 0x78000000
|
||||
|
||||
#define VHT_SIG_B_SU40_INFO_RX_NDP_COPY_OFFSET 0x00000004
|
||||
#define VHT_SIG_B_SU40_INFO_RX_NDP_COPY_LSB 31
|
||||
#define VHT_SIG_B_SU40_INFO_RX_NDP_COPY_MSB 31
|
||||
#define VHT_SIG_B_SU40_INFO_RX_NDP_COPY_MASK 0x80000000
|
||||
|
||||
#endif
|
||||
173
hw/kiwi/v2/vht_sig_b_su80_info.h
Normal file
173
hw/kiwi/v2/vht_sig_b_su80_info.h
Normal file
|
|
@ -0,0 +1,173 @@
|
|||
|
||||
/*
|
||||
* Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
#ifndef _VHT_SIG_B_SU80_INFO_H_
|
||||
#define _VHT_SIG_B_SU80_INFO_H_
|
||||
#if !defined(__ASSEMBLER__)
|
||||
#endif
|
||||
|
||||
#define NUM_OF_DWORDS_VHT_SIG_B_SU80_INFO 4
|
||||
|
||||
struct vht_sig_b_su80_info {
|
||||
#ifndef WIFI_BIT_ORDER_BIG_ENDIAN
|
||||
uint32_t length : 21,
|
||||
vhtb_reserved : 2,
|
||||
tail : 6,
|
||||
reserved_0 : 2,
|
||||
rx_ndp : 1;
|
||||
uint32_t length_copy_a : 21,
|
||||
vhtb_reserved_copy_a : 2,
|
||||
tail_copy_a : 6,
|
||||
reserved_1 : 2,
|
||||
rx_ndp_copy_a : 1;
|
||||
uint32_t length_copy_b : 21,
|
||||
vhtb_reserved_copy_b : 2,
|
||||
tail_copy_b : 6,
|
||||
reserved_2 : 2,
|
||||
rx_ndp_copy_b : 1;
|
||||
uint32_t length_copy_c : 21,
|
||||
vhtb_reserved_copy_c : 2,
|
||||
tail_copy_c : 6,
|
||||
reserved_3 : 2,
|
||||
rx_ndp_copy_c : 1;
|
||||
#else
|
||||
uint32_t rx_ndp : 1,
|
||||
reserved_0 : 2,
|
||||
tail : 6,
|
||||
vhtb_reserved : 2,
|
||||
length : 21;
|
||||
uint32_t rx_ndp_copy_a : 1,
|
||||
reserved_1 : 2,
|
||||
tail_copy_a : 6,
|
||||
vhtb_reserved_copy_a : 2,
|
||||
length_copy_a : 21;
|
||||
uint32_t rx_ndp_copy_b : 1,
|
||||
reserved_2 : 2,
|
||||
tail_copy_b : 6,
|
||||
vhtb_reserved_copy_b : 2,
|
||||
length_copy_b : 21;
|
||||
uint32_t rx_ndp_copy_c : 1,
|
||||
reserved_3 : 2,
|
||||
tail_copy_c : 6,
|
||||
vhtb_reserved_copy_c : 2,
|
||||
length_copy_c : 21;
|
||||
#endif
|
||||
};
|
||||
|
||||
#define VHT_SIG_B_SU80_INFO_LENGTH_OFFSET 0x00000000
|
||||
#define VHT_SIG_B_SU80_INFO_LENGTH_LSB 0
|
||||
#define VHT_SIG_B_SU80_INFO_LENGTH_MSB 20
|
||||
#define VHT_SIG_B_SU80_INFO_LENGTH_MASK 0x001fffff
|
||||
|
||||
#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_OFFSET 0x00000000
|
||||
#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_LSB 21
|
||||
#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_MSB 22
|
||||
#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_MASK 0x00600000
|
||||
|
||||
#define VHT_SIG_B_SU80_INFO_TAIL_OFFSET 0x00000000
|
||||
#define VHT_SIG_B_SU80_INFO_TAIL_LSB 23
|
||||
#define VHT_SIG_B_SU80_INFO_TAIL_MSB 28
|
||||
#define VHT_SIG_B_SU80_INFO_TAIL_MASK 0x1f800000
|
||||
|
||||
#define VHT_SIG_B_SU80_INFO_RESERVED_0_OFFSET 0x00000000
|
||||
#define VHT_SIG_B_SU80_INFO_RESERVED_0_LSB 29
|
||||
#define VHT_SIG_B_SU80_INFO_RESERVED_0_MSB 30
|
||||
#define VHT_SIG_B_SU80_INFO_RESERVED_0_MASK 0x60000000
|
||||
|
||||
#define VHT_SIG_B_SU80_INFO_RX_NDP_OFFSET 0x00000000
|
||||
#define VHT_SIG_B_SU80_INFO_RX_NDP_LSB 31
|
||||
#define VHT_SIG_B_SU80_INFO_RX_NDP_MSB 31
|
||||
#define VHT_SIG_B_SU80_INFO_RX_NDP_MASK 0x80000000
|
||||
|
||||
#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_A_OFFSET 0x00000004
|
||||
#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_A_LSB 0
|
||||
#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_A_MSB 20
|
||||
#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_A_MASK 0x001fffff
|
||||
|
||||
#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_A_OFFSET 0x00000004
|
||||
#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_A_LSB 21
|
||||
#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_A_MSB 22
|
||||
#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_A_MASK 0x00600000
|
||||
|
||||
#define VHT_SIG_B_SU80_INFO_TAIL_COPY_A_OFFSET 0x00000004
|
||||
#define VHT_SIG_B_SU80_INFO_TAIL_COPY_A_LSB 23
|
||||
#define VHT_SIG_B_SU80_INFO_TAIL_COPY_A_MSB 28
|
||||
#define VHT_SIG_B_SU80_INFO_TAIL_COPY_A_MASK 0x1f800000
|
||||
|
||||
#define VHT_SIG_B_SU80_INFO_RESERVED_1_OFFSET 0x00000004
|
||||
#define VHT_SIG_B_SU80_INFO_RESERVED_1_LSB 29
|
||||
#define VHT_SIG_B_SU80_INFO_RESERVED_1_MSB 30
|
||||
#define VHT_SIG_B_SU80_INFO_RESERVED_1_MASK 0x60000000
|
||||
|
||||
#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_A_OFFSET 0x00000004
|
||||
#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_A_LSB 31
|
||||
#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_A_MSB 31
|
||||
#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_A_MASK 0x80000000
|
||||
|
||||
#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_B_OFFSET 0x00000008
|
||||
#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_B_LSB 0
|
||||
#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_B_MSB 20
|
||||
#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_B_MASK 0x001fffff
|
||||
|
||||
#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_B_OFFSET 0x00000008
|
||||
#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_B_LSB 21
|
||||
#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_B_MSB 22
|
||||
#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_B_MASK 0x00600000
|
||||
|
||||
#define VHT_SIG_B_SU80_INFO_TAIL_COPY_B_OFFSET 0x00000008
|
||||
#define VHT_SIG_B_SU80_INFO_TAIL_COPY_B_LSB 23
|
||||
#define VHT_SIG_B_SU80_INFO_TAIL_COPY_B_MSB 28
|
||||
#define VHT_SIG_B_SU80_INFO_TAIL_COPY_B_MASK 0x1f800000
|
||||
|
||||
#define VHT_SIG_B_SU80_INFO_RESERVED_2_OFFSET 0x00000008
|
||||
#define VHT_SIG_B_SU80_INFO_RESERVED_2_LSB 29
|
||||
#define VHT_SIG_B_SU80_INFO_RESERVED_2_MSB 30
|
||||
#define VHT_SIG_B_SU80_INFO_RESERVED_2_MASK 0x60000000
|
||||
|
||||
#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_B_OFFSET 0x00000008
|
||||
#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_B_LSB 31
|
||||
#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_B_MSB 31
|
||||
#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_B_MASK 0x80000000
|
||||
|
||||
#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_C_OFFSET 0x0000000c
|
||||
#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_C_LSB 0
|
||||
#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_C_MSB 20
|
||||
#define VHT_SIG_B_SU80_INFO_LENGTH_COPY_C_MASK 0x001fffff
|
||||
|
||||
#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_C_OFFSET 0x0000000c
|
||||
#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_C_LSB 21
|
||||
#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_C_MSB 22
|
||||
#define VHT_SIG_B_SU80_INFO_VHTB_RESERVED_COPY_C_MASK 0x00600000
|
||||
|
||||
#define VHT_SIG_B_SU80_INFO_TAIL_COPY_C_OFFSET 0x0000000c
|
||||
#define VHT_SIG_B_SU80_INFO_TAIL_COPY_C_LSB 23
|
||||
#define VHT_SIG_B_SU80_INFO_TAIL_COPY_C_MSB 28
|
||||
#define VHT_SIG_B_SU80_INFO_TAIL_COPY_C_MASK 0x1f800000
|
||||
|
||||
#define VHT_SIG_B_SU80_INFO_RESERVED_3_OFFSET 0x0000000c
|
||||
#define VHT_SIG_B_SU80_INFO_RESERVED_3_LSB 29
|
||||
#define VHT_SIG_B_SU80_INFO_RESERVED_3_MSB 30
|
||||
#define VHT_SIG_B_SU80_INFO_RESERVED_3_MASK 0x60000000
|
||||
|
||||
#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_C_OFFSET 0x0000000c
|
||||
#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_C_LSB 31
|
||||
#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_C_MSB 31
|
||||
#define VHT_SIG_B_SU80_INFO_RX_NDP_COPY_C_MASK 0x80000000
|
||||
|
||||
#endif
|
||||
Loading…
Reference in a new issue