From 6492d16d8bf8438cb59c63d242a2585c650117a5 Mon Sep 17 00:00:00 2001 From: Huang Yiwei Date: Fri, 10 Jul 2020 17:52:34 +0800 Subject: [PATCH 001/103] dt-bindings: ramoops: Add mem-type bindings snapshot Add mem-type bindings snapshot to ramoops. This option is used to determine the memory type of reserved region. It is compatible with existing option and provide another full cached memory type. Change-Id: I6a545e6f0ce26904c753b23404bc1e6bc1faaebb --- bindings/reserved-memory/ramoops.txt | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/bindings/reserved-memory/ramoops.txt b/bindings/reserved-memory/ramoops.txt index 0eba562fe5c6..c0db67bec227 100644 --- a/bindings/reserved-memory/ramoops.txt +++ b/bindings/reserved-memory/ramoops.txt @@ -45,6 +45,12 @@ Optional properties: - unbuffered: if present, use unbuffered mappings to map the reserved region (defaults to buffered mappings) +- mem-type: determine the memory type of the reserved region, compatible with + , 0: writecombine(same as is not set), 1: noncached + (same as is set), 2: normal memory(fully cached for better + performance) + (defaults to 0: writecombine) + - no-dump-oops: if present, only dump panics (defaults to panics and oops) - flags: if present, pass ramoops behavioral flags (defaults to 0, From 02878921f6fcecc11dcc78dc9aee0542a1dfa954 Mon Sep 17 00:00:00 2001 From: Naveen Yadav Date: Mon, 20 Apr 2020 01:39:26 +0530 Subject: [PATCH 002/103] dt-bindings: Add support for GDSC flag to skip disable Add new gdsc flag "qcom,skip-disable-before-sw-enable" to skip the GDSC disable call in case if the gdsc is enabled by entity external to HLOS. Change-Id: I2519c1b7a36a5b89df1a92c1c39f5f3413927548 --- bindings/regulator/gdsc-regulator.txt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/bindings/regulator/gdsc-regulator.txt b/bindings/regulator/gdsc-regulator.txt index 1d3f65a75b74..0234b27be56c 100644 --- a/bindings/regulator/gdsc-regulator.txt +++ b/bindings/regulator/gdsc-regulator.txt @@ -55,6 +55,9 @@ Optional properties: - reset-names: reset signal name strings sorted in the same order as the resets property. These can be supplied only if we support qcom,skip-logic-collapse. + - qcom,skip-disable-before-sw-enable : Presence denotes a hardware requirement + to leave the GDSC on that has been + enabled by an entity external to HLOS. Example: gdsc_oxili_gx: qcom,gdsc@fd8c4024 { From 6cde4d7b06955de643844049b376cec8590e65b8 Mon Sep 17 00:00:00 2001 From: Mike Tipton Date: Wed, 12 Aug 2020 22:50:21 -0700 Subject: [PATCH 003/103] ARM: dts: msm: Add resources for Lahaina CC runtime_pm Add necessary clock and interconnect resources for runtime_pm of CAM_CC, DISP_CC, and VIDEO_CC. Change-Id: Iadb7650c5909d276f7a4f58fb895e9d621120b6b --- qcom/lahaina.dtsi | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/qcom/lahaina.dtsi b/qcom/lahaina.dtsi index a5ee90add681..979c9e5ded95 100644 --- a/qcom/lahaina.dtsi +++ b/qcom/lahaina.dtsi @@ -2330,8 +2330,9 @@ reg-name = "cc_base"; vdd_mm-supply = <&VDD_MM_LEVEL>; vdd_mx-supply = <&VDD_MXA_LEVEL>; - clock-names = "cfg_ahb_clk"; + interconnects = <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_VENUS_CFG>; clocks = <&clock_gcc GCC_VIDEO_AHB_CLK>; + clock-names = "iface"; #clock-cells = <1>; #reset-cells = <1>; }; @@ -2342,8 +2343,9 @@ reg-names = "cc_base"; vdd_mm-supply = <&VDD_MM_LEVEL>; vdd_mx-supply = <&VDD_MXA_LEVEL>; - clock-names = "cfg_ahb_clk"; + interconnects = <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_CAMERA_CFG>; clocks = <&clock_gcc GCC_CAMERA_AHB_CLK>; + clock-names = "iface"; #clock-cells = <1>; #reset-cells = <1>; }; @@ -2353,8 +2355,9 @@ reg = <0xaf00000 0x20000>; reg-name = "cc_base"; vdd_mm-supply = <&VDD_MM_LEVEL>; - clock-names = "cfg_ahb_clk"; + interconnects = <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_DISPLAY_CFG>; clocks = <&clock_gcc GCC_DISP_AHB_CLK>; + clock-names = "iface"; #clock-cells = <1>; #reset-cells = <1>; }; From 8ec1e5c371cd48819e98a967f812b83e0b0e73f4 Mon Sep 17 00:00:00 2001 From: Huang Yiwei Date: Fri, 10 Jul 2020 11:43:13 +0800 Subject: [PATCH 004/103] ARM: dts: msm: Add Pmesg Reserved Memory for shima Add Pmesg reserved memory to enable the function to collect user-space log in pstore. And the mem-type is set to 2 for better performance. Change-Id: I6b842a0df7f70e0ef00234649e244bb4156b3d85 --- qcom/shima.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi index 1b885982b7a2..259bdc6a3f9f 100644 --- a/qcom/shima.dtsi +++ b/qcom/shima.dtsi @@ -386,6 +386,13 @@ size = <0x0 0x1400000>; }; + qcom: ramoops { + compatible = "ramoops"; + reg = <0x0 0xa9000000 0x0 0x200000>; + pmsg-size = <0x200000>; + mem-type = <2>; + }; + /* global autoconfigured region for contiguous allocations */ linux,cma { compatible = "shared-dma-pool"; From c33bdf4e3f71d737019d0d4ab22776faea62d3ad Mon Sep 17 00:00:00 2001 From: Manikandan Mohan Date: Thu, 13 Aug 2020 23:06:32 -0700 Subject: [PATCH 005/103] ARM: dts: msm: Update cnss device tree node for interconnect paths Configure bandwidth vote data for individual platform interconnect paths. Change-Id: I875bad28fc271a318bf38c794f1599d55b1af330 --- bindings/cnss/cnss-wlan.txt | 4 +++- qcom/lahaina.dtsi | 40 ++++++++++++++++++++++++++----------- 2 files changed, 31 insertions(+), 13 deletions(-) diff --git a/bindings/cnss/cnss-wlan.txt b/bindings/cnss/cnss-wlan.txt index 6dcde8ad4264..2b7b43d31969 100644 --- a/bindings/cnss/cnss-wlan.txt +++ b/bindings/cnss/cnss-wlan.txt @@ -71,7 +71,9 @@ Optional properties: specifications, should be drived depending on products - qcom,wlan-cbc-enabled: boolean property to control cold boot calibration - interconnects: Interconnect framework setup for bus configuration - - qcom,bus-bw-cfg-num: Number of bus bandwidth voting cases + - interconnect-names: Interconnect path names as strings + - qcom,icc-path-count: Number of Interconnect paths for this platform + - qcom,bus-bw-cfg-count: Number of bus bandwidth voting cases - qcom,bus-bw-cfg: Bus bandwidth voting data - qcom,tcs_offset_int_pow_amp_vreg: TCS CMD register offset for Voltage regulator used in internal power amplifier for QCA6490 diff --git a/qcom/lahaina.dtsi b/qcom/lahaina.dtsi index a5ee90add681..cdeeca9c4250 100644 --- a/qcom/lahaina.dtsi +++ b/qcom/lahaina.dtsi @@ -5295,22 +5295,38 @@ wlan-ant-switch-supply = <&L7E>; qcom,wlan-ant-switch-config = <2800000 2800000 0 0 0>; - interconnects = <&aggre2_noc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>; - qcom,bus-bw-cfg-num = <7>; + interconnects = + <&aggre2_noc MASTER_PCIE_0 &aggre2_noc SLAVE_ANOC_PCIE_GEM_NOC>, + <&gem_noc MASTER_ANOC_PCIE_GEM_NOC &mc_virt SLAVE_EBI1>; + interconnect-names = "pcie_to_memnoc", "memnoc_to_ddr"; + + qcom,icc-path-count = <2>; + qcom,bus-bw-cfg-count = <7>; qcom,bus-bw-cfg = - /* no vote */ + /** ICC Path 1 **/ + <0 0>, /* no vote */ + /* idle: 0-18 Mbps snoc/anoc: 100 Mhz ddr: 451.2 MHz */ + <2250 390000>, + /* low: 18-60 Mbps snoc/anoc: 100 Mhz ddr: 451.2 MHz */ + <7500 390000>, + /* medium: 60-240 Mbps snoc/anoc: 200 Mhz ddr: 451.2 MHz */ + <30000 790000>, + /* high: 240-1080 Mbps snoc/anoc: 200 Mhz ddr: 451.2 MHz */ + <100000 790000>, + /* very high: > 1080 Mbps snoc/anoc: 403 Mhz ddr: 451.2 MHz */ + <175000 1600000>, + /* low (latency critical): 18-60 Mbps snoc/anoc: 200 Mhz + * ddr: 547.2 MHz + */ + <7500 390000>, + + /** ICC Path 2 **/ <0 0>, - /* idle: 0-18 Mbps ddr freq: 451.2 MHz */ - <2250 1600000>, - /* low: 18-60 Mbps ddr freq: 451.2 MHz */ - <7500 1600000>, - /* medium: 60-240 Mbps ddr freq: 451.2 MHz */ + <2250 1804800>, + <7500 1804800>, <30000 1804800>, - /* high: 240 - 1080 Mbps ddr freq: 451.2 MHz */ <100000 1804800>, - /* high: 1080 - 1400 Mbps ddr freq: 451.2 MHz */ - <175000 1804800>, - /* low (latency critical): 18 - 60 Mbps, ddr freq: 547.2 MHz */ + <175000 6220800>, <7500 2188800>; mhi,max-channels = <30>; From de07f53a52eca56ceeece66280a2d35a69ac0f6d Mon Sep 17 00:00:00 2001 From: "Tao,Zhang" Date: Mon, 24 Aug 2020 15:14:43 +0800 Subject: [PATCH 006/103] ARM: dts: msm: Modify reset cti to cti6 for shima Modify reset cti of tmc to cti6 for shima. Change-Id: I2a4e5a1d4a9a794d02333d17043c9d7171a212f7 --- qcom/shima-coresight.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/qcom/shima-coresight.dtsi b/qcom/shima-coresight.dtsi index 74d196646886..e6b90830fa55 100644 --- a/qcom/shima-coresight.dtsi +++ b/qcom/shima-coresight.dtsi @@ -107,7 +107,7 @@ coresight-name = "coresight-tmc-etf"; coresight-csr = <&swao_csr>; - coresight-ctis = <&cti0_swao &cti3_swao>; + coresight-ctis = <&cti0 &cti6>; clocks = <&aopcc QDSS_CLK>; clock-names = "apb_pclk"; @@ -154,7 +154,7 @@ qcom,sw-usb; coresight-name = "coresight-tmc-etr"; - coresight-ctis = <&cti0 &cti3_swao>; + coresight-ctis = <&cti0 &cti6>; coresight-csr = <&csr>; clocks = <&aopcc QDSS_CLK>; From 337a02b8e94f523298c9b2437b2525d1c8c1cc46 Mon Sep 17 00:00:00 2001 From: Mohammed Siddiq Date: Tue, 25 Aug 2020 15:20:45 +0530 Subject: [PATCH 007/103] ARM: dts: msm: Enable CNSS2 node for shima Enable CNSS2 device tree entry for shima. Change-Id: I869c8e018ce6bf2374de25075693e8222c8dc489 --- qcom/shima.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi index 5bac8606be0a..6dc42cebb0c9 100644 --- a/qcom/shima.dtsi +++ b/qcom/shima.dtsi @@ -3169,7 +3169,6 @@ }; wlan: qcom,cnss-qca6490@b0000000 { - status = "disabled"; compatible = "qcom,cnss-qca6490"; reg = <0xb0000000 0x10000>; reg-names = "smmu_iova_ipa"; From 4cb4b936dc907c00dc12b11f476c50ffc047ce91 Mon Sep 17 00:00:00 2001 From: Ram Chandrasekar Date: Tue, 25 Aug 2020 16:30:37 -0700 Subject: [PATCH 008/103] dt-bindings: thermal: sdpm: Add regulator phandle Certain domains regulator also needs to be monitored to vote for a frequency value of 0 when the domain is power collapsed. This property is optional only to the domains whose power state also needs to be monitored. Change-Id: I4be14fa4a0b1655290122ac4b0dd53ffe0d85a11 --- bindings/thermal/qcom-sdpm.txt | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/bindings/thermal/qcom-sdpm.txt b/bindings/thermal/qcom-sdpm.txt index 8a0a0f9fefc0..0bb0d20c4976 100644 --- a/bindings/thermal/qcom-sdpm.txt +++ b/bindings/thermal/qcom-sdpm.txt @@ -29,6 +29,13 @@ Properties: Value type: Definition: List of clock names matching the clock order mentioned in the clocks property. + +- -supply: + Usage: Optional + Value type: + Definition: phandle to the regulator device tree node that powers + this domain. + - cpu: Usage: optional Value type: @@ -46,9 +53,10 @@ Example: cx_sdpm@0x00634000 { compatible = "qcom,sdpm"; reg = <0x00634000 0x1000>; - clock-names = "cam_cc", "compo_aux"; + clock-names = "cam_cc_ipe", "compo_aux"; clocks = <&clock_camcc CAM_CC_IPE_0_CLK_SRC>, <&clk_m_a2_div1 CLK_M_COMPO_AUX>; + cam_cc_ipe-supply = <&cam_cc_ipe_0_gdsc>; cpu = <&CPU7>; csr-id = <5 7 4>; //CSR 5 <=> cam_cc From eefd9fa07d7f49722ac48856411e14c6c90a70b7 Mon Sep 17 00:00:00 2001 From: Krishna Manikandan Date: Fri, 28 Aug 2020 10:06:59 +0530 Subject: [PATCH 009/103] ARM: dts: qcom: add sde-rsc-rpmh driver to disp_rsc node Add sde rsc rpmhdriver as a child of display RSC. Change-Id: I5916fb67d45ef4f691756077acd7459b0cbdddec --- qcom/shima.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi index 4af7105c1cbf..75d35348d82c 100644 --- a/qcom/shima.dtsi +++ b/qcom/shima.dtsi @@ -1730,6 +1730,11 @@ compatible = "qcom,bcm-voter"; qcom,tcs-wait = ; }; + + sde_rsc_rpmh { + compatible = "qcom,sde-rsc-rpmh"; + cell-index = <0>; + }; }; spmi_bus: qcom,spmi@c440000 { From bc08a547f8be8000d253ab2904740f8af01c735e Mon Sep 17 00:00:00 2001 From: "Isaac J. Manjarres" Date: Fri, 28 Aug 2020 14:25:16 -0700 Subject: [PATCH 010/103] dt-bindings: Document the qcom,vmid-cp-camera-preview-ro property Document the qcom,vmid-cp-camera-preview-ro secure buffer property. This property is used to communicate to the secure buffer driver that buffers accessible to VMID_CP_CAMERA_PREVIEW should be mapped with read-only permissions. Change-Id: Ib867fd2a060448fc6996fddde6367fa4e6c1d5d8 --- bindings/soc/qcom/qcom,secure-buffer.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/bindings/soc/qcom/qcom,secure-buffer.yaml b/bindings/soc/qcom/qcom,secure-buffer.yaml index f4fc40003f2b..acf73ff89425 100644 --- a/bindings/soc/qcom/qcom,secure-buffer.yaml +++ b/bindings/soc/qcom/qcom,secure-buffer.yaml @@ -19,6 +19,12 @@ properties: items: - const: qcom,secure-buffer + qcom,vmid-cp-camera-preview-ro: + $ref: /schemas/types.yaml#/definitions/flag + description: + Buffers accessible to VMID_CP_CAMERA_PREVIEW must be mapped with + read-only permissions. + required: - compatible From 098d3b54d098f4171d7d72fd0debfe57c71665fe Mon Sep 17 00:00:00 2001 From: "Isaac J. Manjarres" Date: Fri, 28 Aug 2020 14:29:47 -0700 Subject: [PATCH 011/103] ARM: dts: msm: Enable qcom,vmid-cp-camera-preview-ro on Lahaina The secure camera preview pipeline on Lahaina has buffers that are shared by the display and secure camera hardware. On older architecture, the buffers were not shareable, as the display hardware needed write-access to the buffer, which could compromise the integrity of the data populated by the secure camera hardware. The display hardware on Lahaina has been upgraded, such that it no longer needs write-access to the buffer, which allows the buffer to be shared between both peripherals. Thus, ensure that the mappings for the display hardware on Lahaina are read-only, so that the integrity of the contents of the buffer cannot be compromised. Change-Id: Ib1f867e49455799acd8797a9d26a9243fb0546e7 --- qcom/lahaina.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/lahaina.dtsi b/qcom/lahaina.dtsi index aaa56c2436d4..6737fffeb8d3 100644 --- a/qcom/lahaina.dtsi +++ b/qcom/lahaina.dtsi @@ -2738,6 +2738,7 @@ qcom-secure-buffer { compatible = "qcom,secure-buffer"; + qcom,vmid-cp-camera-preview-ro; }; qcom-mem-buf { From a452e2201d5da55109b5e5314b6acc225543476c Mon Sep 17 00:00:00 2001 From: "Tao,Zhang" Date: Sat, 29 Aug 2020 11:10:40 +0800 Subject: [PATCH 012/103] ARM: dts: msm: Add transaction timeout config for shima Add transaction timeout config for shima. Set it to zero and doesn't write timeout value to register. Change-Id: I9750baac51b4406670bf453fc0efcc707486169d --- qcom/shima.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi index 4af7105c1cbf..bede9c52d7e3 100644 --- a/qcom/shima.dtsi +++ b/qcom/shima.dtsi @@ -605,6 +605,8 @@ reg = <0x117f000 0x1000>, <0x1112000 0x6000>; + qcom,transaction_timeout = <0>; + reg-names = "dcc-base", "dcc-ram-base"; dcc-ram-offset = <0x12000>; }; From 4bc5faf5f2cecd1b30ca580bc2cea6f29dce1693 Mon Sep 17 00:00:00 2001 From: Kiran Gunda Date: Thu, 20 Aug 2020 12:11:04 +0530 Subject: [PATCH 013/103] dt-bindings: backlight: Add DT bindings for qcom-spmi-wled driver Add DT bindings for Qualcomm SPMI WLED driver that supports controlling backlight for LCD panels that uses pmi8998, PM8150L and PM6150L. This is taken as a snapshot from msm-4.19 kernel 'commit 9b82b280d402 ("arm64: defconfig: Enable dm-snapshot")'. Change-Id: Ib32b1185e50032db66a5db833c2a39f92eafdfb4 --- bindings/leds/backlight/qcom-spmi-wled.txt | 303 +++++++++++++++++++++ 1 file changed, 303 insertions(+) create mode 100644 bindings/leds/backlight/qcom-spmi-wled.txt diff --git a/bindings/leds/backlight/qcom-spmi-wled.txt b/bindings/leds/backlight/qcom-spmi-wled.txt new file mode 100644 index 000000000000..a0447c6d6469 --- /dev/null +++ b/bindings/leds/backlight/qcom-spmi-wled.txt @@ -0,0 +1,303 @@ +Bindings for Qualcomm Technologies, Inc. WLED driver + +WLED (White Light Emitting Diode) driver is used for controlling display +backlight that is part of PMIC on Qualcomm Technologies, Inc. reference +platforms. The PMIC is connected to the host processor via SPMI bus. + +- compatible + Usage: required + Value type: + Definition: should be one of the below. + "qcom,pmi8998-spmi-wled", + "qcom,pm8150l-spmi-wled", + "qcom,pm6150l-spmi-wled" + "qcom,pm660l-spmi-wled" + +- reg + Usage: required + Value type: + Definition: Base address and size of the WLED modules. + +- reg-names + Usage: required + Value type: + Definition: Names associated with base addresses. should be + "wled-ctrl-base", "wled-sink-base". + +- interrupts + Usage: optional + Value type: + Definition: Interrupts associated with WLED. Interrupts can be + specified as per the encoding listed under + Documentation/devicetree/bindings/spmi/ + qcom,spmi-pmic-arb.txt. + +- interrupt-names + Usage: optional + Value type: + Definition: Interrupt names associated with the interrupts. + Currently supported interrupts are "sc-irq", "ovp-irq", + "pre-flash-irq" and "flash-irq". Pre_flash and flash + interrupts can be specified only for PMICs that has WLED5. + +- label + Usage: required + Value type: + Definition: The name of the backlight device. + +- default-brightness + Usage: optional + Value type: + Definition: Brightness value on boot. Default is 2048. + Range of values are: + For pmi8998, it is 0-4095. + For pm8150l, this can vary from 0-4095 or 0-32767 depending + on the brightness control mode. If CABC is enabled, 0-4095 + range is used. + +- max-brightness + Usage: optional + Value type: + Definition: Maximum brightness level. Allowed values are: + For pmi8998, it is 4095. + For pm8150l, this can be either 4095 or 32767. + If CABC is enabled, this is capped to 4095. + +- qcom,fs-current-limit + Usage: optional + Value type: + Definition: per-string full scale current limit in uA. value from + 0 to 30000 with 5000 uA resolution. Default: 25000 uA + +- qcom,boost-current-limit + Usage: optional + Value type: + Definition: ILIM threshold in mA. values are 105, 280, 450, 620, 970, + 1150, 1300, 1500. Default: 970 mA + +- qcom,switching-freq + Usage: optional + Value type: + Definition: Switching frequency in KHz. values are + 600, 640, 685, 738, 800, 872, 960, 1066, 1200, 1371, + 1600, 1920, 2400, 3200, 4800, 9600. + Default: 800 KHz + +- qcom,ovp + Usage: optional + Value type: + Definition: Over-voltage protection limit in mV. values are 31100, + 29600, 19600, 18100. + Default: 29600 mV + +- qcom,string-cfg + Usage: optional + Value type: + Definition: Bit mask of the WLED strings. Bit 0 to 3 indicates strings + 0 to 3 respectively. WLED module has four strings of leds + numbered from 0 to 3. Each string of leds are operated + individually. Specify the strings using the bit mask. Any + combination of led strings can be used. + Default value is 15 (b1111). + +- qcom,en-cabc + Usage: optional + Value type: + Definition: Specify if cabc (content adaptive backlight control) is + needed. + +- qcom,ext-pfet-sc-pro-en + Usage: optional + Value type: + Definition: Specify if external PFET control for short circuit + protection is needed. This is not applicable for PM8150L. + +- qcom,auto-calibration + Usage: optional + Value type: + Definition: Enables auto-calibration of the WLED sink configuration. + +- qcom,modulator-sel + Usage: optional + Value type: + Definition: Selects the modulator used for brightness modulation. + Allowed values are: + 0 - Modulator A + 1 - Modulator B + If not specified, then modulator A will be used by default. + This property is applicable only to WLED5 peripheral. + +- qcom,cabc-sel + Usage: optional + Value type: + Definition: Selects the CABC pin signal used for brightness modulation. + Allowed values are: + 0 - CABC disabled + 1 - CABC 1 + 2 - CABC 2 + 3 - External signal (e.g. LPG) is used for dimming + This property is applicable only to WLED5 peripheral. + +- qcom,pmic-revid + Usage: optional + Value type: + Definition: If specified, can be used to get PMIC revision information. + +- qcom,leds-per-string + Usage: optional + Value type: + Definition: If specified, can be used to calculate available current + during selfie flash operation. If not specified, available + current calculated is simply the configured threshold. + +Following properties are for child subnodes that are needed for WLED preflash +(or torch), flash and switch. These child subnodes can be specified only for +PMICs that has WLED5 (e.g. PM8150L). + +For wled_torch child subnode, + +- label + Usage: required + Value type: + Definition: Should be "torch". + +- qcom,default-led-trigger + Usage: optional + Value type: + Definition: Name for LED trigger. If unspecified, "wled_torch" is used. + +- qcom,wled-torch-fsc + Usage: optional + Value type: + Definition: WLED torch full scale current in mA. This configures the + maximum current allowed for torch device. Allowed values + are from 5 to 60 mA with a step of 5 mA. If not specified, + default value is set to 30 mA. + +- qcom,wled-torch-step + Usage: optional + Value type: + Definition: WLED torch step delay in us. This configures the step delay + when the output is ramped up to the desired target current. + Allowed values are from 50 to 400 us with a step of 50 us. + If not specified, default value is set to 200 us. + +- qcom,wled-torch-timer + Usage: optional + Value type: + Definition: WLED torch safety timer in ms. This configures the safety + timer to turn off torch automatically after timer expiry. + Allowed values are: 50, 100, 200, 400, 600, 800, 1000 and + 1200. If not specified, default value is set to 1200 ms. + +For wled_flash child subnode, + +- label + Usage: required + Value type: + Definition: Should be "flash". + +- qcom,default-led-trigger + Usage: optional + Value type: + Definition: Name for LED trigger. If unspecified, "wled_flash" is used. + +- qcom,wled-flash-fsc + Usage: optional + Value type: + Definition: WLED flash full scale current in mA. This configures the + maximum current allowed for flash device. Allowed values + are from 5 to 60 mA with a step of 5 mA. If not specified, + default value is set to 40 mA. + +- qcom,wled-flash-step + Usage: optional + Value type: + Definition: WLED flash step delay in us. This configures the step delay + when the output is ramped up to the desired target current. + Allowed values are from 50 to 400 us with a step of 50 us. + If not specified, default value is set to 200 us. + +- qcom,wled-flash-timer + Usage: optional + Value type: + Definition: WLED flash safety timer in ms. This configures the safety + timer to turn off flash automatically after timer expiry. + Allowed values are: 50, 100, 200, 400, 600, 800, 1000 and + 1200. If not specified, default value is set to 100 ms. + +For wled_switch child subnode, + +- label + Usage: required + Value type: + Definition: Should be "switch". + +- qcom,default-led-trigger + Usage: optional + Value type: + Definition: Name for LED trigger. If unspecified, "wled_switch" is + used. + +Example: + +qcom-wled@d800 { + compatible = "qcom,pmi8998-spmi-wled"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xd800 0xd900>; + reg-names = "wled-ctrl-base", "wled-sink-base"; + label = "backlight"; + + interrupts = <0x3 0xd8 0x2 IRQ_TYPE_EDGE_RISING>, + <0x3 0xd8 0x1 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "sc-irq", "ovp-irq"; + qcom,fs-current-limit = <25000>; + qcom,boost-current-limit = <970>; + qcom,switching-freq = <800>; + qcom,ovp = <29600>; + qcom,string-cfg = <15>; +}; + +qcom-wled@d800 { + compatible = "qcom,pm8150l-spmi-wled"; + #address-cells = <2>; + #size-cells = <0>; + reg = <0xd800 0x100>, <0xd900 0x100>; + reg-names = "wled-ctrl-base", "wled-sink-base"; + label = "backlight"; + + interrupts = <0x5 0xd8 0x1 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "ovp-irq"; + qcom,string-cfg = <7>; + + wled_torch: qcom,wled-torch { + label = "torch"; + qcom,wled-torch-fsc = <40>; + qcom,wled-torch-step = <300>; + qcom,wled-torch-timer = <600>; + }; + + wled_flash: qcom,wled-flash { + label = "flash"; + qcom,wled-flash-fsc = <60>; + qcom,wled-flash-step = <100>; + qcom,wled-flash-timer = <200>; + }; + + wled_switch: qcom,wled-switch { + label = "switch"; + }; +}; + +qcom,leds@d800 { + compatible = "qcom,pm660l-spmi-wled"; + reg = <0xd800 0x100>, + <0xd900 0x100>; + reg-names = "qpnp-wled-ctrl-base", + "qpnp-wled-sink-base"; + interrupts = <0x3 0xd8 0x1 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "ovp-irq"; + linux,name = "wled"; + linux,default-led-trigger = "bkl-trigger"; +}; From e73b86b7aea2ed5eb808a0507e1048506fcc607b Mon Sep 17 00:00:00 2001 From: David Collins Date: Mon, 31 Aug 2020 14:33:08 -0700 Subject: [PATCH 014/103] ARM: dts: msm: reduce S2E regulator minimum voltage for Lahaina Reduce the minimum allowed voltage for PMR735A SMPS 2 (S2E) to 500 mV so that retention voltage voting can be performed. Change-Id: Iba4800a371f7f421daa940f26b687ba9f239317e --- qcom/lahaina-regulators.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/lahaina-regulators.dtsi b/qcom/lahaina-regulators.dtsi index c7579bec6687..2176d9f1487d 100644 --- a/qcom/lahaina-regulators.dtsi +++ b/qcom/lahaina-regulators.dtsi @@ -826,7 +826,7 @@ S2E: pmr735a_s2: regulator-pmr735a-s2 { regulator-name = "pmr735a_s2"; qcom,set = ; - regulator-min-microvolt = <800000>; + regulator-min-microvolt = <500000>; regulator-max-microvolt = <976000>; qcom,init-voltage = <852000>; }; From ec67f3b01894b5362da599dbddd4a5406a2d7376 Mon Sep 17 00:00:00 2001 From: "Tao,Zhang" Date: Wed, 20 May 2020 13:47:51 +0800 Subject: [PATCH 015/103] ARM: dts: msm: Add jtagv8 devices for shima Jtagv8 driver can be used to save and restore debug and ETM registers across power collapse. Change-Id: If322843d066e77f5b3aa2b78f2c7b913f6418d8b --- qcom/shima.dtsi | 88 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 88 insertions(+) diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi index 4af7105c1cbf..ac2e12bd89ff 100644 --- a/qcom/shima.dtsi +++ b/qcom/shima.dtsi @@ -609,6 +609,94 @@ dcc-ram-offset = <0x12000>; }; + jtag_mm0: jtagmm@7040000 { + compatible = "qcom,jtagv8-mm"; + reg = <0x7040000 0x1000>; + reg-names = "etm-base"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "core_clk"; + + qcom,coresight-jtagmm-cpu = <&CPU0>; + }; + + jtag_mm1: jtagmm@7140000 { + compatible = "qcom,jtagv8-mm"; + reg = <0x7140000 0x1000>; + reg-names = "etm-base"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "core_clk"; + + qcom,coresight-jtagmm-cpu = <&CPU1>; + }; + + jtag_mm2: jtagmm@7240000 { + compatible = "qcom,jtagv8-mm"; + reg = <0x7240000 0x1000>; + reg-names = "etm-base"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "core_clk"; + + qcom,coresight-jtagmm-cpu = <&CPU2>; + }; + + jtag_mm3: jtagmm@7340000 { + compatible = "qcom,jtagv8-mm"; + reg = <0x7340000 0x1000>; + reg-names = "etm-base"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "core_clk"; + + qcom,coresight-jtagmm-cpu = <&CPU3>; + }; + + jtag_mm4: jtagmm@7440000 { + compatible = "qcom,jtagv8-mm"; + reg = <0x7440000 0x1000>; + reg-names = "etm-base"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "core_clk"; + + qcom,coresight-jtagmm-cpu = <&CPU4>; + }; + + jtag_mm5: jtagmm@7540000 { + compatible = "qcom,jtagv8-mm"; + reg = <0x7540000 0x1000>; + reg-names = "etm-base"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "core_clk"; + + qcom,coresight-jtagmm-cpu = <&CPU5>; + }; + + jtag_mm6: jtagmm@7640000 { + compatible = "qcom,jtagv8-mm"; + reg = <0x7640000 0x1000>; + reg-names = "etm-base"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "core_clk"; + + qcom,coresight-jtagmm-cpu = <&CPU6>; + }; + + jtag_mm7: jtagmm@7740000 { + compatible = "qcom,jtagv8-mm"; + reg = <0x7740000 0x1000>; + reg-names = "etm-base"; + + clocks = <&aopcc QDSS_CLK>; + clock-names = "core_clk"; + + qcom,coresight-jtagmm-cpu = <&CPU7>; + }; + kryo-erp { compatible = "arm,arm64-kryo-cpu-erp"; interrupts = , From 23a03965875cb9989241e6de8feb6861aa3ba045 Mon Sep 17 00:00:00 2001 From: Faiyaz Mohammed Date: Tue, 1 Sep 2020 10:19:20 +0530 Subject: [PATCH 016/103] ARM: dts: msm: Add the offlineable memory sizes for Shima Add the device-tree node for the mem-offline driver to convey the sizes of the offlineable memory. Change-Id: If70f8bb53c238410f7d9ad307d7e42d78bcb6ec5 --- qcom/shima.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi index 4af7105c1cbf..acae77e45002 100644 --- a/qcom/shima.dtsi +++ b/qcom/shima.dtsi @@ -33,6 +33,15 @@ #size-cells = <2>; memory { device_type = "memory"; reg = <0 0 0 0>; }; + mem-offline { + compatible = "qcom,mem-offline"; + offline-sizes = <0x1 0x40000000 0x0 0x40000000>, + <0x1 0xc0000000 0x0 0x80000000>, + <0x2 0xc0000000 0x1 0x40000000>; + granule = <512>; + mboxes = <&qmp_aop 0>; + }; + aliases { ufshc1 = &ufshc_mem; /* Embedded UFS Slot */ sdhc1 = &sdhc_1; /*SDC1 eMMC slot*/ From 8c9af21bdd37b15e27816f2632524eff3d65a328 Mon Sep 17 00:00:00 2001 From: Praveen Kurapati Date: Tue, 25 Aug 2020 19:53:30 +0530 Subject: [PATCH 017/103] ARM: dts: msm: Enable ep delay for holi Add support for enabling endpoint delay for holi target. Change-Id: Icdafab5a24b8cc3bb7042e7abc81195bec71aef3 --- qcom/holi.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/holi.dtsi b/qcom/holi.dtsi index d40ab330e2a6..dfc656f2732f 100644 --- a/qcom/holi.dtsi +++ b/qcom/holi.dtsi @@ -2602,6 +2602,7 @@ qcom,lan-rx-napi; qcom,wan-use-skb-page; qcom,rmnet-ctl-enable; + qcom,ipa-endp-delay-wa; qcom,tx-wrapper-cache-max-size = <400>; clock-names = "core_clk"; clocks = <&rpmcc RPM_SMD_IPA_CLK>; From e866f533b894a597677a6c55468b1c341dd6727d Mon Sep 17 00:00:00 2001 From: "Tao,Zhang" Date: Tue, 1 Sep 2020 14:29:38 +0800 Subject: [PATCH 018/103] ARM: dts: msm: add osm register to minidump for shima Add osm register to minidump on shima for new feature. Change-Id: Ie344a26f5a081b966313c3e051279f706c223632 --- qcom/shima.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi index ac2e12bd89ff..37cbb561e643 100644 --- a/qcom/shima.dtsi +++ b/qcom/shima.dtsi @@ -3293,6 +3293,11 @@ qcom,dump-id = <0x104>; }; + osm_reg { + qcom,dump-size = <0x400>; + qcom,dump-id = <0x163>; + }; + pcu_reg { qcom,dump-size = <0x400>; qcom,dump-id = <0x164>; From 16b7be13acf6de291351db91061e8f5456aa624d Mon Sep 17 00:00:00 2001 From: Fenglin Wu Date: Mon, 17 Aug 2020 13:12:47 +0800 Subject: [PATCH 019/103] bindings: qcom-hv-haptics: add PBS device for triggering ISC config ISC (short circuit current) config for LRA impedance detection need to be set by triggering a PBS sequence. Add the PBS device information for this. Change-Id: I475c76a96d609d3aa67dd89f8f4bc9ef856cf1d6 --- bindings/input/qcom-hv-haptics.txt | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/bindings/input/qcom-hv-haptics.txt b/bindings/input/qcom-hv-haptics.txt index cea8fc575603..128e9266baac 100644 --- a/bindings/input/qcom-hv-haptics.txt +++ b/bindings/input/qcom-hv-haptics.txt @@ -112,6 +112,13 @@ Properties: Definition: Phandle of the nvmem device used for haptics configuration. Please refer to nvmem bindings as described in bindings/nvmem/nvmem.txt. +- qcom,pbs-client: + Usage: optional + Value type: + Definition: Phandle of the PBS client used for triggering PBS to configure + haptics ISC (short circuit current) config during LRA impedance + detection. + The following properties are only required when LRA actuator is used: - qcom,lra-period-us: @@ -262,6 +269,7 @@ Example: nvmem-cells = <&hap_cl_brake>; nvmem-names = "hap_cfg_sdam"; nvmem = <&pmk8350_sdam_46>; + qcom,pbs-client = <&pm8350b_pbs2>; qcom,vmax-mv = <900>; qcom,brake-mode = ; qcom,brake-pattern = /bits/ 8 <0xff 0x3f 0x1f>; From 0ac2ac10535764805b9b8ef8f62ef13c6b18fb8f Mon Sep 17 00:00:00 2001 From: Fenglin Wu Date: Mon, 17 Aug 2020 13:25:47 +0800 Subject: [PATCH 020/103] ARM: dts: msm: add PBS device for PM8350B haptics ISC config Add PBS device for triggering PBS to configure haptics ISC config during LRA impedance detection sequence. Change-Id: Ibf17b5081c0ddd2fc4ab5778e2c7aa62e8be57f4 --- qcom/lahaina-pmic-overlay.dtsi | 1 + qcom/pm8350b.dtsi | 5 +++++ 2 files changed, 6 insertions(+) diff --git a/qcom/lahaina-pmic-overlay.dtsi b/qcom/lahaina-pmic-overlay.dtsi index 04f9febe27b1..28c0947af072 100644 --- a/qcom/lahaina-pmic-overlay.dtsi +++ b/qcom/lahaina-pmic-overlay.dtsi @@ -354,6 +354,7 @@ nvmem-cells = <&hap_cl_brake>; nvmem-names = "hap_cfg_sdam"; nvmem = <&pmk8350_sdam_46>; + qcom,pbs-client = <&pm8350b_pbs2>; }; &pmr735a_tz { diff --git a/qcom/pm8350b.dtsi b/qcom/pm8350b.dtsi index aa966642e70e..c9110d289922 100644 --- a/qcom/pm8350b.dtsi +++ b/qcom/pm8350b.dtsi @@ -21,6 +21,11 @@ #thermal-sensor-cells = <0>; }; + pm8350b_pbs2: qcom,pbs@1900 { + compatible = "qcom,qpnp-pbs"; + reg = <0x1900>; + }; + pm8350b_gpios: pinctrl@8800 { compatible = "qcom,pm8350b-gpio"; reg = <0x8800>; From 968974fb97f230873c459f34f35e322c4d64ea70 Mon Sep 17 00:00:00 2001 From: Jishnu Prakash Date: Tue, 1 Sep 2020 16:50:39 +0530 Subject: [PATCH 021/103] ARM: dts: msm: Add dpdm supply for PM7250b for holi Add dpdm supply for PM7250b for holi. Change-Id: Id860c355a7d92a6ac607e041eaece5e2e0dde1c9 --- qcom/holi-atp.dtsi | 2 ++ qcom/holi-cdp.dtsi | 2 ++ qcom/holi-mtp-usbc.dtsi | 2 ++ qcom/holi-mtp.dtsi | 2 ++ qcom/holi-qrd.dtsi | 2 ++ 5 files changed, 10 insertions(+) diff --git a/qcom/holi-atp.dtsi b/qcom/holi-atp.dtsi index ab7daf265da5..61266afe5746 100644 --- a/qcom/holi-atp.dtsi +++ b/qcom/holi-atp.dtsi @@ -246,6 +246,8 @@ }; &pm7250b_charger { + dpdm-supply = <&qusb_phy0>; + smb5_vbus: qcom,smb5-vbus { regulator-name = "smb5-vbus"; }; diff --git a/qcom/holi-cdp.dtsi b/qcom/holi-cdp.dtsi index d7e950570492..b1379debf603 100644 --- a/qcom/holi-cdp.dtsi +++ b/qcom/holi-cdp.dtsi @@ -237,6 +237,8 @@ #include "camera/holi-camera-sensor-cdp.dtsi" &pm7250b_charger { + dpdm-supply = <&qusb_phy0>; + smb5_vbus: qcom,smb5-vbus { regulator-name = "smb5-vbus"; }; diff --git a/qcom/holi-mtp-usbc.dtsi b/qcom/holi-mtp-usbc.dtsi index ede4c9f9c84b..bfb99171157a 100644 --- a/qcom/holi-mtp-usbc.dtsi +++ b/qcom/holi-mtp-usbc.dtsi @@ -201,6 +201,8 @@ }; &pm7250b_charger { + dpdm-supply = <&qusb_phy0>; + smb5_vbus: qcom,smb5-vbus { regulator-name = "smb5-vbus"; }; diff --git a/qcom/holi-mtp.dtsi b/qcom/holi-mtp.dtsi index 23e65b9e01d7..1bf80cf75004 100644 --- a/qcom/holi-mtp.dtsi +++ b/qcom/holi-mtp.dtsi @@ -256,6 +256,8 @@ #include "camera/holi-camera-sensor-mtp.dtsi" &pm7250b_charger { + dpdm-supply = <&qusb_phy0>; + smb5_vbus: qcom,smb5-vbus { regulator-name = "smb5-vbus"; }; diff --git a/qcom/holi-qrd.dtsi b/qcom/holi-qrd.dtsi index ff21d1605104..e8ac31401e88 100644 --- a/qcom/holi-qrd.dtsi +++ b/qcom/holi-qrd.dtsi @@ -330,6 +330,8 @@ }; &pm7250b_charger { + dpdm-supply = <&qusb_phy0>; + smb5_vbus: qcom,smb5-vbus { regulator-name = "smb5-vbus"; }; From 6f119bf8a65f4474af369adf050f5ff5f580ea8f Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Tue, 1 Sep 2020 17:59:06 +0530 Subject: [PATCH 022/103] bindings: clock: rpmcc: Add clk handoff property Add this optional property in the case where the driver needs to send initial high votes to RPM. Change-Id: Ic08dec9a8ff440816389fc7c7548365c72dced42 --- bindings/clock/qcom,rpmcc.txt | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/bindings/clock/qcom,rpmcc.txt b/bindings/clock/qcom,rpmcc.txt index 3fba2772a36d..498c5389a4a8 100644 --- a/bindings/clock/qcom,rpmcc.txt +++ b/bindings/clock/qcom,rpmcc.txt @@ -30,6 +30,10 @@ suspended or in deep idle. If it is important that the clock keeps running during system suspend, you need to specify the non-active clock, the one not containing *_A_* in the enumerator name. +Optional properties: +- qcom,hw-clk-handoff : Add this property to support initial high votes on the + to be sent to RPM as proxy votes. + Example: smd { compatible = "qcom,smd"; From adc1cd257234fddedb0166f0ed7ebdc989ab8d00 Mon Sep 17 00:00:00 2001 From: Jishnu Prakash Date: Wed, 2 Sep 2020 11:41:52 +0530 Subject: [PATCH 023/103] dt-bindings: backlight: Update qcom-spmi-wled DT bindings Add IIO properties io-channels and io-channel-names, which may be used for WLED to read QG channels. While at it, remove usage of PMIC revid. Change-Id: Ib8503190f0012b85016231d9697c65407ac01a47 --- bindings/leds/backlight/qcom-spmi-wled.txt | 25 +++++++++++++++++----- 1 file changed, 20 insertions(+), 5 deletions(-) diff --git a/bindings/leds/backlight/qcom-spmi-wled.txt b/bindings/leds/backlight/qcom-spmi-wled.txt index a0447c6d6469..5ef7ce36d223 100644 --- a/bindings/leds/backlight/qcom-spmi-wled.txt +++ b/bindings/leds/backlight/qcom-spmi-wled.txt @@ -138,11 +138,6 @@ platforms. The PMIC is connected to the host processor via SPMI bus. 3 - External signal (e.g. LPG) is used for dimming This property is applicable only to WLED5 peripheral. -- qcom,pmic-revid - Usage: optional - Value type: - Definition: If specified, can be used to get PMIC revision information. - - qcom,leds-per-string Usage: optional Value type: @@ -150,6 +145,18 @@ platforms. The PMIC is connected to the host processor via SPMI bus. during selfie flash operation. If not specified, available current calculated is simply the configured threshold. +- io-channels + Usage: optional + Value type: + Definition: IIO channel specifiers for each name in io-channel-names. + +- io-channel-names + Usage: optional + Value type: + Definition: Names of the IIO channels that are used by WLED. + For details about IIO bindings see: + Documentation/devicetree/bindings/iio/iio-bindings.txt + Following properties are for child subnodes that are needed for WLED preflash (or torch), flash and switch. These child subnodes can be specified only for PMICs that has WLED5 (e.g. PM8150L). @@ -271,6 +278,14 @@ qcom-wled@d800 { interrupt-names = "ovp-irq"; qcom,string-cfg = <7>; + io-channels = <&pm7250b_qg PSY_IIO_RESISTANCE>, + <&pm7250b_qg PSY_IIO_VOLTAGE_OCV>, + <&pm7250b_qg PSY_IIO_CURRENT_NOW>; + + io-channel-names = "rbatt", + "voltage_ocv", + "current_now"; + wled_torch: qcom,wled-torch { label = "torch"; qcom,wled-torch-fsc = <40>; From 70c5ddb1f717403badb64ceba10f9a5f4d246e99 Mon Sep 17 00:00:00 2001 From: Jishnu Prakash Date: Mon, 31 Aug 2020 22:30:30 +0530 Subject: [PATCH 024/103] ARM: dts: msm: Add WLED support on PM6150l for holi Add WLED support on PM6150l for holi. Also add QG IIO channels required by WLED. Change-Id: Ia43387d875abf0365e68f77afb5775c25d2d9f9d --- qcom/holi-pmic-overlay.dtsi | 9 +++++++++ qcom/pm6150l.dtsi | 30 ++++++++++++++++++++++++++++++ 2 files changed, 39 insertions(+) diff --git a/qcom/holi-pmic-overlay.dtsi b/qcom/holi-pmic-overlay.dtsi index fdea52c3dee0..7935292f7f9c 100644 --- a/qcom/holi-pmic-overlay.dtsi +++ b/qcom/holi-pmic-overlay.dtsi @@ -259,6 +259,15 @@ "flash_active"; }; +&pm6150l_wled { + io-channels = <&pm7250b_qg PSY_IIO_RESISTANCE>, + <&pm7250b_qg PSY_IIO_VOLTAGE_OCV>, + <&pm7250b_qg PSY_IIO_CURRENT_NOW>; + io-channel-names = "rbatt", + "voltage_ocv", + "current_now"; +}; + &thermal_zones { chg-skin-therm-usr { polling-delay-passive = <0>; diff --git a/qcom/pm6150l.dtsi b/qcom/pm6150l.dtsi index 9d98f0d301e0..4608262095b2 100644 --- a/qcom/pm6150l.dtsi +++ b/qcom/pm6150l.dtsi @@ -281,6 +281,36 @@ }; }; + pm6150l_wled: qcom,wled@d800 { + compatible = "qcom,pm6150l-spmi-wled"; + reg = <0xd800>, <0xd900>; + reg-names = "wled-ctrl-base", "wled-sink-base"; + label = "backlight"; + interrupts = <0x5 0xd8 0x1 IRQ_TYPE_EDGE_RISING>, + <0x5 0xd8 0x4 IRQ_TYPE_EDGE_BOTH>, + <0x5 0xd8 0x5 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "ovp-irq", "pre-flash-irq", + "flash-irq"; + qcom,auto-calibration; + status = "disabled"; + + wled_flash: qcom,wled-flash { + label = "flash"; + qcom,default-led-trigger = "wled_flash"; + }; + + wled_torch: qcom,wled-torch { + label = "torch"; + qcom,default-led-trigger = "wled_torch"; + qcom,wled-torch-timer = <1200>; + }; + + wled_switch: qcom,wled-switch { + label = "switch"; + qcom,default-led-trigger = "wled_switch"; + }; + }; + pm6150l_lpg: qcom,pwms@b100 { compatible = "qcom,pwm-lpg"; reg = <0xb100 0x300>, <0xb000 0x100>; From d325771eae38250d95811f779cf4e76d35da6fdc Mon Sep 17 00:00:00 2001 From: Vatsal Bucha Date: Wed, 2 Sep 2020 15:45:32 +0530 Subject: [PATCH 025/103] ARM: dts: msm: Change bit value to be read for loading adsp2 Change bit value to be read for loading adsp2. Change-Id: Ic6cac2ada902019cc6802b86909a4a97725542b7 --- qcom/shima-audio-overlay.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/shima-audio-overlay.dtsi b/qcom/shima-audio-overlay.dtsi index 17ca6790ffa1..b6068bbf2c95 100644 --- a/qcom/shima-audio-overlay.dtsi +++ b/qcom/shima-audio-overlay.dtsi @@ -418,5 +418,5 @@ nvmem-cells = <&adsp_variant>; nvmem-cell-names = "adsp_variant"; adsp-fw-names = "adsp2"; - adsp-fw-bit-values = <0x1>; + adsp-fw-bit-values = <0x4>; }; From 4e63ed8ec1fb1d771900f191da74f5bd67ca7e57 Mon Sep 17 00:00:00 2001 From: "Vangala, Amarnath" Date: Fri, 28 Aug 2020 15:43:17 +0530 Subject: [PATCH 026/103] ARM: dts: msm: correction to adsp variant read entry Correction to the number of bits read for adsp variant identification. Include adsp_variant read entry for holi-atp variant. Update dtsi for ATP variant. Change-Id: I6b95d9f7b1e9a7196195b2e9cc29eae0567ba716 --- qcom/holi-atp-overlay.dts | 39 +++++++++++++++++++++++++++++++++++++++ qcom/holi-atp.dtsi | 1 + qcom/holi.dtsi | 2 +- 3 files changed, 41 insertions(+), 1 deletion(-) diff --git a/qcom/holi-atp-overlay.dts b/qcom/holi-atp-overlay.dts index a2d3433c67a0..8062ff331274 100644 --- a/qcom/holi-atp-overlay.dts +++ b/qcom/holi-atp-overlay.dts @@ -9,3 +9,42 @@ qcom,msm-id = <454 0x10000>, <472 0x10000>; qcom,board-id = <33 0>; }; + +&wsa881x_i2c_e { + status = "disabled"; +}; + +&wsa881x_i2c_44 { + status = "disabled"; +}; + +&wcd937x_tx_slave { + status = "disabled"; +}; + +&wcd937x_rx_slave { + status = "disabled"; +}; + +&wcd937x_codec { + status = "disabled"; +}; + +&holi_snd { + qcom,wcd-disabled = <1>; + qcom,audio-routing = + "RX_TX DEC0_INP", "TX DEC0 MUX", + "RX_TX DEC1_INP", "TX DEC1 MUX", + "RX_TX DEC2_INP", "TX DEC2 MUX", + "RX_TX DEC3_INP", "TX DEC3 MUX", + "VA SWR_INPUT", "VA_SWR_CLK", + "VA_AIF1 CAP", "VA_SWR_CLK", + "VA_AIF2 CAP", "VA_SWR_CLK", + "VA_AIF3 CAP", "VA_SWR_CLK", + "VA DMIC0", "Digital Mic0", + "VA DMIC1", "Digital Mic1", + "VA DMIC2", "Digital Mic2", + "VA DMIC3", "Digital Mic3", + "VA DMIC4", "Digital Mic4", + "VA DMIC5", "Digital Mic5"; +}; diff --git a/qcom/holi-atp.dtsi b/qcom/holi-atp.dtsi index ab7daf265da5..d6a7f5516163 100644 --- a/qcom/holi-atp.dtsi +++ b/qcom/holi-atp.dtsi @@ -1,3 +1,4 @@ +#include "holi-audio-overlay.dtsi" #include #include #include "holi-pmic-overlay.dtsi" diff --git a/qcom/holi.dtsi b/qcom/holi.dtsi index af27b19b522b..695e3ee67de5 100644 --- a/qcom/holi.dtsi +++ b/qcom/holi.dtsi @@ -2695,7 +2695,7 @@ adsp_variant: adsp_variant@1E6 { reg = <0x1E6 0x2>; - bits = <6 9>; + bits = <6 4>; }; feat_conf8: feat_conf8@6024 { From c3372ac34deba5693cb11f414c0ba1ae5e783561 Mon Sep 17 00:00:00 2001 From: Dikshita Agarwal Date: Wed, 2 Sep 2020 16:37:55 +0530 Subject: [PATCH 027/103] ARM: dts: msm: update low SVS clock corner for holi Update low SVS corner from 133.33 to 133.00 for core clock and vcodec clock. Change-Id: I0e5eb6540573e041409a6937e8a4bcf2217d99b9 --- qcom/holi-vidc.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/holi-vidc.dtsi b/qcom/holi-vidc.dtsi index abc6b40d33c5..5b3aa57de254 100644 --- a/qcom/holi-vidc.dtsi +++ b/qcom/holi-vidc.dtsi @@ -25,7 +25,7 @@ qcom,proxy-clock-names = "core_clk", "iface_clk", "bus_clk", "core0_clk", "core0_bus_clk", "throttle_clk"; qcom,clock-configs = <0x1 0x0 0x0 0x1 0x0 0x0>; - qcom,allowed-clock-rates = <133330000 240000000 300000000 + qcom,allowed-clock-rates = <133000000 240000000 300000000 384000000>; /* Bus Interconnects */ From 31af8bcbfdd1decfb28420db3259a5730de43178 Mon Sep 17 00:00:00 2001 From: Ziqi Chen Date: Wed, 2 Sep 2020 19:23:09 +0800 Subject: [PATCH 028/103] ARM: dts: msm: Change cd-gpio polarity setting for QRD Shima According to QRD Shima HW design, the logic level of cd-gpio is LOW with card and is HIGH without card. Set cd-gpio flag to GPIO_ACTIVE_LOW for low active card installed interruption. Change-Id: If131dc4c1464df565390d0c7be85b110f7cb3e11 --- qcom/shima-qrd.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/shima-qrd.dtsi b/qcom/shima-qrd.dtsi index 35beafd3de2e..19e40d9abd8e 100644 --- a/qcom/shima-qrd.dtsi +++ b/qcom/shima-qrd.dtsi @@ -79,7 +79,7 @@ qcom,vdd-io-voltage-level = <1800000 2960000>; qcom,vdd-io-current-level = <0 22000>; - cd-gpios = <&tlmm 92 GPIO_ACTIVE_HIGH>; + cd-gpios = <&tlmm 92 GPIO_ACTIVE_LOW>; }; &ufsphy_mem { From 3be4a3857996e9a32723d9389e5c1af9a50e6d1c Mon Sep 17 00:00:00 2001 From: Krishna Manikandan Date: Wed, 2 Sep 2020 17:20:22 +0530 Subject: [PATCH 029/103] ARM: dts: msm: add cont splash memory for shima target Add cont splash memory node containing base address and size for shima target. Change-Id: Ied6a72ec7a6a48f4ccb32f2c268266288292d97b --- qcom/shima.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi index eb6782df00d1..8fa02e33ede3 100644 --- a/qcom/shima.dtsi +++ b/qcom/shima.dtsi @@ -436,6 +436,10 @@ size = <0x0 0x1C00000>; }; + splash_memory: splash_region { + reg = <0x0 0xe1000000 0x0 0x02300000>; + label = "cont_splash_region"; + }; }; chosen { From 670b377fc95c49fd1affa55128db1465215356c0 Mon Sep 17 00:00:00 2001 From: Shashank Babu Chinta Venkata Date: Wed, 26 Aug 2020 22:12:19 -0700 Subject: [PATCH 030/103] ARM: dts: msm: alter trusted vm mem lend properties Alter size for QUPv3 Serial Engine 4 memory for lending during trusted touch usecase. Change-Id: I8f3a6411cdee2441f47a2fb6da7e1785727fc8c3 --- qcom/lahaina-vm.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/lahaina-vm.dtsi b/qcom/lahaina-vm.dtsi index c7e230103dee..8e541a5713b1 100644 --- a/qcom/lahaina-vm.dtsi +++ b/qcom/lahaina-vm.dtsi @@ -314,7 +314,7 @@ st,touch-environment = "tvm"; st,trusted-touch-spi-irq = <566>; st,trusted-touch-io-bases = <0xF114000 0xF115000 0xF116000 0xF117000 0x990000 0x00910000>; - st,trusted-touch-io-sizes = <0x1000 0x1000 0x1000 0x1000 0x4000 0x4000>; + st,trusted-touch-io-sizes = <0x1000 0x1000 0x1000 0x1000 0x1000 0x4000>; }; }; From 007225a16f76168d63ab98465cce1dac6deb411e Mon Sep 17 00:00:00 2001 From: xsangh Date: Fri, 28 Aug 2020 17:50:28 +0800 Subject: [PATCH 031/103] ARM: dts: msm: update SHIMA QRD device information Explicitly disable left WSA to avoid soundwire enumeration error on QRD SHIMA. Change-Id: I0815e77ca0028435dbeaeedbaa70385ea7f4c396 --- qcom/shima-qrd.dtsi | 28 +++++++++++++++++++++++----- 1 file changed, 23 insertions(+), 5 deletions(-) diff --git a/qcom/shima-qrd.dtsi b/qcom/shima-qrd.dtsi index 35beafd3de2e..2526105f6985 100644 --- a/qcom/shima-qrd.dtsi +++ b/qcom/shima-qrd.dtsi @@ -220,10 +220,24 @@ }; }; +&wsa883x_0221 { + status = "disabled"; +}; + &shima_snd { qcom,model = "lahaina-shimaqrd-snd-card"; qcom,audio-routing = + "AMIC1", "Analog Mic1", + "Analog Mic1", "MIC BIAS3", + "AMIC2", "Analog Mic2", + "Analog Mic2", "MIC BIAS2", + "AMIC3", "Analog Mic3", + "Analog Mic3", "MIC BIAS3", + "AMIC4", "Analog Mic4", + "Analog Mic4", "MIC BIAS1", + "AMIC5", "Analog Mic5", + "Analog Mic5", "MIC BIAS4", "TX DMIC0", "Digital Mic0", "Digital Mic0", "MIC BIAS1", "TX DMIC1", "Digital Mic1", @@ -247,7 +261,6 @@ "RX_TX DEC1_INP", "TX DEC1 MUX", "RX_TX DEC2_INP", "TX DEC2 MUX", "RX_TX DEC3_INP", "TX DEC3 MUX", - "SpkrLeft IN", "WSA_SPK1 OUT", "SpkrRight IN", "WSA_SPK2 OUT", "TX SWR_INPUT", "WCD_TX_OUTPUT", "VA SWR_INPUT", "VA_SWR_CLK", @@ -260,8 +273,13 @@ "VA DMIC2", "Digital Mic2", "VA DMIC3", "Digital Mic3", "VA DMIC4", "Digital Mic4", - "VA DMIC5", "Digital Mic5"; - + "VA DMIC5", "Digital Mic5", + "VA DMIC0", "VA MIC BIAS1", + "VA DMIC1", "VA MIC BIAS3", + "VA DMIC2", "VA MIC BIAS4", + "VA DMIC3", "VA MIC BIAS1", + "VA DMIC4", "VA MIC BIAS3", + "VA DMIC5", "VA MIC BIAS4"; qcom,swr-dmic-max-devs = <0>; qcom,cdc-dmic01-gpios = <&cdc_dmic01_gpios>; @@ -274,10 +292,10 @@ asoc-codec = <&stub_codec>, <&bolero>, <&wcd938x_codec>, <&swr_haptics>, - <&wsa883x_0221>, <&wsa883x_0222>; + <&wsa883x_0222>; asoc-codec-names = "msm-stub-codec.1", "bolero_codec", "wcd938x_codec", "swr-haptics", - "wsa-codec1", "wsa-codec2"; + "wsa-codec2"; qcom,wsa-max-devs = <1>; qcom,msm_audio_ssr_devs = <&audio_apr>, <&q6core>, <&lpi_tlmm>, <&bolero>; From fd6e9a276f2add4be3f21745970e3bf35b1224e9 Mon Sep 17 00:00:00 2001 From: gqiaorui Date: Thu, 13 Aug 2020 16:43:39 +0800 Subject: [PATCH 032/103] ARM: dts: msm: shima sod qrd camera dts changes support for shima sod qrd camera birngup. CRs-Fixed: 2754689 Change-Id: I30a3c360f37fbd9c1408bf7c45c2e38ec4647f65 --- qcom/shima-qrd.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/shima-qrd.dtsi b/qcom/shima-qrd.dtsi index 35beafd3de2e..4da3dc289287 100644 --- a/qcom/shima-qrd.dtsi +++ b/qcom/shima-qrd.dtsi @@ -4,6 +4,7 @@ #include "shima-thermal-overlay.dtsi" #include "shima-audio-overlay.dtsi" #include "display/shima-sde-display-qrd.dtsi" +#include "camera/shima-camera-sensor-qrd.dtsi" &soc { gpio_keys { From afc0f64f633cef02b5c14b874fe5a6d5f9bdaa5a Mon Sep 17 00:00:00 2001 From: Faiyaz Mohammed Date: Thu, 3 Sep 2020 09:33:32 +0530 Subject: [PATCH 033/103] ARM: dts: msm: updates the shima VM ION same as lahaina Update the shima VM ION same as lahiana because tui mem-buf feature of shima is same as lahaina. Change-Id: Ic1fb0ade5f5b7e6cf1590d0856f51730d36db064 --- qcom/shima-vm-ion.dtsi | 15 --------------- qcom/shima-vm.dtsi | 2 +- 2 files changed, 1 insertion(+), 16 deletions(-) delete mode 100644 qcom/shima-vm-ion.dtsi diff --git a/qcom/shima-vm-ion.dtsi b/qcom/shima-vm-ion.dtsi deleted file mode 100644 index 010dec0a5607..000000000000 --- a/qcom/shima-vm-ion.dtsi +++ /dev/null @@ -1,15 +0,0 @@ -#include - -/ { - qcom,ion { - compatible = "qcom,msm-ion"; - #address-cells = <1>; - #size-cells = <0>; - - tui_heap: qcom,ion-heap-tui { /* TRUSTED UI CARVEOUT HEAP */ - reg = ; - qcom,dynamic-heap; - qcom,ion-heap-type = "MSM_CARVEOUT"; - }; - }; -}; diff --git a/qcom/shima-vm.dtsi b/qcom/shima-vm.dtsi index 360c435790da..8a1fb3b5d52c 100644 --- a/qcom/shima-vm.dtsi +++ b/qcom/shima-vm.dtsi @@ -225,4 +225,4 @@ ; }; }; -#include "shima-vm-ion.dtsi" +#include "lahaina-vm-ion.dtsi" From ce0c17e2d495170b63174681a3ab8727a1e5e1bc Mon Sep 17 00:00:00 2001 From: Fenglin Wu Date: Tue, 1 Sep 2020 18:39:05 +0800 Subject: [PATCH 034/103] ARM: dts: msm: add haptics configuration for shima target Add hap_cfg_sdam device node for haptics drive to trigger VREG enabling/disabling sequence and get boot up CAL_TLRA_CL_STS value. Also add PBS device node for haptics driver to trigger PBS to configure haptics ISC setting for LRA impedance detection. Change-Id: I27d751dd2210e2793a65725ebc9b3a848c233b20 --- qcom/shima-pmic-overlay.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/qcom/shima-pmic-overlay.dtsi b/qcom/shima-pmic-overlay.dtsi index 7a3fa06e69f9..ba8b1550e28f 100644 --- a/qcom/shima-pmic-overlay.dtsi +++ b/qcom/shima-pmic-overlay.dtsi @@ -495,6 +495,9 @@ &pm8350b_haptics { nvmem-cell-names = "hap_cl_brake"; nvmem-cells = <&hap_cl_brake>; + nvmem-names = "hap_cfg_sdam"; + nvmem = <&pmk8350_sdam_46>; + qcom,pbs-client = <&pm8350b_pbs2>; }; &pmr735b_tz { From 4408340b6fc53d31a9993798cb8f3533f7336218 Mon Sep 17 00:00:00 2001 From: Naveen Yadav Date: Thu, 3 Sep 2020 10:26:09 +0530 Subject: [PATCH 035/103] ARM: dts: msm: Update mc_virt interconnect node for SDXLEMUR Fix typographical error to fix the compilation issue. Change-Id: I924d558e2916935c3c12ce751ec8fc5e07b2aa43 --- qcom/sdxlemur.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index 9eb6143d4074..ba69d5c837c6 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -462,7 +462,7 @@ mc_virt: interconnect { compatible = "qcom,sdxlemur-mc_virt"; #interconnect-cells = <1>; - qcom,bcm-voter-names = "hlos" + qcom,bcm-voter-names = "hlos"; qcom,bcm-voters = <&apps_bcm_voter>; }; From 1bcabdfebe181941318318c75925d3b377e82115 Mon Sep 17 00:00:00 2001 From: Anjaneya Prasad Musunuri Date: Sun, 30 Aug 2020 15:52:04 +0530 Subject: [PATCH 036/103] ARM: dts: msm: Add fps entry for holi/shima Add fps detection entry for holi/shima Update gaming node to read four bytes. Change-Id: I4969237a6f48115b54290d1a6644a1798f69b281 --- qcom/holi.dtsi | 7 +++++-- qcom/shima.dtsi | 4 ++++ 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/qcom/holi.dtsi b/qcom/holi.dtsi index af27b19b522b..c17d812d7efb 100644 --- a/qcom/holi.dtsi +++ b/qcom/holi.dtsi @@ -2699,14 +2699,17 @@ }; feat_conf8: feat_conf8@6024 { - reg = <0x6024 0x2>; - bits = <21 1>; + reg = <0x6024 0x4>; }; gpu_gaming_bin: gpu_gaming_bin@6026 { reg = <0x6026 0x1>; bits = <5 1>; }; + + feat_conf9: feat_conf9@6028 { + reg = <0x6028 0x4>; + }; }; }; diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi index 4af7105c1cbf..ebc9fdd7c294 100644 --- a/qcom/shima.dtsi +++ b/qcom/shima.dtsi @@ -3242,6 +3242,10 @@ feat_conf_m7: feat_conf_m7@6020 { reg = <0x6020 0x4>; }; + + feat_conf_qc_spare_20_lsb: feat_conf_qc_spare_20_lsb@4700 { + reg = <0x4700 0x4>; + }; }; wlan: qcom,cnss-qca6490@b0000000 { From ac8b6dfbf2f9524f50a4b6735b7c8b36a4dd908e Mon Sep 17 00:00:00 2001 From: Tony Truong Date: Thu, 3 Sep 2020 10:56:00 -0700 Subject: [PATCH 037/103] ARM: dts: msm: update phandle for pcie_pipe_clk_ext_src for sdxlemur Using wrong phandle for PCIe root complex pcie_pipe_clk_ext_src. Therefore, update to use the correct phandle on sdxlemur. Change-Id: I9cb3a9b362dd72a1d08be7e6de4c6db7d4d86a17 --- qcom/sdxlemur-pcie.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/sdxlemur-pcie.dtsi b/qcom/sdxlemur-pcie.dtsi index b411c80be87f..753019979959 100644 --- a/qcom/sdxlemur-pcie.dtsi +++ b/qcom/sdxlemur-pcie.dtsi @@ -70,7 +70,7 @@ <&gcc GCC_PCIE_SLEEP_CLK>, <&gcc GCC_PCIE_RCHNG_PHY_CLK>, <&gcc GCC_PCIE_PIPE_CLK_SRC>, - <&gcc PCIE_PIPE_CLK>; + <&pcie_pipe_clk>; clock-names = "pcie_0_pipe_clk", "pcie_0_ref_clk_src", "pcie_0_aux_clk", "pcie_0_cfg_ahb_clk", From a2d331323f7984f1a45b84236185a6f8ec3957bf Mon Sep 17 00:00:00 2001 From: Subbaraman Narayanamurthy Date: Thu, 3 Sep 2020 16:29:33 -0700 Subject: [PATCH 038/103] dt-bindings: iio: qcom,spmi-vadc: update prescale ratios Update prescale ratios to support the new channels. Change-Id: I4d37e9653962954e856f464df32297d9aa90757a --- bindings/iio/adc/qcom,spmi-vadc.txt | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/bindings/iio/adc/qcom,spmi-vadc.txt b/bindings/iio/adc/qcom,spmi-vadc.txt index baa11b61266c..aca5cecf2c47 100644 --- a/bindings/iio/adc/qcom,spmi-vadc.txt +++ b/bindings/iio/adc/qcom,spmi-vadc.txt @@ -83,7 +83,9 @@ Channel node properties: fed to VADC. The configuration for this node is to know the pre-determined ratio and use it for post scaling. Select one from the following options. - <1 1>, <1 3>, <1 4>, <1 6>, <1 20>, <1 8>, <10 81>, <1 10> + <1 1>, <1 3>, <1 4>, <1 6>, <1 20>, <1 8>, <10 81>, <1 10>, <1 16>, + <32 100>, <14, 100>, <28, 100>, <1000 305185>, <1000 610370> + If property is not found default value depending on chip will be used. - qcom,ratiometric: From f45fc97a8a2b4c62ec8478aa6bea02ca38d7d5e2 Mon Sep 17 00:00:00 2001 From: Yue Ma Date: Fri, 22 May 2020 14:25:03 -0700 Subject: [PATCH 039/103] ARM: dts: msm: Enable CNSS PM domain support for Lahaina Enable use-pm-domain to let CNSS driver use PM domain ops for Lahaina. Also update missing binding document. Change-Id: I6bd1503d2ad612054e1951f7c2f15948224f4f09 --- bindings/cnss/cnss-wlan.txt | 8 ++++++++ qcom/lahaina.dtsi | 1 + 2 files changed, 9 insertions(+) diff --git a/bindings/cnss/cnss-wlan.txt b/bindings/cnss/cnss-wlan.txt index 6dcde8ad4264..b9afd01aae80 100644 --- a/bindings/cnss/cnss-wlan.txt +++ b/bindings/cnss/cnss-wlan.txt @@ -69,6 +69,14 @@ Optional properties: - qcom,mhi: phandle to indicate the device which needs MHI support. - qcom,cap-tsf-gpio: WLAN_TSF_CAPTURED GPIO signal specified by the chip specifications, should be drived depending on products + - cnss-daemon-support: Boolean property to decide whether cnss_daemon + userspace QMI client is supported. + - use-nv-mac: Boolean property to indicate whether NV MAC is used or not. + - qcom,set-wlaon-pwr-ctrl: Boolean property to indicate if set + WLAON_QFPROM_PWR_CTRL_REG register during power on + and off sequences. + - use-pm-domain: Boolean property to indicate if driver needs to use PM + domain or not. - qcom,wlan-cbc-enabled: boolean property to control cold boot calibration - interconnects: Interconnect framework setup for bus configuration - qcom,bus-bw-cfg-num: Number of bus bandwidth voting cases diff --git a/qcom/lahaina.dtsi b/qcom/lahaina.dtsi index b1aecf09e4ed..be0c78872ac8 100644 --- a/qcom/lahaina.dtsi +++ b/qcom/lahaina.dtsi @@ -5326,6 +5326,7 @@ qcom,wlan-cbc-enabled; /* RPMH_PDC_WLAN_RF_TCS<6>_CMD<2> offset */ qcom,tcs_offset_int_pow_amp_vreg = <0x4D0>; + use-pm-domain; vdd-wlan-aon-supply = <&S2E>; qcom,vdd-wlan-aon-config = <950000 952000 0 0 1>; From 60ce56e260fbe2854fb0fa00e11fd6079451c6c2 Mon Sep 17 00:00:00 2001 From: Yuanfang Zhang Date: Fri, 4 Sep 2020 13:14:28 +0800 Subject: [PATCH 040/103] ARM: dts: msm: add osm register to minidump for holi Add osm register to minidump on holi for new feature. Change-Id: Icbe03ce0f9c84862ac774829d8a4fb0aa0097cf3 --- qcom/holi.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/qcom/holi.dtsi b/qcom/holi.dtsi index f1ab2ea2a27e..b51fe3c951cd 100644 --- a/qcom/holi.dtsi +++ b/qcom/holi.dtsi @@ -835,6 +835,11 @@ qcom,dump-id = <0x104>; }; + osm_reg { + qcom,dump-size = <0x400>; + qcom,dump-id = <0x163>; + }; + pcu_reg { qcom,dump-size = <0x400>; qcom,dump-id = <0x164>; From 823d3b26d547d95d45957ea4d346e049dc49f53a Mon Sep 17 00:00:00 2001 From: Jagadeesh Kona Date: Wed, 2 Sep 2020 13:19:49 +0530 Subject: [PATCH 041/103] dt-bindings: clk: Add support for flag to send BIMC logging request Add new AOP flag "qcom,clk-stop-bimc-log" to send a BIMC logging request to AOP during kernel panic. Change-Id: Ic810a770387648e18c0718851c53fec72f173349 --- bindings/clock/qcom,aop-qmp.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/bindings/clock/qcom,aop-qmp.txt b/bindings/clock/qcom,aop-qmp.txt index 231b8a36420b..38a1b6db3228 100644 --- a/bindings/clock/qcom,aop-qmp.txt +++ b/bindings/clock/qcom,aop-qmp.txt @@ -7,6 +7,8 @@ Required properties : - mboxes : list of QMP mailbox phandle and channel identifier tuples. - mbox-names: List of identifier strings for each mailbox channel. Must contain "qdss_clk". +- qcom,clk-stop-bimc-log: Presence indicates a BIMC logging request will + be sent to AOP during kernel panic. Example : clock_qdss: qcom,aopclk { From 5083fb500618f466a35d83907d21a73667e3cb95 Mon Sep 17 00:00:00 2001 From: Jagadeesh Kona Date: Wed, 2 Sep 2020 13:25:28 +0530 Subject: [PATCH 042/103] ARM: dts: msm: Add support for BIMC logging for AOPCC Add support to send a BIMC logging request to AOP during the kernel panic. Change-Id: I610e090af5e835cfd8d094056bd25256436ce8cd --- qcom/shima.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi index eb6782df00d1..57c2e7cdf68e 100644 --- a/qcom/shima.dtsi +++ b/qcom/shima.dtsi @@ -789,6 +789,7 @@ mboxes = <&qmp_aop 0>; mbox-names = "qdss_clk"; #clock-cells = <1>; + qcom,clk-stop-bimc-log; }; gcc: clock-controller@100000 { From 23efcaf1675c4b5da60948f26013e00fe2156aac Mon Sep 17 00:00:00 2001 From: Prakash Gupta Date: Fri, 4 Sep 2020 14:22:36 +0530 Subject: [PATCH 043/103] ARM: dts: msm: updated memory map v2 for holi Updated memory map inline with v2 for holi. Change-Id: I92162c7b2e37097b14e84922edf99e28d6acc126 --- qcom/holi.dtsi | 5 ----- 1 file changed, 5 deletions(-) diff --git a/qcom/holi.dtsi b/qcom/holi.dtsi index f1ab2ea2a27e..77b1999cdc75 100644 --- a/qcom/holi.dtsi +++ b/qcom/holi.dtsi @@ -315,11 +315,6 @@ reg = <0x0 0xc0000000 0x0 0x5100000>; }; - pil_trustedvm_mem: pil_trustedvm_region@d0000000 { - no-map; - reg = <0x0 0xd0000000 0x0 0xa600000>; - }; - secure_display_memory: secure_display_region { compatible = "shared-dma-pool"; alloc-ranges = <0 0x00000000 0 0xffffffff>; From 5fef9b0c514cb93398b2afc2c898c1c4cbf8ff1a Mon Sep 17 00:00:00 2001 From: Jagadeesh Kona Date: Fri, 4 Sep 2020 14:47:55 +0530 Subject: [PATCH 044/103] ARM: dts: msm: Add EPSS hardware GT interrupts for SHIMA Add EPSS hardware GT interrupt which get triggered when LMH throttle occurs. Change-Id: I5937c9f584a50df7cf21226e2ad4915c4788d782 --- qcom/shima.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi index ae02be1e1589..e35ee673bc8b 100644 --- a/qcom/shima.dtsi +++ b/qcom/shima.dtsi @@ -986,6 +986,11 @@ qcom,lut-row-size = <4>; qcom,skip-enable-check; + interrupts = , + , + ; + interrupt-names = "dcvsh0_int", "dcvsh1_int", "dcvsh2_int"; + #freq-domain-cells = <2>; }; From e10cef3d127da8281333057d8c20c2bc5be60acf Mon Sep 17 00:00:00 2001 From: Manaf Meethalavalappu Pallikunhi Date: Wed, 11 Sep 2019 23:05:08 +0530 Subject: [PATCH 045/103] dt-bindings: Add limits cdsp isens driver Add driver to read limits cdsp Isens calibration data from SMEM and enable sysfs file support to userspace daemon to access this data. This driver is needed to avoid multiple re-calibration. Change-Id: I47993fdc3fceb754a720f016108d716345b5ee3f --- bindings/thermal/qti-isense-cdsp.txt | 14 ++++++++++++++ 1 file changed, 14 insertions(+) create mode 100644 bindings/thermal/qti-isense-cdsp.txt diff --git a/bindings/thermal/qti-isense-cdsp.txt b/bindings/thermal/qti-isense-cdsp.txt new file mode 100644 index 000000000000..587c03920cdc --- /dev/null +++ b/bindings/thermal/qti-isense-cdsp.txt @@ -0,0 +1,14 @@ +=============================================================================== +QTI Limits cdsp isense driver: +=============================================================================== +Limits cdsp isense driver reads cdsp isense calibration data from shared memory +and enables sysfs file support to access the data read from shared memory. + +Required Parameters: +- compatible: must be 'qcom,msm-limits-cdsp' for limits cdsp isense driver. + +Optional Parameters: + + lmh_isense_cdsp { + compatible = "qcom,msm-limits-cdsp"; + }; From 862f13b0bdbf46b7c568f570d7a54cfc3167d74d Mon Sep 17 00:00:00 2001 From: Nitin Rawat Date: Fri, 4 Sep 2020 21:23:20 +0530 Subject: [PATCH 046/103] ARM: dts: msm: Update UFS VCC regulator min voltage for shima Update UFS VCC regulator min voltage for shima. Change-Id: Ic7cae6c255a2f5ef4dcbaa5027d46fc31139f6eb --- qcom/shima-idp.dtsi | 2 +- qcom/shima-qrd.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/qcom/shima-idp.dtsi b/qcom/shima-idp.dtsi index b851aabc7c87..4ed070c7cf23 100644 --- a/qcom/shima-idp.dtsi +++ b/qcom/shima-idp.dtsi @@ -98,7 +98,7 @@ vdd-hba-fixed-regulator; vcc-supply = <&L7B>; - vcc-voltage-level = <2504000 2950000>; + vcc-voltage-level = <2950000 2960000>; vcc-low-voltage-sup; vcc-max-microamp = <800000>; diff --git a/qcom/shima-qrd.dtsi b/qcom/shima-qrd.dtsi index 1e07f86bcd8c..c2e070fedf1b 100644 --- a/qcom/shima-qrd.dtsi +++ b/qcom/shima-qrd.dtsi @@ -98,7 +98,7 @@ vdd-hba-fixed-regulator; vcc-supply = <&L7B>; - vcc-voltage-level = <2504000 2950000>; + vcc-voltage-level = <2950000 2960000>; vcc-low-voltage-sup; vcc-max-microamp = <800000>; From 3ac722a6bf77cb252bb4a7163bd3d4f026662368 Mon Sep 17 00:00:00 2001 From: Nitin Rawat Date: Fri, 4 Sep 2020 09:11:44 -0700 Subject: [PATCH 047/103] Revert "ARM: dts: msm: Disable lpm" This reverts commit 990ada8165fe46c297a816c71aea205fdba21d2f. Change-Id: I3679890d72bff97b6778cca5e622160224bb71f2 --- qcom/shima.dtsi | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi index d34d5f62ee3b..e6c611317c2d 100644 --- a/qcom/shima.dtsi +++ b/qcom/shima.dtsi @@ -1478,9 +1478,8 @@ qcom,iommu-dma = "bypass"; dma-coherent; - qcom,disable-lpm; - rpm-level = <0>; - spm-level = <0>; + rpm-level = <3>; + spm-level = <5>; status = "disabled"; From 7db2a3f608aad8f0932ed2b95f4daef2995cce29 Mon Sep 17 00:00:00 2001 From: Jagadeesh Kona Date: Mon, 22 Jun 2020 19:58:20 +0530 Subject: [PATCH 048/103] ARM: dts: msm: Add cpufreq hw debug support for HOLI and SHIMA Add support to print cpufreq hw debug registers on HOLI and SHIMA. Change-Id: Ic2bd35bfaa3c374461333bdd936407b710d3f6e9 --- qcom/holi.dtsi | 7 +++++++ qcom/shima.dtsi | 8 ++++++++ 2 files changed, 15 insertions(+) diff --git a/qcom/holi.dtsi b/qcom/holi.dtsi index f1ab2ea2a27e..134c90f93f55 100644 --- a/qcom/holi.dtsi +++ b/qcom/holi.dtsi @@ -1243,6 +1243,13 @@ #freq-domain-cells = <2>; }; + qcom,cpufreq-hw-debug@0fd91000 { + compatible = "qcom,cpufreq-hw-epss-debug"; + reg = <0x0fd91000 0x800>; + reg-names = "domain-top"; + qcom,freq-hw-domain = <&cpufreq_hw 0>, <&cpufreq_hw 1>; + }; + ddr_bw_opp_table: ddr-bw-opp-table { compatible = "operating-points-v2"; BW_OPP_ENTRY( 200, 4); /* 762 MB/s */ diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi index ae02be1e1589..e49259f837ee 100644 --- a/qcom/shima.dtsi +++ b/qcom/shima.dtsi @@ -989,6 +989,14 @@ #freq-domain-cells = <2>; }; + qcom,cpufreq-hw-debug@18591000 { + compatible = "qcom,cpufreq-hw-epss-debug"; + reg = <0x18591000 0x800>; + reg-names = "domain-top"; + qcom,freq-hw-domain = <&cpufreq_hw 0>, <&cpufreq_hw 1>, + <&cpufreq_hw 2>; + }; + qcom_tzlog: tz-log@0x146aa720 { compatible = "qcom,tz-log"; reg = <0x146aa720 0x3000>; From 0c023677acf16398d530fbdb82b5cbd97f52b279 Mon Sep 17 00:00:00 2001 From: Jagadeesh Kona Date: Fri, 4 Sep 2020 23:07:45 +0530 Subject: [PATCH 049/103] ARM: dts: msm: Set RETAIN_FF flag for GDSC's Add support to set RETAIN_FF flag of GDSC's to enable data retention feature. Change-Id: I88aab484ec555498b494dc78b474a2b653ed6996 --- qcom/shima.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi index ae02be1e1589..54b5d8890017 100644 --- a/qcom/shima.dtsi +++ b/qcom/shima.dtsi @@ -3704,18 +3704,22 @@ }; &gcc_pcie_0_gdsc { + qcom,retain-regs; status = "ok"; }; &gcc_pcie_1_gdsc { + qcom,retain-regs; status = "ok"; }; &gcc_ufs_phy_gdsc { + qcom,retain-regs; status = "ok"; }; &gcc_usb30_prim_gdsc { + qcom,retain-regs; status = "ok"; }; @@ -3756,6 +3760,7 @@ clock-names = "ahb_clk"; parent-supply = <&VDD_CX_LEVEL>; vdd_parent-supply = <&VDD_CX_LEVEL>; + qcom,retain-regs; status = "ok"; }; @@ -3765,6 +3770,7 @@ qcom,support-hw-trigger; parent-supply = <&VDD_CX_LEVEL>; vdd_parent-supply = <&VDD_CX_LEVEL>; + qcom,retain-regs; status = "ok"; }; @@ -3773,6 +3779,7 @@ clock-names = "ahb_clk"; parent-supply = <&VDD_CX_LEVEL>; vdd_parent-supply = <&VDD_CX_LEVEL>; + qcom,retain-regs; status = "ok"; }; @@ -3781,6 +3788,7 @@ clock-names = "ahb_clk"; parent-supply = <&VDD_CX_LEVEL>; vdd_parent-supply = <&VDD_CX_LEVEL>; + qcom,retain-regs; status = "ok"; }; @@ -3789,6 +3797,7 @@ clock-names = "ahb_clk"; parent-supply = <&VDD_CX_LEVEL>; vdd_parent-supply = <&VDD_CX_LEVEL>; + qcom,retain-regs; status = "ok"; }; @@ -3798,6 +3807,7 @@ qcom,support-hw-trigger; parent-supply = <&VDD_CX_LEVEL>; vdd_parent-supply = <&VDD_CX_LEVEL>; + qcom,retain-regs; status = "ok"; }; @@ -3807,6 +3817,7 @@ qcom,support-hw-trigger; parent-supply = <&VDD_CX_LEVEL>; vdd_parent-supply = <&VDD_CX_LEVEL>; + qcom,retain-regs; status = "ok"; }; @@ -3815,6 +3826,7 @@ clock-names = "ahb_clk"; parent-supply = <&VDD_CX_LEVEL>; vdd_parent-supply = <&VDD_CX_LEVEL>; + qcom,retain-regs; status = "ok"; }; @@ -3823,6 +3835,7 @@ clock-names = "ahb_clk"; parent-supply = <&VDD_GFX_LEVEL>; vdd_parent-supply = <&VDD_GFX_LEVEL>; + qcom,retain-regs; status = "ok"; }; @@ -3832,6 +3845,7 @@ qcom,support-hw-trigger; parent-supply = <&VDD_CX_LEVEL>; vdd_parent-supply = <&VDD_CX_LEVEL>; + qcom,retain-regs; status = "ok"; }; @@ -3840,6 +3854,7 @@ clock-names = "ahb_clk"; parent-supply = <&VDD_CX_LEVEL>; vdd_parent-supply = <&VDD_CX_LEVEL>; + qcom,retain-regs; status = "ok"; }; @@ -3849,6 +3864,7 @@ qcom,support-hw-trigger; parent-supply = <&VDD_CX_LEVEL>; vdd_parent-supply = <&VDD_CX_LEVEL>; + qcom,retain-regs; status = "ok"; }; @@ -3857,6 +3873,7 @@ clock-names = "ahb_clk"; parent-supply = <&VDD_CX_LEVEL>; vdd_parent-supply = <&VDD_CX_LEVEL>; + qcom,retain-regs; status = "ok"; }; From 876ed30bec8e9e517d3e95a9c4b48e167777aaaf Mon Sep 17 00:00:00 2001 From: Saurabh Sahu Date: Sat, 5 Sep 2020 16:23:57 +0530 Subject: [PATCH 050/103] ARM: dts: msm: Add support for BIMC stop logging for HOLI Add support to send a BIMC stop logging request to rpm when panic happens for HOLI. Change-Id: Iaeb9602eebdef2752f0707719d7c6c64c8fe34be --- qcom/holi.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/holi.dtsi b/qcom/holi.dtsi index 134c90f93f55..b40a2daf9ce4 100644 --- a/qcom/holi.dtsi +++ b/qcom/holi.dtsi @@ -1156,6 +1156,7 @@ rpmcc: clock-controller { compatible = "qcom,rpmcc-holi"; + qcom,bimc-log-stop; #clock-cells = <1>; #reset-cells = <1>; }; From 6f5655e6cc86c2cb7221acdec7568e2047ef8b76 Mon Sep 17 00:00:00 2001 From: Rajeev Nandan Date: Sat, 29 Aug 2020 16:36:43 +0530 Subject: [PATCH 051/103] ARM: dts: msm: add proxy votes for display regulators on Shima This change adds a proxy vote for supplies to support amoled displays. This is needed for continuous splash screen usecase. Change-Id: Iaf647f54df39713a21c915c4f9ad697f97b5dee6 --- qcom/shima-regulators.dtsi | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/qcom/shima-regulators.dtsi b/qcom/shima-regulators.dtsi index deb4771646b5..e592f7a5df8e 100644 --- a/qcom/shima-regulators.dtsi +++ b/qcom/shima-regulators.dtsi @@ -673,14 +673,17 @@ ; qcom,mode-threshold-currents = <0 30000>; + proxy-supply = <&pm8350c_l12>; L12C: pm8350c_l12: regulator-pm8350c-l12 { regulator-name = "pm8350c_l12"; qcom,set = ; - regulator-min-microvolt = <1620000>; + regulator-min-microvolt = <1920000>; regulator-max-microvolt = <1980000>; - qcom,init-voltage = <1620000>; + qcom,init-voltage = <1920000>; qcom,init-mode = ; + qcom,proxy-consumer-enable; + qcom,proxy-consumer-current = <60700>; }; }; @@ -692,6 +695,7 @@ ; qcom,mode-threshold-currents = <0 30000>; + proxy-supply = <&pm8350c_l13>; L13C: pm8350c_l13: regulator-pm8350c-l13 { regulator-name = "pm8350c_l13"; @@ -700,6 +704,8 @@ regulator-max-microvolt = <3544000>; qcom,init-voltage = <2700000>; qcom,init-mode = ; + qcom,proxy-consumer-enable; + qcom,proxy-consumer-current = <30000>; }; }; From 3f0774f30c4fe9fad1d90841224ed31170620705 Mon Sep 17 00:00:00 2001 From: Ritesh Kumar Date: Wed, 26 Aug 2020 12:47:16 +0530 Subject: [PATCH 052/103] ARM: dts: msm: Add trusted touch properties to focaltech Add trusted touch properties to focaltech node to support VM(virtual machine) enabled trusted touch on lahaina QRD. Change-Id: I9e054583ca69c87bf94f18a3ea1fd97881c875e5 --- qcom/lahaina-qrd-common.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/qcom/lahaina-qrd-common.dtsi b/qcom/lahaina-qrd-common.dtsi index 438c2393b90e..fde9bc11fb6f 100644 --- a/qcom/lahaina-qrd-common.dtsi +++ b/qcom/lahaina-qrd-common.dtsi @@ -205,6 +205,12 @@ panel = <&dsi_r66451_amoled_cmd &dsi_r66451_amoled_video>; + + focaltech,trusted-touch-mode = "vm_mode"; + focaltech,touch-environment = "pvm"; + focaltech,trusted-touch-spi-irq = <566>; + focaltech,trusted-touch-io-bases = <0xF114000 0xF115000 0xF116000 0xF117000 0x990000 0x00910000>; + focaltech,trusted-touch-io-sizes = <0x1000 0x1000 0x1000 0x1000 0x4000 0x4000>; }; }; From 15950989abb01dfedd6882a824e6a1d2338830f7 Mon Sep 17 00:00:00 2001 From: Jishnu Prakash Date: Fri, 4 Sep 2020 19:12:40 +0530 Subject: [PATCH 053/103] bindings: smb1398: Update SMB1398 DT bindings Update IIO properties io-channels and io-channel-names, which may be used for SMB1398 to read ADC, SMB5 and CP_SLAVE channels. Change-Id: I52eda2fbd366f8d128011ff0e365e5319d9189d7 --- .../power/supply/qcom/smb1398-charger.txt | 21 ++++++++++++------- 1 file changed, 14 insertions(+), 7 deletions(-) diff --git a/bindings/power/supply/qcom/smb1398-charger.txt b/bindings/power/supply/qcom/smb1398-charger.txt index 5f1588f6a647..869af88da4c5 100644 --- a/bindings/power/supply/qcom/smb1398-charger.txt +++ b/bindings/power/supply/qcom/smb1398-charger.txt @@ -43,16 +43,19 @@ Charger specific properties: required when SMB1396 working as a DIV2 CP master. - io-channels -- io-channel-names Usage: optional - Value type: - Definition: The IIO channel for measuring SMB1398 die temperature, - io-channel-names should be "die-temp". For other details about - IIO bindings see: + Value type: + Definition: IIO channel specifiers for each name in io-channel-names. + For other details about IIO bindings see: Documentation/devicetree/bindings/iio/iio-bindings.txt These properties are required when SMB1396 working as a DIV2 CP master. +- io-channel-names + Usage: optional + Value type: + Definition: Names of the IIO channels that are used by CP master. + - qcom,div2-cp-min-ilim-ua Usage: optional Value type: @@ -86,8 +89,12 @@ smb1398_charger: qcom,combo_charger { interrupt-parent = <&smb1398>; status = "disabled"; - io-channels = <&pm8150b_vadc ADC_AMUX_THM2>; - io-channel-names = "die_temp"; + io-channels = <&smb1396_div2_cp_slave PSY_IIO_CURRENT_CAPABILITY>, + <&pm7250b_charger PSY_IIO_USB_REAL_TYPE>, + <&pm7250b_vadc ADC5_AMUX_THM2>; + io-channel-names = "current_capability", + "real_type", + "die_temp"; interrupts = <0x26 0x1 IRQ_TYPE_EDGE_RISING>, <0x26 0x3 IRQ_TYPE_EDGE_RISING>, From ef808f2559fce97b6a17a7fb29f9d2c9a9d203be Mon Sep 17 00:00:00 2001 From: Mohammed Siddiq Date: Mon, 7 Sep 2020 11:57:54 +0530 Subject: [PATCH 054/103] ARM: dts: msm: Update cnss dt node for bus bandwidth for shima Configure bandwidth vote data for individual platform interconnect paths. Change-Id: Ic8d97324109e31092169a06ab0e690ac61eccc92 --- qcom/shima.dtsi | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi index 4170db3da48b..b418926e5ee7 100644 --- a/qcom/shima.dtsi +++ b/qcom/shima.dtsi @@ -3398,6 +3398,40 @@ wlan-ant-switch-supply = <&L11C>; qcom,wlan-ant-switch-config = <2800000 2800000 0 0 0>; + interconnects = + <&aggre2_noc MASTER_PCIE_0 &aggre2_noc SLAVE_ANOC_PCIE_GEM_NOC>, + <&gem_noc MASTER_ANOC_PCIE_GEM_NOC &mc_virt SLAVE_EBI1>; + interconnect-names = "pcie_to_memnoc", "memnoc_to_ddr"; + + qcom,icc-path-count = <2>; + qcom,bus-bw-cfg-count = <7>; + qcom,bus-bw-cfg = + /** ICC Path 1 **/ + <0 0>, /* no vote */ + /* idle: 0-18 Mbps snoc/anoc: 100 Mhz ddr: 451.2 MHz */ + <2250 390000>, + /* low: 18-60 Mbps snoc/anoc: 100 Mhz ddr: 451.2 MHz */ + <7500 390000>, + /* medium: 60-240 Mbps snoc/anoc: 200 Mhz ddr: 451.2 MHz */ + <30000 790000>, + /* high: 240-1080 Mbps snoc/anoc: 200 Mhz ddr: 451.2 MHz */ + <100000 790000>, + /* very high: > 1080 Mbps snoc/anoc: 403 Mhz ddr: 451.2 MHz */ + <175000 1600000>, + /* low (latency critical): 18-60 Mbps snoc/anoc: 200 Mhz + * ddr: 547.2 MHz + */ + <7500 390000>, + + /** ICC Path 2 **/ + <0 0>, + <2250 1804800>, + <7500 1804800>, + <30000 1804800>, + <100000 1804800>, + <175000 6220800>, + <7500 2188800>; + mhi,max-channels = <30>; mhi,timeout = <10000>; mhi,buffer-len = <0x8000>; From c8f2acd66ff56d0a4edb2e779d3da13a7e24280a Mon Sep 17 00:00:00 2001 From: Mayank Grover Date: Mon, 7 Sep 2020 13:02:53 +0530 Subject: [PATCH 055/103] ARM: dts: msm: Add support for CDP LCD platform for holi Add platform support for CDP-LCD attached platform for holi target. Change-Id: I4aeb86fab91039119930b13cb3bcde9c54beff1c --- qcom/Makefile | 3 +++ qcom/holi-cdp-lcd-overlay.dts | 16 ++++++++++++++++ qcom/holi-cdp-lcd.dts | 10 ++++++++++ qcom/holi-cdp-lcd.dtsi | 1 + 4 files changed, 30 insertions(+) create mode 100644 qcom/holi-cdp-lcd-overlay.dts create mode 100644 qcom/holi-cdp-lcd.dts create mode 100644 qcom/holi-cdp-lcd.dtsi diff --git a/qcom/Makefile b/qcom/Makefile index a8abb1f7cdcd..36a9f1af0936 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -75,6 +75,7 @@ ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y) dtbo-$(CONFIG_ARCH_HOLI) += holi-rumi-overlay.dtbo \ holi-mtp-overlay.dtbo \ holi-cdp-overlay.dtbo \ + holi-cdp-lcd-overlay.dtbo \ holi-qrd-overlay.dtbo \ holi-atp-overlay.dtbo \ holi-mtp-usbc-overlay.dtbo @@ -82,6 +83,7 @@ dtbo-$(CONFIG_ARCH_HOLI) += holi-rumi-overlay.dtbo \ holi-rumi-overlay.dtbo-base := holi.dtb holi-mtp-overlay.dtbo-base := holi.dtb holi-cdp-overlay.dtbo-base := holi.dtb +holi-cdp-lcd-overlay.dtbo-base := holi.dtb holi-qrd-overlay.dtbo-base := holi.dtb holi-atp-overlay.dtbo-base := holi.dtb holi-mtp-usbc-overlay.dtbo-base := holi.dtb @@ -89,6 +91,7 @@ else dtb-$(CONFIG_ARCH_HOLI) += holi-rumi.dtb \ holi-mtp.dtb \ holi-cdp.dtb \ + holi-cdp-lcd.dtb \ holi-qrd.dtb \ holi-atp.dtb \ holi-mtp-usbc.dtb diff --git a/qcom/holi-cdp-lcd-overlay.dts b/qcom/holi-cdp-lcd-overlay.dts new file mode 100644 index 000000000000..f3905d1643ce --- /dev/null +++ b/qcom/holi-cdp-lcd-overlay.dts @@ -0,0 +1,16 @@ +/dts-v1/; +/plugin/; + +#include "holi-cdp-lcd.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Holi CDP-LCD attached"; + compatible = "qcom,holi-cdp", "qcom,holi", "qcom,cdp"; + qcom,msm-id = <454 0x10000>, <472 0x10000>; + qcom,board-id = <1 1>; +}; + +&wsa881x_analog_reset_gpio { + pinctrl-0 = <&spkr_1_sd_n_active>; + pinctrl-1 = <&spkr_1_sd_n_sleep>; +}; diff --git a/qcom/holi-cdp-lcd.dts b/qcom/holi-cdp-lcd.dts new file mode 100644 index 000000000000..3c55b4643ed3 --- /dev/null +++ b/qcom/holi-cdp-lcd.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "holi.dtsi" +#include "holi-cdp-lcd.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Holi CDP-LCD attach"; + compatible = "qcom,holi-cdp", "qcom,holi", "qcom,cdp"; + qcom,board-id = <1 1>; +}; diff --git a/qcom/holi-cdp-lcd.dtsi b/qcom/holi-cdp-lcd.dtsi new file mode 100644 index 000000000000..3021000b5376 --- /dev/null +++ b/qcom/holi-cdp-lcd.dtsi @@ -0,0 +1 @@ +#include "holi-cdp.dtsi" From ec23d1f74edba4405cf73f96d5ef0ad18879c73a Mon Sep 17 00:00:00 2001 From: Harshal Ahire Date: Tue, 1 Sep 2020 18:38:20 +0530 Subject: [PATCH 056/103] ARM: dts: msm: add support for 1 MB SKU for holi Add new sound-card name for holi to pick proper acdb files for 1 MB SKU version. Change-Id: I2d1325f5673ca7b21cfbe286a2b5351f3abc8fb9 --- qcom/holi-audio-overlay.dtsi | 5 +++++ qcom/holi-qrd.dtsi | 1 + 2 files changed, 6 insertions(+) diff --git a/qcom/holi-audio-overlay.dtsi b/qcom/holi-audio-overlay.dtsi index 93fd6e0ce027..9075c50d7352 100644 --- a/qcom/holi-audio-overlay.dtsi +++ b/qcom/holi-audio-overlay.dtsi @@ -231,6 +231,7 @@ &holi_snd { qcom,model = "holi-mtp-snd-card"; + qcom,sku-model = "holi-mtpsku1-snd-card"; qcom,msm-mi2s-master = <1>, <1>, <1>, <1>; qcom,wcn-btfm = <1>; qcom,tdm-max-slots = <4>; @@ -279,6 +280,10 @@ qcom,msm-mbhc-gnd-swh = <1>; qcom,cdc-dmic01-gpios = <&cdc_dmic01_gpios>; qcom,cdc-dmic23-gpios = <&cdc_dmic23_gpios>; + + nvmem-cells = <&adsp_variant>; + nvmem-cell-names = "adsp_variant"; + asoc-codec = <&stub_codec>, <&bolero>, <&wcd937x_codec>, <&wsa881x_i2c_e>, <&wsa881x_i2c_f>; diff --git a/qcom/holi-qrd.dtsi b/qcom/holi-qrd.dtsi index e8ac31401e88..94c86b3bbf90 100644 --- a/qcom/holi-qrd.dtsi +++ b/qcom/holi-qrd.dtsi @@ -146,6 +146,7 @@ &holi_snd { qcom,model = "holi-qrd-snd-card"; + qcom,sku-model = "holi-qrdsku1-snd-card"; qcom,msm-mi2s-master = <1>, <1>, <1>, <1>; qcom,wcn-btfm = <1>; qcom,audio-routing = From 609f70f965a2cc68e4d42e99718e7fb921d19ed8 Mon Sep 17 00:00:00 2001 From: Vishvanath Singh Date: Mon, 31 Aug 2020 12:52:06 +0530 Subject: [PATCH 057/103] ARM: dts: msm: support for qdss clock in llcc shima Add qdss clock support for llcc inorder to support llcc perfmon module functionality in shima. Change-Id: Iaa2b6116477c462aebdcea645a27aafefbd15aee --- qcom/shima.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi index 4170db3da48b..12f216ff1a21 100644 --- a/qcom/shima.dtsi +++ b/qcom/shima.dtsi @@ -2013,6 +2013,8 @@ reg = <0x9200000 0xd0000> , <0x9600000 0x50000>; reg-names = "llcc_base", "llcc_broadcast_base"; cap-based-alloc-and-pwr-collapse; + clocks = <&aopcc QDSS_CLK>; + clock-names = "qdss_clk"; }; clk_virt: interconnect { From 0f0af0a543a2b0d1cc7d5cf5f96f8661d46f8244 Mon Sep 17 00:00:00 2001 From: Odelu Kukatla Date: Mon, 7 Sep 2020 00:40:20 +0530 Subject: [PATCH 058/103] ARM: dts: msm: Add handles for PCIE clocks PCIE cocks need to be enabled for QoS settings programming, so add PCIE clock handles. Change-Id: I882f07b33b3e7ffaaabeaca258831b8ac0757973 --- qcom/shima-pcie.dtsi | 2 +- qcom/shima.dtsi | 8 ++++---- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/qcom/shima-pcie.dtsi b/qcom/shima-pcie.dtsi index 4a05eff1809e..32573d6def76 100644 --- a/qcom/shima-pcie.dtsi +++ b/qcom/shima-pcie.dtsi @@ -59,7 +59,7 @@ RPMH_REGULATOR_LEVEL_NOM 100000000>; /* Gen3 */ interconnect-names = "icc_path"; - interconnects = <&aggre2_noc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>; + interconnects = <&aggre1_noc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>; clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, <&rpmhcc RPMH_CXO_CLK>, diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi index 4170db3da48b..7fb43f4babef 100644 --- a/qcom/shima.dtsi +++ b/qcom/shima.dtsi @@ -2052,7 +2052,9 @@ #interconnect-cells = <1>; qcom,bcm-voter-names = "hlos"; qcom,bcm-voters = <&apps_bcm_voter>; - clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + clocks = <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; }; @@ -2062,9 +2064,7 @@ #interconnect-cells = <1>; qcom,bcm-voter-names = "hlos"; qcom,bcm-voters = <&apps_bcm_voter>; - clocks = <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>, - <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>, - <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, <&rpmhcc RPMH_IPA_CLK>; }; From 47856a185b81d332088ff6f4e7b4ccbe0393ffec Mon Sep 17 00:00:00 2001 From: Anmolpreet Kaur Date: Mon, 18 May 2020 16:06:59 +0530 Subject: [PATCH 059/103] dt-bindings: Add dts entries for haven Add device tree entries for smcinvoke and qtee_shmbridge in haven dtsi file. Change-Id: I34f20282e52542b21d0733daec2109c2143b476d --- qcom/lahaina-vm.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/qcom/lahaina-vm.dtsi b/qcom/lahaina-vm.dtsi index 8e541a5713b1..d1ed67b215f5 100644 --- a/qcom/lahaina-vm.dtsi +++ b/qcom/lahaina-vm.dtsi @@ -332,6 +332,15 @@ qcom,le-vm; status = "disabled"; }; + + qcom_smcinvoke { + compatible = "qcom,smcinvoke"; + }; + + qtee_shmbridge { + compatible = "qcom,tee-shared-memory-bridge"; + qcom,support-hypervisor; + }; }; #include "lahaina-vm-ion.dtsi" From 6081877ba473ba2f3b8b3b0c9101f1eb142cd6eb Mon Sep 17 00:00:00 2001 From: Imran Ahmad Date: Tue, 8 Sep 2020 16:00:29 +0530 Subject: [PATCH 060/103] dt-bindings: Add snapshot of qpnp-smblite documentation Add snapshot of qpnp-smblite documentation from msm-4.19 as of commit 77dd65e822dd ("Merge ARM: dts: msm: Add device tree files for Litomagnus variant"). Change-Id: Ib9ade60c9e64f92bea59001206fd40a646e883cc --- bindings/power/supply/qcom/qpnp-smblite.txt | 334 ++++++++++++++++++++ 1 file changed, 334 insertions(+) create mode 100644 bindings/power/supply/qcom/qpnp-smblite.txt diff --git a/bindings/power/supply/qcom/qpnp-smblite.txt b/bindings/power/supply/qcom/qpnp-smblite.txt new file mode 100644 index 000000000000..137518e988eb --- /dev/null +++ b/bindings/power/supply/qcom/qpnp-smblite.txt @@ -0,0 +1,334 @@ +Qualcomm Technologies, Inc. SMBLITE Charger Specific Bindings + +SMBLITE Charger is an efficient programmable battery charger capable of charging a +lithium-ion battery over micro-USB or USB Type-C. + +======================= +Required Node Structure +======================= + +SMBLITE Charger must be described in two levels of devices nodes. + +=================================== +First Level Node - SMBLITE Charger +=================================== + +Charger specific properties: +- compatible + Usage: required + Value type: + Definition: "qcom,qpnp-smblite". + +- qcom,pmic-revid + Usage: required + Value type: phandle + Definition: Should specify the phandle of PMI's revid module. This is used to + identify the PMI subtype. + +- io-channels +- io-channel-names + Usage: optional + Value type: + Definition: For details about IIO bindings see: + Documentation/devicetree/bindings/iio/iio-bindings.txt + +- qcom,batteryless-platform + Usage: optional + Value type: + Definition: Boolean flag which indicates that the platform does not have a + battery, and therefore charging should be disabled. In + addition battery properties will be faked such that the device + assumes normal operation. + +- qcom,fcc-max-ua + Usage: optional + Value type: + Definition: Specifies the maximum fast charge current in micro-amps in + battery profile. + If the value is not present, 1Amp is used as default. + +- qcom,fv-max-uv + Usage: optional + Value type: + Definition: Specifies the maximum float voltage in micro-volts in + battery profile. + If the value is not present, 4.35V is used as default. + +- qcom,usb-icl-ua + Usage: optional + Value type: + Definition: Specifies the USB input current limit in micro-amps. + If the value is not present, 1.5Amps is used as default. + +- qcom,thermal-mitigation + Usage: optional + Value type: Array of + Definition: Array of fast charge current limit values for + different system thermal mitigation levels. + This should be a flat array that denotes the + maximum charge current in mA for each thermal + level. + +- qcom,chg-inhibit-threshold-mv + Usage: optional + Value type: + Definition: Charge inhibit threshold in milli-volts. Charging will be + inhibited when the battery voltage is within this threshold + from Vfloat at charger insertion. If this is not specified + then charge inhibit will be disabled by default. + Allowed values are: 50, 100, 200, 300. + +- qcom,chg-term-src + Usage: optional + Value type: + Definition: Specify either the ADC or analog comparators to be used in order + to set threshold values for charge termination current. + 0 - Unspecified + 1 - Select ADC comparator + 2 - Select ANALOG comparator + +- qcom,chg-term-current-ma + Usage: optional + Value type: + Definition: When ADC comparator is selected as qcom,chg-term-src, this + parameter should be set to the desired upper threshold. + +- qcom,chg-term-base-current-ma + Usage: optional + Value type: + Definition: When ADC comparator is selected as qcom,chg-term-src, this + parameter should be set to the desired lower threshold. + +- qcom,auto-recharge-soc + Usage: optional + Value type: + Definition: Specifies the SOC threshold at which the charger will + restart charging after termination. The value specified + ranges from 0 - 100. The feature is enabled if this + property is specified with a valid SOC value. + +- qcom,auto-recharge-vbat-mv + Usage: optional + Value type: + Definition: Specifies the battery voltage threshold at which the charger + will restart charging after termination. The value specified + is in milli-volts. + +- qcom,suspend-input-on-debug-batt + Usage: optional + Value type: + Definition: Boolean flag which when present enables input suspend for + debug battery. + +- qcom,fake-chg-status-on-debug-batt + Usage: optional + Value type: + Definition: Boolean flag which when present shows charging status as + unknown for debug battery. This needs to be specified only if + the device needs to be kept powered on always with + "svc power stayon true". + +- qcom,typec-legacy-rp-icl + Usage: optional + Value type: bool + Definition: Boolean property to enable setting ICL based on Rp for + Type-C non-compliant legacy cables. + +- qcom,wd-bark-time-secs + Usage: optional + Value type: + Definition: WD bark-timeout in seconds. The possible values are + 16, 32, 64, 128. If not defined it defaults to 64. + +- qcom,battery-data + Usage: optional + Value type: + Definition: Specifies the phandle of the node which contains the battery + profiles supported on the device. + +- qcom,flash-derating-soc + Usage: optional + Value type: + Definition: SOC threshold in percentage below which hardware will start + derating flash. This is only applicable to certain PMICs like + PMI632 which has SCHGM_FLASH peripheral. + +- qcom,flash-disable-soc + Usage: optional + Value type: + Definition: SOC threshold in percentage below which hardware will disable + flash. This is only applicable to certain PMICs like PMI632 + which has SCHGM_FLASH peripheral. + +- qcom,headroom-mode + Usage: optional + Value type: + Definition: Specifies flash hardware headroom management policy. The + possible values are: + <0>: Fixed mode, constant 5V at flash input. + <1>: Adaptive mode allows charger output voltage to be + dynamically controlled by the flash module based on the + required flash headroom. + This is only applicable to certain PMICs like PMI632 which + has SCHGM_FLASH peripheral. + +- qcom,fcc-stepping-enable + Usage: optional + Value type: bool + Definition: Boolean flag which when present enables stepwise change in FCC. + The default stepping rate is 100mA/sec. + +- qcom,disable-suspend-on-collapse + Usage: optional + Value type: bool + Definition: Boolean flag which when present disables suspend on collapse + feature of charger hardware. + +- qcom,fcc-step-delay-ms + Usage: optional + Value type: + Definition: Specifies the delay between each step of FCC stepper algorithm. + If left unspecified, the default value is 1 Sec. + +- qcom,fcc-step-size-ua + Usage: optional + Value type: + Definition: Specifies the step size of each step of FCC stepper algorithm. + If left unspecified, the default value is 100mA. + +================================================= +Second Level Nodes - SMBLITE Charger Peripherals +================================================= + +Peripheral specific properties: +- reg + Usage: required + Value type: + Definition: Address and size of the peripheral's register block. + +- interrupts + Usage: required + Value type: + Definition: Peripheral interrupt specifier. + +- interrupt-names + Usage: required + Value type: + Definition: Interrupt names. This list must match up 1-to-1 with the + interrupts specified in the 'interrupts' property. + +======= +Example +======= + +pm2250_charger: qcom,qpnp-smblite { + compatible = "qcom,qpnp-smblite"; + #address-cells = <1>; + #size-cells = <1>; + #cooling-cells = <2>; + + qcom,pmic-revid = <&pm2250_revid>; + qcom,chgr@1000 { + reg = <0x1000 0x100>; + interrupts = + <0x0 0x10 0x1 IRQ_TYPE_EDGE_RISING>, + <0x0 0x10 0x0 IRQ_TYPE_EDGE_RISING>, + <0x0 0x10 0x4 IRQ_TYPE_EDGE_RISING>, + <0x0 0x10 0x7 IRQ_TYPE_EDGE_RISING>; + + interrupt-names = "chgr-error", + "chg-state-change", + "buck-oc", + "vph-ov"; + }; + + qcom,dcdc@1100 { + reg = <0x1100 0x100>; + interrupts = + <0x0 0x11 0x0 IRQ_TYPE_EDGE_RISING>, + <0x0 0x11 0x1 IRQ_TYPE_EDGE_RISING>, + <0x0 0x11 0x2 IRQ_TYPE_EDGE_RISING>, + <0x0 0x11 0x6 IRQ_TYPE_EDGE_RISING>, + <0x0 0x11 0x7 IRQ_TYPE_EDGE_BOTH>; + + interrupt-names = "otg-fail", + "otg-fault", + "skip-mode", + "input-current-limiting", + "switcher-power-ok"; + }; + + qcom,batif@1200 { + reg = <0x1200 0x100>; + interrupts = + <0x0 0x12 0x0 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x12 0x1 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x12 0x2 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x12 0x3 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x12 0x4 IRQ_TYPE_EDGE_RISING>; + + interrupt-names = "bat-temp", + "bat-therm-or-id-missing", + "bat-low", + "bat-ov", + "bsm-active"; + }; + + qcom,usb@1300 { + reg = <0x1300 0x100>; + interrupts = + <0x0 0x13 0x0 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x13 0x1 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x13 0x2 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x13 0x3 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x13 0x4 IRQ_TYPE_EDGE_RISING>, + <0x0 0x13 0x6 IRQ_TYPE_EDGE_RISING>; + + interrupt-names = "usbin-plugin", + "usbin-collapse", + "usbin-uv", + "usbin-ov", + "usbin-gtvt", + "usbin-icl-change"; + }; + + qcom,typec@1500 { + reg = <0x1500 0x100>; + interrupts = + <0x0 0x15 0x0 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x15 0x1 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x15 0x2 IRQ_TYPE_EDGE_RISING>, + <0x0 0x15 0x4 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x15 0x5 IRQ_TYPE_EDGE_RISING>, + <0x0 0x15 0x6 IRQ_TYPE_EDGE_RISING>, + <0x0 0x15 0x7 IRQ_TYPE_EDGE_RISING>; + + interrupt-names = "typec-or-rid-detect-change", + "typec-vpd-detect", + "typec-cc-state-change", + "typec-vbus-change", + "typec-attach-detach", + "typec-legacy-cable-detect", + "typec-try-snk-src-detect"; + }; + + qcom,misc@1600 { + reg = <0x1600 0x100>; + interrupts = + <0x0 0x16 0x0 IRQ_TYPE_EDGE_RISING>, + <0x0 0x16 0x1 IRQ_TYPE_EDGE_RISING>, + <0x0 0x16 0x2 IRQ_TYPE_EDGE_RISING>, + <0x0 0x16 0x3 IRQ_TYPE_EDGE_RISING>, + <0x0 0x16 0x4 IRQ_TYPE_EDGE_RISING>, + <0x0 0x16 0x5 IRQ_TYPE_EDGE_RISING>, + <0x0 0x16 0x6 IRQ_TYPE_EDGE_BOTH>; + + interrupt-names = "wdog-snarl", + "wdog-bark", + "aicl-fail", + "aicl-done", + "imp-trigger", + "all-chnl-cond-done", + "temp-change"; + }; +}; From 63ee6dc21bebea6acbe1385e56dbd8b6b61f88da Mon Sep 17 00:00:00 2001 From: Sarthak Garg Date: Wed, 2 Sep 2020 11:15:52 +0530 Subject: [PATCH 061/103] ARM: dts: msm: Add PM-QOS and clk scaling support for shima Add PM-QOS and clk scaling support for eMMC/SD card on shima. Change-Id: I9baac414190bc6940211e4965504f2908accf6cc --- qcom/shima.dtsi | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi index ae02be1e1589..5f84b3f98e3e 100644 --- a/qcom/shima.dtsi +++ b/qcom/shima.dtsi @@ -1736,7 +1736,20 @@ non-removable; supports-cqe; + qcom,devfreq,freq-table = <50000000 200000000>; + qcom,scaling-lower-bus-speed-mode = "DDR52"; + status = "disabled"; + + qos0 { + mask = <0x0f>; + vote = <61>; + }; + + qos1 { + mask = <0xf0>; + vote = <67>; + }; }; sdhc_2: sdhci@8804000 { @@ -1784,7 +1797,19 @@ /* DLL HSR settings. Refer go/hsr - DLL settings */ qcom,dll-hsr-list = <0x0007642c 0x0 0x10 0x2C010800 0x80040868>; + qcom,devfreq,freq-table = <50000000 202000000>; + status = "disabled"; + + qos0 { + mask = <0x0f>; + vote = <61>; + }; + + qos1 { + mask = <0xf0>; + vote = <67>; + }; }; apps_rsc: rsc@18200000 { From 96c337f3f40ee08491377429c8a637cf839ac33d Mon Sep 17 00:00:00 2001 From: Sarthak Garg Date: Wed, 2 Sep 2020 10:23:53 +0530 Subject: [PATCH 062/103] ARM: dts: msm: Add PM-QOS and clk scaling support for holi Add PM-QOS and clk scaling support for eMMC/SD card on holi. Change-Id: I0d46a2a15a99af9be807e8cc41dcddd741c81b12 --- qcom/holi.dtsi | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/qcom/holi.dtsi b/qcom/holi.dtsi index f1ab2ea2a27e..faffdc18deaa 100644 --- a/qcom/holi.dtsi +++ b/qcom/holi.dtsi @@ -2204,7 +2204,20 @@ non-removable; supports-cqe; + qcom,devfreq,freq-table = <50000000 200000000>; + qcom,scaling-lower-bus-speed-mode = "DDR52"; + status = "disabled"; + + qos0 { + mask = <0x3f>; + vote = <61>; + }; + + qos1 { + mask = <0xc0>; + vote = <67>; + }; }; sdhc_2: sdhci@4784000 { @@ -2251,7 +2264,19 @@ iommus = <&apps_smmu 0x40 0x0>; qcom,iommu-dma = "bypass"; + qcom,devfreq,freq-table = <50000000 202000000>; + status = "disabled"; + + qos0 { + mask = <0x3f>; + vote = <61>; + }; + + qos1 { + mask = <0xc0>; + vote = <67>; + }; }; qcom,lpass@a400000 { From 6d624f3500e772ede0931a24169f0990af3e1ff8 Mon Sep 17 00:00:00 2001 From: Hareesh Gundu Date: Tue, 8 Sep 2020 20:15:00 +0530 Subject: [PATCH 063/103] ARM: dts: msm: Update GPU clock names for holi Update GPU clock names for holi to match with clock description. Change-Id: I4cc05e00cf9a37f79af857049bd4084d84b9058c --- qcom/holi-gpu.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/qcom/holi-gpu.dtsi b/qcom/holi-gpu.dtsi index 969737edfde3..c0728369bff4 100644 --- a/qcom/holi-gpu.dtsi +++ b/qcom/holi-gpu.dtsi @@ -25,8 +25,8 @@ msm_gpu: qcom,kgsl-3d0@5900000 { <&gcc GCC_GPU_MEMNOC_GFX_CLK>, <&gpucc GPU_CC_CX_GMU_CLK>; - clock-names = "core_clk", "rbbmtimer_clk", "mem_clk", - "iface_clk", "mem_iface_clk", "gmu_clk"; + clock-names = "core_clk", "rbbmtimer_clk", "iface_clk", + "ahb_clk", "mem_clk", "gmu_clk"; vddcx-supply = <&gpu_cx_gdsc>; vdd-supply = <&gpu_gx_gdsc>; From 925e17be1e1defb826888a7f354b79c5dd52e44e Mon Sep 17 00:00:00 2001 From: Murali Nalajala Date: Tue, 8 Sep 2020 12:35:05 -0700 Subject: [PATCH 064/103] ARM: dts: msm: remove spmi pmic address range MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit SPMI PMIC region was originally statically mapped in DT, but was removed and now subsections of it are dynamically lent instead. This was prior to RM parsing the LE VM DT; it looks like the region was kept in the DT, and now with DT parsing in RM the region is statically mapped again, and we’re seeing MEM_LEND failures due to conflicts with the region. Removing it should solve the issue. Change-Id: Ifaebc488a281966fbb193ecfb5e0f01ddd0279c1 --- qcom/lahaina-vm.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/qcom/lahaina-vm.dtsi b/qcom/lahaina-vm.dtsi index 8e541a5713b1..7db47e057a60 100644 --- a/qcom/lahaina-vm.dtsi +++ b/qcom/lahaina-vm.dtsi @@ -118,7 +118,6 @@ iomemory-ranges = <0x0 0x92c000 0x0 0x92c000 0x0 0x4000 0x0 0x0 0xc400000 0x0 0xc400000 0x0 0x30000 0x1 0x0 0xc440000 0x0 0xc440000 0x0 0x10000 0x1 - 0x0 0xc600000 0x0 0xc600000 0x0 0x2000000 0x1 0x0 0xe600000 0x0 0xe600000 0x0 0x100000 0x1 0x0 0xe700000 0x0 0xe700000 0x0 0xa0000 0x1 0x0 0xae8f000 0x0 0xae8f000 0x0 0x1000 0x0>; From bee6beacb153e3fbc993eadd277e25ec830b591a Mon Sep 17 00:00:00 2001 From: Ram Chandrasekar Date: Fri, 8 May 2020 11:49:20 -0700 Subject: [PATCH 065/103] ARM: dts: msm: Add MX SDPM configuration for lahaina Add MX SDPM configuration to monitor Camera, Video and other misc clocks for lahaina. Change-Id: I935ffb623a44b2306e62eb6982b137502fb41457 --- qcom/lahaina-thermal.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/qcom/lahaina-thermal.dtsi b/qcom/lahaina-thermal.dtsi index 4dea98aea115..fef8b81ceadb 100644 --- a/qcom/lahaina-thermal.dtsi +++ b/qcom/lahaina-thermal.dtsi @@ -17,6 +17,20 @@ }; }; +&soc { + mx_sdpm@0x00636000 { + compatible = "qcom,sdpm"; + reg = <0x00636000 0x1000>; + clock-names = "cam_cc_ipe", "video_cc_mvs0", "gcc_gp1"; + clocks = <&clock_camcc CAM_CC_IPE_0_CLK_SRC>, + <&clock_videocc VIDEO_CC_MVS0_CLK_SRC>, + <&clock_gcc GCC_GP1_CLK_SRC>; + cam_cc_ipe-supply = <&cam_cc_ipe_0_gdsc>; + video_cc_mvs0-supply = <&video_cc_mvs0_gdsc>; + csr-id = <1 3 5>; + }; +}; + &cpufreq_hw { qcom,cpu-isolation { compatible = "qcom,cpu-isolate"; From 0a0cf60da385fa87c91b1a87c0c8ef481ec93bd5 Mon Sep 17 00:00:00 2001 From: Ram Chandrasekar Date: Fri, 17 Jul 2020 12:32:27 -0700 Subject: [PATCH 066/103] ARM: dts: msm: Configure Policy engine for lahaina Enable policy engine sensor driver for MX rail policy engine hardware for lahaina. policy engine will recommend mitigation for all MX clients based on operating level. Change-Id: I55e2fed4f9b9e9ef3ea9bc0a575bebbcc45be705 --- qcom/lahaina-thermal.dtsi | 38 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/qcom/lahaina-thermal.dtsi b/qcom/lahaina-thermal.dtsi index fef8b81ceadb..561b0db16801 100644 --- a/qcom/lahaina-thermal.dtsi +++ b/qcom/lahaina-thermal.dtsi @@ -29,6 +29,13 @@ video_cc_mvs0-supply = <&video_cc_mvs0_gdsc>; csr-id = <1 3 5>; }; + + mx_pe: mx_rdpm_pe@0x00637000 { + compatible = "qcom,policy-engine"; + #thermal-sensor-cells = <0>; + reg = <0x00637000 0x1000>; + interrupts = ; + }; }; &cpufreq_hw { @@ -1134,5 +1141,36 @@ }; }; + mx-pe-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&mx_pe>; + thermal-governor = "step_wise"; + trips { + mx_pe_config1: mx-pe-config1 { + temperature = <1>; + hysteresis = <1>; + type = "passive"; + }; + + mx_pe_config2: mx-pe-config2 { + temperature = <2>; + hysteresis = <1>; + type = "passive"; + }; + }; + + cooling-maps { + mx_pe_cdev_1 { + trip = <&mx_pe_config1>; + cooling-device = <&cdsp_sw 1 1>; + }; + + mx_pe_cdev_2 { + trip = <&mx_pe_config2>; + cooling-device = <&msm_gpu 1 1>; + }; + }; + }; }; From 6c88af7e6b1e684be14de65fd50b00f90061014f Mon Sep 17 00:00:00 2001 From: Jack Pham Date: Wed, 9 Sep 2020 00:44:08 -0700 Subject: [PATCH 067/103] ARM: dts: msm: Update QMP USB UNI PHY sequence for Lahaina to v0.96 Update the QMP USB UNI PHY init sequence to the HSR v0.96 release. This should improve 5Gbps RX performance. Change-Id: I9ca5f7fab357312d9022ed6de29829bb0599c564 --- qcom/lahaina-usb.dtsi | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/qcom/lahaina-usb.dtsi b/qcom/lahaina-usb.dtsi index dfb0f8d3899b..c0b48ff2a264 100644 --- a/qcom/lahaina-usb.dtsi +++ b/qcom/lahaina-usb.dtsi @@ -510,11 +510,11 @@ USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH2 0xFF 0 USB3_UNI_QSERDES_RX_RX_MODE_00_HIGH 0x7F 0 USB3_UNI_QSERDES_RX_RX_MODE_00_LOW 0xFF 0 - USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH4 0xB4 0 + USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH4 0xA9 0 USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH3 0x7B 0 - USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH2 0x5C 0 - USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH 0xDC 0 - USB3_UNI_QSERDES_RX_RX_MODE_01_LOW 0xDC 0 + USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH2 0xE4 0 + USB3_UNI_QSERDES_RX_RX_MODE_01_HIGH 0x24 0 + USB3_UNI_QSERDES_RX_RX_MODE_01_LOW 0x64 0 USB3_UNI_QSERDES_RX_UCDR_PI_CONTROLS 0x99 0 USB3_UNI_QSERDES_RX_UCDR_SB2_THRESH1 0x08 0 USB3_UNI_QSERDES_RX_UCDR_SB2_THRESH2 0x08 0 @@ -523,7 +523,7 @@ USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_FO_GAIN 0x2F 0 USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_COUNT_LOW 0xFF 0 USB3_UNI_QSERDES_RX_UCDR_FASTLOCK_COUNT_HIGH 0x0F 0 - USB3_UNI_QSERDES_RX_UCDR_FO_GAIN 0x09 0 + USB3_UNI_QSERDES_RX_UCDR_FO_GAIN 0x0A 0 USB3_UNI_QSERDES_RX_VGA_CAL_CNTRL1 0x54 0 USB3_UNI_QSERDES_RX_VGA_CAL_CNTRL2 0x0F 0 USB3_UNI_QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2 0x0F 0 @@ -538,9 +538,10 @@ USB3_UNI_QSERDES_RX_SIGDET_ENABLES 0x00 0 USB3_UNI_QSERDES_TX_LANE_MODE_1 0xA5 0 USB3_UNI_QSERDES_TX_LANE_MODE_2 0x82 0 + USB3_UNI_QSERDES_TX_LANE_MODE_3 0x3F 0 USB3_UNI_QSERDES_TX_LANE_MODE_4 0x3F 0 USB3_UNI_QSERDES_TX_PI_QEC_CTRL 0x21 0 - USB3_UNI_QSERDES_TX_RES_CODE_LANE_OFFSET_TX 0x08 0 + USB3_UNI_QSERDES_TX_RES_CODE_LANE_OFFSET_TX 0x10 0 USB3_UNI_QSERDES_TX_RES_CODE_LANE_OFFSET_RX 0x0E 0 USB3_UNI_PCS_LOCK_DETECT_CONFIG1 0xD0 0 USB3_UNI_PCS_LOCK_DETECT_CONFIG2 0x07 0 From d3b1f5b25f6eb47209d55ad4c292c8cbecd496b9 Mon Sep 17 00:00:00 2001 From: Ritesh Kumar Date: Tue, 8 Sep 2020 19:32:44 +0530 Subject: [PATCH 068/103] ARM: dts: msm: 60Hz panel touch support on shima Add 60Hz command mode panel touch support on shima platform. Change-Id: I4867a8e490979de51282d01adada129e096b6f47 --- qcom/shima-idp.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/qcom/shima-idp.dtsi b/qcom/shima-idp.dtsi index 658759cfe27f..30f33b86cf9e 100644 --- a/qcom/shima-idp.dtsi +++ b/qcom/shima-idp.dtsi @@ -179,7 +179,8 @@ panel = <&dsi_r66451_amoled_cmd &dsi_r66451_amoled_video - &dsi_r66451_amoled_60hz_video>; + &dsi_r66451_amoled_60hz_video + &dsi_r66451_amoled_60hz_cmd>; }; }; From db37df704a9a49933521634355b75e65e8a106f2 Mon Sep 17 00:00:00 2001 From: Neeraj Upadhyay Date: Wed, 9 Sep 2020 17:29:03 +0530 Subject: [PATCH 069/103] ARM: dts: msm: Enable RCU expedited and no-cb cpus for Shima Enable RCU expedited mode for low latency RCU waits and no cbs to improve cpuidle behavior for Shima SoC. Change-Id: I9c79e432322db50f3e6f528a7695129e7f9b0268 --- qcom/shima.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi index 12f216ff1a21..457d3ddbc27f 100644 --- a/qcom/shima.dtsi +++ b/qcom/shima.dtsi @@ -443,7 +443,7 @@ }; chosen { - bootargs = "log_buf_len=256K earlycon=msm_geni_serial,0x994000"; + bootargs = "log_buf_len=256K earlycon=msm_geni_serial,0x994000 rcupdate.rcu_expedited=1 rcu_nocbs=0-7"; }; soc: soc { }; From 3ed9595ed0ade111134ec8634c3dbfa46ce92ec2 Mon Sep 17 00:00:00 2001 From: Faiz Nabi Kuchay Date: Wed, 9 Sep 2020 18:17:21 +0530 Subject: [PATCH 070/103] ARM: dts: qcom: add wsa base address to pkd reg Update the vbatt and temperature packed address to use WSA883X_BASE. Add static cps speaker protection configurations to enable cps speaker protection feature. Change-Id: I9ec6c0fb85afb135e630667fd64ed98c1607dd15 --- qcom/shima-audio-overlay.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/shima-audio-overlay.dtsi b/qcom/shima-audio-overlay.dtsi index a3b3958d27a3..c8c1d52a1d68 100644 --- a/qcom/shima-audio-overlay.dtsi +++ b/qcom/shima-audio-overlay.dtsi @@ -316,7 +316,7 @@ "wsa-codec1", "wsa-codec2"; qcom,wsa-max-devs = <2>; qcom,cps_reg_phy_addr = <0x3250300 0x3250304 0x3250318>; - qcom,cps_wsa_vbatt_temp_reg_addr = <0x0000429 0x0000422>; + qcom,cps_wsa_vbatt_temp_reg_addr = <0x0003429 0x0003422>; qcom,cps_threshold_levels = <148 168>; qcom,cps_normal_values = <0x8E 0x8F 0x8F>; qcom,cps_lower1_values = <0x10 0xD0 0xD0>; From 34da9bde8e54849d1884af10dbc77c4b45297a7a Mon Sep 17 00:00:00 2001 From: Saurabh Sahu Date: Tue, 8 Sep 2020 09:56:34 +0530 Subject: [PATCH 071/103] bindings: clock: Add support for flag to stop bimc logging Add flag in rpmcc to send request to RPM to stop the bimc logging. Change-Id: I03435431991ba7aa140744fbd12c056fab2c27d4 --- bindings/clock/qcom,rpmcc.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/bindings/clock/qcom,rpmcc.txt b/bindings/clock/qcom,rpmcc.txt index 498c5389a4a8..3d073dd00e36 100644 --- a/bindings/clock/qcom,rpmcc.txt +++ b/bindings/clock/qcom,rpmcc.txt @@ -33,6 +33,8 @@ not containing *_A_* in the enumerator name. Optional properties: - qcom,hw-clk-handoff : Add this property to support initial high votes on the to be sent to RPM as proxy votes. +- qcom,bimc-log-stop : Add this property to request RPM to stop the bimc + logging. Example: smd { From 9a8efe83bac56b041c6f65ab00b68a2f140de3c1 Mon Sep 17 00:00:00 2001 From: Ritesh Kumar Date: Wed, 9 Sep 2020 19:43:50 +0530 Subject: [PATCH 072/103] ARM: dts: msm: Add reserved memory for dfps data region on Shima Add reserved memory region dfps_data_region on shima target. Change-Id: Ie35b14a580ac9590fd61d77255afc9a435c6a913 --- qcom/shima.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi index 12f216ff1a21..33f6fec9d94d 100644 --- a/qcom/shima.dtsi +++ b/qcom/shima.dtsi @@ -440,6 +440,11 @@ reg = <0x0 0xe1000000 0x0 0x02300000>; label = "cont_splash_region"; }; + + dfps_data_memory: dfps_data_memory { + reg = <0x0 0xe3300000 0x0 0x0100000>; + label = "dfps_data_memory"; + }; }; chosen { From 1fb68d969c806a6b86ed215f2bd69f7f6055aacc Mon Sep 17 00:00:00 2001 From: Tony Truong Date: Wed, 9 Sep 2020 09:20:58 -0700 Subject: [PATCH 073/103] ARM: dts: msm: Update PCIe0 PHY settings to v1.01 for lahaina v2.1 Update PCIe0 PHY setting to version 1.01 based on hardware recommendation for lahaina v2.1. Change-Id: I5c9e0babc90ffaebe6867a724944cd883e5d3acd --- qcom/lahaina-v2.1.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/qcom/lahaina-v2.1.dtsi b/qcom/lahaina-v2.1.dtsi index f3752b851370..15408d1cb09f 100644 --- a/qcom/lahaina-v2.1.dtsi +++ b/qcom/lahaina-v2.1.dtsi @@ -8,7 +8,7 @@ &pcie0 { qcom,l1ss-sleep-disable = <0x0>; - qcom,pcie-phy-ver = <21100>; + qcom,pcie-phy-ver = <21101>; qcom,phy-sequence = <0x0240 0x03 0x0 0x0094 0x08 0x0 0x0154 0x34 0x0 @@ -66,6 +66,7 @@ 0x1180 0xa6 0x0 0x1190 0x34 0x0 0x10d8 0x07 0x0 + 0x0e3c 0x1d 0x0 0x0e40 0x0c 0x0 0x10dc 0x00 0x0 0x104c 0x08 0x0 @@ -78,7 +79,7 @@ 0x06a8 0x0f 0x0 0x0048 0x90 0x0 0x0620 0xc1 0x0 - 0x0388 0xa8 0x0 + 0x0388 0x77 0x0 0x0398 0x0b 0x0 0x02dc 0x05 0x0 0x0200 0x00 0x0 From b7c94b0b84873faa42195ef0f319818600425f76 Mon Sep 17 00:00:00 2001 From: Mukesh Ojha Date: Wed, 9 Sep 2020 22:04:49 +0530 Subject: [PATCH 074/103] ARM: dts: msm: Keep a DDR proxy vote for modem pil for Shima Keep a proxy DDR vote for modem pil, to meet the bandwidth requirements during modem SSR. Change-Id: I2150ca5d28a31ff824015d2a623fa173214bd6e3 --- qcom/shima.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi index 4170db3da48b..16cdc2c5d74e 100644 --- a/qcom/shima.dtsi +++ b/qcom/shima.dtsi @@ -2663,6 +2663,8 @@ qcom,signal-aop; qcom,complete-ramdump; + interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>; + /* Inputs from mss */ interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, <&modem_smp2p_in 0 0>, From def53353f6bff28def1a1619a08b4c87941a9460 Mon Sep 17 00:00:00 2001 From: Tony Truong Date: Wed, 9 Sep 2020 09:43:00 -0700 Subject: [PATCH 075/103] ARM: dts: msm: Update PCIe1 PHY settings to v1.06 for lahaina Update PCIe1 PHY setting to version v1.06 based on hardware recommendation for lahaina. Change-Id: I89df7f8202ae97d5fc0fe4059d379d97a23dba69 --- qcom/lahaina-pcie.dtsi | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/qcom/lahaina-pcie.dtsi b/qcom/lahaina-pcie.dtsi index 055e3d3bc9d3..451f2627764f 100644 --- a/qcom/lahaina-pcie.dtsi +++ b/qcom/lahaina-pcie.dtsi @@ -336,7 +336,7 @@ qcom,slv-addr-space-size = <0x20000000>; qcom,ep-latency = <10>; - qcom,pcie-phy-ver = <1104>; + qcom,pcie-phy-ver = <1106>; qcom,phy-status-offset = <0x214>; qcom,phy-status-bit = <6>; qcom,phy-power-down-offset = <0x240>; @@ -408,12 +408,16 @@ 0x1978 0x5c 0x0 0x197c 0x34 0x0 0x1980 0xa6 0x0 + 0x10cc 0xf0 0x0 + 0x18cc 0xf0 0x0 0x10d8 0x0f 0x0 0x18d8 0x0f 0x0 0x10dc 0x00 0x0 0x18dc 0x00 0x0 0x11a4 0x38 0x0 0x19a4 0x38 0x0 + 0x0e3c 0x1d 0x0 + 0x163c 0x1d 0x0 0x0e40 0x0c 0x0 0x1640 0x0c 0x0 0x1190 0x34 0x0 @@ -423,7 +427,7 @@ 0x1050 0x08 0x0 0x1850 0x08 0x0 0x02dc 0x05 0x0 - 0x0388 0x88 0x0 + 0x0388 0x77 0x0 0x0398 0x0b 0x0 0x03e0 0x0f 0x0 0x060c 0x1d 0x0 From fef117d47d1e3076446c04882ea7d004e742ba5b Mon Sep 17 00:00:00 2001 From: Young Kwak Date: Tue, 25 Aug 2020 21:46:09 +0900 Subject: [PATCH 076/103] ARM: dts: msm: Add tzone-names for lahaina GPU Add GPU tzone-names to get the GPU temperature on lahaina. CRs-Fixed: 2765368 Change-Id: I8acbb6aee4a98f9e1e3b3b18a77cd798dc24ff3a --- bindings/gpu/adreno.txt | 6 +++--- qcom/lahaina-gpu.dtsi | 2 ++ 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/bindings/gpu/adreno.txt b/bindings/gpu/adreno.txt index 4356056a77d9..de91a4ee875e 100644 --- a/bindings/gpu/adreno.txt +++ b/bindings/gpu/adreno.txt @@ -198,9 +198,9 @@ Optional Properties: baseAddr - base address of the qtimer memory region size - size of the qtimer region -- qcom,tsens-name: - Specify the name of GPU temperature sensor. This name will be used - to get the temperature from the thermal driver API. +- qcom,tzone-names: + Specify the names of GPU thermal zones. These will be used + to get gpu temperature from the thermal driver API. - qcom,enable-midframe-timer: Boolean. Enables the use of midframe sampling timer. This timer diff --git a/qcom/lahaina-gpu.dtsi b/qcom/lahaina-gpu.dtsi index 1292871e224f..bcd4c115d580 100644 --- a/qcom/lahaina-gpu.dtsi +++ b/qcom/lahaina-gpu.dtsi @@ -51,6 +51,8 @@ qcom,gpu-qdss-stm = <0x161c0000 0x40000>; /* base addr, size */ + qcom,tzone-names = "gpuss-0-usr", "gpuss-1-usr"; + interconnects = <&gem_noc MASTER_GFX3D &mc_virt SLAVE_EBI1>; interconnect-names = "gpu_icc_path"; From ea4e6c99bdb73a0322d58592332b4687d7777481 Mon Sep 17 00:00:00 2001 From: Amir Samuelov Date: Thu, 3 Sep 2020 17:55:35 +0300 Subject: [PATCH 077/103] ARM: dts: msm: spss_utils: spss shared registers provide spss shared registers address to spss_utils. Change-Id: I7d2727a2936f9dc3770bb4483fa7778e6475f046 --- qcom/lahaina.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/lahaina.dtsi b/qcom/lahaina.dtsi index b1aecf09e4ed..5545caa29a7f 100644 --- a/qcom/lahaina.dtsi +++ b/qcom/lahaina.dtsi @@ -5212,6 +5212,7 @@ qcom,spss-test-firmware-name = "spss1t"; /* 8 chars max */ qcom,spss-prod-firmware-name = "spss1p"; /* 8 chars max */ qcom,spss-debug-reg-addr = <0x01886020>; + qcom,spss-scsr-regs-addr = <0x01880000>; /* SPU shared register */ qcom,spss-emul-type-reg-addr = <0x01fc8004>; pil-mem = <&pil_spss_mem>; qcom,pil-size = <0x0F0000>; // padding to 960 KB From 0b66ae83074a005bfc2361664c8e25ffc01e0e96 Mon Sep 17 00:00:00 2001 From: Aasir Rasheed Date: Thu, 10 Sep 2020 16:07:07 +0530 Subject: [PATCH 078/103] ARM: dts: msm: Update cnss dt node for bus bandwidth for shima Configure bandwidth vote data from aggre2_noc to aggre1_noc. Change-Id: If02573cf171022a3b69cf72f868a7345489d1f2a --- qcom/shima.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi index c60a2aa56528..f552b2fa60bf 100644 --- a/qcom/shima.dtsi +++ b/qcom/shima.dtsi @@ -3432,7 +3432,7 @@ qcom,wlan-ant-switch-config = <2800000 2800000 0 0 0>; interconnects = - <&aggre2_noc MASTER_PCIE_0 &aggre2_noc SLAVE_ANOC_PCIE_GEM_NOC>, + <&aggre1_noc MASTER_PCIE_0 &aggre1_noc SLAVE_ANOC_PCIE_GEM_NOC>, <&gem_noc MASTER_ANOC_PCIE_GEM_NOC &mc_virt SLAVE_EBI1>; interconnect-names = "pcie_to_memnoc", "memnoc_to_ddr"; From 8b88a78edae695ba0905367f19c639016c5332b0 Mon Sep 17 00:00:00 2001 From: Ritesh Kumar Date: Thu, 10 Sep 2020 16:55:27 +0530 Subject: [PATCH 079/103] ARM: dts: msm: alter size for QUPv3 SE4 on lahaina QRD Alter size for Serial Engine 4 memory while lending in trusted touch usecase. Change-Id: Iadebef94e608f0af73408be85aa8c2a673a2a759 --- qcom/lahaina-qrd-common.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/lahaina-qrd-common.dtsi b/qcom/lahaina-qrd-common.dtsi index fde9bc11fb6f..87a2b5fff5b6 100644 --- a/qcom/lahaina-qrd-common.dtsi +++ b/qcom/lahaina-qrd-common.dtsi @@ -210,7 +210,7 @@ focaltech,touch-environment = "pvm"; focaltech,trusted-touch-spi-irq = <566>; focaltech,trusted-touch-io-bases = <0xF114000 0xF115000 0xF116000 0xF117000 0x990000 0x00910000>; - focaltech,trusted-touch-io-sizes = <0x1000 0x1000 0x1000 0x1000 0x4000 0x4000>; + focaltech,trusted-touch-io-sizes = <0x1000 0x1000 0x1000 0x1000 0x1000 0x4000>; }; }; From 45e58cc22c8249a9fdf495ba3affbfbfcde2bef7 Mon Sep 17 00:00:00 2001 From: Ritesh Kumar Date: Sun, 6 Sep 2020 02:15:13 +0530 Subject: [PATCH 080/103] ARM: dts: msm: Add focaltech node in trustedvm devicetree Add focaltech node for trusted vm device tree and enable trusted touch on trusted vm for lahaina qrd. Also, move fts node to mtp and cdp vm dtsi file. Change-Id: I2e8f80a2b6c622c02526cbc6a2b2a1f8d632d593 --- qcom/lahaina-vm-cdp.dtsi | 17 +++++++++++++++++ qcom/lahaina-vm-mtp.dtsi | 17 +++++++++++++++++ qcom/lahaina-vm-qrd.dtsi | 13 +++++++++++++ qcom/lahaina-vm.dtsi | 13 ------------- 4 files changed, 47 insertions(+), 13 deletions(-) diff --git a/qcom/lahaina-vm-cdp.dtsi b/qcom/lahaina-vm-cdp.dtsi index e62004ae5e1e..56be11e2913b 100644 --- a/qcom/lahaina-vm-cdp.dtsi +++ b/qcom/lahaina-vm-cdp.dtsi @@ -1 +1,18 @@ /*#include "display/lahaina-sde-display-cdp.dtsi"*/ + +&qupv3_se4_i2c { + status = "ok"; + st_fts@49 { + compatible = "st,fts"; + reg = <0x49>; + st,x-flip = <1>; + st,y-flip = <1>; + st,regulator_dvdd = "vdd"; + st,regulator_avdd = "avdd"; + st,trusted-touch-mode = "vm_mode"; + st,touch-environment = "tvm"; + st,trusted-touch-spi-irq = <566>; + st,trusted-touch-io-bases = <0xF114000 0xF115000 0xF116000 0xF117000 0x990000 0x00910000>; + st,trusted-touch-io-sizes = <0x1000 0x1000 0x1000 0x1000 0x1000 0x4000>; + }; +}; diff --git a/qcom/lahaina-vm-mtp.dtsi b/qcom/lahaina-vm-mtp.dtsi index 7411556ed73b..135ba4fbeeb6 100644 --- a/qcom/lahaina-vm-mtp.dtsi +++ b/qcom/lahaina-vm-mtp.dtsi @@ -1 +1,18 @@ /*#include "display/lahaina-sde-display-mtp.dtsi"*/ + +&qupv3_se4_i2c { + status = "ok"; + st_fts@49 { + compatible = "st,fts"; + reg = <0x49>; + st,x-flip = <1>; + st,y-flip = <1>; + st,regulator_dvdd = "vdd"; + st,regulator_avdd = "avdd"; + st,trusted-touch-mode = "vm_mode"; + st,touch-environment = "tvm"; + st,trusted-touch-spi-irq = <566>; + st,trusted-touch-io-bases = <0xF114000 0xF115000 0xF116000 0xF117000 0x990000 0x00910000>; + st,trusted-touch-io-sizes = <0x1000 0x1000 0x1000 0x1000 0x1000 0x4000>; + }; +}; diff --git a/qcom/lahaina-vm-qrd.dtsi b/qcom/lahaina-vm-qrd.dtsi index ed306e6a6f78..51e7b6de33a9 100644 --- a/qcom/lahaina-vm-qrd.dtsi +++ b/qcom/lahaina-vm-qrd.dtsi @@ -1 +1,14 @@ /*#include "display/lahaina-sde-display-qrd.dtsi"*/ + +&qupv3_se4_i2c { + status = "ok"; + focaltech@38 { + compatible = "focaltech,fts_ts"; + reg = <0x38>; + focaltech,trusted-touch-mode = "vm_mode"; + focaltech,touch-environment = "tvm"; + focaltech,trusted-touch-spi-irq = <566>; + focaltech,trusted-touch-io-bases = <0xF114000 0xF115000 0xF116000 0xF117000 0x990000 0x00910000>; + focaltech,trusted-touch-io-sizes = <0x1000 0x1000 0x1000 0x1000 0x1000 0x4000>; + }; +}; diff --git a/qcom/lahaina-vm.dtsi b/qcom/lahaina-vm.dtsi index 16ccc249fafa..5f14095b5dd1 100644 --- a/qcom/lahaina-vm.dtsi +++ b/qcom/lahaina-vm.dtsi @@ -302,19 +302,6 @@ qcom,wrapper-core = <&qupv3_0>; qcom,le-vm; status = "ok"; - st_fts@49 { - compatible = "st,fts"; - reg = <0x49>; - st,x-flip = <1>; - st,y-flip = <1>; - st,regulator_dvdd = "vdd"; - st,regulator_avdd = "avdd"; - st,trusted-touch-mode = "vm_mode"; - st,touch-environment = "tvm"; - st,trusted-touch-spi-irq = <566>; - st,trusted-touch-io-bases = <0xF114000 0xF115000 0xF116000 0xF117000 0x990000 0x00910000>; - st,trusted-touch-io-sizes = <0x1000 0x1000 0x1000 0x1000 0x1000 0x4000>; - }; }; qupv3_se4_spi: spi@990000 { From efc201b44b1386c781f8ac4dc29e66ac109f8c5c Mon Sep 17 00:00:00 2001 From: Ritesh Kumar Date: Sun, 6 Sep 2020 02:21:58 +0530 Subject: [PATCH 081/103] ARM: dts: msm: Include display panel for Trusted UI Include display panel for Truested UI on lahaina QRD. Change-Id: Id3531e9d073bb3ec09f36e5b3107ac56da09b430 --- qcom/lahaina-vm.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/qcom/lahaina-vm.dtsi b/qcom/lahaina-vm.dtsi index 5f14095b5dd1..24826e34f88b 100644 --- a/qcom/lahaina-vm.dtsi +++ b/qcom/lahaina-vm.dtsi @@ -334,3 +334,5 @@ #include "display/trustedvm-lahaina-sde-display.dtsi" #include "display/dsi-panel-sw43404-amoled-dsc-wqhd-cmd.dtsi" #include "display/dsi-panel-sw43404-amoled-dsc-wqhd-video.dtsi" +#include "display/dsi-panel-r66451-dsc-fhd-plus-cmd.dtsi" +#include "display/dsi-panel-r66451-dsc-fhd-plus-video.dtsi" From 8b39e87824d73e8e7bf42074315eb168308d32e3 Mon Sep 17 00:00:00 2001 From: Jishnu Prakash Date: Wed, 9 Sep 2020 16:34:34 +0530 Subject: [PATCH 082/103] ARM: dts: msm: Enable WLED for holi LCD platform Enable WLED in place of AMOLED for holi CDP platform using LCD. Change-Id: If005a5d52d82e4c72bfcea2b46550121172d8714 --- qcom/holi-cdp-lcd.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/qcom/holi-cdp-lcd.dtsi b/qcom/holi-cdp-lcd.dtsi index 3021000b5376..b5e20250c0b9 100644 --- a/qcom/holi-cdp-lcd.dtsi +++ b/qcom/holi-cdp-lcd.dtsi @@ -1 +1,16 @@ #include "holi-cdp.dtsi" + +&pm6150a_amoled { + status = "disabled"; +}; + +&pm6150l_lcdb { + status = "ok"; +}; + +&pm6150l_wled { + status = "ok"; + qcom,string-cfg = <15>; + qcom,leds-per-string = <4>; +}; + From c3cdcaddc2241a2e31aa45c2866ac620929d9a15 Mon Sep 17 00:00:00 2001 From: "Isaac J. Manjarres" Date: Tue, 1 Sep 2020 01:30:19 -0700 Subject: [PATCH 083/103] ARM: dts: msm: Use a carveout for memshare memory The memshare driver currently uses CMA memory for its usecases. This is problematic, as CMA memory has a normal cached mapping in the kernel, which allows for speculative access. This makes it possible for a speculative cache-line fill to occur, prior to the memory being unmapped from the stage-2 page tables of Linux, as well as XPU protected. The cache-line can later be evicted, while the memory is still XPU protected. This results in a write to the system cache, which is blocked by the XPU, resulting in an XPU violation. Given the nature of the memshare usecases (i.e. the memory is allocated once, and never given back to Linux), move the memshare driver to using a carveout. Using a carveout makes it so that there are no normal cached mappings in the kernel for the memory, which prevents speculative cache-line fills from occurring. Change-Id: I97e2fe144c8fde364ecd40fdd181a881ca93c4b1 --- qcom/holi.dtsi | 9 +++++++++ qcom/lahaina.dtsi | 14 ++++++++++++++ qcom/shima.dtsi | 9 +++++++++ 3 files changed, 32 insertions(+) diff --git a/qcom/holi.dtsi b/qcom/holi.dtsi index bb11e3532557..b6200c578fcd 100644 --- a/qcom/holi.dtsi +++ b/qcom/holi.dtsi @@ -381,6 +381,14 @@ alignment = <0x0 0x400000>; size = <0x0 0x1000000>; }; + + memshare_mem: memshare_region { + compatible = "shared-dma-pool"; + no-map; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + alignment = <0x0 0x100000>; + size = <0x0 0x800000>; + }; }; soc: soc { }; @@ -1044,6 +1052,7 @@ qcom,client_3 { compatible = "qcom,memshare-peripheral"; qcom,peripheral-size = <0x500000>; + memory-region = <&memshare_mem>; qcom,client-id = <1>; qcom,allocate-on-request; label = "modem"; diff --git a/qcom/lahaina.dtsi b/qcom/lahaina.dtsi index ad41e9a34f1d..24a2aa33f694 100644 --- a/qcom/lahaina.dtsi +++ b/qcom/lahaina.dtsi @@ -523,6 +523,19 @@ label = "dfps_data_region"; }; + memshare_mem: memshare_region { + compatible = "shared-dma-pool"; + no-map; + /* + * Memory shared with modem needs to be outside of + * the CLADE address space, which begins at + * 0xE0000000 and spans 512 MB. + */ + alloc-ranges = <0x0 0x00000000 0x0 0xdfffffff>; + alignment = <0x0 0x100000>; + size = <0x0 0x800000>; + }; + non_secure_display_memory: non_secure_display_region { compatible = "shared-dma-pool"; alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; @@ -2288,6 +2301,7 @@ qcom,client_3 { compatible = "qcom,memshare-peripheral"; qcom,peripheral-size = <0x500000>; + memory-region = <&memshare_mem>; qcom,client-id = <1>; qcom,allocate-on-request; label = "modem"; diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi index c60a2aa56528..1fbf1e069ec4 100644 --- a/qcom/shima.dtsi +++ b/qcom/shima.dtsi @@ -428,6 +428,14 @@ size = <0x0 0x400000>; }; + memshare_mem: memshare_region { + compatible = "shared-dma-pool"; + no-map; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + alignment = <0x0 0x100000>; + size = <0x0 0x800000>; + }; + dump_mem: mem_dump_region { compatible = "shared-dma-pool"; alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; @@ -775,6 +783,7 @@ qcom,client_3 { compatible = "qcom,memshare-peripheral"; qcom,peripheral-size = <0x500000>; + memory-region = <&memshare_mem>; qcom,client-id = <1>; qcom,allocate-on-request; label = "modem"; From 9f163a1164f69443baf43ddc9672c1dbe9e6c70e Mon Sep 17 00:00:00 2001 From: Ram Chandrasekar Date: Fri, 4 Sep 2020 10:54:56 -0700 Subject: [PATCH 084/103] ARM: dts: msm: Add a two second polling for PMIC alarm in lahaina Add a two second polling for PMIC temperature alarm sensor to ensure the software is in sync with hardware. Change-Id: I5d0fc8eba6295b338252833581207d2ab189e33b --- qcom/pm8350.dtsi | 2 +- qcom/pm8350b.dtsi | 2 +- qcom/pm8350c.dtsi | 2 +- qcom/pmr735a.dtsi | 2 +- qcom/pmr735b.dtsi | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/qcom/pm8350.dtsi b/qcom/pm8350.dtsi index f833cdfcce88..62e0670463e9 100644 --- a/qcom/pm8350.dtsi +++ b/qcom/pm8350.dtsi @@ -34,7 +34,7 @@ &thermal_zones { pm8350_temp_alarm: pm8350_tz { polling-delay-passive = <100>; - polling-delay = <0>; + polling-delay = <2000>; thermal-governor = "step_wise"; thermal-sensors = <&pm8350_tz>; diff --git a/qcom/pm8350b.dtsi b/qcom/pm8350b.dtsi index c9110d289922..b84ffeffe9b3 100644 --- a/qcom/pm8350b.dtsi +++ b/qcom/pm8350b.dtsi @@ -223,7 +223,7 @@ &thermal_zones { pm8350b_temp_alarm: pm8350b_tz { polling-delay-passive = <100>; - polling-delay = <0>; + polling-delay = <2000>; thermal-governor = "step_wise"; thermal-sensors = <&pm8350b_tz>; diff --git a/qcom/pm8350c.dtsi b/qcom/pm8350c.dtsi index 18213cc1a503..4f73e63f992f 100644 --- a/qcom/pm8350c.dtsi +++ b/qcom/pm8350c.dtsi @@ -230,7 +230,7 @@ &thermal_zones { pm8350c_temp_alarm: pm8350c_tz { polling-delay-passive = <100>; - polling-delay = <0>; + polling-delay = <2000>; thermal-governor = "step_wise"; thermal-sensors = <&pm8350c_tz>; diff --git a/qcom/pmr735a.dtsi b/qcom/pmr735a.dtsi index d1459e152b68..338d801b8d39 100644 --- a/qcom/pmr735a.dtsi +++ b/qcom/pmr735a.dtsi @@ -34,7 +34,7 @@ &thermal_zones { pmr735a_temp_alarm: pmr735a_tz { polling-delay-passive = <100>; - polling-delay = <0>; + polling-delay = <2000>; thermal-governor = "step_wise"; thermal-sensors = <&pmr735a_tz>; diff --git a/qcom/pmr735b.dtsi b/qcom/pmr735b.dtsi index 50f05e4ae90d..420d0cd6b7f9 100644 --- a/qcom/pmr735b.dtsi +++ b/qcom/pmr735b.dtsi @@ -34,7 +34,7 @@ &thermal_zones { pmr735b_temp_alarm: pmr735b_tz { polling-delay-passive = <100>; - polling-delay = <0>; + polling-delay = <2000>; thermal-governor = "step_wise"; thermal-sensors = <&pmr735b_tz>; From 8ac529888ab91917efcbec94bf464e0073789132 Mon Sep 17 00:00:00 2001 From: Yuanfang Zhang Date: Fri, 11 Sep 2020 10:51:31 +0800 Subject: [PATCH 085/103] ARM: dts: msm: Correct name of tpdm ACTPM on holi The coresight TPDM name for ACTPM is spelled wrong as ACPTM, this change fix this issue. Change-Id: I0d5d6b3d40ac2b705a98a2b33ac49e7ccefc6bcf --- qcom/holi-coresight.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/qcom/holi-coresight.dtsi b/qcom/holi-coresight.dtsi index f6db99b519d2..bb43ec947b84 100644 --- a/qcom/holi-coresight.dtsi +++ b/qcom/holi-coresight.dtsi @@ -353,13 +353,13 @@ }; }; - tpdm_acptm: tpdm@9860000 { + tpdm_actpm: tpdm@9860000 { compatible = "arm,primecell"; arm,primecell-periphid = <0x000bb968>; reg = <0x9860000 0x1000>; reg-names = "tpdm-base"; - coresight-name = "coresight-tpdm-acptm"; + coresight-name = "coresight-tpdm-actpm"; clocks = <&rpmcc RPM_SMD_QDSS_CLK>; clock-names = "apb_pclk"; From 78902b1136867da6dcbaa3306ae286038a06f3d3 Mon Sep 17 00:00:00 2001 From: Gaurav Kohli Date: Thu, 10 Sep 2020 16:38:00 +0530 Subject: [PATCH 086/103] dt-bindings: Add Dt binding for rimps mailbox Adding rimps mailbox controller Dt binding. Change-Id: I4b20b50f9a2d600affba29e518eaae28ad8e6275 --- bindings/soc/qcom/qcom,rimps.yaml | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) create mode 100644 bindings/soc/qcom/qcom,rimps.yaml diff --git a/bindings/soc/qcom/qcom,rimps.yaml b/bindings/soc/qcom/qcom,rimps.yaml new file mode 100644 index 000000000000..4b75a6fb96fb --- /dev/null +++ b/bindings/soc/qcom/qcom,rimps.yaml @@ -0,0 +1,28 @@ +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bindings/soc/qcom/qcom,rimps.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. Rimps Mailbox controller driver + +description: | + This mailbox controller act as interface to do doorbell between + HLOS and Rimps subsystem. + +properties: + compatible: + Usage: required + Value type: + Definition: Must be "qcom,rimps" + +example: + - | + qcom,rimps@0f400000 { + #address-cells = <2>; + #size-cells = <2>; + compatible = "qcom,rimps"; + reg = <0x0f400000 0x10>, + <0x0fd90000 0x2000>; + #mbox-cells = <1>; + status = "ok"; + }; From 7bde323c183835739501a26b8fc002b40b3f3d3a Mon Sep 17 00:00:00 2001 From: "Tao,Zhang" Date: Fri, 11 Sep 2020 17:59:00 +0800 Subject: [PATCH 087/103] ARM: dts: msm: Add llcc dcache dump nodes for shima Add llcc_1_dcache and llcc_2_dcache dump node to support these two registers dump. Change-Id: I7a390633f7b24bbce828104c85e4787019ba9206 --- qcom/shima.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi index c60a2aa56528..8dde846ab102 100644 --- a/qcom/shima.dtsi +++ b/qcom/shima.dtsi @@ -3348,6 +3348,16 @@ qcom,dump-id = <0x102>; }; + LLCC_1: llcc_1_dcache { + qcom,dump-size = <0x1141c0>; + qcom,dump-id = <0x140>; + }; + + LLCC_2: llcc_2_dcache { + qcom,dump-size = <0x1141c0>; + qcom,dump-id = <0x141>; + }; + misc_data { qcom,dump-size = <0x1000>; qcom,dump-id = <0xe8>; From 82fe61de79267f9dab408e85325bc3c7227b661d Mon Sep 17 00:00:00 2001 From: Govindaraj Rajagopal Date: Fri, 11 Sep 2020 15:34:59 +0530 Subject: [PATCH 088/103] ARM: dts: msm: Add DMA coherency hint for shima Add 'dma-coherent-hint-cached' property to vidc context banks in order to skip explicit cache operations from vidc driver. Change-Id: I2b95b803d00f7ead89435b7760b6e01e136214e6 --- qcom/shima-vidc.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/shima-vidc.dtsi b/qcom/shima-vidc.dtsi index c345c997e467..0c18ced0caaa 100644 --- a/qcom/shima-vidc.dtsi +++ b/qcom/shima-vidc.dtsi @@ -54,6 +54,7 @@ qcom,iommu-pagetable = "LLC"; buffer-types = <0xfff>; virtual-addr-pool = <0x25800000 0xba800000>; + dma-coherent-hint-cached; }; secure_non_pixel_cb { From e125a334037fc4364d9d85e57f25b6e67eb8aaa5 Mon Sep 17 00:00:00 2001 From: Hareesh Gundu Date: Mon, 17 Aug 2020 14:28:17 +0530 Subject: [PATCH 089/103] ARM: dts: msm: Add GPU SMMU clocks for holi Add required GPU SMMU clocks for holi to avoid the un-clocked register access from the gpu driver. Change-Id: I3d46b26d8a0c1dc106aba675e9df26d48528001e --- qcom/holi-gpu.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/qcom/holi-gpu.dtsi b/qcom/holi-gpu.dtsi index 969737edfde3..0ccb298d8451 100644 --- a/qcom/holi-gpu.dtsi +++ b/qcom/holi-gpu.dtsi @@ -314,6 +314,13 @@ msm_gpu: qcom,kgsl-3d0@5900000 { vddcx-supply = <&gpu_cx_gdsc>; + clocks = <&gcc GCC_BIMC_GPU_AXI_CLK>, + <&gpucc GPU_CC_AHB_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>; + + clock-names = "gcc_bimc_gpu_axi", "gpu_cc_ahb", + "gcc_gpu_memnoc_gfx"; + gfx3d_user: gfx3d_user { compatible = "qcom,smmu-kgsl-cb"; iommus = <&kgsl_smmu 0x0>; From 71d7684d12ad41795359fc3c0812bee7987431b5 Mon Sep 17 00:00:00 2001 From: Ram Chandrasekar Date: Fri, 11 Sep 2020 14:33:49 -0700 Subject: [PATCH 090/103] Revert "ARM: dts: msm: Add a two second polling for PMIC alarm in lahaina" This reverts commit 9f163a1164f69443baf43ddc9672c1dbe9e6c70e. The two second polling could trigger a shutdown when there is spurious high temperature read in ADC sensor. Change-Id: I2aee6827ff7caefddd881dafb77e85646515b013 --- qcom/pm8350.dtsi | 2 +- qcom/pm8350b.dtsi | 2 +- qcom/pm8350c.dtsi | 2 +- qcom/pmr735a.dtsi | 2 +- qcom/pmr735b.dtsi | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/qcom/pm8350.dtsi b/qcom/pm8350.dtsi index 62e0670463e9..f833cdfcce88 100644 --- a/qcom/pm8350.dtsi +++ b/qcom/pm8350.dtsi @@ -34,7 +34,7 @@ &thermal_zones { pm8350_temp_alarm: pm8350_tz { polling-delay-passive = <100>; - polling-delay = <2000>; + polling-delay = <0>; thermal-governor = "step_wise"; thermal-sensors = <&pm8350_tz>; diff --git a/qcom/pm8350b.dtsi b/qcom/pm8350b.dtsi index b84ffeffe9b3..c9110d289922 100644 --- a/qcom/pm8350b.dtsi +++ b/qcom/pm8350b.dtsi @@ -223,7 +223,7 @@ &thermal_zones { pm8350b_temp_alarm: pm8350b_tz { polling-delay-passive = <100>; - polling-delay = <2000>; + polling-delay = <0>; thermal-governor = "step_wise"; thermal-sensors = <&pm8350b_tz>; diff --git a/qcom/pm8350c.dtsi b/qcom/pm8350c.dtsi index 4f73e63f992f..18213cc1a503 100644 --- a/qcom/pm8350c.dtsi +++ b/qcom/pm8350c.dtsi @@ -230,7 +230,7 @@ &thermal_zones { pm8350c_temp_alarm: pm8350c_tz { polling-delay-passive = <100>; - polling-delay = <2000>; + polling-delay = <0>; thermal-governor = "step_wise"; thermal-sensors = <&pm8350c_tz>; diff --git a/qcom/pmr735a.dtsi b/qcom/pmr735a.dtsi index 338d801b8d39..d1459e152b68 100644 --- a/qcom/pmr735a.dtsi +++ b/qcom/pmr735a.dtsi @@ -34,7 +34,7 @@ &thermal_zones { pmr735a_temp_alarm: pmr735a_tz { polling-delay-passive = <100>; - polling-delay = <2000>; + polling-delay = <0>; thermal-governor = "step_wise"; thermal-sensors = <&pmr735a_tz>; diff --git a/qcom/pmr735b.dtsi b/qcom/pmr735b.dtsi index 420d0cd6b7f9..50f05e4ae90d 100644 --- a/qcom/pmr735b.dtsi +++ b/qcom/pmr735b.dtsi @@ -34,7 +34,7 @@ &thermal_zones { pmr735b_temp_alarm: pmr735b_tz { polling-delay-passive = <100>; - polling-delay = <2000>; + polling-delay = <0>; thermal-governor = "step_wise"; thermal-sensors = <&pmr735b_tz>; From 0e3f40297c19593da77ab810e7e50ffcfd0b11d9 Mon Sep 17 00:00:00 2001 From: Mohammed Mirza Mandayappurath Manzoor Date: Sun, 30 Aug 2020 20:18:50 -0700 Subject: [PATCH 091/103] ARM: dts: qcom: Update ACD control register values for A660v2 Update the dvm values for optimizing ACD performance and enable ACD on lower levels. Change-Id: I0031f5cbb0e19b132980951b4ff9abeff9204656 --- qcom/lahaina-v2-gpu.dtsi | 20 ++++++++++++++------ 1 file changed, 14 insertions(+), 6 deletions(-) diff --git a/qcom/lahaina-v2-gpu.dtsi b/qcom/lahaina-v2-gpu.dtsi index 55666de74e94..46b86a1604f0 100644 --- a/qcom/lahaina-v2-gpu.dtsi +++ b/qcom/lahaina-v2-gpu.dtsi @@ -23,7 +23,7 @@ qcom,bus-min-ddr8 = <11>; qcom,bus-max-ddr8 = <11>; - qcom,acd-level = <0x882c5ffd>; + qcom,acd-level = <0x882a5ffd>; }; qcom,gpu-pwrlevel@1 { @@ -39,7 +39,7 @@ qcom,bus-min-ddr8 = <11>; qcom,bus-max-ddr8 = <11>; - qcom,acd-level = <0xa82d5ffd>; + qcom,acd-level = <0xa82a5ffd>; }; qcom,gpu-pwrlevel@2 { @@ -55,7 +55,7 @@ qcom,bus-min-ddr8 = <11>; qcom,bus-max-ddr8 = <11>; - qcom,acd-level = <0xa82d5ffd>; + qcom,acd-level = <0xa82a5ffd>; }; qcom,gpu-pwrlevel@3 { @@ -71,7 +71,7 @@ qcom,bus-min-ddr8 = <10>; qcom,bus-max-ddr8 = <11>; - qcom,acd-level = <0xa82c5ffd>; + qcom,acd-level = <0x882b5ffd>; }; qcom,gpu-pwrlevel@4 { @@ -87,7 +87,7 @@ qcom,bus-min-ddr8 = <7>; qcom,bus-max-ddr8 = <11>; - qcom,acd-level = <0x882d5ffd>; + qcom,acd-level = <0xa82b5ffd>; }; qcom,gpu-pwrlevel@5 { @@ -103,7 +103,7 @@ qcom,bus-min-ddr8 = <7>; qcom,bus-max-ddr8 = <9>; - qcom,acd-level = <0xa82d5ffd>; + qcom,acd-level = <0xa82c5ffd>; }; qcom,gpu-pwrlevel@6 { @@ -118,6 +118,8 @@ qcom,bus-freq-ddr8 = <7>; qcom,bus-min-ddr8 = <5>; qcom,bus-max-ddr8 = <7>; + + qcom,acd-level = <0xa82c5ffd>; }; qcom,gpu-pwrlevel@7 { @@ -132,6 +134,8 @@ qcom,bus-freq-ddr8 = <7>; qcom,bus-min-ddr8 = <5>; qcom,bus-max-ddr8 = <7>; + + qcom,acd-level = <0xa82d5ffd>; }; qcom,gpu-pwrlevel@8 { @@ -146,6 +150,8 @@ qcom,bus-freq-ddr8 = <6>; qcom,bus-min-ddr8 = <5>; qcom,bus-max-ddr8 = <7>; + + qcom,acd-level = <0x882e5ffd>; }; qcom,gpu-pwrlevel@9 { @@ -160,6 +166,8 @@ qcom,bus-freq-ddr8 = <2>; qcom,bus-min-ddr8 = <2>; qcom,bus-max-ddr8 = <7>; + + qcom,acd-level = <0x882f5ffd>; }; }; }; From bb9d9bc7d75218874196011913d0dfd9cd2d954a Mon Sep 17 00:00:00 2001 From: Jishnu Prakash Date: Fri, 28 Aug 2020 10:19:02 +0530 Subject: [PATCH 092/103] ARM: dts: msm: Enable smb1398 on holi MTP and QRD Enable smb1398 master and slave charge pump nodes on holi MTP and QRD. Change-Id: Ib8bd88613ef69b18b344af5085d2d3269eb9bd38 --- qcom/holi-mtp-usbc.dtsi | 95 +++++++++++++++++++++++++++++++++++++++-- qcom/holi-mtp.dtsi | 95 +++++++++++++++++++++++++++++++++++++++-- qcom/holi-qrd.dtsi | 95 +++++++++++++++++++++++++++++++++++++++-- qcom/smb1398.dtsi | 58 +++++++++++++++++++++++++ 4 files changed, 331 insertions(+), 12 deletions(-) create mode 100644 qcom/smb1398.dtsi diff --git a/qcom/holi-mtp-usbc.dtsi b/qcom/holi-mtp-usbc.dtsi index bfb99171157a..ce89821b2afb 100644 --- a/qcom/holi-mtp-usbc.dtsi +++ b/qcom/holi-mtp-usbc.dtsi @@ -128,7 +128,15 @@ <&pm7250b_qg PSY_IIO_CHARGE_COUNTER>, <&pm7250b_qg PSY_IIO_CYCLE_COUNT>, <&pm7250b_qg PSY_IIO_CHARGE_FULL_DESIGN>, - <&pm7250b_qg PSY_IIO_TIME_TO_FULL_NOW>; + <&pm7250b_qg PSY_IIO_TIME_TO_FULL_NOW>, + <&smb1396_div2_cp_master PSY_IIO_PARALLEL_MODE>, + <&smb1396_div2_cp_master PSY_IIO_PARALLEL_OUTPUT_MODE>, + <&smb1396_div2_cp_master PSY_IIO_MIN_ICL>, + <&smb1396_div2_cp_master PSY_IIO_CP_SWITCHER_EN>, + <&smb1396_div2_cp_master PSY_IIO_CP_ENABLE>, + <&smb1396_div2_cp_master PSY_IIO_CP_ILIM>, + <&smb1396_div2_cp_master PSY_IIO_CP_DIE_TEMP>, + <&smb1396_div2_cp_slave PSY_IIO_CURRENT_CAPABILITY>; io-channel-names = "usb_in_voltage", "usb_in_current", "chg_temp", @@ -152,7 +160,15 @@ "charge_counter", "cycle_count", "charge_full_design", - "time_to_full_now"; + "time_to_full_now", + "parallel_mode", + "parallel_output_mode", + "min_icl", + "cp_switcher_en", + "cp_enable", + "cp_ilim", + "cp_die_temp", + "current_capability"; qcom,battery-data = <&mtp_batterydata>; qcom,sec-charger-config = <1>; qcom,auto-recharge-soc = <98>; @@ -177,13 +193,15 @@ <&pm7250b_charger PSY_IIO_INPUT_CURRENT_LIMITED>, <&pm7250b_charger PSY_IIO_RECHARGE_SOC>, <&pm7250b_charger PSY_IIO_FORCE_RECHARGE>, - <&pm7250b_charger PSY_IIO_CHARGE_DONE>; + <&pm7250b_charger PSY_IIO_CHARGE_DONE>, + <&smb1396_div2_cp_master PSY_IIO_CP_ENABLE>; io-channel-names = "batt-therm", "batt-id", "input_current_limited", "recharge_soc", "force_recharge", - "charge_done"; + "charge_done", + "cp_charging_enabled"; qcom,battery-data = <&mtp_batterydata>; qcom,qg-iterm-ma = <150>; qcom,hold-soc-while-full; @@ -212,6 +230,75 @@ }; }; +&pm7250b_vadc { + smb1390_therm@e { + qcom,scale-fn-type = ; + }; +}; + +&pm7250b_gpios { + smb_stat { + smb_stat_default: smb_stat_default { + pins = "gpio6"; + function = "normal"; + input-enable; + bias-pull-up; + qcom,pull-up-strength = ; + power-source = <0>; + }; + }; +}; + +&qupv3_se10_i2c { + qcom,clk-freq-out = <100000>; + status = "ok"; + #include "smb1398.dtsi" +}; + +&smb1396 { + interrupts = <0x2 0xc5 0x0 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&spmi_bus>; + interrupt-names = "smb1396"; + pinctrl-names = "default"; + qcom,enable-toggle-stat; + pinctrl-0 = <&smb_stat_default>; + status = "ok"; +}; + +&smb1396_div2_cp_master { + io-channels = <&smb1396_div2_cp_slave PSY_IIO_CURRENT_CAPABILITY>, + <&smb1396_div2_cp_slave PSY_IIO_CP_ENABLE>, + <&smb1396_div2_cp_slave PSY_IIO_CP_INPUT_CURRENT_MAX>, + <&pm7250b_vadc ADC5_AMUX_THM2>, + <&pm7250b_charger PSY_IIO_USB_REAL_TYPE>, + <&pm7250b_charger PSY_IIO_ADAPTER_CC_MODE>, + <&pm7250b_charger PSY_IIO_PD_CURRENT_MAX>, + <&pm7250b_charger PSY_IIO_USB_INPUT_CURRENT_SETTLED>, + <&pm7250b_charger PSY_IIO_SMB_EN_MODE>, + <&pm7250b_charger PSY_IIO_SMB_EN_REASON>; + io-channel-names = "current_capability", + "cp_enable", + "cp_input_current_max", + "die_temp", + "real_type", + "adapter_cc_mode", + "pd_current_max", + "input_current_settled", + "smb_en_mode", + "smb_en_reason"; + qcom,parallel-input-mode = <1>; /* USBIN */ + qcom,parallel-output-mode = <2>; /* VBAT */ + status = "ok"; +}; + +&smb1396_slave { + status = "ok"; +}; + +&smb1396_div2_cp_slave { + status = "ok"; +}; + &pm7250b_pdphy { vdd-pdphy-supply = <&L3A>; vbus-supply = <&smb5_vbus>; diff --git a/qcom/holi-mtp.dtsi b/qcom/holi-mtp.dtsi index 1bf80cf75004..e88f4165c040 100644 --- a/qcom/holi-mtp.dtsi +++ b/qcom/holi-mtp.dtsi @@ -185,7 +185,15 @@ <&pm7250b_qg PSY_IIO_CHARGE_COUNTER>, <&pm7250b_qg PSY_IIO_CYCLE_COUNT>, <&pm7250b_qg PSY_IIO_CHARGE_FULL_DESIGN>, - <&pm7250b_qg PSY_IIO_TIME_TO_FULL_NOW>; + <&pm7250b_qg PSY_IIO_TIME_TO_FULL_NOW>, + <&smb1396_div2_cp_master PSY_IIO_PARALLEL_MODE>, + <&smb1396_div2_cp_master PSY_IIO_PARALLEL_OUTPUT_MODE>, + <&smb1396_div2_cp_master PSY_IIO_MIN_ICL>, + <&smb1396_div2_cp_master PSY_IIO_CP_SWITCHER_EN>, + <&smb1396_div2_cp_master PSY_IIO_CP_ENABLE>, + <&smb1396_div2_cp_master PSY_IIO_CP_ILIM>, + <&smb1396_div2_cp_master PSY_IIO_CP_DIE_TEMP>, + <&smb1396_div2_cp_slave PSY_IIO_CURRENT_CAPABILITY>; io-channel-names = "usb_in_voltage", "usb_in_current", "chg_temp", @@ -209,7 +217,15 @@ "charge_counter", "cycle_count", "charge_full_design", - "time_to_full_now"; + "time_to_full_now", + "parallel_mode", + "parallel_output_mode", + "min_icl", + "cp_switcher_en", + "cp_enable", + "cp_ilim", + "cp_die_temp", + "current_capability"; qcom,battery-data = <&mtp_batterydata>; qcom,sec-charger-config = <1>; qcom,auto-recharge-soc = <98>; @@ -234,13 +250,15 @@ <&pm7250b_charger PSY_IIO_INPUT_CURRENT_LIMITED>, <&pm7250b_charger PSY_IIO_RECHARGE_SOC>, <&pm7250b_charger PSY_IIO_FORCE_RECHARGE>, - <&pm7250b_charger PSY_IIO_CHARGE_DONE>; + <&pm7250b_charger PSY_IIO_CHARGE_DONE>, + <&smb1396_div2_cp_master PSY_IIO_CP_ENABLE>; io-channel-names = "batt-therm", "batt-id", "input_current_limited", "recharge_soc", "force_recharge", - "charge_done"; + "charge_done", + "cp_charging_enabled"; qcom,battery-data = <&mtp_batterydata>; qcom,qg-iterm-ma = <150>; qcom,hold-soc-while-full; @@ -253,6 +271,75 @@ qcom,use-cp-iin-sns; }; +&pm7250b_vadc { + smb1390_therm@e { + qcom,scale-fn-type = ; + }; +}; + +&pm7250b_gpios { + smb_stat { + smb_stat_default: smb_stat_default { + pins = "gpio6"; + function = "normal"; + input-enable; + bias-pull-up; + qcom,pull-up-strength = ; + power-source = <0>; + }; + }; +}; + +&qupv3_se10_i2c { + qcom,clk-freq-out = <100000>; + status = "ok"; + #include "smb1398.dtsi" +}; + +&smb1396 { + interrupts = <0x2 0xc5 0x0 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&spmi_bus>; + interrupt-names = "smb1396"; + pinctrl-names = "default"; + qcom,enable-toggle-stat; + pinctrl-0 = <&smb_stat_default>; + status = "ok"; +}; + +&smb1396_div2_cp_master { + io-channels = <&smb1396_div2_cp_slave PSY_IIO_CURRENT_CAPABILITY>, + <&smb1396_div2_cp_slave PSY_IIO_CP_ENABLE>, + <&smb1396_div2_cp_slave PSY_IIO_CP_INPUT_CURRENT_MAX>, + <&pm7250b_vadc ADC5_AMUX_THM2>, + <&pm7250b_charger PSY_IIO_USB_REAL_TYPE>, + <&pm7250b_charger PSY_IIO_ADAPTER_CC_MODE>, + <&pm7250b_charger PSY_IIO_PD_CURRENT_MAX>, + <&pm7250b_charger PSY_IIO_USB_INPUT_CURRENT_SETTLED>, + <&pm7250b_charger PSY_IIO_SMB_EN_MODE>, + <&pm7250b_charger PSY_IIO_SMB_EN_REASON>; + io-channel-names = "current_capability", + "cp_enable", + "cp_input_current_max", + "die_temp", + "real_type", + "adapter_cc_mode", + "pd_current_max", + "input_current_settled", + "smb_en_mode", + "smb_en_reason"; + qcom,parallel-input-mode = <1>; /* USBIN */ + qcom,parallel-output-mode = <2>; /* VBAT */ + status = "ok"; +}; + +&smb1396_slave { + status = "ok"; +}; + +&smb1396_div2_cp_slave { + status = "ok"; +}; + #include "camera/holi-camera-sensor-mtp.dtsi" &pm7250b_charger { diff --git a/qcom/holi-qrd.dtsi b/qcom/holi-qrd.dtsi index 94c86b3bbf90..f82bf2910819 100644 --- a/qcom/holi-qrd.dtsi +++ b/qcom/holi-qrd.dtsi @@ -260,7 +260,15 @@ <&pm7250b_qg PSY_IIO_CHARGE_COUNTER>, <&pm7250b_qg PSY_IIO_CYCLE_COUNT>, <&pm7250b_qg PSY_IIO_CHARGE_FULL_DESIGN>, - <&pm7250b_qg PSY_IIO_TIME_TO_FULL_NOW>; + <&pm7250b_qg PSY_IIO_TIME_TO_FULL_NOW>, + <&smb1396_div2_cp_master PSY_IIO_PARALLEL_MODE>, + <&smb1396_div2_cp_master PSY_IIO_PARALLEL_OUTPUT_MODE>, + <&smb1396_div2_cp_master PSY_IIO_MIN_ICL>, + <&smb1396_div2_cp_master PSY_IIO_CP_SWITCHER_EN>, + <&smb1396_div2_cp_master PSY_IIO_CP_ENABLE>, + <&smb1396_div2_cp_master PSY_IIO_CP_ILIM>, + <&smb1396_div2_cp_master PSY_IIO_CP_DIE_TEMP>, + <&smb1396_div2_cp_slave PSY_IIO_CURRENT_CAPABILITY>; io-channel-names = "usb_in_voltage", "usb_in_current", "chg_temp", @@ -284,7 +292,15 @@ "charge_counter", "cycle_count", "charge_full_design", - "time_to_full_now"; + "time_to_full_now", + "parallel_mode", + "parallel_output_mode", + "min_icl", + "cp_switcher_en", + "cp_enable", + "cp_ilim", + "cp_die_temp", + "current_capability"; qcom,battery-data = <&qrd_batterydata>; qcom,sec-charger-config = <1>; qcom,auto-recharge-soc = <98>; @@ -312,13 +328,15 @@ <&pm7250b_charger PSY_IIO_INPUT_CURRENT_LIMITED>, <&pm7250b_charger PSY_IIO_RECHARGE_SOC>, <&pm7250b_charger PSY_IIO_FORCE_RECHARGE>, - <&pm7250b_charger PSY_IIO_CHARGE_DONE>; + <&pm7250b_charger PSY_IIO_CHARGE_DONE>, + <&smb1396_div2_cp_master PSY_IIO_CP_ENABLE>; io-channel-names = "batt-therm", "batt-id", "input_current_limited", "recharge_soc", "force_recharge", - "charge_done"; + "charge_done", + "cp_charging_enabled"; qcom,qg-iterm-ma = <150>; qcom,hold-soc-while-full; qcom,linearize-soc; @@ -381,3 +399,72 @@ &usb0 { extcon = <&pm7250b_pdphy>, <&eud>; }; + +&pm7250b_vadc { + smb1390_therm@e { + qcom,scale-fn-type = ; + }; +}; + +&pm7250b_gpios { + smb_stat { + smb_stat_default: smb_stat_default { + pins = "gpio6"; + function = "normal"; + input-enable; + bias-pull-up; + qcom,pull-up-strength = ; + power-source = <0>; + }; + }; +}; + +&qupv3_se10_i2c { + qcom,clk-freq-out = <100000>; + status = "ok"; + #include "smb1398.dtsi" +}; + +&smb1396 { + interrupts = <0x2 0xc5 0x0 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&spmi_bus>; + interrupt-names = "smb1396"; + pinctrl-names = "default"; + qcom,enable-toggle-stat; + pinctrl-0 = <&smb_stat_default>; + status = "ok"; +}; + +&smb1396_div2_cp_master { + io-channels = <&smb1396_div2_cp_slave PSY_IIO_CURRENT_CAPABILITY>, + <&smb1396_div2_cp_slave PSY_IIO_CP_ENABLE>, + <&smb1396_div2_cp_slave PSY_IIO_CP_INPUT_CURRENT_MAX>, + <&pm7250b_vadc ADC5_AMUX_THM2>, + <&pm7250b_charger PSY_IIO_USB_REAL_TYPE>, + <&pm7250b_charger PSY_IIO_ADAPTER_CC_MODE>, + <&pm7250b_charger PSY_IIO_PD_CURRENT_MAX>, + <&pm7250b_charger PSY_IIO_USB_INPUT_CURRENT_SETTLED>, + <&pm7250b_charger PSY_IIO_SMB_EN_MODE>, + <&pm7250b_charger PSY_IIO_SMB_EN_REASON>; + io-channel-names = "current_capability", + "cp_enable", + "cp_input_current_max", + "die_temp", + "real_type", + "adapter_cc_mode", + "pd_current_max", + "input_current_settled", + "smb_en_mode", + "smb_en_reason"; + qcom,parallel-input-mode = <1>; /* USBIN */ + qcom,parallel-output-mode = <2>; /* VBAT */ + status = "ok"; +}; + +&smb1396_slave { + status = "ok"; +}; + +&smb1396_div2_cp_slave { + status = "ok"; +}; diff --git a/qcom/smb1398.dtsi b/qcom/smb1398.dtsi new file mode 100644 index 000000000000..d9a6c8e9b3d2 --- /dev/null +++ b/qcom/smb1398.dtsi @@ -0,0 +1,58 @@ +#include + +smb1396: qcom,smb1396@34 { + compatible = "qcom,i2c-pmic"; + reg = <0x34>; + #address-cells = <1>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <3>; + qcom,periph-map = <0x6 0x26 0x27>; + status = "disabled"; + + smb1396_div2_cp_master: qcom,div2_cp { + compatible = "qcom,smb1396-div2-cp-master"; + #io-channel-cells = <1>; + interrupts = <0x26 0x1 IRQ_TYPE_EDGE_RISING>, + <0x26 0x3 IRQ_TYPE_EDGE_RISING>, + <0x26 0x5 IRQ_TYPE_EDGE_RISING>, + <0x26 0x7 IRQ_TYPE_EDGE_RISING>, + <0x27 0x5 IRQ_TYPE_EDGE_RISING>, + <0x27 0x6 IRQ_TYPE_EDGE_RISING>, + <0x27 0x7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "temp-shdwn", + "div2-irev", + "usbin-uv", + "usbin-ov", + "div2-ilim", + "div2-win-uv", + "div2-win-ov"; + qcom,div2-cp-min-ilim-ua = <1000000>; + status = "disabled"; + }; +}; + +smb1396_slave: qcom,smb1396@35 { + compatible = "qcom,i2c-pmic"; + reg = <0x35>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + smb1396_div2_cp_slave: qcom,div2_cp_slave { + compatible = "qcom,smb1396-div2-cp-slave"; + #io-channel-cells = <1>; + status = "disabled"; + }; +}; + +smb1398: qcom,smb1398@36 { + compatible = "qcom,i2c-pmic"; + reg = <0x36>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + smb1398_pre_regulator: qcom,pre_regulator { + compatible = "qcom,smb1398-pre-regulator"; + status = "disabled"; + }; +}; From 3423646dce6deadaaffc595d5cd5b73e3871eb60 Mon Sep 17 00:00:00 2001 From: Ritesh Kumar Date: Sun, 6 Sep 2020 02:30:51 +0530 Subject: [PATCH 093/103] ARM: dts: msm: Select default panel for trusted UI Display Select default panel for trusted UI Display on lahaina QRD target. Change-Id: I91e1bee82d99b10e74175159168ea1cc9e9b8b15 --- qcom/lahaina-vm-qrd.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/qcom/lahaina-vm-qrd.dtsi b/qcom/lahaina-vm-qrd.dtsi index 51e7b6de33a9..f2010601c08b 100644 --- a/qcom/lahaina-vm-qrd.dtsi +++ b/qcom/lahaina-vm-qrd.dtsi @@ -12,3 +12,7 @@ focaltech,trusted-touch-io-sizes = <0x1000 0x1000 0x1000 0x1000 0x1000 0x4000>; }; }; + +&sde_dsi { + qcom,dsi-default-panel = <&dsi_r66451_amoled_cmd>; +}; From 1234c88ffaa32a438dc3c58e0cd74a395599d02b Mon Sep 17 00:00:00 2001 From: Prakruthi Deepak Heragu Date: Sat, 12 Sep 2020 20:05:13 -0700 Subject: [PATCH 094/103] ARM: dts: qcom: Add devicetree files for board v2 Add new device tree files for board v2 devices. Change-Id: I9b11d95c59483f6b2689244d90bcdb310bacf5cc --- qcom/Makefile | 4 ++++ qcom/lahaina-mtp-v2-overlay.dts | 10 ++++++++++ qcom/lahaina-mtp-v2.dts | 10 ++++++++++ qcom/lahaina-mtp-v2.dtsi | 1 + 4 files changed, 25 insertions(+) create mode 100644 qcom/lahaina-mtp-v2-overlay.dts create mode 100644 qcom/lahaina-mtp-v2.dts create mode 100644 qcom/lahaina-mtp-v2.dtsi diff --git a/qcom/Makefile b/qcom/Makefile index 8b1c257d0fef..f3f6967b0e99 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -14,6 +14,7 @@ dtbo-$(CONFIG_ARCH_LAHAINA) += lahaina-rumi-overlay.dtbo \ lahainap-atp-overlay.dtbo \ lahainap-qrd-overlay.dtbo \ lahaina-cdp-v2.2-overlay.dtbo \ + lahaina-mtp-v2-overlay.dtbo \ lahaina-mtp-v2.1-overlay.dtbo lahaina-rumi-overlay.dtbo-base := lahaina.dtb @@ -31,6 +32,8 @@ lahainap-atp-overlay.dtbo-base := lahainap.dtb lahainap-v2.dtb lahainap-v2.1.dtb lahainap-qrd-overlay.dtbo-base := lahainap.dtb lahainap-v2.dtb lahainap-v2.1.dtb lahaina-cdp-v2.2-overlay.dtbo-base := lahaina.dtb lahaina-v2.dtb \ lahaina-v2.1.dtb +lahaina-mtp-v2-overlay.dtbo-base := lahaina.dtb lahaina-v2.dtb \ + lahaina-v2.1.dtb lahaina-mtp-v2.1-overlay.dtbo-base := lahaina.dtb lahaina-v2.dtb \ lahaina-v2.1.dtb else @@ -68,6 +71,7 @@ dtb-$(CONFIG_ARCH_LAHAINA) += lahaina-rumi.dtb \ lahainap-v2.1-cdp.dtb \ lahainap-v2.1-atp.dtb \ lahainap-v2.1-qrd.dtb \ + lahaina-mtp-v2.dtb \ lahaina-mtp-v2.1.dtb endif diff --git a/qcom/lahaina-mtp-v2-overlay.dts b/qcom/lahaina-mtp-v2-overlay.dts new file mode 100644 index 000000000000..a7c202eff4ec --- /dev/null +++ b/qcom/lahaina-mtp-v2-overlay.dts @@ -0,0 +1,10 @@ +/dts-v1/; +/plugin/; + +#include "lahaina-mtp-v2.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Lahaina MTP v2"; + compatible = "qcom,lahaina-mtp", "qcom,lahaina", "qcom,mtp"; + qcom,board-id = <0x20008 0>; +}; diff --git a/qcom/lahaina-mtp-v2.dts b/qcom/lahaina-mtp-v2.dts new file mode 100644 index 000000000000..9727744cbc29 --- /dev/null +++ b/qcom/lahaina-mtp-v2.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "lahaina-v2.dtsi" +#include "lahaina-mtp-v2.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Lahaina MTP v2"; + compatible = "qcom,lahaina-mtp", "qcom,lahaina", "qcom,mtp"; + qcom,board-id = <0x20008 0>; +}; diff --git a/qcom/lahaina-mtp-v2.dtsi b/qcom/lahaina-mtp-v2.dtsi new file mode 100644 index 000000000000..af2a598d00ab --- /dev/null +++ b/qcom/lahaina-mtp-v2.dtsi @@ -0,0 +1 @@ +#include "lahaina-mtp.dtsi" From fac9cbdd40b974487f469ebeae105a8e111cf91c Mon Sep 17 00:00:00 2001 From: Santosh Mardi Date: Thu, 10 Sep 2020 17:36:25 +0530 Subject: [PATCH 095/103] dt-bindings: add bindings for RIMPS memlat Add initial dt-bindings for RIMPS memlat and logging drivers. Change-Id: I64a8cf4c77c4eb9c3333ac53ae603ef0ace3f0c8 --- bindings/soc/qcom/qcom,rimps-log.yaml | 31 ++++++++++ bindings/soc/qcom/qcom,rimps-memlat.txt | 80 +++++++++++++++++++++++++ 2 files changed, 111 insertions(+) create mode 100644 bindings/soc/qcom/qcom,rimps-log.yaml create mode 100644 bindings/soc/qcom/qcom,rimps-memlat.txt diff --git a/bindings/soc/qcom/qcom,rimps-log.yaml b/bindings/soc/qcom/qcom,rimps-log.yaml new file mode 100644 index 000000000000..3b9e7304c75c --- /dev/null +++ b/bindings/soc/qcom/qcom,rimps-log.yaml @@ -0,0 +1,31 @@ +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bindings/soc/qcom/qcom,rimps-log.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. Rimps Logging + +description: | + RIMPS logging is a device that uses mailbox to collect the logs + generated from rimps, and dump them into a dedicated log buffer + through ipc_logging framework. + An instance of rimps-log should have the mailbox controller phandle and + addresses of log buffer set aside for this purpose. + +properties: + compatible: + Usage: required + Value type: + Definition: Must be "qcom,rimps-log" + +example: + - | + +rimps_log: qcom,rimps_log@fd04780 { + #address-cells = <2>; + #size-cells = <2>; + compatible = "qcom,rimps-log"; + reg = <0x0fd04580 0x200>, + <0x0fd04780 0x200>; + mboxes = <&rimps 1>; + }; diff --git a/bindings/soc/qcom/qcom,rimps-memlat.txt b/bindings/soc/qcom/qcom,rimps-memlat.txt new file mode 100644 index 000000000000..1499c394e5e6 --- /dev/null +++ b/bindings/soc/qcom/qcom,rimps-memlat.txt @@ -0,0 +1,80 @@ +RIMPS memory latency + +RIMPS memlat is a device that represents the use of the PMU in ARM cores +to measure the parameters for latency driven memory access patterns in rimps. + +Required structure: +An instance of rimps-memlat must be described in two levels of device nodes. +The first level describes the controller while the second level describes the +monitors that the controller manages. At least one monitor is required per +controller. + +[First Level Nodes] +Required properties: +- compatible: Must be "qcom,rimps-memlat-cpugrp" +- qcom,cpulist: List of CPU phandles to be monitored in a + cluster. Must be a superset of cpulists + described in second level nodes. +- reg-names: pmu-base addresses need to store the pmu events + during LPM and hotplug scenario. + +[Second Level Nodes] +Required properties: +- compatible: Must be "qcom,rimps-memlat-mon-l3" +- qcom,core-dev-table: A mapping table of core frequency to a required + bandwidth vote at the given core frequency. + A phandle that contains this property may be + provided instead (to share tables across nodes). +- qcom,cachemiss-ev: The cache miss event that this monitor is + supposed to measure. Optional for compute only. +- reg-names: ftbl_base address required to populate + L3 frequency and perf_base address required to know the current + L3 frequency set. +Optional properties: +- qcom,cpulist: List of CPU phandles to be monitored in a + cluster. Must be a subset of the cpulist + described in first level node. Defaults to + cpulist in first level node if not specified. +- qcom,inst-ev: The instruction count event that this monitor is + supposed to measure. Defaults to 0x08 if not + specified. +- qcom,stall-cycle-ev: The stall cycle count that this monitor is + supposed to measure. Assumes 100% stall if not + specified. + +Example: + + cpu0_grp: qcom,cpu0_grp { + compatible = "qcom,rimps-memlat-cpugrp"; + qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + reg = <0x0fd04900 0x1000>; + reg-names = "pmu-base"; + + cpu0_rimps_l3_latmon: qcom,cpu0-rimps-l3-latmon { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "qcom,rimps-memlat-mon-l3"; + qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>; + qcom,cachemiss-ev = <0x17>; + reg = <0x18590100 0xa0>, <0x18590320 0x4>; + reg-names = "ftbl-base", "perf-base"; + + qcom,core-dev-table = + < 300000 300000000 >, + < 403200 403200000 >, + < 499200 499200000 >, + < 691200 614400000 >, + < 806400 710400000 >, + < 998400 806400000 >, + < 1190400 998400000 >, + < 1286400 1094400000 >, + < 1459200 1248000000 >, + < 1728000 1344000000 >, + < 1804800 1440000000 >, + < 1900800 1516800000 >; + }; + }; From 61a90222d37b2222c48e8f88f8ad98cf9e26ddc0 Mon Sep 17 00:00:00 2001 From: Mukesh Ojha Date: Mon, 31 Aug 2020 22:21:41 +0530 Subject: [PATCH 096/103] ARM: dts: msm: Enable shutdown ack smp2p interrupt for adsp/cdsp Enable shutdown ack smp2p interrupt for adsp/cdsp for Shima, so that it can handle the ack sent by the subsystem for a shutdown. Change-Id: Ifbc3ae53941b5eb00ec21cdf367987f3647f7085 --- qcom/shima.dtsi | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi index 1fbf1e069ec4..eac57078d2ef 100644 --- a/qcom/shima.dtsi +++ b/qcom/shima.dtsi @@ -2760,13 +2760,15 @@ <&adsp_smp2p_in 0 0>, <&adsp_smp2p_in 2 0>, <&adsp_smp2p_in 1 0>, - <&adsp_smp2p_in 3 0>; + <&adsp_smp2p_in 3 0>, + <&adsp_smp2p_in 7 0>; interrupt-names = "qcom,wdog", "qcom,err-fatal", "qcom,proxy-unvote", "qcom,err-ready", - "qcom,stop-ack"; + "qcom,stop-ack", + "qcom,shutdown-ack"; /* Outputs to lpass */ qcom,smem-states = <&adsp_smp2p_out 0>; @@ -2809,13 +2811,15 @@ <&cdsp_smp2p_in 0 0>, <&cdsp_smp2p_in 2 0>, <&cdsp_smp2p_in 1 0>, - <&cdsp_smp2p_in 3 0>; + <&cdsp_smp2p_in 3 0>, + <&cdsp_smp2p_in 7 0>; interrupt-names = "qcom,wdog", "qcom,err-fatal", "qcom,proxy-unvote", "qcom,err-ready", - "qcom,stop-ack"; + "qcom,stop-ack", + "qcom,shutdown-ack"; /* Outputs to turing */ qcom,smem-states = <&cdsp_smp2p_out 0>; From 37d600e71ecc32785526eb12096b9481b91912f5 Mon Sep 17 00:00:00 2001 From: Ritesh Kumar Date: Mon, 14 Sep 2020 12:28:33 +0530 Subject: [PATCH 097/103] ARM: dts: msm: Add trusted touch properties for shima Add trusted touch properties to focaltech node to support VM(virtual machine) enabled trusted touch on shima platform. Change-Id: I7fa55db0905ab800e960981c6bd1fb7704f58dd6 --- qcom/shima-idp.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/qcom/shima-idp.dtsi b/qcom/shima-idp.dtsi index 30f33b86cf9e..4129d14e14e9 100644 --- a/qcom/shima-idp.dtsi +++ b/qcom/shima-idp.dtsi @@ -181,6 +181,12 @@ &dsi_r66451_amoled_video &dsi_r66451_amoled_60hz_video &dsi_r66451_amoled_60hz_cmd>; + + focaltech,trusted-touch-mode = "vm_mode"; + focaltech,touch-environment = "pvm"; + focaltech,trusted-touch-spi-irq = <566>; + focaltech,trusted-touch-io-bases = <0xF114000 0xF115000 0xF116000 0xF117000 0x988000 0x00910000>; + focaltech,trusted-touch-io-sizes = <0x1000 0x1000 0x1000 0x1000 0x1000 0x4000>; }; }; From 3342752ca6b7316de5165bc98679b3375715c6c9 Mon Sep 17 00:00:00 2001 From: Mayank Grover Date: Mon, 14 Sep 2020 12:17:04 +0530 Subject: [PATCH 098/103] ARM: dts: msm: Add mpm counter node for boot_stats Add mpm counter node to enable boot_stats collection for holi. Change-Id: I40962247765b07a7b62d3205b7c259ea36af020d --- qcom/holi.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/qcom/holi.dtsi b/qcom/holi.dtsi index b6200c578fcd..4a69e5a50b01 100644 --- a/qcom/holi.dtsi +++ b/qcom/holi.dtsi @@ -918,6 +918,12 @@ qcom,rtb-size = <0x100000>; }; + qcom,mpm2-sleep-counter@0x4403000 { + compatible = "qcom,mpm2-sleep-counter"; + reg = <0x4403000 0x1000>; + clock-frequency = <32768>; + }; + wdog: qcom,wdt@f410000 { compatible = "qcom,msm-watchdog"; reg = <0xf410000 0x1000>; From 4b471a8075aa739e37914ca3d3540bf8f0537626 Mon Sep 17 00:00:00 2001 From: Jagadeesh Kona Date: Thu, 10 Sep 2020 09:19:03 +0530 Subject: [PATCH 099/103] ARM: dts: msm: Update the flags for GCC PCIE GDSC's Update the timeout and add flag to skip status check on disable for PCIE GDSC's. Change-Id: I560d9ba9986bb90ba07bf600464b44e4a580d0bd --- qcom/shima-gdsc.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/qcom/shima-gdsc.dtsi b/qcom/shima-gdsc.dtsi index 371f618c038d..4b08898def04 100644 --- a/qcom/shima-gdsc.dtsi +++ b/qcom/shima-gdsc.dtsi @@ -4,6 +4,8 @@ compatible = "qcom,gdsc"; reg = <0x16b004 0x4>; regulator-name = "gcc_pcie_0_gdsc"; + qcom,gds-timeout = <500>; + qcom,no-status-check-on-disable; status = "disabled"; }; @@ -11,6 +13,8 @@ compatible = "qcom,gdsc"; reg = <0x18d004 0x4>; regulator-name = "gcc_pcie_1_gdsc"; + qcom,gds-timeout = <500>; + qcom,no-status-check-on-disable; status = "disabled"; }; From 3a4a44c0e6bbf182492ef250a95008cf775206b9 Mon Sep 17 00:00:00 2001 From: Santosh Mardi Date: Mon, 7 Sep 2020 23:15:22 +0530 Subject: [PATCH 100/103] ARM: dts: msm: update DCVS node mapping table for shima target Update DCVS node mapping table for L3 and ddr for shima target. Change-Id: Id76c399c05b23895041c41ca533083928f644ebc --- qcom/shima.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi index f1ce0c989a2b..6124ff7c837e 100644 --- a/qcom/shima.dtsi +++ b/qcom/shima.dtsi @@ -2176,7 +2176,7 @@ llcc_bw_opp_table: llcc-bw-opp-table { compatible = "operating-points-v2"; BW_OPP_ENTRY( 150, 32); /* 4576 MB/s */ - BW_OPP_ENTRY( 300, 32); /* 9154 MB/s */ + BW_OPP_ENTRY( 300, 32); /* 9155 MB/s */ BW_OPP_ENTRY( 466, 32); /* 14220 MB/s */ BW_OPP_ENTRY( 600, 32); /* 18310 MB/s */ BW_OPP_ENTRY( 806, 32); /* 24596 MB/s */ @@ -2404,7 +2404,7 @@ < 691200 556800000 >, < 940800 652800000 >, < 1171200 844800000 >, - < 1516800 1065600000 >, + < 1516800 1056000000 >, < 1670400 1305600000 >, < 1804800 1420800000 >; }; @@ -2423,7 +2423,7 @@ < 1094400 556800000 >, < 1267200 806400000 >, < 1766400 1190400000 >, - < 2227200 1401600000 >, + < 2169600 1401600000 >, < 2707200 1420800000 >; }; @@ -2660,7 +2660,7 @@ qcom,ddr-type = ; qcom,core-dev-table = < 2361600 MHZ_TO_MBPS( 300, 4) >, - < 2707200 MHZ_TO_MBPS(2033, 4) >; + < 2707200 MHZ_TO_MBPS(2133, 4) >; }; ddr5-map { From 2f28324d935bc528a6999c34343b766c62d71dd9 Mon Sep 17 00:00:00 2001 From: Faiyaz Mohammed Date: Mon, 14 Sep 2020 15:22:54 +0530 Subject: [PATCH 101/103] Revert "ARM: dts: msm: Enable the kgsl coherent test node on Shima" This reverts commit b1816f1bb0508759ad4cc3158d018ca567ff53ac. Change-Id: I3f493cfdab34dc1d900268f3f62994ec5d11c9ec --- qcom/msm-arm-smmu-shima.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/msm-arm-smmu-shima.dtsi b/qcom/msm-arm-smmu-shima.dtsi index 869521cf883e..e8ee9372a3be 100644 --- a/qcom/msm-arm-smmu-shima.dtsi +++ b/qcom/msm-arm-smmu-shima.dtsi @@ -340,6 +340,7 @@ }; kgsl_iommu_coherent_test_device { + status = "disabled"; compatible = "iommu-debug-test"; iommus = <&kgsl_smmu 0x407 0>; qcom,iommu-dma = "disabled"; From 9bfdcbfcea001980ef410cc69d81ed1ddf6ca044 Mon Sep 17 00:00:00 2001 From: Maulik Shah Date: Tue, 15 Sep 2020 13:04:03 +0530 Subject: [PATCH 102/103] ARM: dts: msm: Update PSCI state id for shima The wakeup value will be programmed by the secure firmware. This is noted as the new E3 state for the RSC component. Update state id for the AOSS sleep mode to pass new state. Change-Id: I4c70bfa7f442e28a59d8809d2bd5afb6557de1d8 --- qcom/shima-pm.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/qcom/shima-pm.dtsi b/qcom/shima-pm.dtsi index 52c85035c785..cfd438443c3c 100644 --- a/qcom/shima-pm.dtsi +++ b/qcom/shima-pm.dtsi @@ -58,8 +58,8 @@ entry-latency-us = <3638>; exit-latency-us = <6562>; min-residency-us = <9826>; - arm,psci-suspend-param = <0xc240>; - qcom,psci-mode = <0xc24>; + arm,psci-suspend-param = <0xc340>; + qcom,psci-mode = <0xc34>; qcom,is-reset; qcom,notify-rpm; qcom,min-child-idx = <2>; From 6abfe1df000beaa71e8c89f9d4e8e92d7058d96f Mon Sep 17 00:00:00 2001 From: Maulik Shah Date: Tue, 15 Sep 2020 15:02:35 +0530 Subject: [PATCH 103/103] ARM: dts: msm: Set control TCS count to zero for shima The PDC wakeup value is written to the control TCS. This is now handled in trusted firmware. Set Control TCS count to zero to disable writing to control TCS. Change-Id: If90bea0fadf4decffa2f1ae1c2214cf5b76f5061 --- qcom/shima.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi index c1d6883897d8..2d3b653a0605 100644 --- a/qcom/shima.dtsi +++ b/qcom/shima.dtsi @@ -1863,7 +1863,7 @@ qcom,tcs-config = , , , - ; + ; rpmhcc: qcom,rpmhclk { compatible = "qcom,shima-rpmh-clk";