From d107ab8fbd1e5328832fd67077965243a3339a35 Mon Sep 17 00:00:00 2001 From: Tingwei Zhang Date: Tue, 4 Dec 2018 18:54:34 -0800 Subject: [PATCH] coresight: tmc: clear has_iommu flag when smmu is bypassed When SMMU works in bypass mode, set has_iommu to false. ETR can use SG mode. Change-Id: Ic7a6814cace92098473e4b5302408034e662058d Signed-off-by: Tingwei Zhang Signed-off-by: Mao Jinlong --- drivers/hwtracing/coresight/coresight-tmc-etr.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c index 03f079a2c395..e29675770bcf 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -824,9 +824,22 @@ static struct etr_buf *tmc_alloc_etr_buf(struct tmc_drvdata *drvdata, bool has_sg, has_catu; struct etr_buf *etr_buf; struct device *dev = &drvdata->csdev->dev; + int s1_bypass = 0; + struct iommu_domain *domain; has_etr_sg = tmc_etr_has_cap(drvdata, TMC_ETR_SG); - has_iommu = iommu_get_domain_for_dev(dev->parent); + domain = iommu_get_domain_for_dev(dev->parent); + if (domain) { + iommu_domain_get_attr(domain, DOMAIN_ATTR_S1_BYPASS, + &s1_bypass); + if (s1_bypass) + has_iommu = false; + else + has_iommu = true; + } else { + has_iommu = false; + } + has_catu = !!tmc_etr_get_catu_device(drvdata); has_sg = has_catu || has_etr_sg;