From 02069b8ba48317bcaa7cf5272ed08f375e179dd0 Mon Sep 17 00:00:00 2001 From: "Tao,Zhang" Date: Tue, 27 Oct 2020 11:06:42 +0800 Subject: [PATCH] ARM: dts: msm: Add cti trigger number to device tree for lahaina Add cti trigger number to device tree for lahaina. Since some platforms don't have swao cti, replace configuring cti trigger number as hard code. Change-Id: I5ae1cc25210218f249ea8b34ee493e0b27fef237 --- qcom/lahaina-coresight.dtsi | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/qcom/lahaina-coresight.dtsi b/qcom/lahaina-coresight.dtsi index 3342e9e9e0f5..ff7750e6f034 100644 --- a/qcom/lahaina-coresight.dtsi +++ b/qcom/lahaina-coresight.dtsi @@ -107,7 +107,9 @@ coresight-name = "coresight-tmc-etf"; coresight-csr = <&swao_csr>; - coresight-ctis = <&cti0 &cti6>; + coresight-ctis = <&cti0_swao &cti3_swao>; + cti-reset-trig-num = <0>; + cti-flush-trig-num = <1>; clocks = <&clock_aop QDSS_CLK>; clock-names = "apb_pclk"; @@ -154,7 +156,9 @@ qcom,sw-usb; coresight-name = "coresight-tmc-etr"; - coresight-ctis = <&cti0 &cti6>; + coresight-ctis = <&cti0 &cti3_swao>; + cti-reset-trig-num = <0>; + cti-flush-trig-num = <3>; coresight-csr = <&csr>; clocks = <&clock_aop QDSS_CLK>;