From 087303dadb8f79694d5046ecb32faed75e0fed4a Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Mon, 10 Feb 2020 18:38:02 +0530 Subject: [PATCH] dt-bindings: clock: Add support for clock ids for SHIMA Add clock IDs for CAMCC/DISPCC/GCC/GPUCC/VIDEOCC for clients to be able to request for clocks from these clock controllers. Change-Id: Ic809b350cfb15d7dce4667907fe6176a7293bdcd Signed-off-by: Taniya Das --- include/dt-bindings/clock/qcom,camcc-shima.h | 130 +++++++++++ include/dt-bindings/clock/qcom,dispcc-shima.h | 60 ++++++ include/dt-bindings/clock/qcom,gcc-shima.h | 201 ++++++++++++++++++ include/dt-bindings/clock/qcom,gpucc-shima.h | 54 +++++ .../dt-bindings/clock/qcom,videocc-shima.h | 39 ++++ 5 files changed, 484 insertions(+) create mode 100644 include/dt-bindings/clock/qcom,camcc-shima.h create mode 100644 include/dt-bindings/clock/qcom,dispcc-shima.h create mode 100644 include/dt-bindings/clock/qcom,gcc-shima.h create mode 100644 include/dt-bindings/clock/qcom,gpucc-shima.h create mode 100644 include/dt-bindings/clock/qcom,videocc-shima.h diff --git a/include/dt-bindings/clock/qcom,camcc-shima.h b/include/dt-bindings/clock/qcom,camcc-shima.h new file mode 100644 index 000000000000..e9de638c0531 --- /dev/null +++ b/include/dt-bindings/clock/qcom,camcc-shima.h @@ -0,0 +1,130 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_CAM_CC_SHIMA_H +#define _DT_BINDINGS_CLK_QCOM_CAM_CC_SHIMA_H + +/* CAM_CC clocks */ +#define CAM_CC_PLL0 0 +#define CAM_CC_PLL0_OUT_EVEN 1 +#define CAM_CC_PLL0_OUT_ODD 2 +#define CAM_CC_PLL1 3 +#define CAM_CC_PLL1_OUT_EVEN 4 +#define CAM_CC_PLL2 5 +#define CAM_CC_PLL2_OUT_AUX 6 +#define CAM_CC_PLL2_OUT_AUX2 7 +#define CAM_CC_PLL2_OUT_EARLY 8 +#define CAM_CC_PLL3 9 +#define CAM_CC_PLL3_OUT_EVEN 10 +#define CAM_CC_PLL4 11 +#define CAM_CC_PLL4_OUT_EVEN 12 +#define CAM_CC_PLL5 13 +#define CAM_CC_PLL5_OUT_EVEN 14 +#define CAM_CC_PLL6 15 +#define CAM_CC_PLL6_OUT_EVEN 16 +#define CAM_CC_BPS_AHB_CLK 17 +#define CAM_CC_BPS_AREG_CLK 18 +#define CAM_CC_BPS_AXI_CLK 19 +#define CAM_CC_BPS_CLK 20 +#define CAM_CC_BPS_CLK_SRC 21 +#define CAM_CC_CAMNOC_AXI_CLK 22 +#define CAM_CC_CAMNOC_AXI_CLK_SRC 23 +#define CAM_CC_CAMNOC_DCD_XO_CLK 24 +#define CAM_CC_CCI_0_CLK 25 +#define CAM_CC_CCI_0_CLK_SRC 26 +#define CAM_CC_CCI_1_CLK 27 +#define CAM_CC_CCI_1_CLK_SRC 28 +#define CAM_CC_CORE_AHB_CLK 29 +#define CAM_CC_CPAS_AHB_CLK 30 +#define CAM_CC_CPHY_RX_CLK_SRC 31 +#define CAM_CC_CSI0PHYTIMER_CLK 32 +#define CAM_CC_CSI0PHYTIMER_CLK_SRC 33 +#define CAM_CC_CSI1PHYTIMER_CLK 34 +#define CAM_CC_CSI1PHYTIMER_CLK_SRC 35 +#define CAM_CC_CSI2PHYTIMER_CLK 36 +#define CAM_CC_CSI2PHYTIMER_CLK_SRC 37 +#define CAM_CC_CSI3PHYTIMER_CLK 38 +#define CAM_CC_CSI3PHYTIMER_CLK_SRC 39 +#define CAM_CC_CSI4PHYTIMER_CLK 40 +#define CAM_CC_CSI4PHYTIMER_CLK_SRC 41 +#define CAM_CC_CSI5PHYTIMER_CLK 42 +#define CAM_CC_CSI5PHYTIMER_CLK_SRC 43 +#define CAM_CC_CSIPHY0_CLK 44 +#define CAM_CC_CSIPHY1_CLK 45 +#define CAM_CC_CSIPHY2_CLK 46 +#define CAM_CC_CSIPHY3_CLK 47 +#define CAM_CC_CSIPHY4_CLK 48 +#define CAM_CC_CSIPHY5_CLK 49 +#define CAM_CC_FAST_AHB_CLK_SRC 50 +#define CAM_CC_GDSC_CLK 51 +#define CAM_CC_ICP_AHB_CLK 52 +#define CAM_CC_ICP_CLK 53 +#define CAM_CC_ICP_CLK_SRC 54 +#define CAM_CC_IFE_0_AHB_CLK 55 +#define CAM_CC_IFE_0_AREG_CLK 56 +#define CAM_CC_IFE_0_AXI_CLK 57 +#define CAM_CC_IFE_0_CLK 58 +#define CAM_CC_IFE_0_CLK_SRC 59 +#define CAM_CC_IFE_0_CPHY_RX_CLK 60 +#define CAM_CC_IFE_0_CSID_CLK 61 +#define CAM_CC_IFE_0_CSID_CLK_SRC 62 +#define CAM_CC_IFE_0_DSP_CLK 63 +#define CAM_CC_IFE_1_AHB_CLK 64 +#define CAM_CC_IFE_1_AREG_CLK 65 +#define CAM_CC_IFE_1_AXI_CLK 66 +#define CAM_CC_IFE_1_CLK 67 +#define CAM_CC_IFE_1_CLK_SRC 68 +#define CAM_CC_IFE_1_CPHY_RX_CLK 69 +#define CAM_CC_IFE_1_CSID_CLK 70 +#define CAM_CC_IFE_1_CSID_CLK_SRC 71 +#define CAM_CC_IFE_1_DSP_CLK 72 +#define CAM_CC_IFE_2_AHB_CLK 73 +#define CAM_CC_IFE_2_AREG_CLK 74 +#define CAM_CC_IFE_2_AXI_CLK 75 +#define CAM_CC_IFE_2_CLK 76 +#define CAM_CC_IFE_2_CLK_SRC 77 +#define CAM_CC_IFE_2_CPHY_RX_CLK 78 +#define CAM_CC_IFE_2_CSID_CLK 79 +#define CAM_CC_IFE_2_CSID_CLK_SRC 80 +#define CAM_CC_IFE_LITE_AHB_CLK 81 +#define CAM_CC_IFE_LITE_AXI_CLK 82 +#define CAM_CC_IFE_LITE_CLK 83 +#define CAM_CC_IFE_LITE_CLK_SRC 84 +#define CAM_CC_IFE_LITE_CPHY_RX_CLK 85 +#define CAM_CC_IFE_LITE_CSID_CLK 86 +#define CAM_CC_IFE_LITE_CSID_CLK_SRC 87 +#define CAM_CC_IPE_0_AHB_CLK 88 +#define CAM_CC_IPE_0_AREG_CLK 89 +#define CAM_CC_IPE_0_AXI_CLK 90 +#define CAM_CC_IPE_0_CLK 91 +#define CAM_CC_IPE_0_CLK_SRC 92 +#define CAM_CC_JPEG_CLK 93 +#define CAM_CC_JPEG_CLK_SRC 94 +#define CAM_CC_MCLK0_CLK 95 +#define CAM_CC_MCLK0_CLK_SRC 96 +#define CAM_CC_MCLK1_CLK 97 +#define CAM_CC_MCLK1_CLK_SRC 98 +#define CAM_CC_MCLK2_CLK 99 +#define CAM_CC_MCLK2_CLK_SRC 100 +#define CAM_CC_MCLK3_CLK 101 +#define CAM_CC_MCLK3_CLK_SRC 102 +#define CAM_CC_MCLK4_CLK 103 +#define CAM_CC_MCLK4_CLK_SRC 104 +#define CAM_CC_MCLK5_CLK 105 +#define CAM_CC_MCLK5_CLK_SRC 106 +#define CAM_CC_SLEEP_CLK 107 +#define CAM_CC_SLEEP_CLK_SRC 108 +#define CAM_CC_SLOW_AHB_CLK_SRC 109 +#define CAM_CC_XO_CLK_SRC 110 + +/* CAM_CC resets */ +#define CAM_CC_BPS_BCR 0 +#define CAM_CC_ICP_BCR 1 +#define CAM_CC_IFE_0_BCR 2 +#define CAM_CC_IFE_1_BCR 3 +#define CAM_CC_IFE_2_BCR 4 +#define CAM_CC_IPE_0_BCR 5 + +#endif diff --git a/include/dt-bindings/clock/qcom,dispcc-shima.h b/include/dt-bindings/clock/qcom,dispcc-shima.h new file mode 100644 index 000000000000..19c0478f95e0 --- /dev/null +++ b/include/dt-bindings/clock/qcom,dispcc-shima.h @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SHIMA_H +#define _DT_BINDINGS_CLK_QCOM_DISP_CC_SHIMA_H + +/* DISP_CC clocks */ +#define DISP_CC_PLL0 0 +#define DISP_CC_MDSS_AHB_CLK 1 +#define DISP_CC_MDSS_AHB_CLK_SRC 2 +#define DISP_CC_MDSS_BYTE0_CLK 3 +#define DISP_CC_MDSS_BYTE0_CLK_SRC 4 +#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 5 +#define DISP_CC_MDSS_BYTE0_INTF_CLK 6 +#define DISP_CC_MDSS_BYTE1_CLK 7 +#define DISP_CC_MDSS_BYTE1_CLK_SRC 8 +#define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC 9 +#define DISP_CC_MDSS_BYTE1_INTF_CLK 10 +#define DISP_CC_MDSS_DP_AUX_CLK 11 +#define DISP_CC_MDSS_DP_AUX_CLK_SRC 12 +#define DISP_CC_MDSS_DP_CRYPTO_CLK 13 +#define DISP_CC_MDSS_DP_CRYPTO_CLK_SRC 14 +#define DISP_CC_MDSS_DP_LINK_CLK 15 +#define DISP_CC_MDSS_DP_LINK_CLK_SRC 16 +#define DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC 17 +#define DISP_CC_MDSS_DP_LINK_INTF_CLK 18 +#define DISP_CC_MDSS_DP_PIXEL1_CLK 19 +#define DISP_CC_MDSS_DP_PIXEL1_CLK_SRC 20 +#define DISP_CC_MDSS_DP_PIXEL_CLK 21 +#define DISP_CC_MDSS_DP_PIXEL_CLK_SRC 22 +#define DISP_CC_MDSS_ESC0_CLK 23 +#define DISP_CC_MDSS_ESC0_CLK_SRC 24 +#define DISP_CC_MDSS_ESC1_CLK 25 +#define DISP_CC_MDSS_ESC1_CLK_SRC 26 +#define DISP_CC_MDSS_MDP_CLK 27 +#define DISP_CC_MDSS_MDP_CLK_SRC 28 +#define DISP_CC_MDSS_MDP_LUT_CLK 29 +#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 30 +#define DISP_CC_MDSS_PCLK0_CLK 31 +#define DISP_CC_MDSS_PCLK0_CLK_SRC 32 +#define DISP_CC_MDSS_PCLK1_CLK 33 +#define DISP_CC_MDSS_PCLK1_CLK_SRC 34 +#define DISP_CC_MDSS_ROT_CLK 35 +#define DISP_CC_MDSS_ROT_CLK_SRC 36 +#define DISP_CC_MDSS_RSCC_AHB_CLK 37 +#define DISP_CC_MDSS_RSCC_VSYNC_CLK 38 +#define DISP_CC_MDSS_VSYNC_CLK 39 +#define DISP_CC_MDSS_VSYNC_CLK_SRC 40 +#define DISP_CC_SLEEP_CLK 41 +#define DISP_CC_SLEEP_CLK_SRC 42 +#define DISP_CC_XO_CLK 43 +#define DISP_CC_XO_CLK_SRC 44 + +/* DISP_CC resets */ +#define DISP_CC_MDSS_CORE_BCR 0 +#define DISP_CC_MDSS_RSCC_BCR 1 + +#endif diff --git a/include/dt-bindings/clock/qcom,gcc-shima.h b/include/dt-bindings/clock/qcom,gcc-shima.h new file mode 100644 index 000000000000..02e6b63a853d --- /dev/null +++ b/include/dt-bindings/clock/qcom,gcc-shima.h @@ -0,0 +1,201 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SHIMA_H +#define _DT_BINDINGS_CLK_QCOM_GCC_SHIMA_H + +/* GCC HW clocks */ +#define CORE_BI_PLL_TEST_SE 0 +#define PCIE_0_PIPE_CLK 1 +#define PCIE_1_PIPE_CLK 2 +#define UFS_PHY_RX_SYMBOL_0_CLK 3 +#define UFS_PHY_RX_SYMBOL_1_CLK 4 +#define UFS_PHY_TX_SYMBOL_0_CLK 5 +#define USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK 6 + +/* GCC clocks */ +#define GCC_GPLL0 7 +#define GCC_GPLL0_OUT_EVEN 8 +#define GCC_GPLL0_OUT_ODD 9 +#define GCC_GPLL1 10 +#define GCC_GPLL10 11 +#define GCC_GPLL4 12 +#define GCC_GPLL9 13 +#define GCC_AGGRE_NOC_PCIE_0_AXI_CLK 14 +#define GCC_AGGRE_NOC_PCIE_1_AXI_CLK 15 +#define GCC_AGGRE_NOC_PCIE_TBU_CLK 16 +#define GCC_AGGRE_UFS_PHY_AXI_CLK 17 +#define GCC_AGGRE_USB3_PRIM_AXI_CLK 18 +#define GCC_CAMERA_AHB_CLK 19 +#define GCC_CAMERA_HF_AXI_CLK 20 +#define GCC_CAMERA_SF_AXI_CLK 21 +#define GCC_CAMERA_XO_CLK 22 +#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 23 +#define GCC_CPUSS_AHB_CLK 24 +#define GCC_CPUSS_AHB_CLK_SRC 25 +#define GCC_CPUSS_AHB_POSTDIV_CLK_SRC 26 +#define GCC_CPUSS_GPLL0_CLK_SRC 27 +#define GCC_DDRSS_GPU_AXI_CLK 28 +#define GCC_DDRSS_PCIE_SF_TBU_CLK 29 +#define GCC_DISP_AHB_CLK 30 +#define GCC_DISP_GPLL0_CLK_SRC 31 +#define GCC_DISP_HF_AXI_CLK 32 +#define GCC_DISP_SF_AXI_CLK 33 +#define GCC_DISP_XO_CLK 34 +#define GCC_GP1_CLK 35 +#define GCC_GP1_CLK_SRC 36 +#define GCC_GP2_CLK 37 +#define GCC_GP2_CLK_SRC 38 +#define GCC_GP3_CLK 39 +#define GCC_GP3_CLK_SRC 40 +#define GCC_GPU_CFG_AHB_CLK 41 +#define GCC_GPU_GPLL0_CLK_SRC 42 +#define GCC_GPU_GPLL0_DIV_CLK_SRC 43 +#define GCC_GPU_MEMNOC_GFX_CLK 44 +#define GCC_GPU_SNOC_DVM_GFX_CLK 45 +#define GCC_GPU_TCU_THROTTLE_CFG_AHB_CLK 46 +#define GCC_GPU_TCU_THROTTLE_CORE_CLK 47 +#define GCC_PCIE0_PHY_RCHNG_CLK 48 +#define GCC_PCIE1_PHY_RCHNG_CLK 49 +#define GCC_PCIE_0_AUX_CLK 50 +#define GCC_PCIE_0_AUX_CLK_SRC 51 +#define GCC_PCIE_0_CFG_AHB_CLK 52 +#define GCC_PCIE_0_MSTR_AXI_CLK 53 +#define GCC_PCIE_0_PHY_RCHNG_CLK_SRC 54 +#define GCC_PCIE_0_PIPE_CLK 55 +#define GCC_PCIE_0_PIPE_CLK_SRC 56 +#define GCC_PCIE_0_SLV_AXI_CLK 57 +#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 58 +#define GCC_PCIE_1_AUX_CLK 59 +#define GCC_PCIE_1_AUX_CLK_SRC 60 +#define GCC_PCIE_1_CFG_AHB_CLK 61 +#define GCC_PCIE_1_MSTR_AXI_CLK 62 +#define GCC_PCIE_1_PHY_RCHNG_CLK_SRC 63 +#define GCC_PCIE_1_PIPE_CLK 64 +#define GCC_PCIE_1_PIPE_CLK_SRC 65 +#define GCC_PCIE_1_SLV_AXI_CLK 66 +#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 67 +#define GCC_PDM2_CLK 68 +#define GCC_PDM2_CLK_SRC 69 +#define GCC_PDM_AHB_CLK 70 +#define GCC_PDM_XO4_CLK 71 +#define GCC_QMIP_CAMERA_NRT_AHB_CLK 72 +#define GCC_QMIP_CAMERA_RT_AHB_CLK 73 +#define GCC_QMIP_DISP_AHB_CLK 74 +#define GCC_QMIP_VIDEO_CVP_AHB_CLK 75 +#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 76 +#define GCC_QUPV3_WRAP0_CORE_2X_CLK 77 +#define GCC_QUPV3_WRAP0_CORE_CLK 78 +#define GCC_QUPV3_WRAP0_S0_CLK 79 +#define GCC_QUPV3_WRAP0_S0_CLK_SRC 80 +#define GCC_QUPV3_WRAP0_S1_CLK 81 +#define GCC_QUPV3_WRAP0_S1_CLK_SRC 82 +#define GCC_QUPV3_WRAP0_S2_CLK 83 +#define GCC_QUPV3_WRAP0_S2_CLK_SRC 84 +#define GCC_QUPV3_WRAP0_S3_CLK 85 +#define GCC_QUPV3_WRAP0_S3_CLK_SRC 86 +#define GCC_QUPV3_WRAP0_S4_CLK 87 +#define GCC_QUPV3_WRAP0_S4_CLK_SRC 88 +#define GCC_QUPV3_WRAP0_S5_CLK 89 +#define GCC_QUPV3_WRAP0_S5_CLK_SRC 90 +#define GCC_QUPV3_WRAP0_S6_CLK 91 +#define GCC_QUPV3_WRAP0_S6_CLK_SRC 92 +#define GCC_QUPV3_WRAP0_S7_CLK 93 +#define GCC_QUPV3_WRAP0_S7_CLK_SRC 94 +#define GCC_QUPV3_WRAP1_CORE_2X_CLK 95 +#define GCC_QUPV3_WRAP1_CORE_CLK 96 +#define GCC_QUPV3_WRAP1_S0_CLK 97 +#define GCC_QUPV3_WRAP1_S0_CLK_SRC 98 +#define GCC_QUPV3_WRAP1_S1_CLK 99 +#define GCC_QUPV3_WRAP1_S1_CLK_SRC 100 +#define GCC_QUPV3_WRAP1_S2_CLK 101 +#define GCC_QUPV3_WRAP1_S2_CLK_SRC 102 +#define GCC_QUPV3_WRAP1_S3_CLK 103 +#define GCC_QUPV3_WRAP1_S3_CLK_SRC 104 +#define GCC_QUPV3_WRAP1_S4_CLK 105 +#define GCC_QUPV3_WRAP1_S4_CLK_SRC 106 +#define GCC_QUPV3_WRAP1_S5_CLK 107 +#define GCC_QUPV3_WRAP1_S5_CLK_SRC 108 +#define GCC_QUPV3_WRAP1_S6_CLK 109 +#define GCC_QUPV3_WRAP1_S6_CLK_SRC 110 +#define GCC_QUPV3_WRAP1_S7_CLK 111 +#define GCC_QUPV3_WRAP1_S7_CLK_SRC 112 +#define GCC_QUPV3_WRAP_0_M_AHB_CLK 113 +#define GCC_QUPV3_WRAP_0_S_AHB_CLK 114 +#define GCC_QUPV3_WRAP_1_M_AHB_CLK 115 +#define GCC_QUPV3_WRAP_1_S_AHB_CLK 116 +#define GCC_SDCC1_AHB_CLK 117 +#define GCC_SDCC1_APPS_CLK 118 +#define GCC_SDCC1_APPS_CLK_SRC 119 +#define GCC_SDCC1_ICE_CORE_CLK 120 +#define GCC_SDCC1_ICE_CORE_CLK_SRC 121 +#define GCC_SDCC2_AHB_CLK 122 +#define GCC_SDCC2_APPS_CLK 123 +#define GCC_SDCC2_APPS_CLK_SRC 124 +#define GCC_SDCC4_AHB_CLK 125 +#define GCC_SDCC4_APPS_CLK 126 +#define GCC_SDCC4_APPS_CLK_SRC 127 +#define GCC_SYS_NOC_CPUSS_AHB_CLK 128 +#define GCC_THROTTLE_PCIE_AHB_CLK 129 +#define GCC_TITAN_NRT_THROTTLE_CORE_CLK 130 +#define GCC_TITAN_RT_THROTTLE_CORE_CLK 131 +#define GCC_UFS_PHY_AHB_CLK 132 +#define GCC_UFS_PHY_AXI_CLK 133 +#define GCC_UFS_PHY_AXI_CLK_SRC 134 +#define GCC_UFS_PHY_ICE_CORE_CLK 135 +#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 136 +#define GCC_UFS_PHY_PHY_AUX_CLK 137 +#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 138 +#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 139 +#define GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC 140 +#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 141 +#define GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC 142 +#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 143 +#define GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC 144 +#define GCC_UFS_PHY_UNIPRO_CORE_CLK 145 +#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 146 +#define GCC_USB30_PRIM_MASTER_CLK 147 +#define GCC_USB30_PRIM_MASTER_CLK_SRC 148 +#define GCC_USB30_PRIM_MOCK_UTMI_CLK 149 +#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 150 +#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 151 +#define GCC_USB30_PRIM_SLEEP_CLK 152 +#define GCC_USB3_PRIM_PHY_AUX_CLK 153 +#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 154 +#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 155 +#define GCC_USB3_PRIM_PHY_PIPE_CLK 156 +#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 157 +#define GCC_VIDEO_AHB_CLK 158 +#define GCC_VIDEO_AXI0_CLK 159 +#define GCC_VIDEO_AXI1_CLK 160 +#define GCC_VIDEO_CVP_THROTTLE_CORE_CLK 161 +#define GCC_VIDEO_MVP_THROTTLE_CORE_CLK 162 +#define GCC_VIDEO_XO_CLK 163 +#define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK 164 +#define GCC_UFS_PHY_AXI_HW_CTL_CLK 165 +#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK 166 +#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK 167 +#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK 168 + +/* GCC resets */ +#define GCC_CAMERA_BCR 0 +#define GCC_DISPLAY_BCR 1 +#define GCC_GPU_BCR 2 +#define GCC_PCIE_0_BCR 3 +#define GCC_PCIE_1_BCR 4 +#define GCC_PDM_BCR 5 +#define GCC_QUPV3_WRAPPER_0_BCR 6 +#define GCC_QUPV3_WRAPPER_1_BCR 7 +#define GCC_SDCC1_BCR 8 +#define GCC_SDCC2_BCR 9 +#define GCC_SDCC4_BCR 10 +#define GCC_UFS_PHY_BCR 11 +#define GCC_USB30_PRIM_BCR 12 +#define GCC_USB_PHY_CFG_AHB2PHY_BCR 13 +#define GCC_VIDEO_AXI0_CLK_ARES 14 +#define GCC_VIDEO_AXI1_CLK_ARES 15 +#define GCC_VIDEO_BCR 16 + +#endif diff --git a/include/dt-bindings/clock/qcom,gpucc-shima.h b/include/dt-bindings/clock/qcom,gpucc-shima.h new file mode 100644 index 000000000000..34618346dbaf --- /dev/null +++ b/include/dt-bindings/clock/qcom,gpucc-shima.h @@ -0,0 +1,54 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SHIMA_H +#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SHIMA_H + +/* GPU_CC clocks */ +#define GPU_CC_PLL0 0 +#define GPU_CC_PLL1 1 +#define GPU_CC_ACD_AHB_CLK 2 +#define GPU_CC_ACD_CXO_CLK 3 +#define GPU_CC_AHB_CLK 4 +#define GPU_CC_CB_CLK 5 +#define GPU_CC_CRC_AHB_CLK 6 +#define GPU_CC_CX_APB_CLK 7 +#define GPU_CC_CX_GFX3D_CLK 8 +#define GPU_CC_CX_GFX3D_SLV_CLK 9 +#define GPU_CC_CX_GMU_CLK 10 +#define GPU_CC_CX_SNOC_DVM_CLK 11 +#define GPU_CC_CXO_AON_CLK 12 +#define GPU_CC_CXO_CLK 13 +#define GPU_CC_FREQ_MEASURE_CLK 14 +#define GPU_CC_GMU_CLK_SRC 15 +#define GPU_CC_GX_CXO_CLK 16 +#define GPU_CC_GX_GFX3D_CLK 17 +#define GPU_CC_GX_GFX3D_CLK_SRC 18 +#define GPU_CC_GX_GMU_CLK 19 +#define GPU_CC_GX_VSENSE_CLK 20 +#define GPU_CC_HUB_AHB_DIV_CLK_SRC 21 +#define GPU_CC_HUB_AON_CLK 22 +#define GPU_CC_HUB_CLK_SRC 23 +#define GPU_CC_HUB_CX_INT_CLK 24 +#define GPU_CC_HUB_CX_INT_DIV_CLK_SRC 25 +#define GPU_CC_MND1X_0_GFX3D_CLK 26 +#define GPU_CC_MND1X_1_GFX3D_CLK 27 +#define GPU_CC_RBCPR_AHB_CLK 28 +#define GPU_CC_RBCPR_CLK 29 +#define GPU_CC_RBCPR_CLK_SRC 30 +#define GPU_CC_SLEEP_CLK 31 + +/* GPU_CC resets */ +#define GPUCC_GPU_CC_ACD_BCR 0 +#define GPUCC_GPU_CC_CB_BCR 1 +#define GPUCC_GPU_CC_CX_BCR 2 +#define GPUCC_GPU_CC_FAST_HUB_BCR 3 +#define GPUCC_GPU_CC_GFX3D_AON_BCR 4 +#define GPUCC_GPU_CC_GMU_BCR 5 +#define GPUCC_GPU_CC_GX_BCR 6 +#define GPUCC_GPU_CC_RBCPR_BCR 7 +#define GPUCC_GPU_CC_XO_BCR 8 + +#endif diff --git a/include/dt-bindings/clock/qcom,videocc-shima.h b/include/dt-bindings/clock/qcom,videocc-shima.h new file mode 100644 index 000000000000..8a531d930d4b --- /dev/null +++ b/include/dt-bindings/clock/qcom,videocc-shima.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SHIMA_H +#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SHIMA_H + +/* VIDEO_CC clocks */ +#define VIDEO_PLL0 0 +#define VIDEO_PLL1 1 +#define VIDEO_CC_AHB_CLK 2 +#define VIDEO_CC_AHB_CLK_SRC 3 +#define VIDEO_CC_MVS0_CLK 4 +#define VIDEO_CC_MVS0_CLK_SRC 5 +#define VIDEO_CC_MVS0_DIV_CLK_SRC 6 +#define VIDEO_CC_MVS0C_CLK 7 +#define VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC 8 +#define VIDEO_CC_MVS1_CLK 9 +#define VIDEO_CC_MVS1_CLK_SRC 10 +#define VIDEO_CC_MVS1_DIV2_CLK 11 +#define VIDEO_CC_MVS1_DIV_CLK_SRC 12 +#define VIDEO_CC_MVS1C_CLK 13 +#define VIDEO_CC_MVS1C_DIV2_DIV_CLK_SRC 14 +#define VIDEO_CC_SLEEP_CLK 15 +#define VIDEO_CC_SLEEP_CLK_SRC 16 +#define VIDEO_CC_XO_CLK 17 +#define VIDEO_CC_XO_CLK_SRC 18 + +/* VIDEO_CC resets */ +#define CVP_VIDEO_CC_INTERFACE_BCR 0 +#define CVP_VIDEO_CC_MVS0_BCR 1 +#define CVP_VIDEO_CC_MVS0C_BCR 2 +#define CVP_VIDEO_CC_MVS1_BCR 3 +#define CVP_VIDEO_CC_MVS1C_BCR 4 +#define VIDEO_CC_MVS0C_CLK_ARES 5 +#define VIDEO_CC_MVS1C_CLK_ARES 6 + +#endif