diff --git a/qcom/holi-pinctrl.dtsi b/qcom/holi-pinctrl.dtsi index 22ac7ad13a3e..ea7f0ae0ce02 100644 --- a/qcom/holi-pinctrl.dtsi +++ b/qcom/holi-pinctrl.dtsi @@ -7,5 +7,381 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + + qupv3_se0_i2c_pins: qupv3_se0_i2c_pins { + qupv3_se0_i2c_active: qupv3_se0_i2c_active { + mux { + pins = "gpio0", "gpio1"; + function = "qup00"; + }; + + config { + pins = "gpio0", "gpio1"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se0_i2c_sleep: qupv3_se0_i2c_sleep { + mux { + pins = "gpio0", "gpio1"; + function = "gpio"; + }; + + config { + pins = "gpio0", "gpio1"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se0_spi_pins: qupv3_se0_spi_pins { + qupv3_se0_spi_active: qupv3_se0_spi_active { + mux { + pins = "gpio0", "gpio1", + "gpio2", "gpio3"; + function = "qup00"; + }; + + config { + pins = "gpio0", "gpio1", + "gpio2", "gpio3"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se0_spi_sleep: qupv3_se0_spi_sleep { + mux { + pins = "gpio0", "gpio1", + "gpio2", "gpio3"; + function = "gpio"; + }; + + config { + pins = "gpio0", "gpio1", + "gpio2", "gpio3"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + qupv3_se1_4uart_pins: qupv3_se1_4uart_pins { + qupv3_se1_default_cts: + qupv3_se1_default_cts { + mux { + pins = "gpio61"; + function = "gpio"; + }; + + config { + pins = "gpio61"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + qupv3_se1_default_rtsrx: + qupv3_se1_default_rtsrx { + mux { + pins = "gpio62", "gpio64"; + function = "gpio"; + }; + + config { + pins = "gpio62", "gpio64"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + qupv3_se1_default_tx: + qupv3_se1_default_tx { + mux { + pins = "gpio63"; + function = "gpio"; + }; + + config { + pins = "gpio63"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se1_ctsrx: qupv3_se1_ctsrx { + mux { + pins = "gpio61", "gpio64"; + function = "qup01"; + }; + + config { + pins = "gpio61", "gpio64"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se1_rts: qupv3_se1_rts { + mux { + pins = "gpio62"; + function = "qup01"; + }; + + config { + pins = "gpio62"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + qupv3_se1_tx: qupv3_se1_tx { + mux { + pins = "gpio63"; + function = "qup01"; + }; + + config { + pins = "gpio63"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se2_i2c_pins: qupv3_se2_i2c_pins { + qupv3_se2_i2c_active: qupv3_se2_i2c_active { + mux { + pins = "gpio45", "gpio46"; + function = "qup02"; + }; + + config { + pins = "gpio45", "gpio46"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se2_i2c_sleep: qupv3_se2_i2c_sleep { + mux { + pins = "gpio45", "gpio46"; + function = "gpio"; + }; + + config { + pins = "gpio45", "gpio46"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se2_spi_pins: qupv3_se2_spi_pins { + qupv3_se2_spi_active: qupv3_se2_spi_active { + mux { + pins = "gpio45", "gpio46", + "gpio56", "gpio57"; + function = "qup02"; + }; + + config { + pins = "gpio45", "gpio46", + "gpio56", "gpio57"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se2_spi_sleep: qupv3_se2_spi_sleep { + mux { + pins = "gpio45", "gpio46", + "gpio56", "gpio57"; + function = "gpio"; + }; + + config { + pins = "gpio45", "gpio46", + "gpio56", "gpio57"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + qupv3_se6_i2c_pins: qupv3_se6_i2c_pins { + qupv3_se6_i2c_active: qupv3_se6_i2c_active { + mux { + pins = "gpio13", "gpio14"; + function = "qup10"; + }; + + config { + pins = "gpio13", "gpio14"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se6_i2c_sleep: qupv3_se6_i2c_sleep { + mux { + pins = "gpio13", "gpio14"; + function = "gpio"; + }; + + config { + pins = "gpio13", "gpio14"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se6_spi_pins: qupv3_se6_spi_pins { + qupv3_se6_spi_active: qupv3_se6_spi_active { + mux { + pins = "gpio13", "gpio14", + "gpio15", "gpio16"; + function = "qup10"; + }; + + config { + pins = "gpio13", "gpio14", + "gpio15", "gpio16"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se6_spi_sleep: qupv3_se6_spi_sleep { + mux { + pins = "gpio13", "gpio14", + "gpio15", "gpio16"; + function = "gpio"; + }; + + config { + pins = "gpio13", "gpio14", + "gpio15", "gpio16"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + qupv3_se7_i2c_pins: qupv3_se7_i2c_pins { + qupv3_se7_i2c_active: qupv3_se7_i2c_active { + mux { + pins = "gpio27", "gpio28"; + function = "qup11"; + }; + + config { + pins = "gpio27", "gpio28"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se7_i2c_sleep: qupv3_se7_i2c_sleep { + mux { + pins = "gpio27", "gpio28"; + function = "gpio"; + }; + + config { + pins = "gpio27", "gpio28"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se8_i2c_pins: qupv3_se8_i2c_pins { + qupv3_se8_i2c_active: qupv3_se8_i2c_active { + mux { + pins = "gpio19", "gpio20"; + function = "qup12"; + }; + + config { + pins = "gpio19", "gpio20"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se8_i2c_sleep: qupv3_se8_i2c_sleep { + mux { + pins = "gpio19", "gpio20"; + function = "gpio"; + }; + + config { + pins = "gpio19", "gpio20"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se9_2uart_pins: qupv3_se9_2uart_pins { + qupv3_se9_2uart_active: qupv3_se9_2uart_active { + mux { + pins = "gpio25", "gpio26"; + function = "qup13"; + }; + + config { + pins = "gpio25", "gpio26"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se9_2uart_sleep: qupv3_se9_2uart_sleep { + mux { + pins = "gpio25", "gpio26"; + function = "gpio"; + }; + + config { + pins = "gpio25", "gpio26"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + qupv3_se10_i2c_pins: qupv3_se10_i2c_pins { + qupv3_se10_i2c_active: qupv3_se10_i2c_active { + mux { + pins = "gpio4", "gpio5"; + function = "qup14"; + }; + + config { + pins = "gpio4", "gpio5"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se10_i2c_sleep: qupv3_se10_i2c_sleep { + mux { + pins = "gpio4", "gpio5"; + function = "gpio"; + }; + + config { + pins = "gpio4", "gpio5"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + }; }; diff --git a/qcom/holi-qupv3.dtsi b/qcom/holi-qupv3.dtsi new file mode 100644 index 000000000000..6e6986ad646f --- /dev/null +++ b/qcom/holi-qupv3.dtsi @@ -0,0 +1,323 @@ +#include + +&soc { + /* QUPv3 SE Instances + * Qup0 0: SE 0: I2C, SPI + * Qup0 1: SE 1: HSUART + * Qup0 2: SE 2: I2C, SPI + * Qup0 3: SE 3: Not bolled out + * Qup0 4: SE 4: Not bolled out + * Qup0 5: SE 5: Not bolled out + * Qup1 0: SE 6: I2C, SPI + * Qup1 1: SE 7: I2C + * Qup1 2: SE 8: I2C + * Qup1 3: SE 9: DEBUG UART + * Qup1 4: SE 10: I2C + * Qup1 5: SE 11: Not bolled out + */ + + /* QUPv3_0 wrapper instance */ + qupv3_0: qcom,qupv3_0_geni_se@4ac0000 { + compatible = "qcom,qupv3-geni-se"; + reg = <0x4ac0000 0x2000>; + qcom,msm-bus,num-paths = <2>; + qcom,msm-bus,vectors-bus-ids = + , + ; + qcom,vote-for-bw; + iommus = <&apps_smmu 0x0003 0x0>; + qcom,iommu-dma-addr-pool = <0x40000000 0xc0000000>; + qcom,iommu-dma = "fastmap"; + }; + + /* GPI Instance */ + gpi_dma0: qcom,gpi-dma@4a00000 { + compatible = "qcom,gpi-dma"; + #dma-cells = <5>; + reg = <0x4a00000 0x60000>; + reg-names = "gpi-top"; + iommus = <&apps_smmu 0x0016 0x0>; + qcom,max-num-gpii = <10>; + interrupts = , + , + , + , + , + , + , + , + , + ; + qcom,gpii-mask = <0x1f>; + qcom,ev-factor = <2>; + qcom,iommu-dma-addr-pool = <0x100000 0x100000>; + qcom,gpi-ee-offset = <0x10000>; + status = "ok"; + }; + + qupv3_se0_i2c: i2c@4a80000 { + compatible = "qcom,i2c-geni"; + reg = <0x4a80000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se0_i2c_active>; + pinctrl-1 = <&qupv3_se0_i2c_sleep>; + dmas = <&gpi_dma0 0 0 3 64 0>, + <&gpi_dma0 1 0 3 64 0>; + dma-names = "tx", "rx"; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se0_spi: spi@4a80000 { + compatible = "qcom,spi-geni"; + reg = <0x4a80000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se0_spi_active>; + pinctrl-1 = <&qupv3_se0_spi_sleep>; + dmas = <&gpi_dma0 0 0 1 64 0>, + <&gpi_dma0 1 0 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + /* HS UART Instance */ + qupv3_se1_4uart: qcom,qup_uart@4a84000 { + compatible = "qcom,msm-geni-serial-hs"; + reg = <0x4a84000 0x4000>; + reg-names = "se_phys"; + interrupts-extended = <&intc GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, + <&tlmm 64 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "active", "sleep"; + pinctrl-0 = <&qupv3_se1_default_cts>, + <&qupv3_se1_default_rtsrx>, <&qupv3_se1_default_tx>; + pinctrl-1 = <&qupv3_se1_ctsrx>, <&qupv3_se1_rts>, + <&qupv3_se1_tx>; + pinctrl-2 = <&qupv3_se1_ctsrx>, <&qupv3_se1_rts>, + <&qupv3_se1_tx>; + qcom,wakeup-byte = <0xFD>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se2_i2c: i2c@4a88000 { + compatible = "qcom,i2c-geni"; + reg = <0x4a88000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se2_i2c_active>; + pinctrl-1 = <&qupv3_se2_i2c_sleep>; + dmas = <&gpi_dma0 0 2 3 64 0>, + <&gpi_dma0 1 2 3 64 0>; + dma-names = "tx", "rx"; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + qupv3_se2_spi: spi@4a88000 { + compatible = "qcom,spi-geni"; + reg = <0x4a88000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>, + <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se2_spi_active>; + pinctrl-1 = <&qupv3_se2_spi_sleep>; + dmas = <&gpi_dma0 0 2 1 64 0>, + <&gpi_dma0 1 2 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_0>; + status = "disabled"; + }; + + /* QUPv3_1 wrapper instance */ + qupv3_1: qcom,qupv3_1_geni_se@4cc0000 { + compatible = "qcom,qupv3-geni-se"; + reg = <0x4cc0000 0x2000>; + qcom,msm-bus,num-paths = <2>; + qcom,msm-bus,vectors-bus-ids = + , + ; + qcom,vote-for-bw; + iommus = <&apps_smmu 0x00c3 0x0>; + qcom,iommu-dma-addr-pool = <0x40000000 0xc0000000>; + qcom,iommu-dma = "fastmap"; + }; + + /* GPI Instance */ + gpi_dma1: qcom,gpi-dma@4c00000 { + compatible = "qcom,gpi-dma"; + #dma-cells = <5>; + reg = <0x4c00000 0x60000>; + reg-names = "gpi-top"; + iommus = <&apps_smmu 0x00d6 0x0>; + qcom,max-num-gpii = <10>; + interrupts = , + , + , + , + , + , + , + , + , + ; + qcom,gpii-mask = <0x1f>; + qcom,ev-factor = <2>; + qcom,iommu-dma-addr-pool = <0x100000 0x100000>; + qcom,gpi-ee-offset = <0x10000>; + status = "ok"; + }; + + qupv3_se6_i2c: i2c@4c80000 { + compatible = "qcom,i2c-geni"; + reg = <0x4c80000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>, + <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se6_i2c_active>; + pinctrl-1 = <&qupv3_se6_i2c_sleep>; + dmas = <&gpi_dma1 0 0 3 64 0>, + <&gpi_dma1 1 0 3 64 0>; + dma-names = "tx", "rx"; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se6_spi: spi@4c80000 { + compatible = "qcom,spi-geni"; + reg = <0x4c80000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>, + <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se6_spi_active>; + pinctrl-1 = <&qupv3_se6_spi_sleep>; + dmas = <&gpi_dma1 0 0 1 64 0>, + <&gpi_dma1 1 0 1 64 0>; + dma-names = "tx", "rx"; + spi-max-frequency = <50000000>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se7_i2c: i2c@4c84000 { + compatible = "qcom,i2c-geni"; + reg = <0x4c84000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>, + <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se7_i2c_active>; + pinctrl-1 = <&qupv3_se7_i2c_sleep>; + dmas = <&gpi_dma1 0 1 3 64 0>, + <&gpi_dma1 1 1 3 64 0>; + dma-names = "tx", "rx"; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se8_i2c: i2c@4c88000 { + compatible = "qcom,i2c-geni"; + reg = <0x4c88000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>, + <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se8_i2c_active>; + pinctrl-1 = <&qupv3_se8_i2c_sleep>; + dmas = <&gpi_dma1 0 2 3 64 0>, + <&gpi_dma1 1 2 3 64 0>; + dma-names = "tx", "rx"; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + /* Debug UART Instance */ + qupv3_se9_2uart: qcom,qup_uart@4c8c000 { + compatible = "qcom,msm-geni-console"; + reg = <0x4c8c000 0x4000>; + reg-names = "se_phys"; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>, + <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se9_2uart_active>; + pinctrl-1 = <&qupv3_se9_2uart_sleep>; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + + qupv3_se10_i2c: i2c@4c90000 { + compatible = "qcom,i2c-geni"; + reg = <0x4c90000 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clock-names = "se-clk", "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>, + <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qupv3_se10_i2c_active>; + pinctrl-1 = <&qupv3_se10_i2c_sleep>; + dmas = <&gpi_dma1 0 4 3 64 0>, + <&gpi_dma1 1 4 3 64 0>; + dma-names = "tx", "rx"; + qcom,wrapper-core = <&qupv3_1>; + status = "disabled"; + }; + +}; diff --git a/qcom/holi.dtsi b/qcom/holi.dtsi index 2963243ce21e..5ce0276a9f82 100644 --- a/qcom/holi.dtsi +++ b/qcom/holi.dtsi @@ -19,6 +19,8 @@ aliases { ufshc1 = &ufshc_mem; /* Embedded UFS Slot */ + serial0 = &qupv3_se9_2uart; + hsuart0 = &qupv3_se1_4uart; }; cpus { @@ -1200,6 +1202,8 @@ #include "holi-pm.dtsi" #include "holi-vidc.dtsi" #include "holi-thermal.dtsi" +#include "holi-pinctrl.dtsi" +#include "holi-qupv3.dtsi" &pmk8350 { reg = <6 SPMI_USID>; @@ -1475,3 +1479,7 @@ parent-supply = <&VDD_GFX_LEVEL>; status = "ok"; }; + +&qupv3_se9_2uart { + status = "ok"; +};