From 778eba1b10c92b6a08f8e88465469c276c35d719 Mon Sep 17 00:00:00 2001 From: Jishnu Prakash Date: Thu, 17 Sep 2020 21:43:08 +0530 Subject: [PATCH 01/88] bindings: smb1390: Add binding documents for SMB1390 charger Add binding documentation for SMB1390 charger. SMB1390 is a charge pump PMIC and is used as a companion charger to the primary charging PMIC. This is a snapshot from msm-4.19 commit 94e8e08c6890 (" ARM: dts: msm: Correct the dev_id for hdmi cpu-dai"). Change-Id: Idfc0eadb74e0bfa67842de4f610e208de011b05e --- .../power/supply/qcom/smb1390-charger-psy.txt | 119 ++++++++++++++++++ 1 file changed, 119 insertions(+) create mode 100644 bindings/power/supply/qcom/smb1390-charger-psy.txt diff --git a/bindings/power/supply/qcom/smb1390-charger-psy.txt b/bindings/power/supply/qcom/smb1390-charger-psy.txt new file mode 100644 index 000000000000..b5bcb13f58e9 --- /dev/null +++ b/bindings/power/supply/qcom/smb1390-charger-psy.txt @@ -0,0 +1,119 @@ +Qualcomm Technologies, Inc. SMB1390 Charger Specific Bindings + +SMB1390 charge pump is paired with QTI family of standalone chargers to +enable a high current, high efficiency Li+ battery charging system. + +======================= +Required Node Structure +======================= + +SMB1390 Charger must be described in two levels of device nodes. + +================================== +First Level Node - SMB1390 Charger +================================== + +Charger specific properties: +- compatible + Usage: required + Value type: + Definition: "qcom,smb1390-charger-psy" for master SMB1390 and + "qcom,smb1390-slave" for slave SMB1390. + +- qcom,pmic-revid + Usage: required + Value type: phandle + Definition: Should specify the phandle of SMB's revid module. This is used + to identify the SMB subtype. + +- io-channels +- io-channel-names + Usage: required + Value type: + Definition: For details about IIO bindings see: + Documentation/devicetree/bindings/iio/iio-bindings.txt + +- qcom,min-ilim-ua + Usage: optional + Value type: + Definition: Minimum ILIM supported, if requested ILIM goes below this value + disable SMB1390. If this values is not specified default minimum + ILIM is 1A. + +- qcom,max-temp-alarm-degc + Usage: optional + Value type: + Definition: Maximum die temperature to trigger temp alarm. The value + must be one of the following: + 80, 90, 105, 115. + If this value is not specified or is not one of the above + then default value is 105. + +- qcom,max-cutoff-soc + Usage: optional + Value type: + Definition: SOC beyond which SMB1390 is kept disabled. + If this value is not specified then default value is 85%. + +- qcom,parallel-output-mode + Usage: optional + Value type: + Definition: Defines the SMB1390 output connection topology. + This should be one of the following: + 0 - If SMB1390 output is not connected to anything; + 1 - If SMB1390 output is connected to VPH_PWR; + 2 - If SMB1390 output is connected to VBATT. + If this value is not specified then default value is 1. + +- qcom,parallel-input-mode + Usage: optional + Value type: + Definition: Defines the SMB1390 input connection topology. + This should be one of the following: + 0 - If SMB1390 input is not connected to anything; + 1 - If SMB1390 input is connected to USBIN; + 3 - If SMB1390 input is connected to USBMID. + If this value is not specified then default value is 3. + +================================================ +Second Level Nodes - SMB1390 Charger Peripherals +================================================ + +Peripheral specific properties: +- interrupts + Usage: required + Value type: + Definition: Peripheral interrupt specifier. + +- interrupt-names + Usage: required + Value type: + Definition: Interrupt names. This list must match up 1-to-1 with the + interrupts specified in the 'interrupts' property. + +======= +Example +======= + +smb1390_charger: qcom,charge_pump { + compatible = "qcom,smb1390-charger-psy"; + qcom,pmic-revid = <&smb1390_revid>; + interrupt-parent = <&smb1390>; + status = "disabled"; + + io-channels = <&pm8150b_vadc ADC_AMUX_THM2>; + io-channel-names = "cp_die_temp"; + + qcom,core { + interrupts = <0x10 0x0 IRQ_TYPE_EDGE_RISING>, + <0x10 0x1 IRQ_TYPE_EDGE_RISING>, + <0x10 0x2 IRQ_TYPE_EDGE_RISING>, + <0x10 0x3 IRQ_TYPE_EDGE_RISING>, + <0x10 0x4 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "switcher-off-window", + "switcher-off-fault", + "vph-ov-soft", + "ilim", + "temp-alarm"; + }; +}; From 83562006560706b642f9833f9eec2372717efd33 Mon Sep 17 00:00:00 2001 From: Manu Gautam Date: Mon, 21 Sep 2020 17:32:41 +0530 Subject: [PATCH 02/88] ARM: dts: msm: Use PCIe_MSI for Shima Rely on PCIe controller to use MSI interrupts. Change-Id: I64ecb84d791c83a4710e6570eebd17454dba61d7 --- qcom/shima-pcie.dtsi | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/qcom/shima-pcie.dtsi b/qcom/shima-pcie.dtsi index 32573d6def76..fbe74ebfb44d 100644 --- a/qcom/shima-pcie.dtsi +++ b/qcom/shima-pcie.dtsi @@ -33,7 +33,7 @@ 0 0 0 3 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH 0 0 0 4 &intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; - msi-parent = <&pcie0_msi>; + msi-parent = <&pcie0_msi_snps>; perst-gpio = <&tlmm 94 0>; wake-gpio = <&tlmm 96 0>; @@ -194,6 +194,15 @@ }; }; + pcie0_msi_snps: qcom,pcie0_msi@a0000000 { + compatible = "qcom,pci-msi"; + msi-controller; + reg = <0xa0000000 0x0>; + interrupt-parent = <&intc>; + interrupts = ; + qcom,snps; + }; + pcie0_msi: qcom,pcie0_msi@17a10040 { compatible = "qcom,pci-msi"; msi-controller; From 5913f15c0120a50d5c4988fdf647c5c1cd2189f2 Mon Sep 17 00:00:00 2001 From: Prasad Sodagudi Date: Wed, 9 Sep 2020 16:13:54 -0700 Subject: [PATCH 03/88] ARM: dts: qcom: disable panic on single corruption Disable panic on the single bit corruptions on lahaina_v1 and enable for lahiana_v2 devices. Change-Id: I259b1723a291ffd72a25aa5e3560f7fad69e6257 --- qcom/lahaina-v2.dtsi | 5 +++++ qcom/lahaina.dtsi | 3 ++- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/qcom/lahaina-v2.dtsi b/qcom/lahaina-v2.dtsi index 1391441bb5d8..a390fd1bf7e1 100644 --- a/qcom/lahaina-v2.dtsi +++ b/qcom/lahaina-v2.dtsi @@ -22,6 +22,11 @@ dynamic-power-coefficient = <760>; }; +&kryo_erp { + + /delete-property/ qcom,disable-panic-on-ce; +}; + &sde_dp { /delete-node/ qcom,pll-supply-entries; }; diff --git a/qcom/lahaina.dtsi b/qcom/lahaina.dtsi index bc26eca67236..f734b77a1be6 100644 --- a/qcom/lahaina.dtsi +++ b/qcom/lahaina.dtsi @@ -3240,11 +3240,12 @@ }; }; - kryo-erp { + kryo_erp: erp { compatible = "arm,arm64-kryo-cpu-erp"; interrupts = , ; interrupt-names = "l1-l2-faultirq","l3-scu-faultirq"; + qcom,disable-panic-on-ce; }; tcsr_mutex_block: syscon@1f40000 { From 3ddab065bfebbeb67aeb9707a47c623d79ef63f1 Mon Sep 17 00:00:00 2001 From: Aasir Rasheed Date: Wed, 23 Sep 2020 14:47:59 +0530 Subject: [PATCH 04/88] ARM: dts: msm: Update cnss dt node for holi Configure voting parameter for vdd-cx-mx-config. Change-Id: Ib6aa4a541da297f4b3405ea6a7dd6a1d1c07eeed --- qcom/holi.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/holi.dtsi b/qcom/holi.dtsi index 165d453efd75..e7c69f529ce4 100644 --- a/qcom/holi.dtsi +++ b/qcom/holi.dtsi @@ -2624,7 +2624,7 @@ vdd-1.3-rfa-supply = <&L2E>; vdd-3.3-ch1-supply = <&L11E>; vdd-3.3-ch0-supply = <&L10E>; - qcom,vdd-cx-mx-config = <0 0>; + qcom,vdd-cx-mx-config = <640000 640000>; qcom,vdd-3.3-ch1-config = <3000000 3312000>; qcom,vdd-3.3-ch0-config = <3000000 3312000>; qcom,smp2p_map_wlan_1_in { From 3dad1a1c0c912713b6ab7aea8c8bdf270d13e1b0 Mon Sep 17 00:00:00 2001 From: Vinayak Menon Date: Thu, 10 Sep 2020 12:08:14 +0530 Subject: [PATCH 05/88] ARM: dts: msm: switch off kpti on holi Switch off kpti on holi as target is not vulnerable. Change-Id: Ica232c595152e0cd40303bb2ab6f92231441a684 --- qcom/holi.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/holi.dtsi b/qcom/holi.dtsi index e4f9ed939795..e643db7aa791 100644 --- a/qcom/holi.dtsi +++ b/qcom/holi.dtsi @@ -435,7 +435,7 @@ }; chosen { - bootargs = "rcupdate.rcu_expedited=1 rcu_nocbs=0-7 mem_offline.bypass_send_msg=1"; + bootargs = "rcupdate.rcu_expedited=1 rcu_nocbs=0-7 mem_offline.bypass_send_msg=1 kpti=off"; }; }; From ed8e10b20c2b37033fa207c9ba6f74a21871b744 Mon Sep 17 00:00:00 2001 From: Mukesh Ojha Date: Wed, 23 Sep 2020 23:39:51 +0530 Subject: [PATCH 06/88] ARM: dts: msm: Add device tree for Shima IDP/IDPS with 120fps platform Add device tree support for 1. Shima IDP with 120fps. 2. Shima IDPS digital mics support with 120fps. Change-Id: I7f2e820e2a2b6245b7377bc6432bbcf9e2f9607a --- qcom/Makefile | 12 +++++++++--- qcom/shima-idp-120fps-overlay.dts | 11 +++++++++++ qcom/shima-idp-120fps.dts | 10 ++++++++++ qcom/shima-idp-120fps.dtsi | 4 ++++ qcom/shima-idps-digital-mics-120fps-overlay.dts | 11 +++++++++++ qcom/shima-idps-digital-mics-120fps.dts | 10 ++++++++++ qcom/shima-idps-digital-mics-120fps.dtsi | 6 ++++++ 7 files changed, 61 insertions(+), 3 deletions(-) create mode 100644 qcom/shima-idp-120fps-overlay.dts create mode 100644 qcom/shima-idp-120fps.dts create mode 100644 qcom/shima-idp-120fps.dtsi create mode 100644 qcom/shima-idps-digital-mics-120fps-overlay.dts create mode 100644 qcom/shima-idps-digital-mics-120fps.dts create mode 100644 qcom/shima-idps-digital-mics-120fps.dtsi diff --git a/qcom/Makefile b/qcom/Makefile index 1a1c6f058bd8..7ed2de109fca 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -104,22 +104,28 @@ endif ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y) dtbo-$(CONFIG_ARCH_SHIMA) += \ shima-rumi-overlay.dtbo \ - shima-idp-overlay.dtbo \ + shima-idp-overlay.dtbo \ + shima-idp-120fps-overlay.dtbo \ shima-atp-overlay.dtbo \ shima-qrd-overlay.dtbo \ - shima-idps-digital-mics-overlay.dtbo + shima-idps-digital-mics-overlay.dtbo \ + shima-idps-digital-mics-120fps-overlay.dtbo shima-rumi-overlay.dtbo-base := shima.dtb shima-idp-overlay.dtbo-base := shima.dtb +shima-idp-120fps-overlay.dtbo-base := shima.dtb shima-atp-overlay.dtbo-base := shima.dtb shima-qrd-overlay.dtbo-base := shima.dtb shima-idps-digital-mics-overlay.dtbo-base := shima.dtb +shima-idps-digital-mics-120fps-overlay.dtbo-base := shima.dtb else dtb-$(CONFIG_ARCH_SHIMA) += shima-rumi.dtb \ shima-idp.dtb \ + shima-idp-120fps.dtb \ shima-atp.dtb \ shima-qrd.dtb \ - shima-idps-digital-mics.dtb + shima-idps-digital-mics.dtb \ + shima-idps-digital-mics-120fps.dtb endif ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y) diff --git a/qcom/shima-idp-120fps-overlay.dts b/qcom/shima-idp-120fps-overlay.dts new file mode 100644 index 000000000000..ef17b34fcdb7 --- /dev/null +++ b/qcom/shima-idp-120fps-overlay.dts @@ -0,0 +1,11 @@ +/dts-v1/; +/plugin/; + +#include "shima-idp-120fps.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Shima IDP + 120fps"; + compatible = "qcom,shima-idp", "qcom,shima", "qcom,idp"; + qcom,msm-id = <450 0x10000>; + qcom,board-id = <34 2>; +}; diff --git a/qcom/shima-idp-120fps.dts b/qcom/shima-idp-120fps.dts new file mode 100644 index 000000000000..75ea5988bc79 --- /dev/null +++ b/qcom/shima-idp-120fps.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "shima.dtsi" +#include "shima-idp-120fps.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Shima IDP + 120fps"; + compatible = "qcom,shima-idp", "qcom,shima", "qcom,idp"; + qcom,board-id = <34 2>; +}; diff --git a/qcom/shima-idp-120fps.dtsi b/qcom/shima-idp-120fps.dtsi new file mode 100644 index 000000000000..4f6732d3b955 --- /dev/null +++ b/qcom/shima-idp-120fps.dtsi @@ -0,0 +1,4 @@ +#include "shima-idp.dtsi" + +&soc { +}; diff --git a/qcom/shima-idps-digital-mics-120fps-overlay.dts b/qcom/shima-idps-digital-mics-120fps-overlay.dts new file mode 100644 index 000000000000..b5c784b62fb4 --- /dev/null +++ b/qcom/shima-idps-digital-mics-120fps-overlay.dts @@ -0,0 +1,11 @@ +/dts-v1/; +/plugin/; + +#include "shima-idps-digital-mics-120fps.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Shima IDPS DIGITAL MICS + 120fps"; + compatible = "qcom,shima-idp", "qcom,shima", "qcom,idp"; + qcom,msm-id = <450 0x10000>; + qcom,board-id = <34 3>; +}; diff --git a/qcom/shima-idps-digital-mics-120fps.dts b/qcom/shima-idps-digital-mics-120fps.dts new file mode 100644 index 000000000000..f6773a9471eb --- /dev/null +++ b/qcom/shima-idps-digital-mics-120fps.dts @@ -0,0 +1,10 @@ +/dts-v1/; + +#include "shima.dtsi" +#include "shima-idps-digital-mics-120fps.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Shima IDPS DIGITAL MICS + 120fps"; + compatible = "qcom,shima-idp", "qcom,shima", "qcom,idp"; + qcom,board-id = <34 3>; +}; diff --git a/qcom/shima-idps-digital-mics-120fps.dtsi b/qcom/shima-idps-digital-mics-120fps.dtsi new file mode 100644 index 000000000000..51ccf2dd48fd --- /dev/null +++ b/qcom/shima-idps-digital-mics-120fps.dtsi @@ -0,0 +1,6 @@ +#include "shima-idps-digital-mics.dtsi" + +&soc { +}; + + From 2daf19cb131a0b2a097ef3a0784bd809746ba138 Mon Sep 17 00:00:00 2001 From: Lipsa Rout Date: Mon, 21 Sep 2020 14:17:44 +0530 Subject: [PATCH 07/88] ARM: dts: msm: Add lcd display support on holi Add Qsync FHD display support on holi lcd cdp. Change-Id: Ic407db2f1465dbf8e2285d648d605a055d1219d0 --- qcom/holi-cdp-lcd.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/qcom/holi-cdp-lcd.dtsi b/qcom/holi-cdp-lcd.dtsi index b5e20250c0b9..6e5685c7b540 100644 --- a/qcom/holi-cdp-lcd.dtsi +++ b/qcom/holi-cdp-lcd.dtsi @@ -14,3 +14,8 @@ qcom,leds-per-string = <4>; }; +&sde_dsi { + lab-supply = <&lcdb_ldo_vreg>; + ibb-supply = <&lcdb_ncp_vreg>; + qcom,dsi-default-panel = <&dsi_sharp_qsync_fhd_video>; +}; From e9bbb1233ac9939b65615011b3757e1e50649bbf Mon Sep 17 00:00:00 2001 From: Ritesh Kumar Date: Fri, 25 Sep 2020 14:05:39 +0530 Subject: [PATCH 08/88] ARM: dts: msm: Update L12C min and init voltage on shima Update init voltage and min voltage of L12C LDO to 1.82V on shima platform. Change-Id: I35b641b8ddecf93a5d6443b7861b3f3f0b5c2efa --- qcom/shima-regulators.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/qcom/shima-regulators.dtsi b/qcom/shima-regulators.dtsi index e592f7a5df8e..063c7ff9bbe3 100644 --- a/qcom/shima-regulators.dtsi +++ b/qcom/shima-regulators.dtsi @@ -678,9 +678,9 @@ pm8350c_l12: regulator-pm8350c-l12 { regulator-name = "pm8350c_l12"; qcom,set = ; - regulator-min-microvolt = <1920000>; + regulator-min-microvolt = <1820000>; regulator-max-microvolt = <1980000>; - qcom,init-voltage = <1920000>; + qcom,init-voltage = <1820000>; qcom,init-mode = ; qcom,proxy-consumer-enable; qcom,proxy-consumer-current = <60700>; From fa68b3de801e35327dc59b93c77467b0d2ec29ce Mon Sep 17 00:00:00 2001 From: Neeraj Upadhyay Date: Mon, 28 Sep 2020 09:19:40 +0530 Subject: [PATCH 09/88] ARM: dts: msm: enable vm console suspend for Shima VM Keeping "no_console_suspend" causing a frequent wakeups when VM enter into suspend state. This is because console is implemented on RM console where RM console interrupts are configured as wakeup capable. Remove "no_console_suspend" to avoid wakeups. User can control this feature using below node. echo Y > /sys/module/printk/parameters/console_suspend. Change-Id: I1bd5f0832802ff4b350707632d74aa0f7cd3c9d9 --- qcom/shima-vm.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/shima-vm.dtsi b/qcom/shima-vm.dtsi index 8a1fb3b5d52c..e5cc267dd6c2 100644 --- a/qcom/shima-vm.dtsi +++ b/qcom/shima-vm.dtsi @@ -12,7 +12,7 @@ }; chosen { - bootargs = "nokaslr no_console_suspend root=/dev/ram rw init=/init console=hvc0 loglevel=8"; + bootargs = "nokaslr root=/dev/ram rw init=/init console=hvc0 loglevel=8"; linux,initrd-start = <0x2a900000>; linux,initrd-end = <0x2b100000>; /* 8 MB */ kaslr-seed = <0xfeedbeef 0xc0def00d>; From fd0c05ce1af0e4e34f102c2b103695eb431c499b Mon Sep 17 00:00:00 2001 From: Ravikanth Tuniki Date: Wed, 16 Sep 2020 17:25:55 +0530 Subject: [PATCH 10/88] ARM: dts: msm: Add touch support for holi Add Synaptics dsx touch support for qsync fhd panel on holi cdp. Change-Id: I8969d9599a2998a508089874519f5ca4630d99c7 --- qcom/holi-cdp-lcd.dtsi | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/qcom/holi-cdp-lcd.dtsi b/qcom/holi-cdp-lcd.dtsi index 6e5685c7b540..057607ce47a3 100644 --- a/qcom/holi-cdp-lcd.dtsi +++ b/qcom/holi-cdp-lcd.dtsi @@ -19,3 +19,34 @@ ibb-supply = <&lcdb_ncp_vreg>; qcom,dsi-default-panel = <&dsi_sharp_qsync_fhd_video>; }; + +&qupv3_se8_i2c { + qcom,i2c-touch-active="synaptics,dsx-i2c"; + + synaptics_dsx@22 { + compatible = "synaptics,dsx-i2c"; + reg = <0x22>; + interrupt-parent = <&tlmm>; + interrupts = <39 0x2008>; + vdd-supply = <&L11A>; + avdd-supply = <&L6A>; + pinctrl-names = "pmx_ts_active", "pmx_ts_suspend", + "pmx_ts_release"; + pinctrl-0 = <&ts_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + pinctrl-2 = <&pmx_ts_release>; + synaptics,pwr-reg-name = "avdd"; + synaptics,bus-reg-name = "vdd"; + synaptics,ub-i2c-addr = <0x22>; + synaptics,max-y-for-2d = <1859>; + synaptics,irq-gpio = <&tlmm 22 0x2008>; + synaptics,reset-gpio = <&tlmm 21 0x0>; + synaptics,irq-on-state = <0>; + synaptics,power-delay-ms = <200>; + synaptics,reset-delay-ms = <200>; + synaptics,reset-on-state = <0>; + synaptics,reset-active-ms = <20>; + + panel = <&dsi_sharp_qsync_fhd_video>; + }; +}; From 492e6cc84259e924cff67bfdc3d0b2402d5894c8 Mon Sep 17 00:00:00 2001 From: Harigovindan P Date: Thu, 24 Sep 2020 09:57:30 +0530 Subject: [PATCH 11/88] ARM: dts: msm: Add 144 fps touch support on shima target Add 144 fps panel touch support on shima target. Change-Id: I67d8a042a66c157acbeed0ed1452ed36e0e4c9f7 --- qcom/shima-idp.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/qcom/shima-idp.dtsi b/qcom/shima-idp.dtsi index d0a694ca961b..a4be84ba4aee 100644 --- a/qcom/shima-idp.dtsi +++ b/qcom/shima-idp.dtsi @@ -180,7 +180,8 @@ panel = <&dsi_r66451_amoled_cmd &dsi_r66451_amoled_video &dsi_r66451_amoled_60hz_video - &dsi_r66451_amoled_60hz_cmd>; + &dsi_r66451_amoled_60hz_cmd + &dsi_r66451_amoled_144hz_cmd>; focaltech,trusted-touch-mode = "vm_mode"; focaltech,touch-environment = "pvm"; From 1b10670b1648112337a06dffe97ea49396efec2d Mon Sep 17 00:00:00 2001 From: Armaan Siddiqui Date: Wed, 16 Sep 2020 16:52:46 +0530 Subject: [PATCH 12/88] ARM: dts: msm: add change to support gsi wdi polling Change done to support dynamic allocation of wdi db addr. Change-Id: Ic38446a3d34165f13f5eccd222282a6780e51a6f --- bindings/platform/msm/ipa.txt | 2 ++ qcom/lahaina.dtsi | 1 + qcom/shima.dtsi | 1 + 3 files changed, 4 insertions(+) diff --git a/bindings/platform/msm/ipa.txt b/bindings/platform/msm/ipa.txt index 93d258aa0f08..9b8bc6cead21 100644 --- a/bindings/platform/msm/ipa.txt +++ b/bindings/platform/msm/ipa.txt @@ -74,6 +74,8 @@ memory allocation over a PCIe bridge using wdi-2.0 or not - qcom,ipa-wdi3-over-gsi: Boolean context flag to indicate whether using wdi-3.0 or not +- qcom,gsi_wdi_db_polling: Boolean context flag to indicate whether + using gsi wdi db polling or not - qcom,bandwidth-vote-for-ipa: Boolean context flag to indicate whether ipa clock voting is done by bandwidth voting via msm-bus-scale driver or not diff --git a/qcom/lahaina.dtsi b/qcom/lahaina.dtsi index ce44b9188fda..f8a56095fc67 100644 --- a/qcom/lahaina.dtsi +++ b/qcom/lahaina.dtsi @@ -4614,6 +4614,7 @@ qcom,wan-use-skb-page; qcom,rmnet-ctl-enable; qcom,ipa-uc-holb-monitor; + qcom,gsi_wdi_db_polling; qcom,ipa-holb-monitor-poll-period = <5>; qcom,ipa-holb-monitor-max-cnt-wlan = <10>; qcom,ipa-holb-monitor-max-cnt-usb = <10>; diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi index 14f570b0c84d..55065f1e28e5 100644 --- a/qcom/shima.dtsi +++ b/qcom/shima.dtsi @@ -3705,6 +3705,7 @@ qcom,wan-use-skb-page; qcom,rmnet-ctl-enable; qcom,ipa-uc-holb-monitor; + qcom,gsi_wdi_db_polling; qcom,ipa-holb-monitor-poll-period = <5>; qcom,ipa-holb-monitor-max-cnt-wlan = <10>; qcom,ipa-holb-monitor-max-cnt-usb = <10>; From 77750f931fae97bc18b07e3995b3030ec6e2d5ac Mon Sep 17 00:00:00 2001 From: Ashish Chavan Date: Thu, 24 Sep 2020 15:26:58 +0530 Subject: [PATCH 13/88] ARM: dts: qcom: Update cp channel names for holi Update cp channel names for holi Change-Id: Ibe008356432ca4ab445ae152e585e951c5509746 --- qcom/holi-mtp-usbc.dtsi | 6 +++--- qcom/holi-mtp.dtsi | 6 +++--- qcom/holi-qrd.dtsi | 6 +++--- 3 files changed, 9 insertions(+), 9 deletions(-) diff --git a/qcom/holi-mtp-usbc.dtsi b/qcom/holi-mtp-usbc.dtsi index fddd4d338dda..99073ba1061c 100644 --- a/qcom/holi-mtp-usbc.dtsi +++ b/qcom/holi-mtp-usbc.dtsi @@ -236,9 +236,9 @@ "cycle_count", "charge_full_design", "time_to_full_now", - "parallel_mode", - "parallel_output_mode", - "min_icl", + "cp_parallel_mode", + "cp_parallel_output_mode", + "cp_min_icl", "cp_switcher_en", "cp_enable", "cp_ilim", diff --git a/qcom/holi-mtp.dtsi b/qcom/holi-mtp.dtsi index 25c4885ccb47..77dcb6330af0 100644 --- a/qcom/holi-mtp.dtsi +++ b/qcom/holi-mtp.dtsi @@ -217,9 +217,9 @@ "cycle_count", "charge_full_design", "time_to_full_now", - "parallel_mode", - "parallel_output_mode", - "min_icl", + "cp_parallel_mode", + "cp_parallel_output_mode", + "cp_min_icl", "cp_switcher_en", "cp_enable", "cp_ilim", diff --git a/qcom/holi-qrd.dtsi b/qcom/holi-qrd.dtsi index a9d92ea08dcb..48e5127acab5 100644 --- a/qcom/holi-qrd.dtsi +++ b/qcom/holi-qrd.dtsi @@ -294,9 +294,9 @@ "cycle_count", "charge_full_design", "time_to_full_now", - "parallel_mode", - "parallel_output_mode", - "min_icl", + "cp_parallel_mode", + "cp_parallel_output_mode", + "cp_min_icl", "cp_switcher_en", "cp_enable", "cp_ilim", From c991dea0858fda959ad35479ab9c9474329859ac Mon Sep 17 00:00:00 2001 From: Chandana Kishori Chiluveru Date: Wed, 30 Sep 2020 08:46:07 +0530 Subject: [PATCH 14/88] dt-bindings: Add DT bindings for BLSP UART drivers Add dt-bindings for UART BLSP driver. This change adds a snapshot of BLSP UART driver bindings from the 4.14 branch. kernel-4.14 baseline: 'commit 5b51cb0c0e2c474f1f ("serial: msm_serial_hs: Add snapshot of serial highspeed driver")'. Removed ICB bus voting properties and replaced them with new ICC framework properties. Change-Id: I8316c36375ed34d008e6d6e456e807ecc5814b39 --- bindings/serial/msm_serial_hs.txt | 120 ++++++++++++++++++++++++++++++ 1 file changed, 120 insertions(+) create mode 100644 bindings/serial/msm_serial_hs.txt diff --git a/bindings/serial/msm_serial_hs.txt b/bindings/serial/msm_serial_hs.txt new file mode 100644 index 000000000000..fa2e664fafa8 --- /dev/null +++ b/bindings/serial/msm_serial_hs.txt @@ -0,0 +1,120 @@ +* Qualcomm Technologies Inc, BLSP MSM HSUART + +Required properties: +- compatible : + - "qcom,msm-hsuart-v14" to be used for UARTDM Core v1.4 +- reg : offset and length of the register set for both the device, + uart core and bam core +- reg-names : + - "core_mem" to be used as name of the uart core + - "bam_mem" to be used as name of the bam core +- interrupts : interrupts for both the device,uart core and bam core +- interrupt-names : + - "core_irq" to be used as uart irq + - "bam irq" to be used as bam irq +- #interrupt-cells: Specifies the number of cells needed to encode an interrupt + source. The type shall be a and the value shall be 1 +- #address-cells: Specifies the number of cells needed to encode an address. + The type shall be and the value shall be 0 +- interrupt-parent = It is needed for interrupt mapping +- bam-tx-ep-pipe-index : BAM TX Endpoint Pipe Index for HSUART +- bam-rx-ep-pipe-index : BAM RX Endpoint Pipe Index for HSUART + +BLSP has a static pipe allocation and assumes a pair-pipe for each uart core. +Pipes [2*i : 2*i+1] are allocated for UART cores where i = [0 : 5]. +Hence, Minimum and Maximum permitted value of endpoint pipe index to be used +with uart core is 0 and 11 respectively. + +There is one HSUART block used in MSM devices, +"qcom,msm-hsuart-v14". The msm-serial-hs driver is +able to handle this, and matches against the "qcom,msm-hsuart-v14" +as the compatibility. + +The registers for the "qcom,msm-hsuart-v14" device need to specify both +register blocks - uart core and bam core. + +Example: + + uart7: uart@f995d000 { + compatible = "qcom,msm-hsuart-v14"; + reg = <0xf995d000 0x1000>, + <0xf9944000 0x5000>; + reg-names = "core_mem", "bam_mem"; + interrupt-names = "core_irq", "bam_irq"; + #address-cells = <0>; + interrupt-parent = <&uart7>; + interrupts = <0 1>; + #interrupt-cells = <1>; + interrupt-map = <0 &intc 0 113 0 + 1 &intc 0 239 0> + qcom,bam-tx-ep-pipe-index = <0>; + qcom,bam-rx-ep-pipe-index = <1>; + }; + +Optional properties: +- qcom,-gpio : handle to the GPIO node, see "gpios property" in +Documentation/devicetree/bindings/gpio/gpio.txt. +"gpio-name" can be "tx", "rx", "cts" and "rfr" based on number of UART GPIOs +need to configured. +Gpio's are optional if it is required to be not configured by UART driver or +case where there is nothing connected and we want to use internal loopback mode +for uart. +- qcom, wakeup_irq : UART RX GPIO IRQ line to be configured as wakeup source. +- qcom,inject-rx-on-wakeup : inject_rx_on_wakeup enables feature where on +receiving interrupt with UART RX GPIO IRQ line (i.e. above wakeup_irq property), +HSUART driver injects provided character with property rx_to_inject. +- qcom, rx-char-to-inject : The character to be inserted on wakeup. +- qcom, no-suspend-delay : This decides system to go to suspend immediately +or not + +- interconnects: pairs of phandles and interconnect provider specifier + to denote the edge source and destination ports of + the interconnect path. Please refer to + Documentation/devicetree/bindings/interconnect/ + for more details. +- interconnect-names: List of interconnect path name strings sorted in the same + order as the interconnects property. Consumers drivers will use + interconnect-names to match interconnect paths with interconnect + specifiers. Please refer to Documentation/devicetree/bindings/ + interconnect/ for more details. + +Aliases : +An alias may be optionally used to bind the UART device to a TTY device +(ttyHS) with a given alias number. Aliases are of the form +uart where is an integer representing the alias number to use. +On systems with multiple UART devices present, an alias may optionally be +defined for such devices. The alias value should be from 0 to 255. + +Example: + + aliases { + uart4 = &uart7; // This device will be enumerated as ttyHS4 + }; + + uart7: uart@f995d000 { + compatible = "qcom,msm-hsuart-v14" + reg = <0x19c40000 0x1000">, + <0xf9944000 0x5000>; + reg-names = "core_mem", "bam_mem"; + interrupt-names = "core_irq", "bam_irq", "wakeup_irq"; + #address-cells = <0>; + interrupt-parent = <&uart7>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 113 0 + 1 &intc 0 239 0 + 2 &msmgpio 42 0>; + qcom,tx-gpio = <&msmgpio 41 0x00>; + qcom,rx-gpio = <&msmgpio 42 0x00>; + qcom,cts-gpio = <&msmgpio 43 0x00>; + qcom,rfr-gpio = <&msmgpio 44 0x00>; + qcom,inject-rx-on-wakeup = <1>; + qcom,rx-char-to-inject = <0xFD>; + + qcom,bam-tx-ep-pipe-index = <0>; + qcom,bam-rx-ep-pipe-index = <1>; + + interconnect-names = "blsp-ddr"; + interconnects = <&system_noc MASTER_BLSP_1 &mc_virt SLAVE_EBI1>; + }; From ec9f758a19b5fae404045dea451449f476864b90 Mon Sep 17 00:00:00 2001 From: Vipin Deep Kaur Date: Mon, 28 Sep 2020 15:46:14 +0530 Subject: [PATCH 15/88] dt-bindings: qcom-sps-dma: Add snapshot of SPS DMA driver This change adds a snapshot of SPS DMA driver from the 4.19 branch. kernel-4.19 baseline: 'commit b159d5da02b7 ("dt-bindings: Add documentation for SDM660")'. Change-Id: I1997961ee887e0657602e3456cee7f1ff88ae368 --- bindings/dma/qcom-sps-dma.txt | 42 +++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) create mode 100644 bindings/dma/qcom-sps-dma.txt diff --git a/bindings/dma/qcom-sps-dma.txt b/bindings/dma/qcom-sps-dma.txt new file mode 100644 index 000000000000..c6c8726dac26 --- /dev/null +++ b/bindings/dma/qcom-sps-dma.txt @@ -0,0 +1,42 @@ +* Qualcomm technologies inc, DMA engine driver for BAM (Bus Access Manager). + +Required properties: +- compatible: Should be "qcom,sps-dma". +- reg: Should contain DMA registers location and length. This should include + all of the per-channel registers. +- interrupts: Should contain the BAM interrupt number. +- qcom,summing-threshold: Should contain the BAM event threshold of + the sum of descriptors' sizes in bytes. + +Optional properties: +- qcom,managed-locally : Use when BAM global device control is managed locally + by the application processor. + +Example: + + dma_blsp1: qcom,sps-dma@f9904000 { /* BLSP1 */ + #dma-cells = <4>; + compatible = "qcom,sps-dma"; + reg = <0xf9904000 0x19000>; + interrupts = <0 238 0>; + qcom,summing-threshold = <10>; + }; + +DMA clients connected to the qcom-sps-dma DMA controller must use the format +described in the dma.txt file, using a five-cell specifier for each channel, +a phandle plus four integer cells, as shown below: + +dmas = <[phandle of the dma controller] [pipe index] [number of descriptors] + [sps_connect flags] [sps_register_event flags]>; + +Example: + +i2c_2: i2c@f9924000 { /* BLSP1 QUP2 */ + . + . + . + /* <&phandle pipe-idx n-descs connect-flags event-flags> */ + dmas = <&dma_blsp1 14 32 0x20000020 0x20>, + <&dma_blsp1 15 64 0x20000020 0x20>; + dma-names = "tx", "rx"; +}; From 6f5e4071818ba5f5c7dfae6062d063335bb55ed3 Mon Sep 17 00:00:00 2001 From: Vipin Deep Kaur Date: Thu, 24 Sep 2020 14:09:36 +0530 Subject: [PATCH 16/88] dt-bindings: i2c-msm-v2: Add snapshot of I2C MSM V2 driver This change adds a snapshot of I2C MSM V2 driver from the 4.14 branch. kernel-4.14 baseline: 'commit 2aa77f468a3d ("i2c-msm-v2: Replace HW recovery mechanism with SW bit-banging")'. Change-Id: Ia0604ce27bdf29018b911d7ab2baa3e70d70b31f --- bindings/i2c/i2c-msm-v2.txt | 59 +++++++++++++++++++++++++++++++++++++ 1 file changed, 59 insertions(+) create mode 100644 bindings/i2c/i2c-msm-v2.txt diff --git a/bindings/i2c/i2c-msm-v2.txt b/bindings/i2c/i2c-msm-v2.txt new file mode 100644 index 000000000000..7c0ec7dba150 --- /dev/null +++ b/bindings/i2c/i2c-msm-v2.txt @@ -0,0 +1,59 @@ +Qualcomm Technologies, Inc. I2C controller + +Required properties: + - reg : Offset and length of the register region for the device named in + reg-names and has the same index. + - reg-names : Register region name(s) referenced in reg above + "qup_phys_addr" : Physical address of QUP register space. + - compatible : should be "qcom,i2c-msm-v2" + - interrupts : Interrupt number which correspond to the entry with the same + index in interrupt-names. + - interrupt-names: QUP core interrupt name(s) referenced in interrupts above + "qup_irq" : QUP interrupt used by the controller. + - dmas : DMA engine API's parameters for blsp. + <[phandle of the dma controller] [pipe index] [number of descriptors] + [sps_connect flags] [sps_register_event flags]>; + - dma-names : dma channel names. + - qcom,clk-freq-out : Desired I2C bus clock frequency in Hz + - qcom,clk-freq-in : Supplied core clock frequency in Hz. + - qcom,i2c-dat : specifies GPIO which corresponds to the I2C data line. + - qcom,i2c-clk : specifies GPIO which corresponds to the I2C clock line. + +Required alias: + - The desired bus-number is specified by an alias with the following format: + 'i2c{n}' where n is the bus number. + +Optional property: + - qcom,noise-rjct-scl : number of low samples on clock line to consider it low. + When missing default to 0. + - qcom,noise-rjct-sda : number of low samples on data line to consider it low. + When missing default to 0. + - qcom,disable-dma : disables DMA transfer mode. + - qcom,master-id : Master-port value used on voting for the clock path. + - qcom,high-time-clk-div : high time divider value to configure clk-ctl + register. When missing, default to the value given in driver. + - qcom,fs-clk-div: fs divider value to configure clk-ctl register. When + missing, default to the value given in driver. + +Example: + aliases { + i2c10 = &i2c_10; + }; + + i2c_10: i2c@f9966000 { + compatible = "qcom,i2c-msm-v2"; + reg-names = "qup_phys_addr", "dma_phys_addr"; + reg = <0xf9966000 0x1000>; + interrupt-names = "qup_irq"; + interrupts = <0 104 0>; + dmas = <&dma_blsp1 14 32 0x20000020 0x20>, + <&dma_blsp1 15 64 0x20000020 0x20>; + dma-names = "tx", "rx"; + qcom,clk-freq-out = <100000>; + qcom,clk-freq-in = <24000000>; + qcom,noise-rjct-scl = <0>; + qcom,noise-rjct-sda = <0>; + qcom,i2c-dat = <&tlmm 67 0x00>; + qcom,i2c-clk = <&tlmm 68 0x00>; + + }; From 81a0a04825de2f5fab0fd9a62766cb4200833537 Mon Sep 17 00:00:00 2001 From: Sriharsha Allenki Date: Wed, 30 Sep 2020 09:50:48 +0530 Subject: [PATCH 17/88] ARM: dts: msm: Enable U1 and U2 on Holi The USB Gen1 DWC3 controller supports the U1 and U2 in USB3.0 mode. Hence enable the same on Holi. Change-Id: Ic6a84900803f8dc12aef6e3eba56b06e4a4487d2 --- qcom/holi-usb.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/qcom/holi-usb.dtsi b/qcom/holi-usb.dtsi index beca47439f58..d7859b6330c5 100644 --- a/qcom/holi-usb.dtsi +++ b/qcom/holi-usb.dtsi @@ -66,8 +66,6 @@ linux,sysdev_is_parent; snps,disable-clk-gating; snps,is-utmi-l1-suspend; - snps,dis-u1-entry-quirk; - snps,dis-u2-entry-quirk; snps,dis_u2_susphy_quirk; snps,has-lpm-erratum; snps,hird-threshold = /bits/ 8 <0x0>; From c9d559494c4733c2be2705a503ed03cfc9d50caa Mon Sep 17 00:00:00 2001 From: Chandana Kishori Chiluveru Date: Thu, 17 Sep 2020 18:01:52 +0530 Subject: [PATCH 18/88] ARM: dts: msm: Add BLSP DTSI nodes on sdxlemur Add BLSP(I2C, SPI and UART) DTSI nodes on sdxlemur Change-Id: I7f6b1ce3ec27421500a5b52072b202c56fcdd618 --- qcom/sdxlemur-blsp.dtsi | 545 ++++++++++++++++++++++ qcom/sdxlemur-pinctrl.dtsi | 903 +++++++++++++++++++++++++++++++++++++ qcom/sdxlemur.dtsi | 3 +- 3 files changed, 1450 insertions(+), 1 deletion(-) create mode 100644 qcom/sdxlemur-blsp.dtsi diff --git a/qcom/sdxlemur-blsp.dtsi b/qcom/sdxlemur-blsp.dtsi new file mode 100644 index 000000000000..997db6b37078 --- /dev/null +++ b/qcom/sdxlemur-blsp.dtsi @@ -0,0 +1,545 @@ +#include "sdxlemur-pinctrl.dtsi" + +/ { + aliases { + i2c1 = &i2c_1; + i2c2 = &i2c_2; + i2c3 = &i2c_3; + i2c4 = &i2c_4; + i2c5 = &i2c_5; + i2c6 = &i2c_6; + i2c7 = &i2c_7; + spi1 = &spi_1; + spi2 = &spi_2; + spi3 = &spi_3; + spi4 = &spi_4; + }; +}; + +&soc { + dma_blsp1: qcom,sps-dma@804000 { /* BLSP1 */ + #dma-cells = <4>; + compatible = "qcom,sps-dma"; + reg = <0x804000 0x23000>; + interrupts = <0 58 IRQ_TYPE_LEVEL_HIGH>; + qcom,summing-threshold = <0x10>; + }; + + i2c_1: i2c@835000 { /* BLSP1 QUP1: GPIO: 2,3 */ + compatible = "qcom,i2c-msm-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x835000 0x600>; + reg-names = "qup_phys_addr"; + interrupt-names = "qup_irq"; + interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dma_blsp1 8 64 0x20000020 0x20>, + <&dma_blsp1 9 32 0x20000020 0x20>; + dma-names = "tx", "rx"; + qcom,master-id = <3>; + qcom,clk-freq-out = <400000>; + qcom,clk-freq-in = <19200000>; + clock-names = "iface_clk", "core_clk"; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>; + pinctrl-names = "i2c_active", "i2c_sleep"; + pinctrl-0 = <&i2c_1_active>; + pinctrl-1 = <&i2c_1_sleep>; + status = "disabled"; + }; + + i2c_2: i2c@836000 { /* BLSP1 QUP2: GPIO: 6,7 */ + compatible = "qcom,i2c-msm-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x836000 0x600>; + reg-names = "qup_phys_addr"; + interrupt-names = "qup_irq"; + interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dma_blsp1 10 64 0x20000020 0x20>, + <&dma_blsp1 11 32 0x20000020 0x20>; + dma-names = "tx", "rx"; + qcom,master-id = <3>; + qcom,clk-freq-out = <400000>; + qcom,clk-freq-in = <19200000>; + clock-names = "iface_clk", "core_clk"; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; + pinctrl-names = "i2c_active", "i2c_sleep"; + pinctrl-0 = <&i2c_2_active>; + pinctrl-1 = <&i2c_2_sleep>; + status = "disabled"; + }; + + i2c_3: i2c@837000 { /* BLSP1 QUP3: GPIO: 10,11 */ + compatible = "qcom,i2c-msm-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x837000 0x600>; + reg-names = "qup_phys_addr"; + interrupt-names = "qup_irq"; + interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dma_blsp1 12 64 0x20000020 0x20>, + <&dma_blsp1 13 32 0x20000020 0x20>; + dma-names = "tx", "rx"; + qcom,master-id = <3>; + qcom,clk-freq-out = <400000>; + qcom,clk-freq-in = <19200000>; + clock-names = "iface_clk", "core_clk"; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>; + pinctrl-names = "i2c_active", "i2c_sleep"; + pinctrl-0 = <&i2c_3_active>; + pinctrl-1 = <&i2c_3_sleep>; + status = "disabled"; + }; + + i2c_4: i2c@838000 { /* BLSP1 QUP4: GPIO: 84,85 */ + compatible = "qcom,i2c-msm-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x838000 0x600>; + reg-names = "qup_phys_addr"; + interrupt-names = "qup_irq"; + interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dma_blsp1 14 64 0x20000020 0x20>, + <&dma_blsp1 15 32 0x20000020 0x20>; + dma-names = "tx", "rx"; + qcom,master-id = <3>; + qcom,clk-freq-out = <400000>; + qcom,clk-freq-in = <19200000>; + clock-names = "iface_clk", "core_clk"; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>; + pinctrl-names = "i2c_active", "i2c_sleep"; + pinctrl-0 = <&i2c_4_active>; + pinctrl-1 = <&i2c_4_sleep>; + status = "disabled"; + }; + + i2c_5: i2c@835000 { /* BLSP1 QUP1: GPIO: 82,83 */ + compatible = "qcom,i2c-msm-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x835000 0x600>; + reg-names = "qup_phys_addr"; + interrupt-names = "qup_irq"; + interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dma_blsp1 8 64 0x20000020 0x20>, + <&dma_blsp1 9 32 0x20000020 0x20>; + dma-names = "tx", "rx"; + qcom,master-id = <3>; + qcom,clk-freq-out = <400000>; + qcom,clk-freq-in = <19200000>; + clock-names = "iface_clk", "core_clk"; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>; + pinctrl-names = "i2c_active", "i2c_sleep"; + pinctrl-0 = <&i2c_5_active>; + pinctrl-1 = <&i2c_5_sleep>; + status = "disabled"; + }; + + i2c_6: i2c@836000 { /* BLSP1 QUP2: GPIO: 65,66 */ + compatible = "qcom,i2c-msm-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x836000 0x600>; + reg-names = "qup_phys_addr"; + interrupt-names = "qup_irq"; + interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dma_blsp1 10 64 0x20000020 0x20>, + <&dma_blsp1 11 32 0x20000020 0x20>; + dma-names = "tx", "rx"; + qcom,master-id = <3>; + qcom,clk-freq-out = <400000>; + qcom,clk-freq-in = <19200000>; + clock-names = "iface_clk", "core_clk"; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>; + pinctrl-names = "i2c_active", "i2c_sleep"; + pinctrl-0 = <&i2c_6_active>; + pinctrl-1 = <&i2c_6_sleep>; + status = "disabled"; + }; + + i2c_7: i2c@838000 { /* BLSP1 QUP4 GPIO: 18,19 */ + compatible = "qcom,i2c-msm-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x838000 0x600>; + reg-names = "qup_phys_addr"; + interrupt-names = "qup_irq"; + interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&dma_blsp1 14 64 0x20000020 0x20>, + <&dma_blsp1 15 32 0x20000020 0x20>; + dma-names = "tx", "rx"; + qcom,master-id = <3>; + qcom,clk-freq-out = <400000>; + qcom,clk-freq-in = <19200000>; + clock-names = "iface_clk", "core_clk"; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>; + pinctrl-names = "i2c_active", "i2c_sleep"; + pinctrl-0 = <&i2c_7_active>; + pinctrl-1 = <&i2c_7_sleep>; + status = "disabled"; + }; + + spi_1: spi@835000 { /* BLSP1 QUP1: GPIO: 80,81,82,83 */ + compatible = "qcom,spi-qup-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "spi_physical", "spi_bam_physical"; + reg = <0x835000 0x600>, + <0x804000 0x23000>; + interrupt-names = "spi_irq", "spi_bam_irq"; + interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>, + <0 58 IRQ_TYPE_LEVEL_HIGH>; + spi-max-frequency = <50000000>; + qcom,use-bam; + qcom,ver-reg-exists; + qcom,bam-consumer-pipe-index = <8>; + qcom,bam-producer-pipe-index = <9>; + qcom,master-id = <3>; + qcom,use-pinctrl; + pinctrl-names = "spi_default", "spi_sleep"; + pinctrl-0 = <&spi_1_active>; + pinctrl-1 = <&spi_1_sleep>; + clock-names = "iface_clk", "core_clk"; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>; + status = "disabled"; + }; + + spi_2: spi@836000 { /* BLSP1 QUP2: GPIO: 4,5,6,7 */ + compatible = "qcom,spi-qup-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "spi_physical", "spi_bam_physical"; + reg = <0x836000 0x600>, + <0x804000 0x23000>; + interrupt-names = "spi_irq", "spi_bam_irq"; + interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>, + <0 58 IRQ_TYPE_LEVEL_HIGH>; + spi-max-frequency = <50000000>; + qcom,use-bam; + qcom,ver-reg-exists; + qcom,bam-consumer-pipe-index = <10>; + qcom,bam-producer-pipe-index = <11>; + qcom,master-id = <3>; + qcom,use-pinctrl; + pinctrl-names = "spi_default", "spi_sleep"; + pinctrl-0 = <&spi_2_active>; + pinctrl-1 = <&spi_2_sleep>; + clock-names = "iface_clk", "core_clk"; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>; + status = "disabled"; + }; + + spi_3: spi@837000 { /* BLSP1 QUP3: GPIO: 8,9,10,11 */ + compatible = "qcom,spi-qup-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "spi_physical", "spi_bam_physical"; + reg = <0x837000 0x600>, + <0x804000 0x23000>; + interrupt-names = "spi_irq", "spi_bam_irq"; + interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>, + <0 58 IRQ_TYPE_LEVEL_HIGH>; + spi-max-frequency = <50000000>; + qcom,use-bam; + qcom,ver-reg-exists; + qcom,bam-consumer-pipe-index = <12>; + qcom,bam-producer-pipe-index = <13>; + qcom,master-id = <3>; + qcom,use-pinctrl; + pinctrl-names = "spi_default", "spi_sleep"; + pinctrl-0 = <&spi_3_active>; + pinctrl-1 = <&spi_3_sleep>; + clock-names = "iface_clk", "core_clk"; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>; + status = "disabled"; + }; + + spi_4: spi@838000 { /* BLSP1 QUP4: GPIO: 16,17,18,19 */ + compatible = "qcom,spi-qup-v2"; + #address-cells = <1>; + #size-cells = <0>; + reg-names = "spi_physical", "spi_bam_physical"; + reg = <0x838000 0x600>, + <0x804000 0x23000>; + interrupt-names = "spi_irq", "spi_bam_irq"; + interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>, + <0 58 IRQ_TYPE_LEVEL_HIGH>; + spi-max-frequency = <50000000>; + qcom,use-bam; + qcom,ver-reg-exists; + qcom,bam-consumer-pipe-index = <14>; + qcom,bam-producer-pipe-index = <15>; + qcom,master-id = <3>; + qcom,use-pinctrl; + pinctrl-names = "spi_default", "spi_sleep"; + pinctrl-0 = <&spi_4_active>; + pinctrl-1 = <&spi_4_sleep>; + clock-names = "iface_clk", "core_clk"; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>; + status = "disabled"; + }; + + blsp1_uart1a_hs: uarta@82f000 { /* BLSP1 UART1: GPIO: 0,1,2,3 */ + compatible = "qcom,msm-hsuart-v14"; + reg-names = "core_mem", "bam_mem"; + reg = <0x82f000 0x200>, + <0x80400 0x23000>; + interrupt-names = "core_irq", "bam_irq", "wakeup_irq"; + #address-cells = <0>; + interrupt-parent = <&blsp1_uart1a_hs>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 24 IRQ_TYPE_LEVEL_HIGH + 1 &intc 0 58 IRQ_TYPE_LEVEL_HIGH + 2 &tlmm 1 IRQ_TYPE_LEVEL_HIGH>; + + qcom,inject-rx-on-wakeup; + qcom,rx-char-to-inject = <0xfd>; + + qcom,bam-tx-ep-pipe-index = <0>; + qcom,bam-rx-ep-pipe-index = <1>; + + clock-names = "iface_clk", "core_clk"; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_UART1_APPS_CLK>; + pinctrl-names = "sleep", "default"; + pinctrl-0 = <&blsp1_uart1a_tx_sleep>, + <&blsp1_uart1a_rxcts_sleep>, <&blsp1_uart1a_rfr_sleep>; + pinctrl-1 = <&blsp1_uart1a_tx_active>, + <&blsp1_uart1a_rxcts_active>, + <&blsp1_uart1a_rfr_active>; + + interconnect-names = "blsp-ddr"; + interconnects = <&system_noc MASTER_BLSP_1 &mc_virt SLAVE_EBI1>; + status = "disabled"; + }; + + blsp1_uart1b_hs: uartb@82f000 { /* BLSP1 UART1: GPIO: 48,49,80,81 */ + compatible = "qcom,msm-hsuart-v14"; + reg-names = "core_mem", "bam_mem"; + reg = <0x82f000 0x200>, + <0x80400 0x23000>; + interrupt-names = "core_irq", "bam_irq", "wakeup_irq"; + #address-cells = <0>; + interrupt-parent = <&blsp1_uart1b_hs>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 24 IRQ_TYPE_LEVEL_HIGH + 1 &intc 0 58 IRQ_TYPE_LEVEL_HIGH + 2 &tlmm 49 IRQ_TYPE_LEVEL_HIGH>; + + qcom,inject-rx-on-wakeup; + qcom,rx-char-to-inject = <0xfd>; + + qcom,bam-tx-ep-pipe-index = <0>; + qcom,bam-rx-ep-pipe-index = <1>; + + clock-names = "iface_clk", "core_clk"; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_UART1_APPS_CLK>; + pinctrl-names = "sleep", "default"; + pinctrl-0 = <&blsp1_uart1b_tx_sleep>, + <&blsp1_uart1b_rxcts_sleep>, <&blsp1_uart1b_rfr_sleep>; + pinctrl-1 = <&blsp1_uart1b_tx_active>, + <&blsp1_uart1b_rxcts_active>, + <&blsp1_uart1b_rfr_active>; + + interconnect-names = "blsp-ddr"; + interconnects = <&system_noc MASTER_BLSP_1 &mc_virt SLAVE_EBI1>; + status = "disabled"; + }; + + blsp1_uart2a_hs: uarta@830000 { /* BLSP1 UART2: GPIO: 4,5,6,7 */ + compatible = "qcom,msm-hsuart-v14"; + reg-names = "core_mem", "bam_mem"; + reg = <0x830000 0x200>, + <0x80400 0x23000>; + interrupt-names = "core_irq", "bam_irq", "wakeup_irq"; + #address-cells = <0>; + interrupt-parent = <&blsp1_uart2a_hs>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 25 IRQ_TYPE_LEVEL_HIGH + 1 &intc 0 58 IRQ_TYPE_LEVEL_HIGH + 2 &tlmm 5 IRQ_TYPE_LEVEL_HIGH>; + + qcom,inject-rx-on-wakeup; + qcom,rx-char-to-inject = <0xfd>; + + qcom,bam-tx-ep-pipe-index = <2>; + qcom,bam-rx-ep-pipe-index = <3>; + + clock-names = "iface_clk", "core_clk"; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_UART1_APPS_CLK>; + pinctrl-names = "sleep", "default"; + pinctrl-0 = <&blsp1_uart2a_tx_sleep>, + <&blsp1_uart2a_rxcts_sleep>, <&blsp1_uart2a_rfr_sleep>; + pinctrl-1 = <&blsp1_uart2a_tx_active>, + <&blsp1_uart2a_rxcts_active>, + <&blsp1_uart2a_rfr_active>; + + interconnect-names = "blsp-ddr"; + interconnects = <&system_noc MASTER_BLSP_1 &mc_virt SLAVE_EBI1>; + status = "disabled"; + }; + + blsp1_uart2b_hs: uartb@830000 { /* BLSP1 UART2: GPIO: 63,64,65,66 */ + compatible = "qcom,msm-hsuart-v14"; + reg-names = "core_mem", "bam_mem"; + reg = <0x830000 0x200>, + <0x80400 0x23000>; + interrupt-names = "core_irq", "bam_irq", "wakeup_irq"; + #address-cells = <0>; + interrupt-parent = <&blsp1_uart2b_hs>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 25 IRQ_TYPE_LEVEL_HIGH + 1 &intc 0 58 IRQ_TYPE_LEVEL_HIGH + 2 &tlmm 64 IRQ_TYPE_LEVEL_HIGH>; + + qcom,inject-rx-on-wakeup; + qcom,rx-char-to-inject = <0xfd>; + + qcom,bam-tx-ep-pipe-index = <2>; + qcom,bam-rx-ep-pipe-index = <3>; + + clock-names = "iface_clk", "core_clk"; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_UART1_APPS_CLK>; + pinctrl-names = "sleep", "default"; + pinctrl-0 = <&blsp1_uart2b_tx_sleep>,<&blsp1_uart2b_rx_sleep>, + <&blsp1_uart2b_cts_sleep>, <&blsp1_uart2b_rfr_sleep>; + pinctrl-1 = <&blsp1_uart2b_tx_active>, + <&blsp1_uart2b_rxcts_active>, + <&blsp1_uart2b_rfr_active>; + + interconnect-names = "blsp-ddr"; + interconnects = <&system_noc MASTER_BLSP_1 &mc_virt SLAVE_EBI1>; + status = "disabled"; + }; + + blsp1_uart3_hs: uart@831000 { /* BLSP1 UART3: GPIO: 8,9,10,11 */ + compatible = "qcom,msm-hsuart-v14"; + reg-names = "core_mem", "bam_mem"; + reg = <0x831000 0x200>, + <0x80400 0x23000>; + interrupt-names = "core_irq", "bam_irq", "wakeup_irq"; + #address-cells = <0>; + interrupt-parent = <&blsp1_uart3_hs>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 26 IRQ_TYPE_LEVEL_HIGH + 1 &intc 0 58 IRQ_TYPE_LEVEL_HIGH + 2 &tlmm 9 IRQ_TYPE_LEVEL_HIGH>; + + qcom,inject-rx-on-wakeup; + qcom,rx-char-to-inject = <0xfd>; + + qcom,bam-tx-ep-pipe-index = <4>; + qcom,bam-rx-ep-pipe-index = <5>; + + clock-names = "iface_clk", "core_clk"; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_UART1_APPS_CLK>; + pinctrl-names = "sleep", "default"; + pinctrl-0 = <&blsp1_uart3_tx_sleep>, + <&blsp1_uart3_rxcts_sleep>, <&blsp1_uart3_rfr_sleep>; + pinctrl-1 = <&blsp1_uart3_tx_active>, + <&blsp1_uart3_rxcts_active>, + <&blsp1_uart3_rfr_active>; + + interconnect-names = "blsp-ddr"; + interconnects = <&system_noc MASTER_BLSP_1 &mc_virt SLAVE_EBI1>; + status = "disabled"; + }; + + blsp1_uart4a_hs: uarta@832000 { /* BLSP1 UART4: GPIO: 22,23,48,49 */ + compatible = "qcom,msm-hsuart-v14"; + reg-names = "core_mem", "bam_mem"; + reg = <0x832000 0x200>, + <0x80400 0x23000>; + interrupt-names = "core_irq", "bam_irq", "wakeup_irq"; + #address-cells = <0>; + interrupt-parent = <&blsp1_uart4a_hs>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 27 IRQ_TYPE_LEVEL_HIGH + 1 &intc 0 58 IRQ_TYPE_LEVEL_HIGH + 2 &tlmm 49 IRQ_TYPE_LEVEL_HIGH>; + + qcom,inject-rx-on-wakeup; + qcom,rx-char-to-inject = <0xfd>; + + qcom,bam-tx-ep-pipe-index = <6>; + qcom,bam-rx-ep-pipe-index = <7>; + + clock-names = "iface_clk", "core_clk"; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_UART1_APPS_CLK>; + pinctrl-names = "sleep", "default"; + pinctrl-0 = <&blsp1_uart4a_tx_sleep>, + <&blsp1_uart4a_rxcts_sleep>, <&blsp1_uart4a_rfr_sleep>; + pinctrl-1 = <&blsp1_uart4a_tx_active>, + <&blsp1_uart4a_rxcts_active>, + <&blsp1_uart4a_rfr_active>; + + interconnect-names = "blsp-ddr"; + interconnects = <&system_noc MASTER_BLSP_1 &mc_virt SLAVE_EBI1>; + status = "disabled"; + }; + + blsp1_uart4b_hs: uartb@832000 { /* BLSP1 UART4: GPIO: 16,17,18,19 */ + compatible = "qcom,msm-hsuart-v14"; + reg-names = "core_mem", "bam_mem"; + reg = <0x832000 0x200>, + <0x80400 0x23000>; + interrupt-names = "core_irq", "bam_irq", "wakeup_irq"; + #address-cells = <0>; + interrupt-parent = <&blsp1_uart4b_hs>; + interrupts = <0 1 2>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc 0 27 IRQ_TYPE_LEVEL_HIGH + 1 &intc 0 58 IRQ_TYPE_LEVEL_HIGH + 2 &tlmm 17 IRQ_TYPE_LEVEL_HIGH>; + + qcom,inject-rx-on-wakeup; + qcom,rx-char-to-inject = <0xfd>; + + qcom,bam-tx-ep-pipe-index = <6>; + qcom,bam-rx-ep-pipe-index = <7>; + + clock-names = "iface_clk", "core_clk"; + clocks = <&gcc GCC_BLSP1_AHB_CLK>, + <&gcc GCC_BLSP1_UART1_APPS_CLK>; + pinctrl-names = "sleep", "default"; + pinctrl-0 = <&blsp1_uart4b_tx_sleep>, + <&blsp1_uart4b_rxcts_sleep>, <&blsp1_uart4b_rfr_sleep>; + pinctrl-1 = <&blsp1_uart4b_tx_active>, + <&blsp1_uart4b_rxcts_active>, + <&blsp1_uart4b_rfr_active>; + + interconnect-names = "blsp-ddr"; + interconnects = <&system_noc MASTER_BLSP_1 &mc_virt SLAVE_EBI1>; + status = "disabled"; + }; + +}; diff --git a/qcom/sdxlemur-pinctrl.dtsi b/qcom/sdxlemur-pinctrl.dtsi index 771cf1df3a0f..fde920065f0b 100644 --- a/qcom/sdxlemur-pinctrl.dtsi +++ b/qcom/sdxlemur-pinctrl.dtsi @@ -93,5 +93,908 @@ }; }; }; + + i2c_1 { + i2c_1_active: i2c_1_active { + mux { + pins = "gpio2", "gpio3"; + function = "blsp_i2c1"; + }; + + config { + pins = "gpio2", "gpio3"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + i2c_1_sleep: i2c_1_sleep { + mux { + pins = "gpio2", "gpio3"; + function = "gpio"; + }; + + config { + pins = "gpio2", "gpio3"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + i2c_2 { + i2c_2_active: i2c_2_active { + mux { + pins = "gpio6", "gpio7"; + function = "blsp_i2c2"; + }; + + config { + pins = "gpio6", "gpio7"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + i2c_2_sleep: i2c_2_sleep { + mux { + pins = "gpio6", "gpio7"; + function = "gpio"; + }; + + config { + pins = "gpio6", "gpio7"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + i2c_3 { + i2c_3_active: i2c_3_active { + mux { + pins = "gpio10", "gpio11"; + function = "blsp_i2c3"; + }; + + config { + pins = "gpio10", "gpio11"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + i2c_3_sleep: i2c_3_sleep { + mux { + pins = "gpio10", "gpio11"; + function = "gpio"; + }; + + config { + pins = "gpio10", "gpio11"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + i2c_4 { + i2c_4_active: i2c_4_active { + mux { + pins = "gpio84", "gpio85"; + function = "blsp_i2c4"; + }; + + config { + pins = "gpio84", "gpio85"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + i2c_4_sleep: i2c_4_sleep { + mux { + pins = "gpio84", "gpio85"; + function = "gpio"; + }; + + config { + pins = "gpio84", "gpio85"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + i2c_5 { + i2c_5_active: i2c_5_active { + mux { + pins = "gpio82", "gpio83"; + function = "blsp_i2c1"; + }; + + config { + pins = "gpio82", "gpio83"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + i2c_5_sleep: i2c_5_sleep { + mux { + pins = "gpio82", "gpio83"; + function = "gpio"; + }; + + config { + pins = "gpio82", "gpio83"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + i2c_6 { + i2c_6_active: i2c_6_active { + mux { + pins = "gpio65", "gpio66"; + function = "blsp_i2c2"; + }; + + config { + pins = "gpio65", "gpio66"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + i2c_6_sleep: i2c_6_sleep { + mux { + pins = "gpio65", "gpio66"; + function = "gpio"; + }; + + config { + pins = "gpio65", "gpio66"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + i2c_7 { + i2c_7_active: i2c_7_active { + mux { + pins = "gpio18", "gpio19"; + function = "blsp_i2c4"; + }; + + config { + pins = "gpio18", "gpio19"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + i2c_7_sleep: i2c_7_sleep { + mux { + pins = "gpio18", "gpio19"; + function = "gpio"; + }; + + config { + pins = "gpio18", "gpio19"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + spi_1 { + spi_1_active: spi_1_active { + mux { + pins = "gpio80", "gpio81", + "gpio82", "gpio83"; + function = "blsp_spi1"; + }; + + config { + pins = "gpio80", "gpio81", + "gpio82", "gpio83"; + drive-strength = <6>; + bias-disable; + }; + }; + + spi_1_sleep: spi_1_sleep { + mux { + pins = "gpio80", "gpio81", + "gpio82", "gpio83"; + function = "gpio"; + }; + + config { + pins = "gpio80", "gpio81", + "gpio82", "gpio83"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + spi_2 { + spi_2_active: spi_2_active { + mux { + pins = "gpio4", "gpio5", + "gpio6", "gpio7"; + function = "blsp_spi2"; + }; + + config { + pins = "gpio4", "gpio5", + "gpio6", "gpio7"; + drive-strength = <6>; + bias-disable; + }; + }; + + spi_2_sleep: spi_2_sleep { + mux { + pins = "gpio4", "gpio5", + "gpio6", "gpio7"; + function = "gpio"; + }; + + config { + pins = "gpio4", "gpio5", + "gpio6", "gpio7"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + spi_3 { + spi_3_active: spi_3_active { + mux { + pins = "gpio8", "gpio9", + "gpio10", "gpio11"; + function = "blsp_spi3"; + }; + + config { + pins = "gpio8", "gpio9", + "gpio10", "gpio11"; + drive-strength = <6>; + bias-disable; + }; + }; + + spi_3_sleep: spi_3_sleep { + mux { + pins = "gpio8", "gpio9", + "gpio10", "gpio11"; + function = "gpio"; + }; + + config { + pins = "gpio8", "gpio9", + "gpio10", "gpio11"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + spi_4 { + spi_4_active: spi_4_active { + mux { + pins = "gpio16", "gpio17", + "gpio18", "gpio19"; + function = "blsp_spi4"; + }; + + config { + pins = "gpio16", "gpio17", + "gpio18", "gpio19"; + drive-strength = <6>; + bias-disable; + }; + }; + + spi_4_sleep: spi_4_sleep { + mux { + pins = "gpio16", "gpio17", + "gpio18", "gpio19"; + function = "gpio"; + }; + + config { + pins = "gpio16", "gpio17", + "gpio18", "gpio19"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + blsp1_uart1a: blsp1_uart1a { + blsp1_uart1a_tx_active: blsp1_uart1a_tx_active { + mux { + pins = "gpio0"; + function = "blsp_uart1"; + }; + + config { + pins = "gpio0"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + blsp1_uart1a_rxcts_active: blsp1_uart1a_rxcts_active { + mux { + pins = "gpio1", "gpio2"; + function = "blsp_uart1"; + }; + + config { + pins = "gpio1", "gpio2"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart1a_rfr_active: blsp1_uart1a_rfr_active { + mux { + pins = "gpio3"; + function = "blsp_uart1"; + }; + + config { + pins = "gpio3"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + blsp1_uart1a_tx_sleep: blsp1_uart1a_tx_sleep { + mux { + pins = "gpio0"; + function = "gpio"; + }; + + config { + pins = "gpio0"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + blsp1_uart1a_rxcts_sleep: blsp1_uart1a_rxcts_sleep { + mux { + pins = "gpio1", "gpio2"; + function = "gpio"; + }; + + config { + pins = "gpio1", "gpio2"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart1a_rfr_sleep: blsp1_uart1a_rfr_sleep { + mux { + pins = "gpio3"; + function = "gpio"; + }; + + config { + pins = "gpio3"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + + blsp1_uart1b: blsp1_uart1b { + blsp1_uart1b_tx_active: blsp1b_uart1_tx_active { + mux { + pins = "gpio48"; + function = "blsp_uart1"; + }; + + config { + pins = "gpio48"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + blsp1_uart1b_rxcts_active: blsp1b_uart1_rxcts_active { + mux { + pins = "gpio49", "gpio80"; + function = "blsp_uart1"; + }; + + config { + pins = "gpio49", "gpio80"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart1b_rfr_active: blsp1_uart1b_rfr_active { + mux { + pins = "gpio81"; + function = "blsp_uart1"; + }; + + config { + pins = "gpio81"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + blsp1_uart1b_tx_sleep: blsp1_uart1b_tx_sleep { + mux { + pins = "gpio48"; + function = "gpio"; + }; + + config { + pins = "gpio48"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + blsp1_uart1b_rxcts_sleep: blsp1_uart1b_rxcts_sleep { + mux { + pins = "gpio49", "gpio80"; + function = "gpio"; + }; + + config { + pins = "gpio49", "gpio80"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart1b_rfr_sleep: blsp1b_uart1_rfr_sleep { + mux { + pins = "gpio81"; + function = "gpio"; + }; + + config { + pins = "gpio81"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + blsp1_uart2a: blsp1_uart2a { + blsp1_uart2a_tx_active: blsp1_uart2a_tx_active { + mux { + pins = "gpio4"; + function = "blsp_uart2"; + }; + + config { + pins = "gpio4"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + blsp1_uart2a_rxcts_active: blsp1_uart2a_rxcts_active { + mux { + pins = "gpio5", "gpio6"; + function = "blsp_uart2"; + }; + + config { + pins = "gpio5", "gpio6"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart2a_rfr_active: blsp1_uart2a_rfr_active { + mux { + pins = "gpio7"; + function = "blsp_uart2"; + }; + + config { + pins = "gpio7"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + blsp1_uart2a_tx_sleep: blsp1_uart2a_tx_sleep { + mux { + pins = "gpio4"; + function = "gpio"; + }; + + config { + pins = "gpio4"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + blsp1_uart2a_rxcts_sleep: blsp1_uart2a_rxcts_sleep { + mux { + pins = "gpio5", "gpio6"; + function = "gpio"; + }; + + config { + pins = "gpio5", "gpio6"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart2a_rfr_sleep: blsp1_uart2a_rfr_sleep { + mux { + pins = "gpio7"; + function = "gpio"; + }; + + config { + pins = "gpio7"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + blsp1_uart2b: blsp1_uart2b { + blsp1_uart2b_tx_active: blsp1_uart2b_tx_active { + mux { + pins = "gpio63"; + function = "blsp_uart2"; + }; + + config { + pins = "gpio63"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + blsp1_uart2b_rxcts_active: blsp1_uart2b_rxcts_active { + mux { + pins = "gpio64", "gpio65"; + function = "blsp_uart2"; + }; + + config { + pins = "gpio64", "gpio65"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart2b_rfr_active: blsp1_uart2b_rfr_active { + mux { + pins = "gpio66"; + function = "blsp_uart2"; + }; + + config { + pins = "gpio66"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + blsp1_uart2b_tx_sleep: blsp1_uart2b_tx_sleep { + mux { + pins = "gpio63"; + function = "gpio"; + }; + + config { + pins = "gpio63"; + drive-strength = <2>; + bias-pull-up; + output-high; + }; + }; + + blsp1_uart2b_rx_sleep: blsp1_uart2b_rx_sleep { + mux { + pins = "gpio64"; + function = "gpio"; + }; + + config { + pins = "gpio64"; + drive-strength = <2>; + bias-pull-down; + input-enable; + }; + }; + + blsp1_uart2b_cts_sleep: blsp1_uart2b_cts_sleep { + mux { + pins = "gpio65"; + function = "gpio"; + }; + + config { + pins = "gpio65"; + drive-strength = <2>; + bias-disable; + input-enable; + }; + }; + + + blsp1_uart2b_rfr_sleep: blsp1_uart2b_rfr_sleep { + mux { + pins = "gpio66"; + function = "gpio"; + }; + + config { + pins = "gpio66"; + drive-strength = <2>; + bias-pull-down; + output-low; + }; + }; + }; + + blsp1_uart3: blsp1_uart3 { + blsp1_uart3_tx_active: blsp1_uart3_tx_active { + mux { + pins = "gpio8"; + function = "blsp_uart3"; + }; + + config { + pins = "gpio8"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + blsp1_uart3_rxcts_active: blsp1_uart3_rxcts_active { + mux { + pins = "gpio9", "gpio10"; + function = "blsp_uart3"; + }; + + config { + pins = "gpio9", "gpio10"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart3_rfr_active: blsp1_uart3_rfr_active { + mux { + pins = "gpio11"; + function = "blsp_uart3"; + }; + + config { + pins = "gpio11"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + blsp1_uart3_tx_sleep: blsp1_uart3_tx_sleep { + mux { + pins = "gpio8"; + function = "gpio"; + }; + + config { + pins = "gpio8"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + blsp1_uart3_rxcts_sleep: blsp1_uart3_rxcts_sleep { + mux { + pins = "gpio9", "gpio10"; + function = "gpio"; + }; + + config { + pins = "gpio9", "gpio10"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart3_rfr_sleep: blsp1_uart3_rfr_sleep { + mux { + pins = "gpio11"; + function = "gpio"; + }; + + config { + pins = "gpio11"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + blsp1_uart4a: blsp1_uart4a { + blsp1_uart4a_tx_active: blsp1_uart4a_tx_active { + mux { + pins = "gpio48"; + function = "blsp_uart4"; + }; + + config { + pins = "gpio48"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + blsp1_uart4a_rxcts_active: blsp1_uart4a_rxcts_active { + mux { + pins = "gpio49", "gpio22"; + function = "blsp_uart4"; + }; + + config { + pins = "gpio49", "gpio22"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart4a_rfr_active: blsp1_uart4a_rfr_active { + mux { + pins = "gpio23"; + function = "blsp_uart4"; + }; + + config { + pins = "gpio23"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + blsp1_uart4a_tx_sleep: blsp1_uart4a_tx_sleep { + mux { + pins = "gpio48"; + function = "gpio"; + }; + + config { + pins = "gpio22"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + blsp1_uart4a_rxcts_sleep: blsp1_uart4a_rxcts_sleep { + mux { + pins = "gpio49", "gpio22"; + function = "gpio"; + }; + + config { + pins = "gpio49", "gpio22"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart4a_rfr_sleep: blsp1_uart4a_rfr_sleep { + mux { + pins = "gpio23"; + function = "gpio"; + }; + + config { + pins = "gpio23"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + blsp1_uart4b: blsp1_uart4b { + blsp1_uart4b_tx_active: blsp1_uart4b_tx_active { + mux { + pins = "gpio16"; + function = "blsp_uart4"; + }; + + config { + pins = "gpio16"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + blsp1_uart4b_rxcts_active: blsp1_uart4b_rxcts_active { + mux { + pins = "gpio17", "gpio18"; + function = "blsp_uart4"; + }; + + config { + pins = "gpio17", "gpio18"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart4b_rfr_active: blsp1_uart4b_rfr_active { + mux { + pins = "gpio19"; + function = "blsp_uart4"; + }; + + config { + pins = "gpio19"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + blsp1_uart4b_tx_sleep: blsp1_uart4b_tx_sleep { + mux { + pins = "gpio16"; + function = "gpio"; + }; + + config { + pins = "gpio16"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + blsp1_uart4b_rxcts_sleep: blsp1_uart4b_rxcts_sleep { + mux { + pins = "gpio17", "gpio18"; + function = "gpio"; + }; + + config { + pins = "gpio17", "gpio18"; + drive-strength = <2>; + bias-disable; + }; + }; + + blsp1_uart4b_rfr_sleep: blsp1_uart4b_rfr_sleep { + mux { + pins = "gpio19"; + function = "gpio"; + }; + + config { + pins = "gpio19"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; }; }; diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index a9a6ec23a414..93f175cfad5c 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -376,7 +376,7 @@ serial_uart: serial@831000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; reg = <0x831000 0x200>; - interrupts = <0 26 0>; + interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>; clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; clock-names = "core", "iface"; @@ -678,3 +678,4 @@ #include "sdxlemur-usb.dtsi" #include "sdxlemur-pm.dtsi" #include "sdxlemur-pcie.dtsi" +#include "sdxlemur-blsp.dtsi" From 4a7b1c3334439c010cb4e9f91d51b429e7b6b7fe Mon Sep 17 00:00:00 2001 From: Vipin Deep Kaur Date: Wed, 30 Sep 2020 11:46:08 +0530 Subject: [PATCH 19/88] dt-bindings: spi_qsd: Add documentation of SPI BLSP driver This change adds a documentation of SPI BLSP driver from the 4.19 branch. kernel-4.19 baseline: 'commit b159d5da02b7 ("dt-bindings: Add documentation for SDM660")'. Change-Id: I64177a6323a14aad4269f7825a8258b7ab1c4389 --- bindings/spi/spi_qsd.txt | 106 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 106 insertions(+) create mode 100644 bindings/spi/spi_qsd.txt diff --git a/bindings/spi/spi_qsd.txt b/bindings/spi/spi_qsd.txt new file mode 100644 index 000000000000..8d50dbbc7917 --- /dev/null +++ b/bindings/spi/spi_qsd.txt @@ -0,0 +1,106 @@ +Qualcomm Technologies, Inc. Serial Peripheral Interface (SPI) + +Required properties: +- compatible : Should be "qcom,spi-qup-v2". +- reg : Offset and length of the register regions for the device +- reg-names : Register region names referenced in reg above. + Required register resource entries are: + "spi_physical" : Physical address of controller register blocks. +- interrupts : Interrupt numbers used by this controller +- interrupt-names : Interrupt resource names referenced in interrupts above. + Required interrupt resource entries are: + "spi_irq" : QUP-core interrupt. +- spi-max-frequency : Specifies maximum SPI clock frequency, Units - Hz. + +Required alias: +- The desired bus-number is specified via an alias with the following format + 'spi{n}' where n is the bus number. + +Optional properties: +- qcom,gpio-mosi : GPIO pin number of the MOSI bus line. +- qcom,gpio-miso : GPIO pin number of the MISO bus line. +- qcom,gpio-clk : GPIO pin number of the CLK bus line. +- qcom,gpio-cs0 : GPIO pin number of the chipselect0 bus line. +- qcom,gpio-cs1 : GPIO pin number of the chipselect1 bus line. +- qcom,gpio-cs2 : GPIO pin number of the chipselect2 bus line. +- qcom,gpio-cs3 : GPIO pin number of the chipselect3 bus line. +- qcom,infinite-mode: When missing or set to zero, QUP uses infinite-mode. When + value is non-zero, the value is the number of words in maximum transfer + length. + - qcom,active-only : Vote for core clock when the application processor goes + to active state and remove that vote when it goes to idle state. This flag may + improve service time of first spi request at the expense of power consumption. + When this entry is not present, voting is done by the runtime-pm callbacks. + - qcom,master-id : Master endpoint number used for voting on clocks using the + bus-scaling driver. + - qcom,rt-priority : whether spi message queue is set to run as a realtime task. + With this spi transaction message pump with high (realtime) priority to reduce + the transfer latency on the bus by minimising the delay between a transfer request + - qcom,shared : whether this qup is shared with other ee's + +Optional properties which are required for support of BAM-mode: +- qcom,ver-reg-exists : Boolean. When present, allows driver to verify if HW + version support latest features (e.g. BAM) and then enable them. Should be + removed for legacy HW. +- qcom,use-bam : Boolean. When present, enables BAM-mode. +- qcom,use-pinctrl : Boolean. When present, enables pinctrl frame work to configure GPIO's + instead of existing gpio mux hence gpio entries are no more required if present. +- pinctrl-names : Property must contain "spi_default" and "spi_sleep" if + pinctrl is to be used. + instead of existing gpio mux hence gpio entries are no more required if present. +- qcom,bam-consumer-pipe-index : BAM consumer-pipe index. +- qcom,bam-producer-pipe-index : BAM producer-pipe index. +- reg-names : register region names referenced in reg. + Required register resource for BAM are: + "spi_bam_physical" : Physical address of BAM for this controller. +- interrupt-names : interrupt resource names referenced in interrupts. + Required interrupt resource from BAM are: + "spi_bam_irq" : BAM interrupt used by the controller. + +Optional SPI slave nodes must be children of the SPI master node and contain +the following properties. +- reg: (required) chip-select address of the device. +- compatible : (required) Name of SPI device following generic names. +- spi-max-frequency : (required) Maximum SPI clocking speed of device in Hz +- interrupts : (recommended) Should contain the SPI slave interrupt number + encoded depending on the type of the interrupt controller. +- interrupt-parent : (recommended) The phandle for the interrupt controller + that services interrupts for this device. +- spi-cpol : (optional) Empty property indicating device requires inverse + clock polarity (CPOL) mode +- spi-cpha : (optional) Empty property indicating device requires shifted + clock phase (CPHA) mode +- spi-cs-high : (optional) Empty property indicating device requires + chip select active high + +Example: + aliases { + spi0 = &spi_0; + }; + + spi_0: spi@f9923000 { + compatible = "qcom,spi-qup-v2"; + + reg-names = "spi_physical", "spi_bam_physical"; + reg = <0xf9923000 0x1000>, + <0xf9904000 0x10000>; + interrupt-names = "spi_irq", "spi_bam_irq"; + interrupts = <0 95 0>, <0 238 0>; + + spi-max-frequency = <19200000>; + #address-cells = <1>; + #size-cells = <0>; + qcom,gpio-mosi = <&msmgpio 0 0>; + qcom,gpio-miso = <&msmgpio 1 0>; + qcom,gpio-clk = <&msmgpio 3 0>; + qcom,gpio-cs2 = <&msmgpio 9 0>; + + qcom,infinite-mode = <0>; + qcom,use-bam; + qcom,use-pinctrl; + qcom,bam-consumer-pipe-index = <12>; + qcom,bam-producer-pipe-index = <13>; + qcom,ver-reg-exists; + qcom,master-id = <86>; + qcom,rt-priority; + }; From 0562eef50365b70fce1aa3999576a21abcedd1f8 Mon Sep 17 00:00:00 2001 From: Neeraj Upadhyay Date: Tue, 22 Sep 2020 10:50:23 +0530 Subject: [PATCH 20/88] ARM: dts: msm: Add psci and scm nodes for Yupik Add scm and psci device nodes for Yupic SoC. Change-Id: Iae18d127d2e01234330f77c52b62a051404fd27b --- qcom/yupik.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index b63c9164c569..6fed717806ee 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -23,6 +23,12 @@ aliases { }; + firmware: firmware { + scm { + compatible = "qcom,scm"; + }; + }; + cpus { #address-cells = <2>; #size-cells = <0>; @@ -207,6 +213,11 @@ interrupts = ; }; + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + ipcc_mproc: qcom,ipcc@408000 { compatible = "qcom,ipcc"; reg = <0x408000 0x1000>; From 02ea70bb21f8e17b314f456640dacadbcf1b1ce0 Mon Sep 17 00:00:00 2001 From: Fenglin Wu Date: Wed, 30 Sep 2020 12:58:31 +0800 Subject: [PATCH 21/88] ARM: dts: msm: Add wireless-fw-name property for Shima platforms Add qcom,wireless-fw-name property for Shima platforms to upgrade wireless charger chip firmware correctly. Change-Id: I761592f9c9e53e7b7b1e351d81a8d4be27baa875 --- qcom/shima-idp.dtsi | 1 + qcom/shima-qrd.dtsi | 1 + 2 files changed, 2 insertions(+) diff --git a/qcom/shima-idp.dtsi b/qcom/shima-idp.dtsi index d0a694ca961b..2b369e508e07 100644 --- a/qcom/shima-idp.dtsi +++ b/qcom/shima-idp.dtsi @@ -150,6 +150,7 @@ &battery_charger { qcom,thermal-mitigation = <3000000 1500000 1000000 500000>; + qcom,wireless-fw-name = "idt9412.bin"; }; &qupv3_se10_i2c { diff --git a/qcom/shima-qrd.dtsi b/qcom/shima-qrd.dtsi index fd21a2271113..d3f8f9815750 100644 --- a/qcom/shima-qrd.dtsi +++ b/qcom/shima-qrd.dtsi @@ -190,6 +190,7 @@ 7500000 7000000 6500000 6000000 5500000 5000000 4500000 4000000 3500000 3000000 2500000 2000000 1500000 1000000 500000>; + qcom,wireless-fw-name = "idt9412.bin"; }; &qupv3_se10_i2c { From 0ca570d4870e42ea11d4f584792e3fc152d7091a Mon Sep 17 00:00:00 2001 From: Raghavendra Rao Ananta Date: Thu, 24 Sep 2020 12:29:13 -0700 Subject: [PATCH 22/88] ARM: dts: msm: Vote for DDR BW for MPSS PIL on Lahaina It is possible that the DDR bandwidth requirements are not met during modem SSR. Hence, explicitly vote for DDR turbo frequency during modem PIL. Change-Id: I5134feaf593673beb8bbdafc416814a5d41fb47b --- qcom/lahaina.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/qcom/lahaina.dtsi b/qcom/lahaina.dtsi index 2f48611e3666..c95a6dfe9c44 100644 --- a/qcom/lahaina.dtsi +++ b/qcom/lahaina.dtsi @@ -4425,6 +4425,8 @@ qcom,vdd_mss-uV-uA = ; qcom,proxy-reg-names = "vdd_cx", "vdd_mss"; + interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>; + qcom,firmware-name = "modem"; memory-region = <&pil_modem_mem>; qcom,proxy-timeout-ms = <10000>; From 12f00961f388955b99f68e4de1e2ba7dff257fc8 Mon Sep 17 00:00:00 2001 From: Ritesh Kumar Date: Thu, 24 Sep 2020 17:12:58 +0530 Subject: [PATCH 23/88] ARM: dts: msm: Select 120Hz panel as default on 120Hz shima dts This change adds support to select 120Hz command mode panel as default panel on shima 120Hz IDP/IDPS platform. Change-Id: I2ca4fb9f181ad3b721ce05a4740cf18f4127bddc --- qcom/shima-idp-120fps.dtsi | 4 ++++ qcom/shima-idps-digital-mics-120fps.dtsi | 4 +++- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/qcom/shima-idp-120fps.dtsi b/qcom/shima-idp-120fps.dtsi index 4f6732d3b955..f110f793bbeb 100644 --- a/qcom/shima-idp-120fps.dtsi +++ b/qcom/shima-idp-120fps.dtsi @@ -2,3 +2,7 @@ &soc { }; + +&sde_dsi { + qcom,dsi-default-panel = <&dsi_r66451_amoled_cmd>; +}; diff --git a/qcom/shima-idps-digital-mics-120fps.dtsi b/qcom/shima-idps-digital-mics-120fps.dtsi index 51ccf2dd48fd..976bee956cd7 100644 --- a/qcom/shima-idps-digital-mics-120fps.dtsi +++ b/qcom/shima-idps-digital-mics-120fps.dtsi @@ -3,4 +3,6 @@ &soc { }; - +&sde_dsi { + qcom,dsi-default-panel = <&dsi_r66451_amoled_cmd>; +}; From d0326a2063dac14bd2502b5c98ede67635da6d4b Mon Sep 17 00:00:00 2001 From: Gopala Krishna Nuthaki Date: Mon, 14 Sep 2020 14:46:57 +0530 Subject: [PATCH 24/88] ARM: dts: msm: update modem qmi sennor list for SHIMA Update modem qmi sensor list for SHIMA. Add msm_skin_therm sensor and remove sys_therm2,sdr_mmw_therm in qmi_sensor list for SHIMA. Change-Id: Ia788efd2289cd485210e92e395f29aba14485046 --- qcom/shima-thermal.dtsi | 67 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 67 insertions(+) diff --git a/qcom/shima-thermal.dtsi b/qcom/shima-thermal.dtsi index 400c81e2b65a..fc97b1dddafa 100644 --- a/qcom/shima-thermal.dtsi +++ b/qcom/shima-thermal.dtsi @@ -2,6 +2,23 @@ #include "lahaina-thermal-modem.dtsi" &qmi_tmd { + modem { + modem_current: modem_current { + qcom,qmi-dev-name = "modem_current"; + #cooling-cells = <2>; + }; + + modem_bw_backoff: modem_bw_backoff { + qcom,qmi-dev-name = "modem_bw_backoff"; + #cooling-cells = <2>; + }; + + modem_wlan_bw: modem_wlan_bw { + qcom,qmi-dev-name = "wlan_bw"; + #cooling-cells = <2>; + }; + }; + cdsp { qcom,instance-id = ; @@ -17,6 +34,38 @@ }; }; +&soc { + qmi-ts-sensors { + modem { + qcom,qmi-sensor-names = "pa", + "pa_1", + "qfe_wtr0", + "modem_tsens", + "qfe_mmw0", + "qfe_mmw1", + "qfe_mmw2", + "qfe_mmw3", + "xo_therm", + "qfe_mmw_streamer0", + "qfe_mmw0_mod", + "qfe_mmw1_mod", + "qfe_mmw2_mod", + "qfe_mmw3_mod", + "qfe_ret_pa0", + "qfe_wtr_pa0", + "qfe_wtr_pa1", + "qfe_wtr_pa2", + "qfe_wtr_pa3", + "sys_therm1", + "modem_tsens1", + "mmw_pa1", + "mmw_pa2", + "mmw_pa3", + "msm_skin_therm"; + }; + }; +}; + &cpufreq_hw { qcom,cpu-isolation { compatible = "qcom,cpu-isolate"; @@ -75,6 +124,24 @@ }; &thermal_zones { + /delete-node/ modem-sdr-mmw-usr; + /delete-node/ modem-ambient-usr; + + msm-skin-therm-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_MSM_SKIN)>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + aoss-0-usr { polling-delay-passive = <0>; polling-delay = <0>; From 8c4d819e50522b88094e229186f4d9002e1efb86 Mon Sep 17 00:00:00 2001 From: Gopala Krishna Nuthaki Date: Mon, 14 Sep 2020 15:01:01 +0530 Subject: [PATCH 25/88] dt-bindings: thermal: Add support for bandwidth cooling devices Add support for modem_bw_backoff and wlan_bw cooling devices. Change-Id: I71fd52e7e1e26ab5b9c8ab7e10ca3da3f14734e1 --- bindings/thermal/qti-qmi-cdev.txt | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/bindings/thermal/qti-qmi-cdev.txt b/bindings/thermal/qti-qmi-cdev.txt index 127a9d8caecf..d22547641936 100644 --- a/bindings/thermal/qti-qmi-cdev.txt +++ b/bindings/thermal/qti-qmi-cdev.txt @@ -41,6 +41,9 @@ Subsystem properties: "modem" -> for processor passive cooling device, "modem_current" -> for current limiting device, "modem_bw" -> for bus bandwidth limiting device, + "modem_bw_backoff" -> for bus bandwidth limit device with + absolute bandwidth reduction from max bandwidth + in 100mbbs resolution, "vbatt_low" -> BCL vbat mitigation device, "mmw0" -> Millimeter wave limiting device 0, "mmw1" -> Millimeter wave limiting device 1, @@ -53,6 +56,7 @@ Subsystem properties: "mmw_skin3" -> MMW skin mitigation device3, "cpr_cold" -> for cpr restriction, "wlan" -> for modem wlan mitigation device, + "wlan_bw" -> for bus bandwidth limiting device, "cdsp_sw" -> for CDSP DCVS mitigation device, "cdsp_hw" -> for CDSP hardware mitigation device, "mmw_skin0_dsc" -> DSC based MMW skin mitigation From adbcb4d69ee738e2699d9287bef8dea4d956a974 Mon Sep 17 00:00:00 2001 From: Gopala Krishna Nuthaki Date: Mon, 14 Sep 2020 15:10:13 +0530 Subject: [PATCH 26/88] dt-bindings: thermal: Add support for modem skin sensor via QMI Add support to expose msm_skin_therm sensor via QMI. Change-Id: I3ee24239314fb25d19267b4199fa2c137a51ffb7 --- bindings/thermal/qti-qmi-sensor.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/bindings/thermal/qti-qmi-sensor.txt b/bindings/thermal/qti-qmi-sensor.txt index 5c8f0bfc7e80..b9a703cf1a14 100644 --- a/bindings/thermal/qti-qmi-sensor.txt +++ b/bindings/thermal/qti-qmi-sensor.txt @@ -61,6 +61,7 @@ Subsystem properties: 28. mmw_pa2 29. mmw_pa3 30. sdr_mmw_therm + 31. msm_skin_therm Example: From 4d515a168df4dbbe20715782c6e1fc75bf37da6a Mon Sep 17 00:00:00 2001 From: Manikandan Mohan Date: Fri, 25 Sep 2020 22:26:57 -0700 Subject: [PATCH 27/88] ARM: dts: msm: Update CNSS node for BT GPIO config QCA6490 requires synchronization between BT and WLAN GPIOs for PMU power up. Update CNSS device tree node for BT GPIO config. Change-Id: I0cd7050dad499378ec6d2bcfbe9d78f4a79a3384 --- bindings/cnss/cnss-wlan.txt | 3 +++ qcom/lahaina.dtsi | 1 + 2 files changed, 4 insertions(+) diff --git a/bindings/cnss/cnss-wlan.txt b/bindings/cnss/cnss-wlan.txt index 02d983d74138..c1de42da51fb 100644 --- a/bindings/cnss/cnss-wlan.txt +++ b/bindings/cnss/cnss-wlan.txt @@ -87,6 +87,9 @@ Optional properties: regulator used in internal power amplifier for QCA6490 - cnss-enable-self-recovery: Boolean property to enable self recovery when recovery is trigeered with reason link down. + - qcom,bt-en-gpio: QCA6490 requires synchronization for BT and WLAN GPIO + enable to resolve PMU power up issues. Provide BT GPIO using + this config param. Example: diff --git a/qcom/lahaina.dtsi b/qcom/lahaina.dtsi index 182e5335c125..adae4ce8f80d 100644 --- a/qcom/lahaina.dtsi +++ b/qcom/lahaina.dtsi @@ -5352,6 +5352,7 @@ <0xb2e5510 0x690>; reg-names = "smmu_iova_ipa", "tcs_cmd"; wlan-en-gpio = <&tlmm 64 0>; + qcom,bt-en-gpio = <&tlmm 65 0>; pinctrl-names = "wlan_en_active", "wlan_en_sleep"; pinctrl-0 = <&cnss_wlan_en_active>; pinctrl-1 = <&cnss_wlan_en_sleep>; From 4bd7a12e8e0bfda12dbaf88b1aff1bf8f2d93a38 Mon Sep 17 00:00:00 2001 From: Naveen Yadav Date: Wed, 30 Sep 2020 17:43:03 +0530 Subject: [PATCH 28/88] ARM: dts: msm: Add debugcc and APSSCC clock nodes for sdxlemur Add debug clock controller node to use the debug clock controller driver for measuring the clocks, also add MCCC and CPUCC device phandle reference to debugcc node to map register space for the apcs diag register. Update apsscc clock node to enable cpu driver for sdxlemur. Change-Id: Iba7b60463462ab8e121b6a72323f1d9a116fe411 --- qcom/sdxlemur.dtsi | 39 +++++++++++++++++++++++++++++++++++---- 1 file changed, 35 insertions(+), 4 deletions(-) diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index de55954f16c2..e0304362d09d 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -6,6 +6,7 @@ #include #include #include +#include / { #address-cells = <1>; @@ -373,6 +374,26 @@ #reset-cells = <1>; }; + clock_apsscc: syscon@17811000 { + compatible = "syscon"; + reg = <0x17811000 0x20>; + }; + + clock_mccc: syscon@90b0000 { + compatible = "syscon"; + reg = <0x90b0000 0x54>; + }; + + clock_debugcc: qcom,cc-debug { + compatible = "qcom,sdxlemur-debugcc"; + qcom,gcc = <&gcc>; + qcom,apsscc = <&clock_apsscc>; + qcom,mccc = <&clock_mccc>; + clock-names = "xo_clk_src"; + clocks = <&rpmhcc RPMH_CXO_CLK>; + #clock-cells = <1>; + }; + serial_uart: serial@831000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; reg = <0x831000 0x200>; @@ -403,10 +424,20 @@ status = "disabled"; }; - apsscc: clock-controller@17808000 { - compatible = "qcom,dummycc"; - clock-output-names = "apsscc_clocks"; - #clock-cells = <1>; + apsscc: clock-controller@17808100 { + compatible = "qcom,sdxlemur-apsscc"; + clocks = <&rpmhcc RPMH_CXO_CLK_A>, <&gcc GPLL0_OUT_EVEN>; + clock-names = "bi_tcxo_ao", "gpll0_out_even"; + reg = <0x17810008 0x16>, + <0x17808100 0x100>; + reg-names = "apcs_cmd", "apcs_pll"; + vdd-lucid-pll-supply = <&VDD_CX_LEVEL_AO>; + cpu-vdd-supply = <&VDD_CX_LEVEL_AO>; + qcom,speed0-bin-v0 = + < 345600000 RPMH_REGULATOR_LEVEL_LOW_SVS>, + < 576000000 RPMH_REGULATOR_LEVEL_SVS>, + < 1094400000 RPMH_REGULATOR_LEVEL_NOM>, + < 1497600000 RPMH_REGULATOR_LEVEL_TURBO>; #reset-cells = <1>; }; From 1821f82015638579535f5ad297e6de3c02e66551 Mon Sep 17 00:00:00 2001 From: Mahesh Kumar Sharma Date: Thu, 24 Sep 2020 15:13:50 -0700 Subject: [PATCH 29/88] ARM: dts: msm: add WL_EN entry in BT node Add WL_EN GPIO entry in BT device tree node to handle AON LDO fully discharge issue. Change-Id: I526d42fb58fef7942280c4fc06ded5a47f7277dd --- bindings/bluetooth/btpower.txt | 2 ++ qcom/lahaina.dtsi | 1 + 2 files changed, 3 insertions(+) diff --git a/bindings/bluetooth/btpower.txt b/bindings/bluetooth/btpower.txt index 8b7d10bda475..391361eef201 100644 --- a/bindings/bluetooth/btpower.txt +++ b/bindings/bluetooth/btpower.txt @@ -11,6 +11,7 @@ Required properties: qcom,qca6390 qcom,qca6490 - qcom,bt-reset-gpio: GPIO pin to bring BT Controller out of reset + - qcom,wl-reset-gpio: GPIO pin for WL_EN toggle Optional properties: - qcom,bt-vdd-pa-supply: Bluetooth VDD PA regulator handle @@ -38,6 +39,7 @@ Example: pinctrl-names = "default"; pinctrl-0 = <&bt_en_sleep>; qcom,bt-reset-gpio = <&tlmm 21 0>; /* BT_EN */ + qcom,wl-reset-gpio = <&tlmm 64 0>; /* WL_EN */ qcom,bt-vdd-aon-supply = <&pm8150_s6>; qcom,bt-vdd-dig-supply = <&pm8009_s2>; qcom,bt-vdd-rfa1-supply = <&pm8150_s5>; diff --git a/qcom/lahaina.dtsi b/qcom/lahaina.dtsi index 182e5335c125..fcf628bce58b 100644 --- a/qcom/lahaina.dtsi +++ b/qcom/lahaina.dtsi @@ -5615,6 +5615,7 @@ /* offset=(0xC8*6) + (0x10*2) */ qcom,tcs_offset_ipa = <0x4D0>; qcom,bt-reset-gpio = <&tlmm 65 0>; /* BT_EN */ + qcom,wl-reset-gpio = <&tlmm 64 0>; /* WL_EN */ qcom,bt-sw-ctrl-gpio = <&tlmm 153 0>; /* SW_CTRL */ qcom,bt-vdd-aon-supply = <&S11B>; qcom,bt-vdd-dig-supply = <&S11B>; From 830398b379d8efe26ad233746ae832fb553081b8 Mon Sep 17 00:00:00 2001 From: Ritesh Kumar Date: Mon, 5 Oct 2020 13:10:23 +0530 Subject: [PATCH 30/88] ARM: dts: msm: Add focaltech touch support on holi cdp This change adds focaltech touch support on holi cdp which is needed for 120Hz video and command mode panels. Change-Id: I03cb8927faeec77cf0af9268d3000f5b3ff75fc3 --- qcom/holi-cdp.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/qcom/holi-cdp.dtsi b/qcom/holi-cdp.dtsi index 5aba97afae07..7cbc0ae32d3c 100644 --- a/qcom/holi-cdp.dtsi +++ b/qcom/holi-cdp.dtsi @@ -232,6 +232,27 @@ panel = <&dsi_rm69299_visionox_amoled_video &dsi_rm69299_visionox_amoled_cmd>; }; + + focaltech@38 { + compatible = "focaltech,fts_ts"; + reg = <0x38>; + interrupt-parent = <&tlmm>; + interrupts = <22 0x2008>; + focaltech,reset-gpio = <&tlmm 21 0x00>; + focaltech,irq-gpio = <&tlmm 22 0x2008>; + focaltech,max-touch-number = <5>; + focaltech,display-coords = <0 0 1080 2340>; + + vdd-supply = <&L6A>; + + pinctrl-names = "pmx_ts_active", "pmx_ts_suspend", + "pmx_ts_release"; + pinctrl-0 = <&ts_active>; + pinctrl-1 = <&ts_int_suspend &ts_reset_suspend>; + pinctrl-2 = <&pmx_ts_release>; + + panel = <&dsi_r66451_amoled_cmd &dsi_r66451_amoled_video>; + }; }; #include "camera/holi-camera-sensor-cdp.dtsi" From fc3b5de115288ee4a86a41e09f9abcbd1ed7631d Mon Sep 17 00:00:00 2001 From: Santosh Mardi Date: Fri, 2 Oct 2020 01:13:41 +0530 Subject: [PATCH 31/88] ARM: dts: msm: remove cpu7 llcc-ddr lat device node Remove cpu7 llcc-ddr lat device node which is similar to latfloor defined already. Change-Id: I7b1102b1e739b9f5325a561e0e122ae2a30f88f8 --- qcom/shima.dtsi | 22 +--------------------- 1 file changed, 1 insertion(+), 21 deletions(-) diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi index 4ff893da146a..14911740621e 100644 --- a/qcom/shima.dtsi +++ b/qcom/shima.dtsi @@ -2596,7 +2596,7 @@ cpu4_llcc_ddr_latmon: qcom,cpu4-llcc-ddr-latmon { compatible = "qcom,arm-memlat-mon"; - qcom,cpulist = <&CPU4 &CPU5 &CPU6>; + qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>; qcom,target-dev = <&cpu4_llcc_ddr_lat>; qcom,cachemiss-ev = <0x1000>; ddr4-map { @@ -2623,26 +2623,6 @@ }; }; - cpu7_llcc_ddr_latmon: qcom,cpu7-llcc-ddr-latmon { - compatible = "qcom,arm-memlat-mon"; - qcom,cpulist = <&CPU7>; - qcom,target-dev = <&cpu4_llcc_ddr_lat>; - qcom,cachemiss-ev = <0x1000>; - ddr4-map { - qcom,ddr-type = ; - qcom,core-dev-table = - < 2361600 MHZ_TO_MBPS( 300, 4) >, - < 2707200 MHZ_TO_MBPS(2133, 4) >; - }; - - ddr5-map { - qcom,ddr-type = ; - qcom,core-dev-table = - < 2361600 MHZ_TO_MBPS( 300, 4) >, - < 2707200 MHZ_TO_MBPS(3196, 4) >; - }; - }; - cpu4_computemon: qcom,cpu4-computemon { compatible = "qcom,arm-compute-mon"; qcom,target-dev = <&cpu4_cpu_ddr_latfloor>; From b7b2a7094851f6c484b8f5b24beab57b058c6a92 Mon Sep 17 00:00:00 2001 From: Ilia Lin Date: Mon, 5 Oct 2020 21:06:06 +0300 Subject: [PATCH 32/88] ARM: dts: msm: Add ipa_hw support for SDXLEMUR Add gsi and ipa_hw support to SDXLEMUR device tree. Change-Id: I763072bebe62be18a70ea92118596d5d59cf6261 --- qcom/sdxlemur.dtsi | 126 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 126 insertions(+) diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index de55954f16c2..dab380a836bb 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -665,6 +665,132 @@ compatible = "qcom,secure-buffer"; }; + qcom,msm_gsi { + compatible = "qcom,msm_gsi"; + }; + + qcom,rmnet-ipa { + compatible = "qcom,rmnet-ipa3"; + qcom,rmnet-ipa-ssr; + }; + + qcom,ipa_fws { + compatible = "qcom,pil-tz-generic"; + qcom,pas-id = <0xf>; + qcom,firmware-name = "ipa_fws"; + qcom,pil-force-shutdown; + }; + + ipa_hw: qcom,ipa@03e00000 { + compatible = "qcom,ipa"; + mboxes = <&qmp_aop 0>; + reg = + <0x3e00000 0x84000>, + <0x3e04000 0xfc000>; + reg-names = "ipa-base", "gsi-base"; + qcom,ipa-cfg-offset = <0x0140000>; + interrupts = + <0 241 IRQ_TYPE_LEVEL_HIGH>, + <0 47 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "ipa-irq", "gsi-irq"; + qcom,ipa-hw-ver = <21>; /* IPA core version = IPAv5.0 */ + qcom,ipa-hw-mode = <0>; + qcom,platform-type = <0>; /* MDM platform */ + qcom,ee = <0>; + qcom,use-ipa-tethering-bridge; + qcom,mhi-event-ring-id-limits = <9 11>; /* start and end */ + qcom,modem-cfg-emb-pipe-flt; + qcom,use-xbl-boot; + qcom,arm-smmu; + qcom,smmu-fast-map; + qcom,ipa-wdi3-over-gsi; + qcom,lan-rx-napi; + qcom,wan-use-skb-page; + qcom,tx-wrapper-cache-max-size = <400>; + qcom,ipa-gpi-event-rp-ddr; + clock-names = "core_clk"; + clocks = <&rpmhcc RPMH_IPA_CLK>; + qcom,interconnect,num-cases = <5>; + qcom,interconnect,num-paths = <4>; + interconnects = <&system_noc MASTER_IPA &mem_noc SLAVE_LLCC>, + <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>, + <&system_noc MASTER_IPA &system_noc SLAVE_IMEM>, + <&mem_noc MASTER_APPSS_PROC &system_noc SLAVE_IPA_CFG>; + + interconnect-names = "ipa_to_llcc", "llcc_to_ebi1", "ipa_to_imem", "appss_to_ipa"; + /* No vote */ + qcom,no-vote = + <0 0 0 0 0 0 0 0>; + + /* SVS2 */ + qcom,svs2 = + <150000 600000 150000 1804000 75000 300000 0 76800>; + + /* SVS */ + qcom,svs = + <625000 1200000 625000 3072000 312500 700000 0 150000>; + + /* NOMINAL */ + qcom,nominal = + <1250000 2400000 1250000 6220800 625000 1500000 0 400000>; + + /* TURBO */ + qcom,turbo = + <2000000 3500000 2000000 7219200 1000000 1920000 0 400000>; + + qcom,bus-vector-names = "MIN", "SVS2", "SVS", "NOMINAL", + "TURBO"; + qcom,throughput-threshold = <600 2500 5000>; + qcom,scaling-exceptions = <>; + + ipa_smmu_ap: ipa_smmu_ap { + compatible = "qcom,ipa-smmu-ap-cb"; + iommus = <&apps_smmu 0x5E0 0x0>; + qcom,iommu-dma-addr-pool = <0x20000000 0x20000000>; + qcom,additional-mapping = + /* modem tables in IMEM */ + <0x14688000 0x14688000 0x3000>; + dma-coherent; + qcom,iommu-dma = "fastmap"; + qcom,ipa-q6-smem-size = <36864>; + }; + + ipa_smmu_wlan: ipa_smmu_wlan { + compatible = "qcom,ipa-smmu-wlan-cb"; + iommus = <&apps_smmu 0x5E1 0x0>; + dma-coherent; + qcom,iommu-dma = "fastmap"; + }; + + ipa_smmu_uc: ipa_smmu_uc { + compatible = "qcom,ipa-smmu-uc-cb"; + iommus = <&apps_smmu 0x5E2 0x0>; + qcom,iommu-dma-addr-pool = <0x20000000 0x20000000>; + qcom,iommu-dma = "fastmap"; + }; + + ipa_smmu_11ad: ipa_smmu_11ad { + compatible = "qcom,ipa-smmu-11ad-cb"; + iommus = <&apps_smmu 0x5E3 0x0>; + dma-coherent; + qcom,shared-cb; + qcom,iommu-group = <>; + }; + + /* smp2p information */ + qcom,smp2p_map_ipa_1_out { + compatible = "qcom,smp2p-map-ipa-1-out"; + qcom,smem-states = <&smp2p_ipa_1_out 0>; + qcom,smem-state-names = "ipa-smp2p-out"; + }; + + qcom,smp2p_map_ipa_1_in { + compatible = "qcom,smp2p-map-ipa-1-in"; + interrupts-extended = <&smp2p_ipa_1_in 0 0>; + interrupt-names = "ipa-smp2p-in"; + }; + }; + spmi_bus: qcom,spmi@c440000 { compatible = "qcom,spmi-pmic-arb"; reg = <0xc440000 0xd00>, From 18fa948509f843ee7fafe8058100e3f41f9f4218 Mon Sep 17 00:00:00 2001 From: Odelu Kukatla Date: Fri, 25 Sep 2020 21:59:43 +0530 Subject: [PATCH 33/88] ARM: dts: msm: Add handles for USB3 interface clocks USB3 AXI cocks need to be enabled for QoS settings programming, so add USB3 AXI clock handles. Change-Id: I4ae6c49a8fc8859345bae24f00eeb0a2b0301288 --- qcom/holi.dtsi | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/qcom/holi.dtsi b/qcom/holi.dtsi index e5a0ef6954b8..bd7dd2432165 100644 --- a/qcom/holi.dtsi +++ b/qcom/holi.dtsi @@ -1033,7 +1033,9 @@ qcom,keepalive; clock-names = "bus", "bus_a"; clocks = <&rpmcc RPM_SMD_SNOC_CLK>, - <&rpmcc RPM_SMD_SNOC_A_CLK>; + <&rpmcc RPM_SMD_SNOC_A_CLK>, + <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>; }; config_noc: interconnect@1900000 { From a8f227ac88fc6cde317c904295775de92d19711d Mon Sep 17 00:00:00 2001 From: Ravikanth Tuniki Date: Tue, 29 Sep 2020 17:00:18 +0530 Subject: [PATCH 34/88] ARM: dts: msm: Add touch support for Command Mode on holi Add Synaptics dsx touch support for qsync fhd command mode panel on holi cdp. Change-Id: If44229045eb4d81d8bd22e40ab80bd95dafe337f --- qcom/holi-cdp-lcd.dtsi | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/qcom/holi-cdp-lcd.dtsi b/qcom/holi-cdp-lcd.dtsi index 057607ce47a3..064ec76ea645 100644 --- a/qcom/holi-cdp-lcd.dtsi +++ b/qcom/holi-cdp-lcd.dtsi @@ -47,6 +47,8 @@ synaptics,reset-on-state = <0>; synaptics,reset-active-ms = <20>; - panel = <&dsi_sharp_qsync_fhd_video>; + panel = <&dsi_sharp_qsync_fhd_video + &dsi_sharp_qsync_fhd_cmd + &dsi_sharp_qsync_fhd_60hz_cmd>; }; }; From 8bfb55bada068d97584c93ed9a95322f0df9720a Mon Sep 17 00:00:00 2001 From: Ashok Vuyyuru Date: Mon, 28 Sep 2020 16:47:06 +0530 Subject: [PATCH 35/88] ARM: dts: msm: Add new DT entry for wan agg pkt size Add new DT entry for wan agg pkt size. Change-Id: I492d8f770df5c5b5d8aef2c27e31e526bbf666f1 --- qcom/shima.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi index 4ff893da146a..ca7fbbd667ae 100644 --- a/qcom/shima.dtsi +++ b/qcom/shima.dtsi @@ -3725,6 +3725,8 @@ qcom,ipa-holb-monitor-max-cnt-usb = <10>; qcom,ipa-holb-monitor-max-cnt-11ad = <10>; qcom,tx-wrapper-cache-max-size = <400>; + /* Entry will be removed once shadow stack changes checked-in */ + qcom,ipa-wan-aggr-pkt-cnt = <2>; qcom,ipa-gpi-event-rp-ddr; clock-names = "core_clk"; clocks = <&rpmhcc RPMH_IPA_CLK>; From 1861fc66f09cbf6d0854ecee732f6b4d84db069a Mon Sep 17 00:00:00 2001 From: Vignesh Kulothungan Date: Fri, 18 Sep 2020 13:30:46 -0700 Subject: [PATCH 36/88] ARM: dts: qcom: add physical addr for swr tx slaves Add dt property to read physical addresses of TX soundwire master slaves. Change-Id: Id37178b6a919d0cb00d56e8639110199d3593bc2 --- qcom/lahaina-audio-overlay.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/qcom/lahaina-audio-overlay.dtsi b/qcom/lahaina-audio-overlay.dtsi index fe10fbdf88e0..4908e26696d8 100644 --- a/qcom/lahaina-audio-overlay.dtsi +++ b/qcom/lahaina-audio-overlay.dtsi @@ -72,6 +72,11 @@ <3 SWRM_TX3_CH1 0x1>, <3 SWRM_TX3_CH2 0x2>, <3 SWRM_TX3_CH3 0x4>, <3 SWRM_TX3_CH4 0x8>; qcom,swr-num-dev = <5>; + qcom,swr-phy-dev-addr = <0x0D 0x01170223>, + <0x08 0x58350223>, + <0x08 0x58350222>, + <0x08 0x58350221>, + <0x08 0x58350220>; qcom,swr-clock-stop-mode0 = <1>; qcom,swr-mstr-irq-wakeup-capable = <1>; wcd938x_tx_slave: wcd938x-tx-slave { From 33a634427c19ed23361a2b7e3c476b45073abc39 Mon Sep 17 00:00:00 2001 From: Faiyaz Mohammed Date: Wed, 7 Oct 2020 10:04:35 +0530 Subject: [PATCH 37/88] ARM: dts: msm: Enable qcom,vmid-cp-camera-preview-ro on Shima The secure camera preview pipeline on Shima has buffers that are shared by the display and secure camera hardware. On older architecture, the buffers were not shareable, as the display hardware needed write-access to the buffer, which could compromise the integrity of the data populated by the secure camera hardware. The display hardware on Shima has been upgraded, such that it no longer needs write-access to the buffer, which allows the buffer to be shared between both peripherals. Thus, ensure that the mappings for the display hardware on Shima are read-only, so that the integrity of the contents of the buffer cannot be compromised. Change-Id: I8c254262b53051f4f2bb9cb477ad70bba2d8ed20 --- qcom/shima.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi index 4ff893da146a..ad3ab7adbb47 100644 --- a/qcom/shima.dtsi +++ b/qcom/shima.dtsi @@ -779,6 +779,7 @@ qcom-secure-buffer { compatible = "qcom,secure-buffer"; + qcom,vmid-cp-camera-preview-ro; }; qcom-mem-buf { From d1b9ca00cc22ece8d077630c2fa6d9a7ebf2914f Mon Sep 17 00:00:00 2001 From: Neeraj Upadhyay Date: Mon, 28 Sep 2020 12:28:47 +0530 Subject: [PATCH 38/88] ARM: dts: msm: Add IMEM entry for Yupik Add entry for system IMEM to read or write various system level configurations. Change-Id: I3e412851c4e86483c6c1968e2463fe6710cd53eb --- qcom/yupik.dtsi | 48 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index a1d399e531df..0e497e60369b 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -401,6 +401,54 @@ }; }; + qcom,msm-imem@146aa000 { + compatible = "qcom,msm-imem"; + reg = <0x146aa000 0x1000>; + ranges = <0x0 0x146aa000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + mem_dump_table@10 { + compatible = "qcom,msm-imem-mem_dump_table"; + reg = <0x10 0x8>; + }; + + restart_reason@65c { + compatible = "qcom,msm-imem-restart_reason"; + reg = <0x65c 0x4>; + }; + + dload_type@1c { + compatible = "qcom,msm-imem-dload-type"; + reg = <0x1c 0x4>; + }; + + boot_stats@6b0 { + compatible = "qcom,msm-imem-boot_stats"; + reg = <0x6b0 0x20>; + }; + + kaslr_offset@6d0 { + compatible = "qcom,msm-imem-kaslr_offset"; + reg = <0x6d0 0xc>; + }; + + pil@94c { + compatible = "qcom,msm-imem-pil"; + reg = <0x94c 0xc8>; + }; + + pil@6dc { + compatible = "qcom,msm-imem-pil-disable-timeout"; + reg = <0x6dc 0x4>; + }; + + diag_dload@c8 { + compatible = "qcom,msm-imem-diag-dload"; + reg = <0xc8 0xc8>; + }; + }; + clocks { xo_board: xo-board { compatible = "fixed-clock"; From a6f736aacaf61ce835076b8668b3a17623c23a6b Mon Sep 17 00:00:00 2001 From: Anmolpreet Kaur Date: Wed, 7 Oct 2020 10:37:56 +0530 Subject: [PATCH 39/88] ARM: dts: msm: Enable smcinvoke and shmbridge on shima Add the device tree entries for smcinvoke and shmbridge on shima vm. Change-Id: Ied6246edcdd957e18678e18c375fa11ccf4ca135 --- qcom/shima-vm.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/qcom/shima-vm.dtsi b/qcom/shima-vm.dtsi index 242012055766..f2651706963a 100644 --- a/qcom/shima-vm.dtsi +++ b/qcom/shima-vm.dtsi @@ -228,6 +228,15 @@ ; }; + qcom_smcinvoke { + compatible = "qcom,smcinvoke"; + }; + + qtee_shmbridge { + compatible = "qcom,tee-shared-memory-bridge"; + qcom,support-hypervisor; + }; + /* * QUPv3 Instances * Qup0 2: SE 10 From 96512cbc99755d07b8556f2ea82c3b52ec64d245 Mon Sep 17 00:00:00 2001 From: yuleiy Date: Fri, 25 Sep 2020 11:40:36 +0800 Subject: [PATCH 40/88] ARM: dts: qcom: Change L4P's max output voltage Change L4P's max output voltage from 2800000 to 2880000 to match holi QRD rear camera0's AVDD requirement. CRs-Fixed: 2792547 External Impact: No. Change-Id: Id9a65b541e7c3d391ff82d25dde73151cb297e24 --- qcom/holi-pmic-overlay.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/holi-pmic-overlay.dtsi b/qcom/holi-pmic-overlay.dtsi index 7935292f7f9c..2cc337167393 100644 --- a/qcom/holi-pmic-overlay.dtsi +++ b/qcom/holi-pmic-overlay.dtsi @@ -482,7 +482,7 @@ reg = <0x4300>; regulator-name = "pm8008_l4"; regulator-min-microvolt = <1500000>; - regulator-max-microvolt = <2800000>; + regulator-max-microvolt = <2880000>; qcom,min-dropout-voltage = <160000>; qcom,hpm-min-load = <10000>; }; From 62b18b73ea7674be94ca8253acf09b15d8b36e00 Mon Sep 17 00:00:00 2001 From: Ram Prakash Gupta Date: Thu, 24 Sep 2020 23:15:31 +0530 Subject: [PATCH 41/88] ARM: dts: msm: Enable smmu for shima ufs Enable smmu for shima ufs. Change-Id: Ib642a274cb1c285aa58a464a3de649a5510e8992 --- qcom/shima.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi index 4ff893da146a..6fdf629dc43a 100644 --- a/qcom/shima.dtsi +++ b/qcom/shima.dtsi @@ -1711,7 +1711,7 @@ reset-names = "rst"; iommus = <&apps_smmu 0x80 0x0>; - qcom,iommu-dma = "bypass"; + qcom,iommu-dma = "fastmap"; dma-coherent; rpm-level = <3>; From 947798dfdc4b199294ace780a6d0820dac30c784 Mon Sep 17 00:00:00 2001 From: Melody Olvera Date: Mon, 5 Oct 2020 10:13:52 -0700 Subject: [PATCH 42/88] ARM: dts: msm: Add board device-tree files for SDXLEMUR target Add devicetree files for various boards available on SDXLEMUR target. Change-Id: Iacd1cbd4260e978387101f95954776fab7e3f042 --- bindings/arm/msm/msm.txt | 1 + qcom/Makefile | 11 ++++++++++- qcom/sdxlemur-mtp-cpe.dts | 11 +++++++++++ qcom/sdxlemur-mtp-cpe.dtsi | 5 +++++ qcom/sdxlemur-mtp-mbb-ntn3-pcie.dts | 11 +++++++++++ qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi | 5 +++++ qcom/sdxlemur-mtp-mbb-pcie-ep.dts | 11 +++++++++++ qcom/sdxlemur-mtp-mbb-pcie-ep.dtsi | 5 +++++ qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dts | 11 +++++++++++ qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dtsi | 5 +++++ qcom/sdxlemur-mtp-mbb.dts | 11 +++++++++++ qcom/sdxlemur-mtp-mbb.dtsi | 5 +++++ qcom/sdxlemur-rcm-pcie-ep.dts | 11 +++++++++++ qcom/sdxlemur-rcm-pcie-ep.dtsi | 5 +++++ qcom/sdxlemur-rcm-rc.dts | 11 +++++++++++ qcom/sdxlemur-rcm-rc.dtsi | 5 +++++ 16 files changed, 123 insertions(+), 1 deletion(-) create mode 100644 qcom/sdxlemur-mtp-cpe.dts create mode 100644 qcom/sdxlemur-mtp-cpe.dtsi create mode 100644 qcom/sdxlemur-mtp-mbb-ntn3-pcie.dts create mode 100644 qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi create mode 100644 qcom/sdxlemur-mtp-mbb-pcie-ep.dts create mode 100644 qcom/sdxlemur-mtp-mbb-pcie-ep.dtsi create mode 100644 qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dts create mode 100644 qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dtsi create mode 100644 qcom/sdxlemur-mtp-mbb.dts create mode 100644 qcom/sdxlemur-mtp-mbb.dtsi create mode 100644 qcom/sdxlemur-rcm-pcie-ep.dts create mode 100644 qcom/sdxlemur-rcm-pcie-ep.dtsi create mode 100644 qcom/sdxlemur-rcm-rc.dts create mode 100644 qcom/sdxlemur-rcm-rc.dtsi diff --git a/bindings/arm/msm/msm.txt b/bindings/arm/msm/msm.txt index 93709ab8e29b..16b9fbede6b4 100644 --- a/bindings/arm/msm/msm.txt +++ b/bindings/arm/msm/msm.txt @@ -235,6 +235,7 @@ compatible = "qcom,sdxprairie-cdp" compatible = "qcom,sdxlemur-rumi" compatible = "qcom,sdxlemur-mtp" compatible = "qcom,sdxlemur-cdp" +compatible = "qcom,sdxlemur-rcm" compatible = "qcom,sdmmagpie-rumi" compatible = "qcom,sdmmagpie-idp" compatible = "qcom,sdmmagpie-qrd" diff --git a/qcom/Makefile b/qcom/Makefile index 1a1c6f058bd8..0655369c6682 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -165,7 +165,16 @@ endif dtb-$(CONFIG_ARCH_SDXLEMUR) += sdxlemur-rumi.dtb \ sdxlemur-cdp.dtb \ - sdxlemur-mtp.dtb + sdxlemur-mtp.dtb \ + sdxlemur-mtp-mbb.dtb \ + sdxlemur-mtp-cpe.dtb \ + sdxlemur-mtp-mbb-ntn3-pcie.dtb \ + sdxlemur-mtp-mbb-pcie-ep.dtb \ + sdxlemur-mtp-mbb-pcie-rc-ep.dtb \ + sdxlemur-mtp-mbb.dtb \ + sdxlemur-rcm-pcie-ep.dtb \ + sdxlemur-rcm-rc.dtb + ifeq ($(CONFIG_ARCH_SHIMA), y) ifeq ($(CONFIG_ARCH_QTI_VM), y) diff --git a/qcom/sdxlemur-mtp-cpe.dts b/qcom/sdxlemur-mtp-cpe.dts new file mode 100644 index 000000000000..696b1ab58713 --- /dev/null +++ b/qcom/sdxlemur-mtp-cpe.dts @@ -0,0 +1,11 @@ +/dts-v1/; + +#include "sdxlemur.dtsi" +#include "sdxlemur-mtp-cpe.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDXLEMUR MTP CPE"; + compatible = "qcom,sdxlemur-mtp", + "qcom,sdxlemur", "qcom,mtp"; + qcom,board-id = <0x6010008 0>; +}; diff --git a/qcom/sdxlemur-mtp-cpe.dtsi b/qcom/sdxlemur-mtp-cpe.dtsi new file mode 100644 index 000000000000..cc3a833f430e --- /dev/null +++ b/qcom/sdxlemur-mtp-cpe.dtsi @@ -0,0 +1,5 @@ + +&soc { + +}; + diff --git a/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dts b/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dts new file mode 100644 index 000000000000..ead998c52e3c --- /dev/null +++ b/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dts @@ -0,0 +1,11 @@ +/dts-v1/; + +#include "sdxlemur.dtsi" +#include "sdxlemur-mtp-mbb-ntn3-pcie.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDXLEMUR MTP MBB NTN3 PCIE"; + compatible = "qcom,sdxlemur-mtp", + "qcom,sdxlemur", "qcom,mtp"; + qcom,board-id = <0x5010008 0>; +}; diff --git a/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi b/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi new file mode 100644 index 000000000000..cc3a833f430e --- /dev/null +++ b/qcom/sdxlemur-mtp-mbb-ntn3-pcie.dtsi @@ -0,0 +1,5 @@ + +&soc { + +}; + diff --git a/qcom/sdxlemur-mtp-mbb-pcie-ep.dts b/qcom/sdxlemur-mtp-mbb-pcie-ep.dts new file mode 100644 index 000000000000..615f5c59659c --- /dev/null +++ b/qcom/sdxlemur-mtp-mbb-pcie-ep.dts @@ -0,0 +1,11 @@ +/dts-v1/; + +#include "sdxlemur.dtsi" +#include "sdxlemur-mtp-mbb-pcie-ep.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDXLEMUR MTP MBB PCIE-EP"; + compatible = "qcom,sdxlemur-mtp", + "qcom,sdxlemur", "qcom,mtp"; + qcom,board-id = <0x4010008 0>; +}; diff --git a/qcom/sdxlemur-mtp-mbb-pcie-ep.dtsi b/qcom/sdxlemur-mtp-mbb-pcie-ep.dtsi new file mode 100644 index 000000000000..cc3a833f430e --- /dev/null +++ b/qcom/sdxlemur-mtp-mbb-pcie-ep.dtsi @@ -0,0 +1,5 @@ + +&soc { + +}; + diff --git a/qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dts b/qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dts new file mode 100644 index 000000000000..c849ed133087 --- /dev/null +++ b/qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dts @@ -0,0 +1,11 @@ +/dts-v1/; + +#include "sdxlemur.dtsi" +#include "sdxlemur-mtp-mbb-pcie-rc-ep.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDXLEMUR MTP MBB RC PCIE-EP"; + compatible = "qcom,sdxlemur-mtp", + "qcom,sdxlemur", "qcom,mtp"; + qcom,board-id = <0x3010008 0>; +}; diff --git a/qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dtsi b/qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dtsi new file mode 100644 index 000000000000..cc3a833f430e --- /dev/null +++ b/qcom/sdxlemur-mtp-mbb-pcie-rc-ep.dtsi @@ -0,0 +1,5 @@ + +&soc { + +}; + diff --git a/qcom/sdxlemur-mtp-mbb.dts b/qcom/sdxlemur-mtp-mbb.dts new file mode 100644 index 000000000000..117c1bb3719b --- /dev/null +++ b/qcom/sdxlemur-mtp-mbb.dts @@ -0,0 +1,11 @@ +/dts-v1/; + +#include "sdxlemur.dtsi" +#include "sdxlemur-mtp-mbb.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDXLEMUR MTP MBB"; + compatible = "qcom,sdxlemur-mtp", + "qcom,sdxlemur", "qcom,mtp"; + qcom,board-id = <0x2010008 0>; +}; diff --git a/qcom/sdxlemur-mtp-mbb.dtsi b/qcom/sdxlemur-mtp-mbb.dtsi new file mode 100644 index 000000000000..cc3a833f430e --- /dev/null +++ b/qcom/sdxlemur-mtp-mbb.dtsi @@ -0,0 +1,5 @@ + +&soc { + +}; + diff --git a/qcom/sdxlemur-rcm-pcie-ep.dts b/qcom/sdxlemur-rcm-pcie-ep.dts new file mode 100644 index 000000000000..11a14dc88bef --- /dev/null +++ b/qcom/sdxlemur-rcm-pcie-ep.dts @@ -0,0 +1,11 @@ +/dts-v1/; + +#include "sdxlemur.dtsi" +#include "sdxlemur-rcm-pcie-ep.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDXLEMUR RCM PCIe-EP"; + compatible = "qcom,sdxlemur-rcm", + "qcom,sdxlemur", "qcom,rcm"; + qcom,board-id = <0x1010015 0>; +}; diff --git a/qcom/sdxlemur-rcm-pcie-ep.dtsi b/qcom/sdxlemur-rcm-pcie-ep.dtsi new file mode 100644 index 000000000000..cc3a833f430e --- /dev/null +++ b/qcom/sdxlemur-rcm-pcie-ep.dtsi @@ -0,0 +1,5 @@ + +&soc { + +}; + diff --git a/qcom/sdxlemur-rcm-rc.dts b/qcom/sdxlemur-rcm-rc.dts new file mode 100644 index 000000000000..f061c22ed532 --- /dev/null +++ b/qcom/sdxlemur-rcm-rc.dts @@ -0,0 +1,11 @@ +/dts-v1/; + +#include "sdxlemur.dtsi" +#include "sdxlemur-rcm-rc.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SDXLEMUR RCM Root Complex"; + compatible = "qcom,sdxlemur-rcm", + "qcom,sdxlemur", "qcom,rcm"; + qcom,board-id = <0x1010015 0>; +}; diff --git a/qcom/sdxlemur-rcm-rc.dtsi b/qcom/sdxlemur-rcm-rc.dtsi new file mode 100644 index 000000000000..cc3a833f430e --- /dev/null +++ b/qcom/sdxlemur-rcm-rc.dtsi @@ -0,0 +1,5 @@ + +&soc { + +}; + From 4ed98c6d4ca06c06f4540c4f4239aff1ca1c0120 Mon Sep 17 00:00:00 2001 From: Ram Prakash Gupta Date: Wed, 16 Sep 2020 01:54:42 +0530 Subject: [PATCH 43/88] ARM: dts: msm: Add ufs dt node for yupik Add ufs dt node support for yupik. Change-Id: I4585ba80587f7c3e668621d98e4603008dd17f0c --- qcom/yupik-rumi.dtsi | 34 +++++++++++ qcom/yupik.dtsi | 140 ++++++++++++++++++++++++++++++++++++++++++- 2 files changed, 173 insertions(+), 1 deletion(-) diff --git a/qcom/yupik-rumi.dtsi b/qcom/yupik-rumi.dtsi index 0987448b8be5..3d00135b89f8 100644 --- a/qcom/yupik-rumi.dtsi +++ b/qcom/yupik-rumi.dtsi @@ -11,3 +11,37 @@ status = "disabled"; }; }; + +&ufsphy_mem { + compatible = "qcom,ufs-phy-qrbtc-sdm845"; + + vdda-phy-supply = <&L10C>; + vdda-pll-supply = <&L6B>; + vdda-phy-max-microamp = <97100>; + vdda-pll-max-microamp = <18400>; + + status = "ok"; +}; + +&ufshc_mem { + limit-tx-hs-gear = <1>; + limit-rx-hs-gear = <1>; + + vdd-hba-supply = <&gcc_ufs_phy_gdsc>; + vdd-hba-fixed-regulator; + + vcc-supply = <&L7B>; + vcc-max-microamp = <800000>; + + vccq-supply = <&L9B>; + vccq-max-microamp = <900000>; + + qcom,vddp-ref-clk-supply = <&L9B>; + qcom,vddp-ref-clk-max-microamp = <100>; + + qcom,disable-lpm; + rpm-level = <0>; + spm-level = <0>; + + status = "ok"; +}; diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index a1d399e531df..6d02b2177e66 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -10,6 +10,7 @@ #include #include #include +#include / { model = "Qualcomm Technologies, Inc. Yupik"; @@ -21,7 +22,9 @@ #size-cells = <2>; memory { device_type = "memory"; reg = <0 0 0 0>; }; - aliases { }; + aliases { + ufshc1 = &ufshc_mem; /* Embedded UFS Slot */ + }; cpus { #address-cells = <2>; @@ -503,6 +506,141 @@ #reset-cells = <1>; }; + ufsphy_mem: ufsphy_mem@1d87000 { + reg = <0x1d87000 0xe00>; + reg-names = "phy_mem"; + #phy-cells = <0>; + + lanes-per-direction = <2>; + clock-names = "ref_clk_src", + "ref_clk", + "ref_aux_clk"; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_1_CLKREF_EN>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; + resets = <&ufshc_mem 0>; + + status = "disabled"; + }; + + ufshc_mem: ufshc@1d84000 { + compatible = "qcom,ufshc"; + reg = <0x1d84000 0x3000>; + reg-names = "ufs_mem"; + interrupts = ; + phys = <&ufsphy_mem>; + phy-names = "ufsphy"; + #reset-cells = <1>; + + lanes-per-direction = <2>; + dev-ref-clk-freq = <0>; /* 19.2 MHz */ + clock-names = + "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "core_clk_ice", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk", + "rx_lane1_sync_clk"; + clocks = + <&gcc GCC_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>, + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; + freq-table-hz = + <75000000 300000000>, + <0 0>, + <0 0>, + <75000000 300000000>, + <75000000 300000000>, + <0 0>, + <0 0>, + <0 0>, + <0 0>; + + qcom,ufs-bus-bw,name = "ufshc_mem"; + qcom,ufs-bus-bw,num-cases = <26>; + qcom,ufs-bus-bw,num-paths = <2>; + qcom,ufs-bus-bw,vectors-KBps = + /* + * During HS G3 UFS runs at nominal voltage corner, vote + * higher bandwidth to push other buses in the data path + * to run at nominal to achieve max throughput. + * 4GBps pushes BIMC to run at nominal. + * 200MBps pushes CNOC to run at nominal. + * Vote for half of this bandwidth for HS G3 1-lane. + * For max bandwidth, vote high enough to push the buses + * to run in turbo voltage corner. + */ + <0 0>, <0 0>, /* No vote */ + <922 0>, <1000 0>, /* PWM G1 */ + <1844 0>, <1000 0>, /* PWM G2 */ + <3688 0>, <1000 0>, /* PWM G3 */ + <7376 0>, <1000 0>, /* PWM G4 */ + <1844 0>, <1000 0>, /* PWM G1 L2 */ + <3688 0>, <1000 0>, /* PWM G2 L2 */ + <7376 0>, <1000 0>, /* PWM G3 L2 */ + <14752 0>, <1000 0>, /* PWM G4 L2 */ + <127796 0>, <1000 0>, /* HS G1 RA */ + <255591 0>, <1000 0>, /* HS G2 RA */ + <2097152 0>, <102400 0>, /* HS G3 RA */ + <4194304 0>, <204800 0>, /* HS G4 RA */ + <255591 0>, <1000 0>, /* HS G1 RA L2 */ + <511181 0>, <1000 0>, /* HS G2 RA L2 */ + <4194304 0>, <204800 0>, /* HS G3 RA L2 */ + <8388608 0>, <409600 0>, /* HS G4 RA L2 */ + <149422 0>, <1000 0>, /* HS G1 RB */ + <298189 0>, <1000 0>, /* HS G2 RB */ + <2097152 0>, <102400 0>, /* HS G3 RB */ + <4194304 0>, <204800 0>, /* HS G4 RB */ + <298189 0>, <1000 0>, /* HS G1 RB L2 */ + <596378 0>, <1000 0>, /* HS G2 RB L2 */ + /* As UFS working in HS G3 RB L2 mode, aggregated + * bandwidth (AB) should take care of providing + * optimum throughput requested. However, as tested, + * in order to scale up CNOC clock, instantaneous + * bindwidth (IB) needs to be given a proper value too. + */ + <4194304 0>, <204800 409600>, /* HS G3 RB L2 */ + <8388608 0>, <409600 409600>, /* HS G4 RB L2 */ + <7643136 0>, <307200 0>; /* Max. bandwidth */ + + qcom,bus-vector-names = "MIN", + "PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1", + "PWM_G1_L2", "PWM_G2_L2", "PWM_G3_L2", "PWM_G4_L2", + "HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1", "HS_RA_G4_L1", + "HS_RA_G1_L2", "HS_RA_G2_L2", "HS_RA_G3_L2", "HS_RA_G4_L2", + "HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1", "HS_RB_G4_L1", + "HS_RB_G1_L2", "HS_RB_G2_L2", "HS_RB_G3_L2", "HS_RB_G4_L2", + "MAX"; + + reset-gpios = <&tlmm 175 GPIO_ACTIVE_LOW>; + resets = <&gcc GCC_UFS_PHY_BCR>; + reset-names = "rst"; + + rpm-level = <3>; + spm-level = <3>; + + status = "disabled"; + + qos0 { + mask = <0xf0>; + vote = <59>; + }; + + qos1 { + mask = <0x0f>; + vote = <65>; + }; + }; + clk_virt: interconnect { compatible = "qcom,yupik-clk_virt"; #interconnect-cells = <1>; From f0104dcca4c819fdaee6161bfa1d767328f8d123 Mon Sep 17 00:00:00 2001 From: Melody Olvera Date: Tue, 29 Sep 2020 13:36:41 -0700 Subject: [PATCH 44/88] ARM: dts: msm: Added pil nodes for sdxlemur Added entries for pil modem nodes on sdxlemur. Change-Id: I9d211a0b0b6d319066bcef5b567ef4122b6c7712 --- qcom/sdxlemur.dtsi | 42 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index de55954f16c2..806d7a85c6c8 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -4,6 +4,7 @@ #include #include #include +#include #include #include @@ -386,6 +387,47 @@ status = "ok"; }; + pil_modem: qcom,mss@4080000 { + compatible = "qcom,pil-tz-generic"; + reg = <0x4080000 0x100>; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + qcom,proxy-clock-names = "xo"; + + vdd_cx-supply = <&VDD_CX_LEVEL>; + qcom,vdd_cx-uV-uA = ; + vdd_mss-supply = <&VDD_MSS_LEVEL>; + qcom,vdd_mss-uV-uA = ; + qcom,proxy-reg-names = "vdd_cx", "vdd_mss"; + + qcom,firmware-name = "modem"; + memory-region = <&mpss_adsp_mem>; + qcom,pas-id = <4>; + qcom,smem-id = <421>; + qcom,sysmon-id = <0>; + qcom,ssctl-instance-id = <0x22>; + + interrupts-extended = <&intc 0 250 1>, + <&modem_smp2p_in 0 0>, + <&modem_smp2p_in 2 0>, + <&modem_smp2p_in 1 0>, + <&modem_smp2p_in 3 0>, + <&modem_smp2p_in 7 0>; + + interrupt-names = "qcom,wdog", + "qcom,err-fatal", + "qcom,proxy-unvote", + "qcom,err-ready", + "qcom,stop-ack", + "qcom,shutdown-ack"; + + qcom,smem-states = <&modem_smp2p_out 0>; + qcom,smem-state-names = "qcom,force-stop"; + + status = "ok"; + }; + qnand_1: nand@1b00000 { compatible = "qcom,msm-nand"; reg = <0x01b00000 0x1000>, From 9236449ef7061dbc0816dda77ada3ec2daf286e6 Mon Sep 17 00:00:00 2001 From: Jishnu Prakash Date: Thu, 8 Oct 2020 10:18:30 +0530 Subject: [PATCH 45/88] bindings: leds: vibrator: Move vibrator LDO documentation to correct folder Move vibrator LDO documentation to bindings folder. Change-Id: I81f873ede92e25797f0f7a1d7aa40c2af382e1c9 --- {qcom => bindings/leds}/leds-qpnp-vibrator-ldo.txt | 0 1 file changed, 0 insertions(+), 0 deletions(-) rename {qcom => bindings/leds}/leds-qpnp-vibrator-ldo.txt (100%) diff --git a/qcom/leds-qpnp-vibrator-ldo.txt b/bindings/leds/leds-qpnp-vibrator-ldo.txt similarity index 100% rename from qcom/leds-qpnp-vibrator-ldo.txt rename to bindings/leds/leds-qpnp-vibrator-ldo.txt From 80c23fdde82b1b3dba86665a239dff3e906172a1 Mon Sep 17 00:00:00 2001 From: Kavya Nunna Date: Wed, 7 Oct 2020 11:52:12 +0530 Subject: [PATCH 46/88] bindings: smb1351: Add documentation for SMB1351 charger Add snapshot of smb1351 charger documentation from msm-4.14 'commit 50f9f83dd79b ("Merge "defconfig : Enable pinctrl and clock driver for SA8195"")'. SMB1351 is a single-cell battery charger. It can charge the battery and power the system via the USB/AC adapter input. Change-Id: Ife4403bfe2ee577f0e4c952432861bcccb3be076 --- .../power/supply/qcom/smb1351-charger.txt | 122 ++++++++++++++++++ 1 file changed, 122 insertions(+) create mode 100644 bindings/power/supply/qcom/smb1351-charger.txt diff --git a/bindings/power/supply/qcom/smb1351-charger.txt b/bindings/power/supply/qcom/smb1351-charger.txt new file mode 100644 index 000000000000..c0aa10941c16 --- /dev/null +++ b/bindings/power/supply/qcom/smb1351-charger.txt @@ -0,0 +1,122 @@ +Qualcomm Technologies, Inc. SMB1351 Charger Specific Bindings + +SMB1351 is a single-cell battery charger. It can charge +the battery and power the system via the USB/AC adapter input. + +The smb1351 interface is via I2C bus. + +Required Properties: +- compatible Must be "qcom,smb1351-charger". +- reg The device 7-bit I2C address. + +Required Properties for standalone charger: +- regulator-name A string used as a descriptive name for OTG regulator. +- pinctrl-names The state name of the pin configuration. Only + support "default". +- pinctrl-0 The phandle of the pin configuration node in + pinctrl for smb_int_pin. + +Optional Properties: + +- interrupts This indicates the IRQ number of the GPIO + connected to the STAT pin. +- qcom,fastchg-current-max-ma Fast Charging current in mA. Supported range is + from 1000mA to 4500mA. +- qcom,chg-autonomous-mode This is a bool property and it indicates that the + charger is configured for autonomous operation and + does not require any software configuration. +- qcom,disable-apsd This is a bool property which disables automatic + power source detection (APSD). If this is set + charger detection is done by DCIN UV irq. +- qcom,charging-disabled This is a bool property which disables charging + by suspending usb. +- qcom,batt-charging-disabled This is a bool property which disables battery + charging. +- qcom,using-pmic-therm This property indicates thermal pin connected to pmic or smb. +- qcom,bms-psy-name This is a string and it points to the bms + power supply name. +- qcom,iterm-ma Specifies the termination current to indicate end-of-charge. + Possible values in mA - 70, 100, 200, 300, 400, 500, 600, 700. +- qcom,iterm-disabled Disables the termination current feature. This is a bool + property. +- qcom,float-voltage-mv Float Voltage in mV - the maximum voltage up to which + the battery is charged. Supported range 3500mV to 4500mV +- qcom,recharge-mv Recharge threshold in mV - the offset from the float-volatge + as which the charger restarts charging. Possible + values are 50mV and 100mV. +- qcom,recharge-disabled Boolean value which disables the auto-recharge. +- qcom,bms-controlled-charging This property enables BMS to control EOC and + recharge. BMS and charger communicates with each + other via power_supply framework. This + property should be used with 'qcom,iterm-disabled' + to ensure EOC detection in charger is disabled. +- qcom,force-hvdcp-2p0 Boolean value which allows to force hvdcp working on 2.0 mode. +- qcom,parallel-charger Boolean value which enables the parallel charger. +- qcom,chg-vadc Corresponding VADC device's phandle. +- qcom,chg-adc_tm phandle to the corresponding VADC device to read the ADC channels. +- qcom,batt-cold-decidegc Cold battery temperature in decidegC. +- qcom,batt-hot-decidegc Hot battery temperature in decidegC. +- qcom,batt-missing-decidegc This is a property indicating battery missing temperature, if + higher than it, battery should exist. +- qcom,batt-warm-decidegc: Warm battery temperature in decidegC. After hitting this threshold, + "qcom,warm-bat-ma" defines maximum charging current and + "qcom,warm-bat-mv" defines maximum target voltage. +- qcom,batt-cool-decidegc: Cool battery temperature in decidegC. After hitting this threshold, + "qcom,cool-bat-ma" defines maximum charging current and + "qcom,cool-bat-mv" defines maximum target voltage. +- qcom,batt-warm-ma: Maximum warm battery charge current in milli-amps. +- qcom,batt-cool-ma: Maximum cool battery charge current in milli-amps. +- qcom,batt-warm-mv: Maximum warm battery target voltage in milli-volts. +- qcom,batt-cool-mv: Maximum cool battery target voltage in milli-volts. +- qcom,parallel-en-pin-polarity Specify the polarity of enable signal controlled + via pin in a parallel-charger configuration. + 0 - Active low and 1 - Active high. + If not specified the default value is active-low. +- qcom,parallel-external-current-sense If present specifies external rsense is + used for charge current sensing. +- qcom,stacked-batfet: Boolean flag. Specifies if parallel charger has stacked BATFET + cofiguration. +- qcom,otg-enable: Boolean value which enables OTG(On-The-Go) + functionality. + +Example for standalone charger: + +&i2c_4 { + smb1351_otg_supply: smb1351-charger@57 { + compatible = "qcom,smb1351-charger"; + reg = <0x57>; + interrupt-parent = <&msm_gpio>; + interrupts = <62 2>; + pinctrl-names = "default"; + pinctrl-0 = <&smb_int_default>; + qcom,float-voltage-mv = <4350>; + qcom,iterm-ma = <100>; + qcom,recharge-mv = <100>; + qcom,bms-psy-name = "bms"; + regulator-name = "smb1351_otg_vreg"; + qcom,using-pmic-therm; + qcom,chg-adc_tm = <&pm8916_adc_tm>; + qcom,chg-vadc = <&pm8916_vadc>; + qcom,batt-hot-decidegc = <550>; + qcom,batt-cold-decidegc = <0>; + qcom,batt-missing-decidegc = <(-200)>; + qcom,batt-warm-decidegc = <500>; + qcom,batt-cool-decidegc = <50>; + qcom,batt-warm-ma = <350>; + qcom,batt-cool-ma = <350>; + qcom,batt-warm-mv = <4200>; + qcom,batt-cool-mv = <4200>; + }; +}; + +Example for parallel charger: + +&i2c_11 { + smb1351-charger@1d { + compatible = "qcom,smb1351-charger"; + reg = <0x1d>; + qcom,parallel-charger; + qcom,float-voltage-mv = <4400>; + qcom,recharge-mv = <100>; + }; +}; From 52c0ae3e868f43d992fc4d145fce8969616e29be Mon Sep 17 00:00:00 2001 From: Rohith Kollalsi Date: Thu, 8 Oct 2020 15:59:10 +0530 Subject: [PATCH 47/88] ARM: dts: msm: Add pm-qos-latency node to improve the ADB throughput Add pm-qos-latency which ensures that cpu is used to its full capability,there by increasing ADB throughput for holi. Change-Id: I95d4b75a7c06863a6e6052fad1df99aafac1109b --- qcom/holi-usb.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/holi-usb.dtsi b/qcom/holi-usb.dtsi index beca47439f58..99450e498134 100644 --- a/qcom/holi-usb.dtsi +++ b/qcom/holi-usb.dtsi @@ -47,6 +47,7 @@ <&bimc MASTER_AMPSS_M0 &config_noc SLAVE_USB3>; qcom,num-gsi-evt-buffs = <0x3>; + qcom,pm-qos-latency = <61>; qcom,gsi-reg-offset = <0x0fc /* GSI_GENERAL_CFG */ 0x110 /* GSI_DBL_ADDR_L */ From 6a4ddcf7bb9bb6eb625b4ea2ff2a4d769d120e38 Mon Sep 17 00:00:00 2001 From: Jagadeesh Kona Date: Wed, 7 Oct 2020 15:43:11 +0530 Subject: [PATCH 48/88] ARM: dts: msm: Remove bi_tcxo_ao clock and vdd_cx_ao handles from GCC Remove bi_tcxo_ao clock handle and vdd_cx_ao handle from GCC node as they are currently unused. Change-Id: I5b444e7dc2260d269f08fdbe6a85c319e5e5e60c --- qcom/shima.dtsi | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi index ca7fbbd667ae..19c14121de92 100644 --- a/qcom/shima.dtsi +++ b/qcom/shima.dtsi @@ -929,10 +929,8 @@ reg = <0x100000 0x1f0000>; reg-names = "cc_base"; vdd_cx-supply = <&VDD_CX_LEVEL>; - vdd_cx_ao-supply = <&VDD_CX_LEVEL_AO>; - clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, - <&sleep_clk>; - clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>; + clock-names = "bi_tcxo", "sleep_clk"; #clock-cells = <1>; #reset-cells = <1>; }; From 81f0e49d1fee1cdc0468c8de28b2caa7a3a3c783 Mon Sep 17 00:00:00 2001 From: Ilia Lin Date: Thu, 8 Oct 2020 19:05:59 +0300 Subject: [PATCH 49/88] ARM: dts: msm: Disable fastmap for IPA CBs on SDXLEMUR The WLAN CB and UC CB SMMUs on the sdxlemur intended to be atomic. Change-Id: If74e9021719086c27eb313017368e427a3b3f330 --- qcom/sdxlemur.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index dab380a836bb..06dcaf8c5ba6 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -759,14 +759,14 @@ compatible = "qcom,ipa-smmu-wlan-cb"; iommus = <&apps_smmu 0x5E1 0x0>; dma-coherent; - qcom,iommu-dma = "fastmap"; + qcom,iommu-dma = "atomic"; }; ipa_smmu_uc: ipa_smmu_uc { compatible = "qcom,ipa-smmu-uc-cb"; iommus = <&apps_smmu 0x5E2 0x0>; qcom,iommu-dma-addr-pool = <0x20000000 0x20000000>; - qcom,iommu-dma = "fastmap"; + qcom,iommu-dma = "atomic"; }; ipa_smmu_11ad: ipa_smmu_11ad { From 012012e3f2c40c0857d91819714a76bb1045cedf Mon Sep 17 00:00:00 2001 From: "Vangala, Amarnath" Date: Thu, 8 Oct 2020 22:20:50 +0530 Subject: [PATCH 50/88] ARM: dts: msm: update sound card name for holi usbc variant update sound card name for usbc variant. Change-Id: I776830ca6f369e710b1bb8b3e237012e1db7454e --- qcom/holi-mtp-usbc.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/holi-mtp-usbc.dtsi b/qcom/holi-mtp-usbc.dtsi index fddd4d338dda..8e7a4528580b 100644 --- a/qcom/holi-mtp-usbc.dtsi +++ b/qcom/holi-mtp-usbc.dtsi @@ -95,7 +95,7 @@ }; &holi_snd { - qcom,model = "holi-mtp-usbc-snd-card"; + qcom,model = "holi-usbc-snd-card"; qcom,msm-mbhc-usbc-audio-supported = <1>; qcom,msm-mbhc-hphl-swh = <0>; qcom,msm-mbhc-gnd-swh = <0>; From e3cf6147147f504395795cb1870198f457443850 Mon Sep 17 00:00:00 2001 From: Asish Bhattacharya Date: Thu, 8 Oct 2020 22:32:08 +0530 Subject: [PATCH 51/88] bindings: Documentation: add SDK audio properties Add audio documentation for SDX target. Change-Id: I49da28bfa0dacb3cde4fdf68b58528d3da8bdec8 --- bindings/sound/qcom-audio-dev.txt | 89 +++++++++++++++++++++++++++++++ 1 file changed, 89 insertions(+) diff --git a/bindings/sound/qcom-audio-dev.txt b/bindings/sound/qcom-audio-dev.txt index be5d91b5c748..1c9bc157da29 100644 --- a/bindings/sound/qcom-audio-dev.txt +++ b/bindings/sound/qcom-audio-dev.txt @@ -2398,3 +2398,92 @@ Example: }; }; +Required properties: +- compatible : "qcom,spf-core-platform" + +Required properties: +- compatible : "qcom,audio-pkt-core-platform" + +Required properties: +- compatible : "qcom,swr-wcd" + +Required properties: +- compatible : "qcom,tavil-i2c" + +Required properties: +- compatible : "qcom,wcd-pinctrl" + +Required properties: +- compatible : "qcom,gpr" + +Required properties: +- compatible : "qcom,spf_core" + +Required properties: +- compatible : "qcom,audio-pkt" + +Required properties: +- compatible : "qcom,audio_prm" + + + +* SDX ASoC Machine driver + +Required properties: +- compatible : "qcom,sdx-asoc-snd-tavil" +- qcom,model : The user-visible name of this sound card. +- qcom,prim_mi2s_aux_master : Handle to prim_master pinctrl configurations +- qcom,prim_mi2s_aux_slave : Handle to prim_slave pinctrl configurations +- qcom,sec_mi2s_aux_master : Handle to sec_master pinctrl configurations +- qcom,sec_mi2s_aux_slave : Handle to sec_slave pinctrl configurations +- asoc-platform: This is phandle list containing the references to platform device + nodes that are used as part of the sound card dai-links. +- asoc-platform-names: This property contains list of platform names. The order of + the platform names should match to that of the phandle order + given in "asoc-platform". +- asoc-cpu: This is phandle list containing the references to cpu dai device nodes + that are used as part of the sound card dai-links. +- asoc-cpu-names: This property contains list of cpu dai names. The order of the + cpu dai names should match to that of the phandle order give + in "asoc-cpu". The cpu names are in the form of "%s.%d" form, + where the id (%d) field represents the back-end AFE port id that + this CPU dai is associated with. +Example: + + sound-tavil { + compatible = "qcom,sdx-asoc-snd-tavil"; + qcom,model = "sdx-tavil-i2s-snd-card"; + qcom,prim_mi2s_aux_master = <&prim_master>; + qcom,prim_mi2s_aux_slave = <&prim_slave>; + qcom,sec_mi2s_aux_master = <&sec_master>; + qcom,sec_mi2s_aux_slave = <&sec_slave>; + + asoc-platform = <&pcm0>, <&pcm1>, <&voip>, <&voice>, + <&loopback>, <&hostless>, <&afe>, <&routing>, + <&pcm_dtmf>, <&host_pcm>, <&compress>; + asoc-platform-names = "msm-pcm-dsp.0", "msm-pcm-dsp.1", + "msm-voip-dsp", "msm-pcm-voice", + "msm-pcm-loopback", "msm-pcm-hostless", + "msm-pcm-afe", "msm-pcm-routing", + "msm-pcm-dtmf", "msm-voice-host-pcm", + "msm-compress-dsp"; + asoc-cpu = <&dai_pri_auxpcm>, <&mi2s_prim>, <&mi2s_sec>, + <&dtmf_tx>, + <&rx_capture_tx>, <&rx_playback_rx>, + <&tx_capture_tx>, <&tx_playback_rx>, + <&afe_pcm_rx>, <&afe_pcm_tx>, <&afe_proxy_rx>, + <&afe_proxy_tx>, <&incall_record_rx>, + <&incall_record_tx>, <&incall_music_rx>, + <&dai_sec_auxpcm>, <&incall2_record_rx>, + <&incall_music_2_rx>, <&incall_music_dl_rx>; + asoc-cpu-names = "msm-dai-q6-auxpcm.1", + "msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1", + "msm-dai-stub-dev.4", "msm-dai-stub-dev.5", + "msm-dai-stub-dev.6", "msm-dai-stub-dev.7", + "msm-dai-stub-dev.8", "msm-dai-q6-dev.224", + "msm-dai-q6-dev.225", "msm-dai-q6-dev.241", + "msm-dai-q6-dev.240", "msm-dai-q6-dev.32771", + "msm-dai-q6-dev.32772", "msm-dai-q6-dev.32773", + "msm-dai-q6-auxpcm.2", "msm-dai-q6-dev.32769", + "msm-dai-q6-dev.32770", "msm-dai-q6-dev.32774"; + }; From ccc3d7329b8e1c3843f5a272d39c12ffa752311b Mon Sep 17 00:00:00 2001 From: Elson Roy Serrao Date: Fri, 9 Oct 2020 07:32:01 -0700 Subject: [PATCH 52/88] ARM: dts: msm: Add interconnect entries for USB on sdxlemur Add interconnect paths for USB peripheral which is required to perform bus voting and related bandwidth constraints for USB functionality and throughput on sdxlemur. Change-Id: Id9e9843c2aad7da4d523f1e4e66d92add60a6b43 --- qcom/sdxlemur-usb.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/qcom/sdxlemur-usb.dtsi b/qcom/sdxlemur-usb.dtsi index d11cad741801..75246348e3cb 100644 --- a/qcom/sdxlemur-usb.dtsi +++ b/qcom/sdxlemur-usb.dtsi @@ -40,6 +40,11 @@ 0x1a4>; /* GSI_IF_STS */ qcom,dwc-usb3-msm-tx-fifo-size = <27696>; + interconnect-names = "usb-ddr", "usb-ipa", "ddr-usb"; + interconnects = <&system_noc MASTER_USB3 &mc_virt SLAVE_EBI1>, + <&system_noc MASTER_USB3 &system_noc SLAVE_IPA_CFG>, + <&mem_noc MASTER_APPSS_PROC &system_noc SLAVE_USB3>; + dwc3@a600000 { compatible = "snps,dwc3"; reg = <0x0a600000 0xcd00>; From 9cf313fc677809e3d50692fd5c33b232b906c2a4 Mon Sep 17 00:00:00 2001 From: Elson Roy Serrao Date: Thu, 8 Oct 2020 12:06:45 -0700 Subject: [PATCH 53/88] ARM: dts: msm: Enable board specific USB detection on sdxlemur Add USB detection through extcon based notification for sdxlemur MTP/CDP. Change-Id: I31ebe73e40dabafea6caa764e887ebf022fcc64f --- qcom/sdxlemur-cdp.dtsi | 4 ++++ qcom/sdxlemur-mtp.dtsi | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/qcom/sdxlemur-cdp.dtsi b/qcom/sdxlemur-cdp.dtsi index 0439a942f1ec..0b6dc2969cd6 100644 --- a/qcom/sdxlemur-cdp.dtsi +++ b/qcom/sdxlemur-cdp.dtsi @@ -7,3 +7,7 @@ &qnand_1 { status = "ok"; }; + +&usb { + extcon = <&vbus_detect>; +}; diff --git a/qcom/sdxlemur-mtp.dtsi b/qcom/sdxlemur-mtp.dtsi index 0439a942f1ec..0b6dc2969cd6 100644 --- a/qcom/sdxlemur-mtp.dtsi +++ b/qcom/sdxlemur-mtp.dtsi @@ -7,3 +7,7 @@ &qnand_1 { status = "ok"; }; + +&usb { + extcon = <&vbus_detect>; +}; From d93309e766182a2789007c53ef6346f57da62e53 Mon Sep 17 00:00:00 2001 From: Maulik Shah Date: Fri, 18 Sep 2020 12:57:41 +0530 Subject: [PATCH 54/88] ARM: dts: msm: Add PDC and RSC devices for yupik Add PDC interrupt controller along with apps and display RSC devices. Change-Id: If262200942bf8937dba7f04ee90f2683918da35d --- qcom/yupik-pinctrl.dtsi | 1 + qcom/yupik.dtsi | 50 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 51 insertions(+) diff --git a/qcom/yupik-pinctrl.dtsi b/qcom/yupik-pinctrl.dtsi index f878cb95d247..baa6f7f738b5 100644 --- a/qcom/yupik-pinctrl.dtsi +++ b/qcom/yupik-pinctrl.dtsi @@ -7,5 +7,6 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; + wakeup-parent = <&pdc>; }; }; diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index d5d4682d9a13..b94c29bff362 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -10,6 +10,7 @@ #include #include #include +#include #include / { @@ -326,6 +327,19 @@ interrupts = ; }; + pdc: interrupt-controller@b220000 { + compatible = "qcom,yupik-pdc"; + reg = <0xb220000 0x30000>, <0x17c000f0 0x60>; + qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, + <55 306 4>, <59 312 3>, <62 374 2>, + <64 434 2>, <66 438 3>, <69 86 1>, + <70 520 54>, <124 609 31>, <155 63 1>, + <156 716 12>; + #interrupt-cells = <2>; + interrupt-parent = <&intc>; + interrupt-controller; + }; + wdog: qcom,wdt@17c10000 { compatible = "qcom,msm-watchdog"; reg = <0x17c10000 0x1000>; @@ -759,6 +773,42 @@ compatible = "qcom,yupik-epss-l3-cpu"; #interconnect-cells = <1>; }; + + apps_rsc: rsc@18200000 { + label = "apps_rsc"; + compatible = "qcom,rpmh-rsc"; + reg = <0x18200000 0x10000>, + <0x18210000 0x10000>, + <0x18220000 0x10000>; + reg-names = "drv-0", "drv-1", "drv-2"; + interrupts = , + , + ; + qcom,tcs-offset = <0xd00>; + qcom,drv-id = <2>; + qcom,tcs-config = , + , + , + ; + + system_pm { + compatible = "qcom,system-pm"; + }; + }; + + disp_rsc: rsc@af20000 { + label = "disp_rsc"; + compatible = "qcom,rpmh-rsc"; + reg = <0xaf20000 0x10000>; + reg-names = "drv-0"; + interrupts = ; + qcom,tcs-offset = <0x1c00>; + qcom,drv-id = <0>; + qcom,tcs-config = , + , + , + ; + }; }; #include "shima-gdsc.dtsi" From 483746e4ea894b1e2f4eb3fcd53b2c2a7acc3be8 Mon Sep 17 00:00:00 2001 From: Maulik Shah Date: Fri, 18 Sep 2020 13:55:50 +0530 Subject: [PATCH 55/88] ARM: dts: msm: Add idle states and stats devices for yupik Add idle states for low power modes along with stats devices. Change-Id: I3d2accba322674fc6688a3b174c94701490c74d4 --- qcom/yupik-pm.dtsi | 185 +++++++++++++++++++++++++++++++++++++++++++++ qcom/yupik.dtsi | 9 +++ 2 files changed, 194 insertions(+) create mode 100644 qcom/yupik-pm.dtsi diff --git a/qcom/yupik-pm.dtsi b/qcom/yupik-pm.dtsi new file mode 100644 index 000000000000..cfd438443c3c --- /dev/null +++ b/qcom/yupik-pm.dtsi @@ -0,0 +1,185 @@ +&soc { + qcom,lpm-levels { + compatible = "qcom,lpm-levels"; + #address-cells = <1>; + #size-cells = <0>; + + qcom,pm-cluster@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + idle-state-name = "L3"; + qcom,clstr-tmr-add = <1000>; + qcom,psci-mode-shift = <4>; + qcom,psci-mode-mask = <0xfff>; + + CLUSTER_WFI: qcom,pm-cluster-level@0 { /* D1 */ + reg = <0>; + compatible = "arm,idle-state"; + idle-state-name = "l3-wfi"; + entry-latency-us = <660>; + exit-latency-us = <600>; + min-residency-us = <1260>; + arm,psci-suspend-param = <0x10>; + qcom,psci-mode = <0x1>; + }; + + CLUSTER_OFF: qcom,pm-cluster-level@1 { /* D4 */ + reg = <1>; + compatible = "arm,idle-state"; + idle-state-name = "l3-pc"; + entry-latency-us = <2752>; + exit-latency-us = <3048>; + min-residency-us = <6118>; + arm,psci-suspend-param = <0x40>; + qcom,psci-mode = <0x4>; + qcom,is-reset; + qcom,min-child-idx = <2>; + }; + + CX_OFF: qcom,pm-cluster-level@2 { /* Cx Off */ + reg = <2>; + compatible = "arm,idle-state"; + idle-state-name = "cx-off"; + entry-latency-us = <3263>; + exit-latency-us = <4562>; + min-residency-us = <8467>; + arm,psci-suspend-param = <0x2240>; + qcom,psci-mode = <0x224>; + qcom,is-reset; + qcom,notify-rpm; + qcom,min-child-idx = <2>; + }; + + LLCC_OFF: qcom,pm-cluster-level@3 { /* AOSS sleep */ + reg = <3>; + compatible = "arm,idle-state"; + idle-state-name = "llcc-off"; + entry-latency-us = <3638>; + exit-latency-us = <6562>; + min-residency-us = <9826>; + arm,psci-suspend-param = <0xc340>; + qcom,psci-mode = <0xc34>; + qcom,is-reset; + qcom,notify-rpm; + qcom,min-child-idx = <2>; + }; + + qcom,pm-cpu@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + qcom,psci-mode-shift = <0>; + qcom,psci-mode-mask = <0xf>; + qcom,ref-stddev = <500>; + qcom,tmr-add = <1000>; + qcom,ref-premature-cnt = <1>; + qcom,disable-ipi-prediction; + qcom,cpu = <&CPU0 &CPU1 &CPU2 &CPU3>; + + SLVR_WFI: qcom,pm-cpu-level@0 { /* C1 */ + reg = <0>; + compatible = "arm,idle-state"; + idle-state-name = "wfi"; + entry-latency-us = <61>; + exit-latency-us = <60>; + min-residency-us = <121>; + arm,psci-suspend-param = <0x1>; + qcom,psci-cpu-mode = <0x1>; + }; + + SLVR_OFF: qcom,pm-cpu-level@1 { /* C3 */ + reg = <1>; + compatible = "arm,idle-state"; + idle-state-name = "pc"; + entry-latency-us = <549>; + exit-latency-us = <901>; + min-residency-us = <1774>; + arm,psci-suspend-param = <0x40000003>; + qcom,psci-cpu-mode = <0x3>; + local-timer-stop; + qcom,is-reset; + qcom,use-broadcast-timer; + }; + + SLVR_RAIL_OFF: qcom,pm-cpu-level@2 { /* C4 */ + reg = <2>; + compatible = "arm,idle-state"; + idle-state-name = "rail-pc"; + entry-latency-us = <702>; + exit-latency-us = <915>; + min-residency-us = <4001>; + arm,psci-suspend-param = <0x40000004>; + qcom,psci-cpu-mode = <0x4>; + local-timer-stop; + qcom,is-reset; + qcom,use-broadcast-timer; + }; + }; + + qcom,pm-cpu@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + qcom,psci-mode-shift = <0>; + qcom,psci-mode-mask = <0xf>; + qcom,cpu = <&CPU4 &CPU5 &CPU6 &CPU7>; + + GOLD_WFI: qcom,pm-cpu-level@0 { /* C1 */ + reg = <0>; + compatible = "arm,idle-state"; + idle-state-name = "wfi"; + entry-latency-us = <55>; + exit-latency-us = <66>; + min-residency-us = <121>; + arm,psci-suspend-param = <0x1>; + qcom,psci-cpu-mode = <0x1>; + }; + + GOLD_OFF: qcom,pm-cpu-level@1 { /* C3 */ + reg = <1>; + compatible = "arm,idle-state"; + idle-state-name = "pc"; + entry-latency-us = <523>; + exit-latency-us = <1244>; + min-residency-us = <2207>; + arm,psci-suspend-param = <0x40000003>; + qcom,psci-cpu-mode = <0x3>; + local-timer-stop; + qcom,is-reset; + qcom,use-broadcast-timer; + }; + + GOLD_RAIL_OFF: qcom,pm-cpu-level@2 { /* C4 */ + reg = <2>; + compatible = "arm,idle-state"; + idle-state-name = "rail-pc"; + entry-latency-us = <526>; + exit-latency-us = <1854>; + min-residency-us = <5555>; + arm,psci-suspend-param = <0x40000004>; + qcom,psci-cpu-mode = <0x4>; + local-timer-stop; + qcom,is-reset; + qcom,use-broadcast-timer; + }; + }; + }; + }; + + rpmh-master-stats@b221200 { + compatible = "qcom,rpmh-master-stats-v1"; + reg = <0xb221200 0x60>; + }; + + soc-sleep-stats@c3f0000 { + compatible = "qcom,rpmh-sleep-stats"; + reg = <0xc3f0000 0x400>; + }; + + ddr-stats@c300000 { + compatible = "qcom,ddr-stats"; + reg = <0xc300000 0x1000>, <0xc3f001c 0x4>; + reg-names = "phys_addr_base", "offset_addr"; + }; +}; diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index b94c29bff362..6ccf7a17fccf 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -42,6 +42,7 @@ compatible = "qcom,kryo"; reg = <0x0 0x0>; enable-method = "psci"; + cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>; next-level-cache = <&L2_0>; L2_0: l2-cache { compatible = "arm,arch-cache"; @@ -60,6 +61,7 @@ compatible = "qcom,kryo"; reg = <0x0 0x100>; enable-method = "psci"; + cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>; next-level-cache = <&L2_1>; L2_1: l2-cache { compatible = "arm,arch-cache"; @@ -73,6 +75,7 @@ compatible = "qcom,kryo"; reg = <0x0 0x200>; enable-method = "psci"; + cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>; next-level-cache = <&L2_2>; L2_2: l2-cache { compatible = "arm,arch-cache"; @@ -86,6 +89,7 @@ compatible = "qcom,kryo"; reg = <0x0 0x300>; enable-method = "psci"; + cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>; next-level-cache = <&L2_3>; L2_3: l2-cache { compatible = "arm,arch-cache"; @@ -99,6 +103,7 @@ compatible = "qcom,kryo"; reg = <0x0 0x400>; enable-method = "psci"; + cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>; next-level-cache = <&L2_4>; L2_4: l2-cache { compatible = "arm,arch-cache"; @@ -112,6 +117,7 @@ compatible = "qcom,kryo"; reg = <0x0 0x500>; enable-method = "psci"; + cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>; next-level-cache = <&L2_5>; L2_5: l2-cache { compatible = "arm,arch-cache"; @@ -125,6 +131,7 @@ compatible = "qcom,kryo"; reg = <0x0 0x600>; enable-method = "psci"; + cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>; next-level-cache = <&L2_6>; L2_6: l2-cache { compatible = "arm,arch-cache"; @@ -138,6 +145,7 @@ compatible = "qcom,kryo"; reg = <0x0 0x700>; enable-method = "psci"; + cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>; next-level-cache = <&L2_7>; L2_7: l2-cache { compatible = "arm,arch-cache"; @@ -813,6 +821,7 @@ #include "shima-gdsc.dtsi" #include "yupik-pinctrl.dtsi" +#include "yupik-pm.dtsi" #include "yupik-stub-regulator.dtsi" &gcc_pcie_0_gdsc { From a5fa3d76462e432bfa20f0f5de33b4049b3055cc Mon Sep 17 00:00:00 2001 From: Pratham Pratap Date: Sun, 30 Aug 2020 16:06:52 +0530 Subject: [PATCH 56/88] ARM: dts: msm: Add USB nodes for Yupik Add USB nodes to support USB in peripheral mode on simulation platforms for Yupik. Change-Id: I5d73cde0fbcfb20eaa4fe578d9a65770c53965dc --- qcom/yupik-rumi.dtsi | 25 ++++++++++++++++ qcom/yupik-usb.dtsi | 68 ++++++++++++++++++++++++++++++++++++++++++++ qcom/yupik.dtsi | 2 ++ 3 files changed, 95 insertions(+) create mode 100644 qcom/yupik-usb.dtsi diff --git a/qcom/yupik-rumi.dtsi b/qcom/yupik-rumi.dtsi index 3d00135b89f8..a7544916452f 100644 --- a/qcom/yupik-rumi.dtsi +++ b/qcom/yupik-rumi.dtsi @@ -10,6 +10,31 @@ wdog: qcom,wdt@17c10000 { status = "disabled"; }; + + usb_emu_phy_0: usb_emu_phy@a720000 { + compatible = "qcom,usb-emu-phy"; + reg = <0x0a720000 0x9500>; + + qcom,emu-init-seq = <0xffff 0x4 + 0xfff0 0x4 + 0x100000 0x20 + 0x0 0x20 + 0x101f0 0x20 + 0x100000 0x3c + 0x0 0x3c + 0x10060 0x3c + 0x0 0x4>; + }; + +}; + +&usb0 { + /delete-property/ extcon; + dwc3@a600000 { + usb-phy = <&usb_emu_phy_0>, <&usb_nop_phy>; + maximum-speed = "high-speed"; + dr_mode = "peripheral"; + }; }; &ufsphy_mem { diff --git a/qcom/yupik-usb.dtsi b/qcom/yupik-usb.dtsi new file mode 100644 index 000000000000..0d8f7d16b223 --- /dev/null +++ b/qcom/yupik-usb.dtsi @@ -0,0 +1,68 @@ +#include + +&soc { + /* Primary USB port related controller */ + usb0: ssusb@a600000 { + compatible = "qcom,dwc-usb3-msm"; + reg = <0xa600000 0x100000>; + reg-names = "core_base"; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + interrupts-extended = <&pdc 14 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 15 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "dp_hs_phy_irq", "pwr_event_irq", + "ss_phy_irq", "dm_hs_phy_irq"; + qcom,use-pdc-interrupts; + + USB3_GDSC-supply = <&gcc_usb30_prim_gdsc>; + clocks = <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>; + clock-names = "core_clk", "iface_clk", "bus_aggr_clk", + "utmi_clk", "sleep_clk"; + + resets = <&gcc GCC_USB30_PRIM_BCR>; + reset-names = "core_reset"; + + qcom,core-clk-rate = <200000000>; + qcom,core-clk-rate-hs = <66666667>; + qcom,num-gsi-evt-buffs = <0x3>; + qcom,gsi-reg-offset = + <0x0fc /* GSI_GENERAL_CFG */ + 0x110 /* GSI_DBL_ADDR_L */ + 0x120 /* GSI_DBL_ADDR_H */ + 0x130 /* GSI_RING_BASE_ADDR_L */ + 0x144 /* GSI_RING_BASE_ADDR_H */ + 0x1a4>; /* GSI_IF_STS */ + qcom,dwc-usb3-msm-tx-fifo-size = <21288>; + + dwc3@a600000 { + compatible = "snps,dwc3"; + reg = <0xa600000 0xcd00>; + interrupts = ; + linux,sysdev_is_parent; + snps,disable-clk-gating; + snps,has-lpm-erratum; + snps,hird-threshold = /bits/ 8 <0x0>; + snps,is-utmi-l1-suspend; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,dis_u2_susphy_quirk; + snps,ssp-u3-u0-quirk; + tx-fifo-resize; + maximum-speed = "super-speed"; + dr_mode = "otg"; + }; + }; + + usb_nop_phy: usb_nop_phy { + compatible = "usb-nop-xceiv"; + }; +}; diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index b94c29bff362..838e6ceccece 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -930,3 +930,5 @@ compatible = "regulator-fixed"; status = "ok"; }; + +#include "yupik-usb.dtsi" From 6323c2618c18cd3cbd438e23fb3f43de866726cf Mon Sep 17 00:00:00 2001 From: Priyanka Gujjula Date: Mon, 12 Oct 2020 17:06:13 +0530 Subject: [PATCH 57/88] dt-bindings: media: Add video driver bindings for Yupik Add the video driver device tree bindings for Yupik. Change-Id: I2e71f1985d7a4a44d41fa1dd3303109826bc4c8b --- bindings/media/video/msm-vidc.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/bindings/media/video/msm-vidc.txt b/bindings/media/video/msm-vidc.txt index e5a9c64a7d52..80f10e86fbe2 100644 --- a/bindings/media/video/msm-vidc.txt +++ b/bindings/media/video/msm-vidc.txt @@ -9,6 +9,7 @@ Required properties: - "qcom,lahaina-vidc" : Invokes driver-specific data for LAHAINA. - "qcom,shima-vidc" : Invokes driver-specific data for SHIMA. - "qcom,holi-vidc" : Invokes driver-specific data for HOLI. + - "qcom,yupik-vidc" : Invokes driver-specific data for YUPIK. Optional properties: - vidc,firmware-name : Video Firmware ELF image name to be loaded by PIL From c626705f1f18b6e9f866c5cdeb3b4c7495c92098 Mon Sep 17 00:00:00 2001 From: Mohammed Siddiq Date: Mon, 12 Oct 2020 18:04:47 +0530 Subject: [PATCH 58/88] ARM: dts: msm: Update CNSS node for BT GPIO config for shima QCA6490 requires synchronization between BT and WLAN GPIOs for PMU power up. Update CNSS device tree node for BT GPIO config. Change-Id: I124eb63c2298ca6c1770021943b5998679cfbdad --- qcom/shima.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi index fd0b467f4806..a1ac1e1b6e00 100644 --- a/qcom/shima.dtsi +++ b/qcom/shima.dtsi @@ -3456,6 +3456,7 @@ reg = <0xb0000000 0x10000>; reg-names = "smmu_iova_ipa"; wlan-en-gpio = <&tlmm 64 0>; + qcom,bt-en-gpio = <&tlmm 65 0>; pinctrl-names = "wlan_en_active", "wlan_en_sleep"; pinctrl-0 = <&cnss_wlan_en_active>; pinctrl-1 = <&cnss_wlan_en_sleep>; From b4f346531e16476be1a692bb308673e3d12625ae Mon Sep 17 00:00:00 2001 From: Jishnu Prakash Date: Fri, 4 Sep 2020 14:28:47 +0530 Subject: [PATCH 59/88] ARM: dts: msm: Update S3A min and init voltages for holi Update SMPS regulator S3A's minimum voltage to RPM_SMD_REGULATOR_LEVEL_NONE and init voltage to RPM_SMD_REGULATOR_LEVEL_LOW_SVS to enable GFX rail collapse for RBSC. Change-Id: Ia768244b267af223ca57f441d80395dd295fc8a8 --- qcom/holi-regulators.dtsi | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/qcom/holi-regulators.dtsi b/qcom/holi-regulators.dtsi index 7d2ca92fd40e..df74687f3251 100644 --- a/qcom/holi-regulators.dtsi +++ b/qcom/holi-regulators.dtsi @@ -32,9 +32,11 @@ regulator-name = "pm6350_s3_level"; qcom,set = <3>; regulator-min-microvolt = - ; + ; regulator-max-microvolt = ; + qcom,init-voltage-level = + ; qcom,use-voltage-level; }; From 624a78e9e352a31a4b26e809b3864bbb4cca58dd Mon Sep 17 00:00:00 2001 From: Santosh Mardi Date: Mon, 12 Oct 2020 17:49:15 +0530 Subject: [PATCH 60/88] ARM: dts: msm: update ddr mapping table for shima target Update ddr mapping table for cpu7 latfloor and cpu0-llcc-ddr-lat voting device. Change-Id: I9f2249bb7ae44665627379bb887a2490d2882d01 --- qcom/shima.dtsi | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi index fd0b467f4806..650f05e7da66 100644 --- a/qcom/shima.dtsi +++ b/qcom/shima.dtsi @@ -2550,7 +2550,6 @@ ddr4-map { qcom,ddr-type = ; qcom,core-dev-table = - < 691200 MHZ_TO_MBPS( 300, 4) >, < 940800 MHZ_TO_MBPS( 451, 4) >, < 1171200 MHZ_TO_MBPS( 547, 4) >, < 1516800 MHZ_TO_MBPS( 768, 4) >, @@ -2560,7 +2559,6 @@ ddr5-map { qcom,ddr-type = ; qcom,core-dev-table = - < 691200 MHZ_TO_MBPS( 300, 4) >, < 940800 MHZ_TO_MBPS( 451, 4) >, < 1171200 MHZ_TO_MBPS( 547, 4) >, < 1516800 MHZ_TO_MBPS( 768, 4) >, @@ -2667,14 +2665,14 @@ ddr4-map { qcom,ddr-type = ; qcom,core-dev-table = - < 2361600 MHZ_TO_MBPS( 300, 4) >, + < 2361600 MHZ_TO_MBPS( 451, 4) >, < 2707200 MHZ_TO_MBPS(2133, 4) >; }; ddr5-map { qcom,ddr-type = ; qcom,core-dev-table = - < 2361600 MHZ_TO_MBPS( 300, 4) >, + < 2361600 MHZ_TO_MBPS( 451, 4) >, < 2707200 MHZ_TO_MBPS(3196, 4) >; }; }; From cec50a1874601f45b968dbd452320f60abc8a61a Mon Sep 17 00:00:00 2001 From: Tushar Nimkar Date: Sun, 11 Oct 2020 12:24:52 +0530 Subject: [PATCH 61/88] ARM: dts: msm: Fix command DB address for sdxlemur This changes the command DB address to correct value. Change-Id: I43bbeae4c6283f6cc3f4dbba382fe76c474fef70 --- qcom/sdxlemur.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index d876a6473abb..7ede38d6815d 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -31,10 +31,10 @@ #size-cells = <1>; ranges; - cmd_db: reserved-memory@8fe20000 { + cmd_db: reserved-memory@8fee0000 { compatible = "qcom,cmd-db"; no-map; - reg = <0x8fe20000 0x20000>; + reg = <0x8fee0000 0x20000>; }; mpss_adsp_mem: mpss_adsp_region@90800000 { From 78d5e84a022c55f540fb37008d5dd0d68742b46f Mon Sep 17 00:00:00 2001 From: Naina Mehta Date: Mon, 5 Oct 2020 16:21:14 +0530 Subject: [PATCH 62/88] dt-bindings: Add qfprom-sys documentation qfprom-sys can be used to export nvmem cell values as sysfs entries to user space. Change-Id: I2bcbf1bbfc0ac187e6f2b7c177b0f2bc14ca654e --- bindings/arm/msm/qcom,qfprom-sys.yaml | 36 +++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) create mode 100644 bindings/arm/msm/qcom,qfprom-sys.yaml diff --git a/bindings/arm/msm/qcom,qfprom-sys.yaml b/bindings/arm/msm/qcom,qfprom-sys.yaml new file mode 100644 index 000000000000..e0da6ada6ff7 --- /dev/null +++ b/bindings/arm/msm/qcom,qfprom-sys.yaml @@ -0,0 +1,36 @@ +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bindings/arm/msm/qcom,qfprom-sys.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. QFPROM_SYS driver binding + +maintainers: + +description: |+ + QFPROM_SYS provides access to the nvmem cells to the user space. + The driver exports the cell values as sysfs entries. + +properties: + compatible: + const: qcom,qfprom-sys + + nvmem-cell-name: + description: array of strings for cell names + + nvmem-cells: + description: phandle to particular cell from provider + +required: + - compatible + - nvmem-cell-name + - nvmem-cells + +example: + - | + qfprom@0 { + compatible = "qcom,qfprom-sys"; + nvmem-cells = <&tsens_calibration1>, <&tsens_calibration2>; + nvmem-cell-names = "calibration1", "calibration2"; + }; +... From f023fb6a0f1979fe1793f5c3f07805177f3a2279 Mon Sep 17 00:00:00 2001 From: Naina Mehta Date: Mon, 5 Oct 2020 15:49:43 +0530 Subject: [PATCH 63/88] ARM: dts: msm: Export qfprom cell to userspace Add support to export qfprom cell values as sysfs entries to userspace. Change-Id: Id4ab00e095c23d195fe017c023099dd100a6eb76 --- qcom/holi.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/qcom/holi.dtsi b/qcom/holi.dtsi index 1d8a294b6fd4..2798bc18d4f9 100644 --- a/qcom/holi.dtsi +++ b/qcom/holi.dtsi @@ -2719,6 +2719,21 @@ reg = <0x6028 0x4>; }; }; + + qfprom_sys: qfprom@0 { + compatible = "qcom,qfprom-sys"; + + nvmem-cells = <&gpu_speed_bin>, + <&adsp_variant>, + <&feat_conf8>, + <&gpu_gaming_bin>, + <&feat_conf9>; + nvmem-cell-names = "gpu_speed_bin", + "adsp_variant", + "feat_conf8", + "gpu_gaming_bin", + "feat_conf9"; + }; }; #include "holi-gpu.dtsi" From 9cb3a6ad060807ce13ef17555a9708f7bc90a119 Mon Sep 17 00:00:00 2001 From: Satish Babu Patakokila Date: Mon, 28 Sep 2020 11:09:33 +0530 Subject: [PATCH 64/88] ARM: dts: msm: add audio routings sdxlemur Add device tree entries for sdxlemur Change-Id: I8a89a2248d6957d8a7445750e27259d3940785e5 --- qcom/sdx-audio-lpass.dtsi | 336 +++++++++++++++++++++++++++++ qcom/sdx-wsa881x.dtsi | 36 ++++ qcom/sdxlemur-audio-overlay.dtsi | 130 +++++++++++ qcom/sdxlemur-audio.dtsi | 43 ++++ qcom/sdxlemur-pinctrl.dtsi | 356 +++++++++++++++++++++++++++++++ qcom/sdxlemur-wcd.dtsi | 68 ++++++ qcom/sdxlemur.dtsi | 31 +++ 7 files changed, 1000 insertions(+) create mode 100644 qcom/sdx-audio-lpass.dtsi create mode 100644 qcom/sdx-wsa881x.dtsi create mode 100644 qcom/sdxlemur-audio-overlay.dtsi create mode 100644 qcom/sdxlemur-audio.dtsi create mode 100644 qcom/sdxlemur-wcd.dtsi diff --git a/qcom/sdx-audio-lpass.dtsi b/qcom/sdx-audio-lpass.dtsi new file mode 100644 index 000000000000..8a5b8374ea3f --- /dev/null +++ b/qcom/sdx-audio-lpass.dtsi @@ -0,0 +1,336 @@ +&soc { + spf_core_platform: spf_core_platform { + compatible = "qcom,spf-core-platform"; + }; + + audio_pkt_core_platform: audio-pkt-platform { + compatible = "qcom,audio-pkt-core-platform"; + }; + + qcom,msm-adsp-loader { + compatible = "qcom,adsp-loader"; + qcom,adsp-state = <0>; + qcom,proc-img-to-load = "modem"; + }; + + qcom,msm-audio-ion { + compatible = "qcom,msm-audio-ion"; + memory-region = <&audio_mem>; + }; + + pcm0: qcom,msm-pcm { + compatible = "qcom,msm-pcm-dsp"; + qcom,msm-pcm-dsp-id = <0>; + }; + + routing: qcom,msm-pcm-routing { + compatible = "qcom,msm-pcm-routing"; + }; + + pcm1: qcom,msm-pcm-low-latency { + compatible = "qcom,msm-pcm-dsp"; + qcom,msm-pcm-dsp-id = <1>; + qcom,msm-pcm-low-latency; + qcom,latency-level = "ultra"; + }; + + qcom,msm-compr-dsp { + compatible = "qcom,msm-compr-dsp"; + }; + + voip: qcom,msm-voip-dsp { + compatible = "qcom,msm-voip-dsp"; + }; + + voice: qcom,msm-pcm-voice { + compatible = "qcom,msm-pcm-voice"; + qcom,destroy-cvd; + }; + + stub_codec: qcom,msm-stub-codec { + compatible = "qcom,msm-stub-codec"; + }; + + qcom,msm-dai-fe { + compatible = "qcom,msm-dai-fe"; + }; + + afe: qcom,msm-pcm-afe { + compatible = "qcom,msm-pcm-afe"; + }; + + hostless: qcom,msm-pcm-hostless { + compatible = "qcom,msm-pcm-hostless"; + }; + + audio_apr: qcom,msm-audio-apr { + compatible = "qcom,msm-audio-apr"; + qcom,subsys-name = "apr_modem"; + }; + + host_pcm: qcom,msm-voice-host-pcm { + compatible = "qcom,msm-voice-host-pcm"; + }; + + loopback: qcom,msm-pcm-loopback { + compatible = "qcom,msm-pcm-loopback"; + }; + + compress: qcom,msm-compress-dsp { + compatible = "qcom,msm-compress-dsp"; + qcom,adsp-version = "MDSP 1.2"; + }; + + qcom,msm-dai-stub { + compatible = "qcom,msm-dai-stub"; + dtmf_tx: qcom,msm-dai-stub-dtmf-tx { + compatible = "qcom,msm-dai-stub-dev"; + qcom,msm-dai-stub-dev-id = <4>; + }; + + rx_capture_tx: qcom,msm-dai-stub-host-rx-capture-tx { + compatible = "qcom,msm-dai-stub-dev"; + qcom,msm-dai-stub-dev-id = <5>; + }; + + rx_playback_rx: qcom,msm-dai-stub-host-rx-playback-rx { + compatible = "qcom,msm-dai-stub-dev"; + qcom,msm-dai-stub-dev-id = <6>; + }; + + tx_capture_tx: qcom,msm-dai-stub-host-tx-capture-tx { + compatible = "qcom,msm-dai-stub-dev"; + qcom,msm-dai-stub-dev-id = <7>; + }; + + tx_playback_rx: qcom,msm-dai-stub-host-tx-playback-rx { + compatible = "qcom,msm-dai-stub-dev"; + qcom,msm-dai-stub-dev-id = <8>; + }; + }; + + qcom,msm-dai-q6 { + compatible = "qcom,msm-dai-q6"; + afe_pcm_rx: qcom,msm-dai-q6-be-afe-pcm-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <224>; + }; + + afe_pcm_tx: qcom,msm-dai-q6-be-afe-pcm-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <225>; + }; + + afe_proxy_rx: qcom,msm-dai-q6-afe-proxy-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <241>; + }; + + afe_proxy_tx: qcom,msm-dai-q6-afe-proxy-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <240>; + }; + + incall_record_rx: qcom,msm-dai-q6-incall-record-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <32771>; + }; + + incall_record_tx: qcom,msm-dai-q6-incall-record-tx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <32772>; + }; + + incall_music_rx: qcom,msm-dai-q6-incall-music-rx { + compatible = "qcom,msm-dai-q6-dev"; + qcom,msm-dai-q6-dev-id = <32773>; + }; + }; + + pcm_dtmf: qcom,msm-pcm-dtmf { + compatible = "qcom,msm-pcm-dtmf"; + }; + + dai_pri_auxpcm: qcom,msm-pri-auxpcm { + compatible = "qcom,msm-auxpcm-dev"; + qcom,msm-cpudai-auxpcm-mode = <0>, <0>; + qcom,msm-cpudai-auxpcm-sync = <1>, <1>; + qcom,msm-cpudai-auxpcm-frame = <5>, <4>; + qcom,msm-cpudai-auxpcm-quant = <2>, <2>; + qcom,msm-cpudai-auxpcm-num-slots = <1>, <1>; + qcom,msm-cpudai-auxpcm-slot-mapping = <1>, <1>; + qcom,msm-cpudai-auxpcm-data = <0>, <0>; + qcom,msm-cpudai-auxpcm-pcm-clk-rate = <2048000>, <2048000>; + qcom,msm-auxpcm-interface = "primary"; + qcom,msm-cpudai-afe-clk-ver = <2>; + }; + + dai_sec_auxpcm: qcom,msm-sec-auxpcm { + compatible = "qcom,msm-auxpcm-dev"; + qcom,msm-cpudai-auxpcm-mode = <0>, <0>; + qcom,msm-cpudai-auxpcm-sync = <1>, <1>; + qcom,msm-cpudai-auxpcm-frame = <5>, <4>; + qcom,msm-cpudai-auxpcm-quant = <2>, <2>; + qcom,msm-cpudai-auxpcm-num-slots = <1>, <1>; + qcom,msm-cpudai-auxpcm-slot-mapping = <1>, <1>; + qcom,msm-cpudai-auxpcm-data = <0>, <0>; + qcom,msm-cpudai-auxpcm-pcm-clk-rate = <2048000>, <2048000>; + qcom,msm-auxpcm-interface = "secondary"; + qcom,msm-cpudai-afe-clk-ver = <2>; + }; + + qcom,msm-dai-tdm-pri-rx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37120>; + qcom,msm-cpudai-tdm-group-num-ports = <1>; + qcom,msm-cpudai-tdm-group-port-id = <36864>; + qcom,msm-cpudai-tdm-clk-rate = <12288000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <0>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <1>; + qcom,msm-cpudai-tdm-clk-attribute = /bits/ 16 <1>; + dai_pri_tdm_rx_0: qcom,msm-dai-q6-tdm-pri-rx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36864>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + + }; + + qcom,msm-dai-tdm-pri-tx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37121>; + qcom,msm-cpudai-tdm-group-num-ports = <1>; + qcom,msm-cpudai-tdm-group-port-id = <36865>; + qcom,msm-cpudai-tdm-clk-rate = <12288000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <0>; + qcom,msm-cpudai-tdm-sync-src = <1>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <1>; + qcom,msm-cpudai-tdm-clk-attribute = /bits/ 16 <1>; + dai_pri_tdm_tx_0: qcom,msm-dai-q6-tdm-pri-tx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36865>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + qcom,msm-dai-tdm-sec-rx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37136>; + qcom,msm-cpudai-tdm-group-num-ports = <1>; + qcom,msm-cpudai-tdm-group-port-id = <36880>; + qcom,msm-cpudai-tdm-clk-rate = <12288000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <0>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <0>; + dai_sec_tdm_rx_0: qcom,msm-dai-q6-tdm-sec-rx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36880>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + qcom,msm-dai-tdm-sec-tx { + compatible = "qcom,msm-dai-tdm"; + qcom,msm-cpudai-tdm-group-id = <37137>; + qcom,msm-cpudai-tdm-group-num-ports = <1>; + qcom,msm-cpudai-tdm-group-port-id = <36881>; + qcom,msm-cpudai-tdm-clk-rate = <12288000>; + qcom,msm-cpudai-tdm-clk-internal = <1>; + qcom,msm-cpudai-tdm-sync-mode = <1>; + qcom,msm-cpudai-tdm-sync-src = <0>; + qcom,msm-cpudai-tdm-data-out = <0>; + qcom,msm-cpudai-tdm-invert-sync = <0>; + qcom,msm-cpudai-tdm-data-delay = <0>; + dai_sec_tdm_tx_0: qcom,msm-dai-q6-tdm-sec-tx-0 { + compatible = "qcom,msm-dai-q6-tdm"; + qcom,msm-cpudai-tdm-dev-id = <36881>; + qcom,msm-cpudai-tdm-data-align = <0>; + }; + }; + + qcom,msm-dai-mi2s { + compatible = "qcom,msm-dai-mi2s"; + mi2s_prim: qcom,msm-dai-q6-mi2s-prim { + compatible = "qcom,msm-dai-q6-mi2s"; + qcom,msm-dai-q6-mi2s-dev-id = <0>; + qcom,msm-mi2s-rx-lines = <2>; + qcom,msm-mi2s-tx-lines = <1>; + }; + + mi2s_sec: qcom,msm-dai-q6-mi2s-sec { + compatible = "qcom,msm-dai-q6-mi2s"; + qcom,msm-dai-q6-mi2s-dev-id = <1>; + qcom,msm-mi2s-rx-lines = <2>; + qcom,msm-mi2s-tx-lines = <1>; + }; + + }; + + prim_master: prim_master_pinctrl { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&pri_ws_active_master + &pri_sck_active_master + &pri_dout_active + &pri_din_active>; + pinctrl-1 = <&pri_ws_sleep + &pri_sck_sleep + &pri_dout_sleep + &pri_din_sleep>; + qcom,mi2s-auxpcm-cdc-gpios; + }; + + prim_slave: prim_slave_pinctrl { + status = "disabled"; + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&pri_ws_active_slave + &pri_sck_active_slave + &pri_dout_active + &pri_din_active>; + pinctrl-1 = <&pri_ws_sleep + &pri_sck_sleep + &pri_dout_sleep + &pri_din_sleep>; + qcom,mi2s-auxpcm-cdc-gpios; + }; + + sec_master: sec_master_pinctrl { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&sec_ws_active_master + &sec_sck_active_master + &sec_dout_active + &sec_din_active>; + pinctrl-1 = <&sec_ws_sleep + &sec_sck_sleep + &sec_dout_sleep + &sec_din_sleep>; + qcom,mi2s-auxpcm-cdc-gpios; + }; + + sec_slave: sec_slave_pinctrl { + status = "disabled"; + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&sec_ws_active_slave + &sec_sck_active_slave + &sec_dout_active + &sec_din_active>; + pinctrl-1 = <&sec_ws_sleep + &sec_sck_sleep + &sec_dout_sleep + &sec_din_sleep>; + qcom,mi2s-auxpcm-cdc-gpios; + }; +}; diff --git a/qcom/sdx-wsa881x.dtsi b/qcom/sdx-wsa881x.dtsi new file mode 100644 index 000000000000..4cf0330514ff --- /dev/null +++ b/qcom/sdx-wsa881x.dtsi @@ -0,0 +1,36 @@ +&soc { + tavil_codec { + swr_master { + compatible = "qcom,swr-wcd"; + #address-cells = <2>; + #size-cells = <0>; + + wsa881x_0211: wsa881x@20170211 { + status = "disabled"; + compatible = "qcom,wsa881x"; + reg = <0x00 0x20170211>; + qcom,spkr-sd-n-node = <&wsa_spkr_wcd_sd1>; + }; + + wsa881x_0212: wsa881x@20170212 { + status = "disabled"; + compatible = "qcom,wsa881x"; + reg = <0x00 0x20170212>; + qcom,spkr-sd-n-node = <&wsa_spkr_wcd_sd2>; + }; + + wsa881x_0213: wsa881x@21170213 { + status = "disabled"; + compatible = "qcom,wsa881x"; + reg = <0x00 0x21170213>; + qcom,spkr-sd-n-node = <&wsa_spkr_wcd_sd1>; + }; + + wsa881x_0214: wsa881x@21170214 { + compatible = "qcom,wsa881x"; + reg = <0x00 0x21170214>; + qcom,spkr-sd-n-node = <&wsa_spkr_wcd_sd2>; + }; + }; + }; +}; diff --git a/qcom/sdxlemur-audio-overlay.dtsi b/qcom/sdxlemur-audio-overlay.dtsi new file mode 100644 index 000000000000..950bc2e383a5 --- /dev/null +++ b/qcom/sdxlemur-audio-overlay.dtsi @@ -0,0 +1,130 @@ +#include "sdxlemur-wcd.dtsi" +#include "sdx-wsa881x.dtsi" +#include + +&snd_934x { + qcom,audio-routing = + "RX_BIAS", "MCLK", + "MADINPUT", "MCLK", + "AMIC2", "MIC BIAS2", + "MIC BIAS2", "Headset Mic", + "AMIC3", "MIC BIAS2", + "MIC BIAS2", "ANCRight Headset Mic", + "AMIC4", "MIC BIAS2", + "MIC BIAS2", "ANCLeft Headset Mic", + "AMIC5", "MIC BIAS3", + "MIC BIAS3", "Handset Mic", + "DMIC1", "MIC BIAS1", + "MIC BIAS1", "Digital Mic1", + "DMIC2", "MIC BIAS3", + "MIC BIAS3", "Digital Mic2", + "DMIC3", "MIC BIAS3", + "MIC BIAS3", "Digital Mic3", + "DMIC4", "MIC BIAS4", + "MIC BIAS4", "Digital Mic4", + "DMIC5", "MIC BIAS4", + "MIC BIAS4", "Digital Mic5", + "SpkrRight IN", "SPK2 OUT"; + + qcom,msm-mbhc-hphl-swh = <1>; + qcom,msm-mbhc-gnd-swh = <1>; + qcom,msm-mbhc-hs-mic-max-threshold-mv = <1700>; + qcom,msm-mbhc-hs-mic-min-threshold-mv = <50>; + qcom,cdc-ext-clk-rate = <19200000>; + qcom,tavil-mclk-clk-freq = <9600000>; + + asoc-codec = <&stub_codec>; + asoc-codec-names = "msm-stub-codec.1"; + + qcom,wsa-max-devs = <2>; + qcom,wsa-devs = <&wsa881x_0211>, <&wsa881x_0212>, + <&wsa881x_0213>, <&wsa881x_0214>; + qcom,wsa-aux-dev-prefix = "SpkrLeft", "SpkrRight", + "SpkrLeft", "SpkrRight"; +}; + +&soc { + wcd9xxx_intc: wcd9xxx-irq { + status = "ok"; + compatible = "qcom,wcd9xxx-irq"; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&tlmm>; + qcom,gpio-connect = <&tlmm 96 0>; + pinctrl-names = "default"; + pinctrl-0 = <&wcd_intr_default>; + }; + + clock_audio_up: audio_ext_clk_up { + compatible = "qcom,audio-ref-clk"; + qcom,codec-ext-clk-src = ; + qcom,codec-lpass-clk-id = <770>; + qcom,codec-lpass-ext-clk-freq = <9600000>; + qcom,use-pinctrl = <1>; + pinctrl-names = "sleep", "active"; + pinctrl-0 = <&i2s_mclk_sleep>; + pinctrl-1 = <&i2s_mclk_active>; + #clock-cells = <1>; + }; + + wcd_rst_gpio: msm_cdc_pinctrl@92 { + compatible = "qcom,msm-cdc-pinctrl"; + qcom,cdc-rst-n-gpio = <&tlmm 92 0>; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&cdc_reset_active>; + pinctrl-1 = <&cdc_reset_sleep>; + }; +}; + +&soc { + wcd934x_cdc: tavil_codec { + compatible = "qcom,tavil-i2c"; + reg = <0x0d>; + + interrupt-parent = <&wcd9xxx_intc>; + interrupts = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 + 17 18 19 20 21 22 23 24 25 26 27 28 29 + 30 31>; + + qcom,wcd-rst-gpio-node = <&wcd_rst_gpio>; + + clock-names = "wcd_clk"; + clocks = <&clock_audio_up 0>; + + cdc-vdd-buck-supply = <&pmxprairie_l6>; + qcom,cdc-vdd-buck-voltage = <1800000 1800000>; + qcom,cdc-vdd-buck-current = <650000>; + + cdc-buck-sido-supply = <&pmxprairie_l6>; + qcom,cdc-buck-sido-voltage = <1800000 1800000>; + qcom,cdc-buck-sido-current = <250000>; + + cdc-vdd-tx-h-supply = <&pmxprairie_l6>; + qcom,cdc-vdd-tx-h-voltage = <1800000 1800000>; + qcom,cdc-vdd-tx-h-current = <25000>; + + cdc-vdd-rx-h-supply = <&pmxprairie_l6>; + qcom,cdc-vdd-rx-h-voltage = <1800000 1800000>; + qcom,cdc-vdd-rx-h-current = <25000>; + + cdc-vddpx-1-supply = <&pmxprairie_l6>; + qcom,cdc-vddpx-1-voltage = <1800000 1800000>; + qcom,cdc-vddpx-1-current = <10000>; + + qcom,cdc-static-supplies = "cdc-vdd-buck", + "cdc-buck-sido", + "cdc-vdd-tx-h", + "cdc-vdd-rx-h", + "cdc-vddpx-1"; + + qcom,cdc-micbias1-mv = <1800>; + qcom,cdc-micbias2-mv = <1800>; + qcom,cdc-micbias3-mv = <1800>; + qcom,cdc-micbias4-mv = <1800>; + + qcom,cdc-mclk-clk-rate = <9600000>; + qcom,cdc-dmic-sample-rate = <4800000>; + + qcom,wdsp-cmpnt-dev-name = "tavil_codec"; + }; +}; diff --git a/qcom/sdxlemur-audio.dtsi b/qcom/sdxlemur-audio.dtsi new file mode 100644 index 000000000000..30535b3a51d6 --- /dev/null +++ b/qcom/sdxlemur-audio.dtsi @@ -0,0 +1,43 @@ +#include "sdx-audio-lpass.dtsi" + +&soc { + snd_934x: sound-tavil { + compatible = "qcom,sdx-asoc-snd-tavil"; + qcom,model = "sdx-tavil-i2s-snd-card"; + qcom,prim_mi2s_aux_master = <&prim_master>; + qcom,prim_mi2s_aux_slave = <&prim_slave>; + qcom,sec_mi2s_aux_master = <&sec_master>; + qcom,sec_mi2s_aux_slave = <&sec_slave>; + + asoc-platform = <&pcm0>, <&pcm1>, <&voip>, <&voice>, + <&loopback>, <&hostless>, <&afe>, <&routing>, + <&pcm_dtmf>, <&host_pcm>, <&compress>; + asoc-platform-names = "msm-pcm-dsp.0", "msm-pcm-dsp.1", + "msm-voip-dsp", "msm-pcm-voice", + "msm-pcm-loopback", "msm-pcm-hostless", + "msm-pcm-afe", "msm-pcm-routing", + "msm-pcm-dtmf", "msm-voice-host-pcm", + "msm-compress-dsp"; + asoc-cpu = <&dai_pri_auxpcm>, <&mi2s_prim>, <&mi2s_sec>, + <&dtmf_tx>, + <&rx_capture_tx>, <&rx_playback_rx>, + <&tx_capture_tx>, <&tx_playback_rx>, + <&afe_pcm_rx>, <&afe_pcm_tx>, <&afe_proxy_rx>, + <&afe_proxy_tx>, <&incall_record_rx>, + <&incall_record_tx>, <&incall_music_rx>, + <&dai_pri_tdm_rx_0>, <&dai_pri_tdm_tx_0>, + <&dai_sec_tdm_rx_0>, <&dai_sec_tdm_tx_0>, + <&dai_sec_auxpcm>; + asoc-cpu-names = "msm-dai-q6-auxpcm.1", + "msm-dai-q6-mi2s.0", "msm-dai-q6-mi2s.1", + "msm-dai-stub-dev.4", "msm-dai-stub-dev.5", + "msm-dai-stub-dev.6", "msm-dai-stub-dev.7", + "msm-dai-stub-dev.8", "msm-dai-q6-dev.224", + "msm-dai-q6-dev.225", "msm-dai-q6-dev.241", + "msm-dai-q6-dev.240", "msm-dai-q6-dev.32771", + "msm-dai-q6-dev.32772", "msm-dai-q6-dev.32773", + "msm-dai-q6-tdm.36864", "msm-dai-q6-tdm.36865", + "msm-dai-q6-tdm.36880", "msm-dai-q6-tdm.36881", + "msm-dai-q6-auxpcm.2"; + }; +}; diff --git a/qcom/sdxlemur-pinctrl.dtsi b/qcom/sdxlemur-pinctrl.dtsi index fde920065f0b..ef506863a580 100644 --- a/qcom/sdxlemur-pinctrl.dtsi +++ b/qcom/sdxlemur-pinctrl.dtsi @@ -996,5 +996,361 @@ }; }; }; + wcd9xxx_intr { + wcd_intr_default: wcd_intr_default { + mux { + pins = "gpio96"; + function = "gpio"; + }; + + config { + pins = "gpio96"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* pull down */ + input-enable; + }; + }; + }; + + cdc_reset_ctrl { + cdc_reset_sleep: cdc_reset_sleep { + mux { + pins = "gpio92"; + function = "gpio"; + }; + + config { + pins = "gpio92"; + drive-strength = <2>; + bias-disable; + output-low; + }; + }; + + cdc_reset_active:cdc_reset_active { + mux { + pins = "gpio92"; + function = "gpio"; + }; + + config { + pins = "gpio92"; + drive-strength = <8>; + bias-pull-down; + output-high; + }; + }; + }; + + i2s_mclk { + i2s_mclk_sleep: i2s_mclk_sleep { + mux { + pins = "gpio62"; + function = "i2s_mclk"; + }; + + config { + pins = "gpio62"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + }; + }; + + i2s_mclk_active: i2s_mclk_active { + mux { + pins = "gpio62"; + function = "i2s_mclk"; + }; + + config { + pins = "gpio62"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL*/ + output-high; + }; + }; + }; + + pmx_pri_mi2s_aux { + pri_ws_sleep: pri_ws_sleep { + mux { + pins = "gpio12"; + function = "gpio"; + }; + + config { + pins = "gpio12"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_sck_sleep: pri_sck_sleep { + mux { + pins = "gpio15"; + function = "gpio"; + }; + + config { + pins = "gpio15"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_dout_sleep: pri_dout_sleep { + mux { + pins = "gpio14"; + function = "gpio"; + }; + + config { + pins = "gpio14"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_ws_active_master: pri_ws_active_master { + mux { + pins = "gpio12"; + function = "pri_mi2s"; + }; + + config { + pins = "gpio12"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL*/ + output-high; + }; + }; + + pri_sck_active_master: pri_sck_active_master { + mux { + pins = "gpio15"; + function = "pri_mi2s"; + }; + + config { + pins = "gpio15"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL*/ + output-high; + }; + }; + + pri_ws_active_slave: pri_ws_active_slave { + mux { + pins = "gpio12"; + function = "pri_mi2s"; + }; + + config { + pins = "gpio12"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL*/ + }; + }; + + pri_sck_active_slave: pri_sck_active_slave { + mux { + pins = "gpio15"; + function = "pri_mi2s"; + }; + + config { + pins = "gpio15"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL*/ + }; + }; + + pri_dout_active: pri_dout_active { + mux { + pins = "gpio14"; + function = "pri_mi2s"; + }; + + config { + pins = "gpio14"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL*/ + output-high; + }; + }; + }; + + pmx_pri_mi2s_aux_din { + pri_din_sleep: pri_din_sleep { + mux { + pins = "gpio13"; + function = "gpio"; + }; + + config { + pins = "gpio13"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + pri_din_active: pri_din_active { + mux { + pins = "gpio13"; + function = "pri_mi2s"; + }; + + config { + pins = "gpio13"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; + + pmx_sec_mi2s_aux { + sec_ws_sleep: sec_ws_sleep { + mux { + pins = "gpio16"; + function = "gpio"; + }; + + config { + pins = "gpio16"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_sck_sleep: sec_sck_sleep { + mux { + pins = "gpio19"; + function = "gpio"; + }; + + config { + pins = "gpio19"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_dout_sleep: sec_dout_sleep { + mux { + pins = "gpio18"; + function = "gpio"; + }; + + config { + pins = "gpio18"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; /* PULL DOWN */ + input-enable; + }; + }; + + sec_ws_active_master: sec_ws_active_master { + mux { + pins = "gpio16"; + function = "sec_mi2s"; + }; + + config { + pins = "gpio16"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL*/ + output-high; + }; + }; + + sec_sck_active_master: sec_sck_active_master { + mux { + pins = "gpio19"; + function = "sec_mi2s"; + }; + + config { + pins = "gpio19"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL*/ + output-high; + }; + }; + + sec_ws_active_slave: sec_ws_active_slave { + mux { + pins = "gpio16"; + function = "sec_mi2s"; + }; + + config { + pins = "gpio16"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL*/ + }; + }; + + sec_sck_active_slave: sec_sck_active_slave { + mux { + pins = "gpio19"; + function = "sec_mi2s"; + }; + + config { + pins = "gpio19"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL*/ + }; + }; + + sec_dout_active: sec_dout_active { + mux { + pins = "gpio18"; + function = "sec_mi2s"; + }; + + config { + pins = "gpio18"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL*/ + output-high; + }; + }; + }; + + pmx_sec_mi2s_aux_din { + sec_din_sleep: sec_din_sleep { + mux { + pins = "gpio17"; + function = "gpio"; + }; + + config { + pins = "gpio17"; + drive-strength = <2>; /* 2 mA */ + bias-disable; /* NO PULL */ + input-enable; + }; + }; + + sec_din_active: sec_din_active { + mux { + pins = "gpio17"; + function = "sec_mi2s"; + }; + + config { + pins = "gpio17"; + drive-strength = <8>; /* 8 mA */ + bias-disable; /* NO PULL */ + }; + }; + }; }; }; diff --git a/qcom/sdxlemur-wcd.dtsi b/qcom/sdxlemur-wcd.dtsi new file mode 100644 index 000000000000..512253fd0ddd --- /dev/null +++ b/qcom/sdxlemur-wcd.dtsi @@ -0,0 +1,68 @@ +&soc { + tavil_codec { + wcd: wcd_pinctrl@5 { + compatible = "qcom,wcd-pinctrl"; + qcom,num-gpios = <5>; + gpio-controller; + #gpio-cells = <2>; + + spkr_1_wcd_en_active: spkr_1_wcd_en_active { + mux { + pins = "gpio2"; + }; + + config { + pins = "gpio2"; + output-high; + }; + }; + + spkr_1_wcd_en_sleep: spkr_1_wcd_en_sleep { + mux { + pins = "gpio2"; + }; + + config { + pins = "gpio2"; + input-enable; + }; + }; + + spkr_2_wcd_en_active: spkr_2_sd_n_active { + mux { + pins = "gpio3"; + }; + + config { + pins = "gpio3"; + output-high; + }; + }; + + spkr_2_wcd_en_sleep: spkr_2_sd_n_sleep { + mux { + pins = "gpio3"; + }; + + config { + pins = "gpio3"; + input-enable; + }; + }; + }; + + wsa_spkr_wcd_sd1: msm_cdc_pinctrll { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&spkr_1_wcd_en_active>; + pinctrl-1 = <&spkr_1_wcd_en_sleep>; + }; + + wsa_spkr_wcd_sd2: msm_cdc_pinctrlr { + compatible = "qcom,msm-cdc-pinctrl"; + pinctrl-names = "aud_active", "aud_sleep"; + pinctrl-0 = <&spkr_2_wcd_en_active>; + pinctrl-1 = <&spkr_2_wcd_en_sleep>; + }; + }; +}; diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index d876a6473abb..d7395e099654 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -3,6 +3,7 @@ #include #include #include +#include #include #include #include @@ -89,6 +90,12 @@ size = <0xC00000>; linux,cma-default; }; + + audio_mem: audio_region@0 { + compatible = "shared-dma-pool"; + no-map; + size = <0x400000>; + }; }; cpus { @@ -648,6 +655,29 @@ 0x2000 3 0x4400 2>; }; + + qcom,gpr { + compatible = "qcom,gpr"; + qcom,glink-channels = "modem_apps"; + qcom,intents = <0x200 20>; + reg = ; + + spf_core { + compatible = "qcom,spf_core"; + reg = ; + }; + + audio-pkt { + compatible = "qcom,audio-pkt"; + qcom,audiopkt-ch-name = "apr_audio_svc"; + reg = ; + }; + + audio_prm { + compatible = "qcom,audio_prm"; + reg = ; + }; + }; }; }; @@ -895,3 +925,4 @@ #include "sdxlemur-pm.dtsi" #include "sdxlemur-pcie.dtsi" #include "sdxlemur-blsp.dtsi" +#include "sdxlemur-audio.dtsi" From 1c594332d7c33b1ff25bd60f41992684a7541352 Mon Sep 17 00:00:00 2001 From: Archit Saxena Date: Wed, 9 Sep 2020 13:18:47 +0530 Subject: [PATCH 65/88] ARM: dts: msm: Add scuba-iot files on 5.4 Add initial scuba iot device tree files for kernel 5.4. Change-Id: Ic891ffc3cd2608571082aa473770b4067f3934c3 --- bindings/arm/msm/msm.txt | 4 + bindings/pinctrl/qcom,scuba-pinctrl.yaml | 195 ++++ qcom/Makefile | 6 + qcom/msm-arm-smmu-scuba.dtsi | 198 ++++ qcom/pm2250-rpm-regulator.dtsi | 439 +++++++++ qcom/pm2250.dtsi | 380 ++++++++ qcom/scuba-ion.dtsi | 35 + qcom/scuba-iot-idp-overlay.dts | 12 + qcom/scuba-iot-idp.dtsi | 40 + qcom/scuba-iot-pinctrl.dtsi | 1096 ++++++++++++++++++++++ qcom/scuba-iot.dts | 9 + qcom/scuba-iot.dtsi | 707 ++++++++++++++ qcom/scuba-regulator.dtsi | 348 +++++++ 13 files changed, 3469 insertions(+) create mode 100644 bindings/pinctrl/qcom,scuba-pinctrl.yaml create mode 100644 qcom/msm-arm-smmu-scuba.dtsi create mode 100644 qcom/pm2250-rpm-regulator.dtsi create mode 100644 qcom/pm2250.dtsi create mode 100644 qcom/scuba-ion.dtsi create mode 100644 qcom/scuba-iot-idp-overlay.dts create mode 100644 qcom/scuba-iot-idp.dtsi create mode 100644 qcom/scuba-iot-pinctrl.dtsi create mode 100644 qcom/scuba-iot.dts create mode 100644 qcom/scuba-iot.dtsi create mode 100644 qcom/scuba-regulator.dtsi diff --git a/bindings/arm/msm/msm.txt b/bindings/arm/msm/msm.txt index 16b9fbede6b4..be6b315b994e 100644 --- a/bindings/arm/msm/msm.txt +++ b/bindings/arm/msm/msm.txt @@ -83,6 +83,9 @@ SoCs: - SDXLEMUR compatible = "qcom,sdxlemur" +- SCUBA + compatible = "qcom,scuba-iot" + - SDMMAGPIE compatible = "qcom,sdmmagpie" @@ -244,3 +247,4 @@ compatible = "qcom,holi-mtp" compatible = "qcom,holi-cdp" compatible = "qcom,holi-qrd" compatible = "qcom,holi-atp" +compatible = "qcom,scuba-idp" diff --git a/bindings/pinctrl/qcom,scuba-pinctrl.yaml b/bindings/pinctrl/qcom,scuba-pinctrl.yaml new file mode 100644 index 000000000000..803943900173 --- /dev/null +++ b/bindings/pinctrl/qcom,scuba-pinctrl.yaml @@ -0,0 +1,195 @@ +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bindings/pinctrl/qcom,scuba-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. SCUBA TLMM block + +description: | + This binding describes the Top Level Mode Multiplexer block found in the + SCUBA platform. + +properties: + compatible: + Usage: required + Value type: + Definition: must be "qcom,scuba-pinctrl" + + reg: + Usage: required + Value type: + Definition: the base address and size of the TLMM register space. + + interrupts: + Usage: required + Value type: + Definition: should specify the TLMM summary IRQ. + + interrupt-controller: + Usage: required + Value type: + Definition: identifies this node as an interrupt controller + + #interrupt-cells: + Usage: required + Value type: + Definition: must be 2. Specifying the pin number and flags, as defined + in + + gpio-controller: + Usage: required + Value type: + Definition: identifies this node as a gpio controller + + #gpio-cells: + Usage: required + Value type: + Definition: must be 2. Specifying the pin number and flags, as defined + in + + wakeup-parent: + Usage: optional + Value type: + Definition: A phandle to the wakeup interrupt controller for the SoC. + + Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for + a general description of GPIO and interrupt bindings. + + Please refer to pinctrl-bindings.txt in this directory for details of the + common pinctrl bindings used by client devices, including the meaning of the + phrase "pin configuration node". + + The pin configuration nodes act as a container for an arbitrary number of + subnodes. Each of these subnodes represents some desired configuration for a + pin, a group, or a list of pins or groups. This configuration can include the + mux function to select on those pin(s)/group(s), and various pin configuration + parameters, such as pull-up, drive strength, etc. + + + PIN CONFIGURATION NODES: + + The name of each subnode is not important; all subnodes should be enumerated + and processed purely based on their content. + + Each subnode only affects those parameters that are explicitly listed. In + other words, a subnode that lists a mux function but no pin configuration + parameters implies no information about any pin configuration parameters. + Similarly, a pin subnode that describes a pullup parameter implies no + information about e.g. the mux function. + + + The following generic properties as defined in pinctrl-bindings.txt are valid + to specify in a pin configuration subnode: + + pins: + Usage: required + Value type: + Definition: List of gpio pins affected by the properties specified in + this subnode. + + Valid pins: + gpio0-gpio155 + Supports mux, bias and drive-strength + + sdc1_clk, sdc1_cmd, sdc1_data sdc2_clk, sdc2_cmd, + sdc2_data sdc1_rclk + Supports bias and drive-strength + + function: + Usage: required + Value type: + Definition: Specify the alternative function to be configured for the + specified pins. Functions are only valid for gpio pins. + Valid values: + blsp_uart1, blsp_spi1, blsp_i2c1, blsp_uim1, atest_tsens, + bimc_dte1, dac_calib0, blsp_spi8, blsp_uart8, blsp_uim8, + qdss_cti_trig_out_b, bimc_dte0, dac_calib1, qdss_cti_trig_in_b, + dac_calib2, atest_tsens2, atest_usb1, blsp_spi10, blsp_uart10, + blsp_uim10, atest_bbrx1, atest_usb13, atest_bbrx0, atest_usb12, + mdp_vsync, edp_lcd, blsp_i2c10, atest_gpsadc1, atest_usb11, + atest_gpsadc0, edp_hot, atest_usb10, m_voc, dac_gpio, atest_char, + cam_mclk, pll_bypassnl, qdss_stm7, blsp_i2c8, qdss_tracedata_b, + pll_reset, qdss_stm6, qdss_stm5, qdss_stm4, atest_usb2, cci_i2c, + qdss_stm3, dac_calib3, atest_usb23, atest_char3, dac_calib4, + qdss_stm2, atest_usb22, atest_char2, qdss_stm1, dac_calib5, + atest_usb21, atest_char1, dbg_out, qdss_stm0, dac_calib6, + atest_usb20, atest_char0, dac_calib10, qdss_stm10, + qdss_cti_trig_in_a, cci_timer4, blsp_spi6, blsp_uart6, blsp_uim6, + blsp2_spi, qdss_stm9, qdss_cti_trig_out_a, dac_calib11, + qdss_stm8, cci_timer0, qdss_stm13, dac_calib7, cci_timer1, + qdss_stm12, dac_calib8, cci_timer2, blsp1_spi, qdss_stm11, + dac_calib9, cci_timer3, cci_async, dac_calib12, blsp_i2c6, + qdss_tracectl_a, dac_calib13, qdss_traceclk_a, dac_calib14, + dac_calib15, hdmi_rcv, dac_calib16, hdmi_cec, pwr_modem, + dac_calib17, hdmi_ddc, pwr_nav, dac_calib18, pwr_crypto, + dac_calib19, hdmi_hot, dac_calib20, dac_calib21, pci_e0, + dac_calib22, dac_calib23, dac_calib24, tsif1_sync, dac_calib25, + sd_write, tsif1_error, blsp_spi2, blsp_uart2, blsp_uim2, + qdss_cti, blsp_i2c2, blsp_spi3, blsp_uart3, blsp_uim3, blsp_i2c3, + uim3, blsp_spi9, blsp_uart9, blsp_uim9, blsp10_spi, blsp_i2c9, + blsp_spi7, blsp_uart7, blsp_uim7, qdss_tracedata_a, blsp_i2c7, + qua_mi2s, gcc_gp1_clk_a, ssc_irq, uim4, blsp_spi11, blsp_uart11, + blsp_uim11, gcc_gp2_clk_a, gcc_gp3_clk_a, blsp_i2c11, cri_trng0, + cri_trng1, cri_trng, qdss_stm18, pri_mi2s, qdss_stm17, blsp_spi4, + blsp_uart4, blsp_uim4, qdss_stm16, qdss_stm15, blsp_i2c4, + qdss_stm14, dac_calib26, spkr_i2s, audio_ref, lpass_slimbus, + isense_dbg, tsense_pwm1, tsense_pwm2, btfm_slimbus, ter_mi2s, + qdss_stm22, qdss_stm21, qdss_stm20, qdss_stm19, gcc_gp1_clk_b, + sec_mi2s, blsp_spi5, blsp_uart5, blsp_uim5, gcc_gp2_clk_b, + gcc_gp3_clk_b, blsp_i2c5, blsp_spi12, blsp_uart12, blsp_uim12, + qdss_stm25, qdss_stm31, blsp_i2c12, qdss_stm30, qdss_stm29, + tsif1_clk, qdss_stm28, tsif1_en, tsif1_data, sdc4_cmd, qdss_stm27, + qdss_traceclk_b, tsif2_error, sdc43, vfr_1, qdss_stm26, tsif2_clk, + sdc4_clk, qdss_stm24, tsif2_en, sdc42, qdss_stm23, qdss_tracectl_b, + sd_card, tsif2_data, sdc41, tsif2_sync, sdc40, mdp_vsync_p_b, + ldo_en, mdp_vsync_s_b, ldo_update, blsp11_uart_tx_b, blsp11_uart_rx_b, + blsp11_i2c_sda_b, prng_rosc, blsp11_i2c_scl_b, uim2, uim1, uim_batt, + pci_e2, pa_indicator, adsp_ext, ddr_bist, qdss_tracedata_11, + qdss_tracedata_12, modem_tsync, nav_dr, nav_pps, pci_e1, gsm_tx, + qspi_cs, ssbi2, ssbi1, mss_lte, qspi_clk, qspi0, qspi1, qspi2, qspi3, + gpio + + bias-disable: + Usage: optional + Value type: + Definition: The specified pins should be configured as no pull. + + bias-pull-down: + Usage: optional + Value type: + Definition: The specified pins should be configured as pull down. + + bias-pull-up: + Usage: optional + Value type: + Definition: The specified pins should be configured as pull up. + + output-high: + Usage: optional + Value type: + Definition: The specified pins are configured in output mode, driven high. + Not valid for sdc pins. + + output-low: + Usage: optional + Value type: + Definition: The specified pins are configured in output mode, driven low. + Not valid for sdc pins. + + drive-strength: + Usage: optional + Value type: + Definition: Selects the drive strength for the specified pins, in mA. + Valid values: 2, 4, 6, 8, 10, 12, 14 and 16 + +examples: + - | + tlmm: pinctrl@400000 { + compatible = "qcom,scuba-pinctrl"; + reg = <0x400000 0x800000>; + interrupts = <0 227 0>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; diff --git a/qcom/Makefile b/qcom/Makefile index 4ff651cd60c3..212ca73f81f0 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -75,6 +75,12 @@ dtb-$(CONFIG_ARCH_LAHAINA) += lahaina-rumi.dtb \ lahaina-mtp-v2.1.dtb endif +ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y) +dtbo-$(CONFIG_ARCH_SCUBA) += scuba-iot-idp-overlay.dtbo + +scuba-iot-idp-overlay.dtbo-base := scuba-iot.dtb +endif + ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y) dtbo-$(CONFIG_ARCH_HOLI) += holi-rumi-overlay.dtbo \ holi-mtp-overlay.dtbo \ diff --git a/qcom/msm-arm-smmu-scuba.dtsi b/qcom/msm-arm-smmu-scuba.dtsi new file mode 100644 index 000000000000..2876f6370a71 --- /dev/null +++ b/qcom/msm-arm-smmu-scuba.dtsi @@ -0,0 +1,198 @@ +#include + +&soc { + kgsl_smmu: kgsl-smmu@0x59a0000 { + status = "disabled"; + compatible = "qcom,qsmmu-v500"; + reg = <0x59a0000 0x10000>, + <0x59c2000 0x20>; + reg-names = "base", "tcu-base"; + #iommu-cells = <2>; + qcom,skip-init; + qcom,no-dynamic-asid; + qcom,use-3-lvl-tables; + #global-interrupts = <1>; + qcom,regulator-names = "vdd"; + #size-cells = <1>; + ranges; + interrupts = , + , + , + , + , + , + , + , + ; + + qcom,actlr = + /* ALL CBs of GFX: +15 deep PF */ + <0x0 0x3ff 0x30B>; + + gfx_0_tbu: gfx_0_tbu@0x59c5000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0x59c5000 0x1000>, + <0x59c2200 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x0 0x400>; + interrupts = ; + }; + }; + + apps_smmu: apps-smmu@0xc600000 { + status = "disabled"; + compatible = "qcom,qsmmu-v500"; + reg = <0xc600000 0x80000>, + <0xc782000 0x20>; + reg-names = "base", "tcu-base"; + #iommu-cells = <2>; + qcom,skip-init; + qcom,use-3-lvl-tables; + #global-interrupts = <1>; + #size-cells = <1>; + #address-cells = <1>; + ranges; + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + qcom,msm-bus,name = "apps_smmu"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,active-only; + qcom,msm-bus,num-paths = <1>; + + qcom,actlr = + /* For rt TBU +3 deep PF */ + <0x400 0x3ff 0x103>, + /* For nrt TBU +3 deep PF */ + <0x800 0x3ff 0x103>; + + anoc_1_tbu: anoc_1_tbu@0xc785000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0xc785000 0x1000>, + <0xc782200 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x0 0x400>; + interrupts = ; + qcom,msm-bus,name = "apps_smmu"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,active-only; + qcom,msm-bus,num-paths = <2>; + + }; + + mm_rt_tbu: mm_rt_tbu@0xc789000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0xc789000 0x1000>, + <0xc782208 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x400 0x400>; + interrupts = ; + qcom,regulator-names = "vdd"; + qcom,msm-bus,name = "apps_smmu"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,active-only; + qcom,msm-bus,num-paths = <2>; + + }; + + mm_nrt_tbu: mm_nrt_tbu@0xc78d000 { + compatible = "qcom,qsmmuv500-tbu"; + reg = <0xc78d000 0x1000>, + <0xc782210 0x8>; + reg-names = "base", "status-reg"; + qcom,stream-id-range = <0x800 0x400>; + interrupts = ; + qcom,regulator-names = "vdd"; + qcom,msm-bus,name = "apps_smmu"; + qcom,msm-bus,num-cases = <2>; + qcom,msm-bus,active-only; + qcom,msm-bus,num-paths = <2>; + + }; + + }; + + kgsl_iommu_test_device { + compatible = "iommu-debug-test"; + qcom,iommu-dma = "disabled"; + iommus = <&kgsl_smmu 0x7 0x0>; + status = "disabled"; + }; + + apps_iommu_test_device { + compatible = "iommu-debug-test"; + qcom,iommu-dma = "disabled"; + iommus = <&apps_smmu 0x1E0 0x0>; + status = "disabled"; + }; + + apps_iommu_coherent_test_device { + compatible = "iommu-debug-test"; + qcom,iommu-dma = "disabled"; + iommus = <&apps_smmu 0x1E1 0x0>; + dma-coherent; + status = "disabled"; + }; +}; diff --git a/qcom/pm2250-rpm-regulator.dtsi b/qcom/pm2250-rpm-regulator.dtsi new file mode 100644 index 000000000000..ed8a655d621f --- /dev/null +++ b/qcom/pm2250-rpm-regulator.dtsi @@ -0,0 +1,439 @@ +&rpm_bus { + rpm-regulator-smpa1 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "smpa"; + qcom,resource-id = <1>; + qcom,regulator-type = <1>; + qcom,hpm-min-load = <100000>; + status = "disabled"; + + regulator-s1 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm2250_s1"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-smpa2 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "smpa"; + qcom,resource-id = <2>; + qcom,regulator-type = <1>; + qcom,hpm-min-load = <100000>; + status = "disabled"; + + regulator-s2 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm2250_s2"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-smpa3 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "smpa"; + qcom,resource-id = <3>; + qcom,regulator-type = <1>; + qcom,hpm-min-load = <100000>; + status = "disabled"; + + regulator-s3 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm2250_s3"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-smpa4 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "smpa"; + qcom,resource-id = <4>; + qcom,regulator-type = <1>; + qcom,hpm-min-load = <100000>; + status = "disabled"; + + regulator-s4 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm2250_s4"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa1 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <1>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l1 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm2250_l1"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa2 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <2>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l2 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm2250_l2"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa3 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <3>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l3 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm2250_l3"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa4 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <4>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l4 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm2250_l4"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa5 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <5>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l5 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm2250_l5"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa6 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <6>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l6 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm2250_l6"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa7 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <7>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l7 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm2250_l7"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa8 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <8>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l8 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm2250_l8"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa9 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <9>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l9 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm2250_l9"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa10 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <10>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l10 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm2250_l10"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa11 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <11>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l11 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm2250_l11"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa12 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <12>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l12 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm2250_l12"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa13 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <13>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l13 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm2250_l13"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa14 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <14>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l14 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm2250_l14"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa15 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <15>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l15 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm2250_l15"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa16 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <16>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l16 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm2250_l16"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa17 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <17>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l17 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm2250_l17"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa18 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <18>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l18 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm2250_l18"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa19 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <19>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l19 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm2250_l19"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa20 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <20>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l20 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm2250_l20"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa21 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <21>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l21 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm2250_l21"; + qcom,set = <3>; + status = "disabled"; + }; + }; + + rpm-regulator-ldoa22 { + compatible = "qcom,rpm-smd-regulator-resource"; + qcom,resource-name = "ldoa"; + qcom,resource-id = <22>; + qcom,regulator-type = <0>; + qcom,regulator-hw-type = "pmic5-ldo"; + qcom,hpm-min-load = <10000>; + status = "disabled"; + + regulator-l22 { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm2250_l22"; + qcom,set = <3>; + status = "disabled"; + }; + }; +}; diff --git a/qcom/pm2250.dtsi b/qcom/pm2250.dtsi new file mode 100644 index 000000000000..c7125e133d60 --- /dev/null +++ b/qcom/pm2250.dtsi @@ -0,0 +1,380 @@ +#include +#include +#include +#include +#include + +&spmi_bus { + #address-cells = <2>; + #size-cells = <0>; + interrupt-controller; + #interrupt-cells = <4>; + + qcom,pm2250@0 { + compatible = "qcom,spmi-pmic"; + reg = <0 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + + pm2250_revid: qcom,revid@100 { + compatible = "qcom,qpnp-revid"; + reg = <0x100 0x100>; + }; + + qcom,power-on@800 { + compatible = "qcom,qpnp-power-on"; + reg = <0x800 0x100>; + interrupts = <0x0 0x8 0x0 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x8 0x1 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "kpdpwr", "resin"; + qcom,pon-dbc-delay = <15625>; + qcom,kpdpwr-sw-debounce; + qcom,system-reset; + qcom,store-hard-reset-reason; + + qcom,pon_1 { + qcom,pon-type = ; + qcom,pull-up = <1>; + linux,code = ; + }; + + qcom,pon_2 { + qcom,pon-type = ; + qcom,pull-up = <1>; + linux,code = ; + }; + }; + + pm2250_tz: qcom,temp-alarm@2400 { + compatible = "qcom,spmi-temp-alarm"; + reg = <0x2400 0x100>; + interrupts = <0x0 0x24 0x0 IRQ_TYPE_EDGE_BOTH>; + io-channels = <&pm2250_vadc ADC5_DIE_TEMP>; + io-channel-names = "thermal"; + #thermal-sensor-cells = <0>; + qcom,temperature-threshold-set = <1>; + }; + + pm2250_vadc: vadc@3100 { + compatible = "qcom,spmi-adc5-lite"; + reg = <0x3100 0x100>; + reg-names = "adc5-usr-base"; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "eoc-int-en-set"; + #io-channel-cells = <1>; + io-channel-ranges; + + /* Channel nodes */ + ref_gnd { + reg = ; + label = "ref_gnd"; + qcom,pre-scaling = <1 1>; + }; + + vref_1p25 { + reg = ; + label = "vref_1p25"; + qcom,pre-scaling = <1 1>; + }; + + die_temp { + reg = ; + label = "die_temp"; + qcom,pre-scaling = <1 1>; + }; + + vph_pwr { + reg = ; + label = "vph_pwr"; + qcom,pre-scaling = <1 3>; + }; + + vbat_sns { + reg = ; + label = "vbat_sns"; + qcom,pre-scaling = <1 3>; + }; + + usb_in_v_div_16 { + reg = ; + label = "usb_in_v_div_16"; + qcom,pre-scaling = <1 16>; + }; + + chg_temp { + reg = ; + label = "chg_temp"; + qcom,pre-scaling = <1 1>; + }; + + bat_therm { + reg = ; + label = "bat_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + bat_therm_30k { + reg = ; + label = "bat_therm_30k"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + bat_therm_400k { + reg = ; + label = "bat_therm_400k"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + i_parallel { + reg = ; + label = "i_parallel"; + qcom,pre-scaling = <1 1>; + }; + + bat_id { + reg = ; + label = "bat_id"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + }; + + + pm2250_gpios: pinctrl@c000 { + compatible = "qcom,spmi-gpio"; + reg = <0xc000 0xa00>; + interrupts = <0x0 0xc0 0 IRQ_TYPE_NONE>, + <0x0 0xc1 0 IRQ_TYPE_NONE>, + <0x0 0xc2 0 IRQ_TYPE_NONE>, + <0x0 0xc3 0 IRQ_TYPE_NONE>, + <0x0 0xc4 0 IRQ_TYPE_NONE>, + <0x0 0xc5 0 IRQ_TYPE_NONE>, + <0x0 0xc6 0 IRQ_TYPE_NONE>, + <0x0 0xc7 0 IRQ_TYPE_NONE>, + <0x0 0xc8 0 IRQ_TYPE_NONE>, + <0x0 0xc9 0 IRQ_TYPE_NONE>; + + interrupt-names = "pm2250_gpio1", "pm2250_gpio2", + "pm2250_gpio3", "pm2250_gpio4", + "pm2250_gpio5", "pm2250_gpio6", + "pm2250_gpio7", "pm2250_gpio8", + "pm2250_gpio9", "pm2250_gpio10"; + + gpio-controller; + #gpio-cells = <2>; + }; + + pm2250_rtc: qcom,pm2250_rtc { + compatible = "qcom,pm8941-rtc"; + interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>; + }; + + pm2250_qg: qpnp,qg { + compatible = "qcom,qpnp-qg-lite"; + #address-cells = <1>; + #size-cells = <1>; + + qcom,vbatt-cutoff-mv = <3400>; + qcom,vbatt-low-mv = <3500>; + qcom,vbatt-low-cold-mv = <3800>; + qcom,vbatt-empty-mv = <3200>; + qcom,vbatt-empty-cold-mv = <3000>; + qcom,s3-entry-fifo-length = <2>; + + qcom,pmic-revid = <&pm2250_revid>; + io-channels = <&pm2250_vadc ADC5_BAT_THERM_100K_PU>, + <&pm2250_vadc ADC5_BAT_ID_100K_PU>; + io-channel-names = "batt-therm", "batt-id"; + + qcom,qgauge@4800 { + status = "okay"; + reg = <0x4800 0x100>; + interrupts = + <0x0 0x48 0x2 IRQ_TYPE_EDGE_RISING>, + <0x0 0x48 0x3 IRQ_TYPE_EDGE_RISING>, + <0x0 0x48 0x5 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "qg-vbat-empty", + "qg-fifo-done", + "qg-good-ocv"; + }; + + qcom,qg-sdam@b600 { + status = "okay"; + reg = <0xb600 0x100>; + }; + }; + + pm2250_charger: qcom,qpnp-smblite { + compatible = "qcom,qpnp-smblite"; + #address-cells = <1>; + #size-cells = <1>; + #cooling-cells = <2>; + + qcom,pmic-revid = <&pm2250_revid>; + qcom,chgr@1000 { + reg = <0x1000 0x100>; + interrupts = + <0x0 0x10 0x1 IRQ_TYPE_EDGE_RISING>, + <0x0 0x10 0x0 IRQ_TYPE_EDGE_RISING>, + <0x0 0x10 0x4 IRQ_TYPE_EDGE_RISING>, + <0x0 0x10 0x7 IRQ_TYPE_EDGE_RISING>; + + interrupt-names = "chgr-error", + "chg-state-change", + "buck-oc", + "vph-ov"; + }; + + qcom,dcdc@1100 { + reg = <0x1100 0x100>; + interrupts = + <0x0 0x11 0x0 IRQ_TYPE_EDGE_RISING>, + <0x0 0x11 0x1 IRQ_TYPE_EDGE_RISING>, + <0x0 0x11 0x2 IRQ_TYPE_EDGE_RISING>, + <0x0 0x11 0x6 IRQ_TYPE_EDGE_RISING>, + <0x0 0x11 0x7 IRQ_TYPE_EDGE_BOTH>; + + interrupt-names = "otg-fail", + "otg-fault", + "skip-mode", + "input-current-limiting", + "switcher-power-ok"; + }; + + qcom,batif@1200 { + reg = <0x1200 0x100>; + interrupts = + <0x0 0x12 0x0 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x12 0x1 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x12 0x2 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x12 0x3 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x12 0x4 IRQ_TYPE_EDGE_RISING>; + + interrupt-names = "bat-temp", + "bat-therm-or-id-missing", + "bat-low", + "bat-ov", + "bsm-active"; + }; + + qcom,usb@1300 { + reg = <0x1300 0x100>; + interrupts = + <0x0 0x13 0x0 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x13 0x1 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x13 0x2 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x13 0x3 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x13 0x4 IRQ_TYPE_EDGE_RISING>, + <0x0 0x13 0x6 IRQ_TYPE_EDGE_RISING>; + + interrupt-names = "usbin-plugin", + "usbin-collapse", + "usbin-uv", + "usbin-ov", + "usbin-gtvt", + "usbin-icl-change"; + }; + + qcom,typec@1500 { + reg = <0x1500 0x100>; + interrupts = + <0x0 0x15 0x0 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x15 0x1 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x15 0x2 IRQ_TYPE_EDGE_RISING>, + <0x0 0x15 0x4 IRQ_TYPE_EDGE_BOTH>, + <0x0 0x15 0x5 IRQ_TYPE_EDGE_RISING>, + <0x0 0x15 0x6 IRQ_TYPE_EDGE_RISING>, + <0x0 0x15 0x7 IRQ_TYPE_EDGE_RISING>; + + interrupt-names = "typec-or-rid-detect-change", + "typec-vpd-detect", + "typec-cc-state-change", + "typec-vbus-change", + "typec-attach-detach", + "typec-legacy-cable-detect", + "typec-try-snk-src-detect"; + }; + + qcom,misc@1600 { + reg = <0x1600 0x100>; + interrupts = + <0x0 0x16 0x0 IRQ_TYPE_EDGE_RISING>, + <0x0 0x16 0x1 IRQ_TYPE_EDGE_RISING>, + <0x0 0x16 0x2 IRQ_TYPE_EDGE_RISING>, + <0x0 0x16 0x3 IRQ_TYPE_EDGE_RISING>, + <0x0 0x16 0x4 IRQ_TYPE_EDGE_RISING>, + <0x0 0x16 0x5 IRQ_TYPE_EDGE_RISING>, + <0x0 0x16 0x6 IRQ_TYPE_EDGE_BOTH>; + + interrupt-names = "wdog-snarl", + "wdog-bark", + "aicl-fail", + "aicl-done", + "imp-trigger", + "all-chnl-cond-done", + "temp-change"; + }; + + qcom,schgm-flashlite@a600 { + reg = <0xa600 0x100>; + interrupts = + <0x0 0xa6 0x2 IRQ_TYPE_EDGE_RISING>, + <0x0 0xa6 0x5 IRQ_TYPE_EDGE_RISING>, + <0x0 0xa6 0x6 IRQ_TYPE_EDGE_RISING>, + <0x0 0xa6 0x7 IRQ_TYPE_EDGE_BOTH>; + + interrupt-names = "flash-state-change", + "ilim1-s1", + "ilim2-s2", + "vreg-ok"; + }; + }; + }; + + pm2250_1: qcom,pm2250@1 { + compatible = "qcom,spmi-pmic"; + reg = <1 SPMI_USID>; + #address-cells = <2>; + #size-cells = <0>; + + pm2250_vib: qcom,vibrator@5600 { + compatible = "qcom,qpnp-vibrator-ldo"; + reg = <0x5600 0x100>; + qcom,vib-ldo-volt-uv = <3000000>; + qcom,disable-overdrive; + }; + + pm2250_pwm1: qcom,pwms@bc00 { + compatible = "qcom,pwm-lpg"; + reg = <0xbc00 0x100>; + reg-names = "lpg-base"; + qcom,num-lpg-channels = <1>; + #pwm-cells = <2>; + }; + + pm2250_pwm2: qcom,pwms@bd00 { + compatible = "qcom,pwm-lpg"; + reg = <0xbd00 0x100>; + reg-names = "lpg-base"; + qcom,num-lpg-channels = <1>; + #pwm-cells = <2>; + }; + + pm2250_pwm3: qcom,pwms@be00 { + compatible = "qcom,pwm-lpg"; + reg = <0xbe00 0x100>; + reg-names = "lpg-base"; + qcom,num-lpg-channels = <1>; + #pwm-cells = <2>; + }; + }; +}; diff --git a/qcom/scuba-ion.dtsi b/qcom/scuba-ion.dtsi new file mode 100644 index 000000000000..cba6f834d9d9 --- /dev/null +++ b/qcom/scuba-ion.dtsi @@ -0,0 +1,35 @@ +&soc { + qcom,ion { + compatible = "qcom,msm-ion"; + #address-cells = <1>; + #size-cells = <0>; + + system_heap: qcom,ion-heap@25 { + reg = <25>; + qcom,ion-heap-type = "SYSTEM"; + }; + + system_secure_heap: qcom,ion-heap@9 { + reg = <9>; + qcom,ion-heap-type = "SYSTEM_SECURE"; + }; + + qcom,ion-heap@10 { /* SECURE DISPLAY HEAP */ + reg = <10>; + memory-region = <&secure_display_memory>; + qcom,ion-heap-type = "HYP_CMA"; + }; + + qcom,ion-heap@27 { /* QSEECOM HEAP */ + reg = <27>; + memory-region = <&qseecom_mem>; + qcom,ion-heap-type = "DMA"; + }; + + qcom,ion-heap@19 { /* QSEECOM HEAP */ + reg = <19>; + memory-region = <&qseecom_ta_mem>; + qcom,ion-heap-type = "DMA"; + }; + }; +}; diff --git a/qcom/scuba-iot-idp-overlay.dts b/qcom/scuba-iot-idp-overlay.dts new file mode 100644 index 000000000000..7f356c2e6abf --- /dev/null +++ b/qcom/scuba-iot-idp-overlay.dts @@ -0,0 +1,12 @@ +/dts-v1/; +/plugin/; + +#include +#include "scuba-iot-idp.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Scuba IDP"; + compatible = "qcom,scuba-idp", "qcom,scuba-iot", "qcom,idp"; + qcom,msm-id = <441 0x10000>, <471 0x10000>; + qcom,board-id = <34 0>; +}; diff --git a/qcom/scuba-iot-idp.dtsi b/qcom/scuba-iot-idp.dtsi new file mode 100644 index 000000000000..d0b147079ba0 --- /dev/null +++ b/qcom/scuba-iot-idp.dtsi @@ -0,0 +1,40 @@ +#include +#include + +&soc { + scuba_batterydata: qcom,battery-data { + qcom,batt-id-range-pct = <15>; + #include "qg-batterydata-alium-3600mah.dtsi" + #include "qg-batterydata-atl466271_3300mAh.dtsi" + }; +}; + +&pm2250_qg { + qcom,battery-data = <&scuba_batterydata>; + qcom,qg-iterm-ma = <150>; + qcom,hold-soc-while-full; + qcom,linearize-soc; + qcom,cl-feedback-on; + qcom,tcss-enable; + qcom,fvss-enable; + qcom,fvss-vbatt-mv = <3500>; + qcom,bass-enable; +}; + +&pm2250_charger { + interrupts-extended = <&tlmm 89 0>; + interrupt-names = "usb_id_irq"; + qcom,usb-id-gpio = <&tlmm 89 0>; + + pinctrl-names = "default"; + pinctrl-0 = <&usb_id_interrupt>; + + qcom,auto-recharge-soc = <98>; + qcom,suspend-input-on-debug-batt; + qcom,battery-data = <&scuba_batterydata>; + io-channels = <&pm2250_vadc ADC5_USB_IN_V_16>, + <&pm2250_vadc ADC5_CHG_TEMP>; + io-channel-names = "usb_in_voltage", + "chg_temp"; + qcom,thermal-mitigation = <2000000 1500000 1000000 500000>; +}; diff --git a/qcom/scuba-iot-pinctrl.dtsi b/qcom/scuba-iot-pinctrl.dtsi new file mode 100644 index 000000000000..d141c10c703b --- /dev/null +++ b/qcom/scuba-iot-pinctrl.dtsi @@ -0,0 +1,1096 @@ +&soc { + tlmm: pinctrl@500000 { + compatible = "qcom,scuba-pinctrl"; + reg = <0x500000 0x300000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + irqdomain-map-pass-thru = <0 0xff>; + irqdomain-map-mask = <0xff 0>; + + qupv3_se4_2uart_pins: qupv3_se4_2uart_pins { + qupv3_se4_2uart_active: qupv3_se4_2uart_active { + mux { + pins = "gpio12", "gpio13"; + function = "qup4"; + }; + + config { + pins = "gpio12", "gpio13"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se4_2uart_sleep: qupv3_se4_2uart_sleep { + mux { + pins = "gpio12", "gpio13"; + function = "gpio"; + }; + + config { + pins = "gpio12", "gpio13"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + /* SDC pin type */ + sdc1_clk_on: sdc1_clk_on { + config { + pins = "sdc1_clk"; + bias-disable; /* NO pull */ + drive-strength = <16>; /* 16 MA */ + }; + }; + + sdc1_clk_off: sdc1_clk_off { + config { + pins = "sdc1_clk"; + bias-disable; /* NO pull */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc1_cmd_on: sdc1_cmd_on { + config { + pins = "sdc1_cmd"; + bias-pull-up; /* pull up */ + drive-strength = <14>; /* 14 MA */ + }; + }; + + sdc1_cmd_off: sdc1_cmd_off { + config { + pins = "sdc1_cmd"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc1_data_on: sdc1_data_on { + config { + pins = "sdc1_data"; + bias-pull-up; /* pull up */ + drive-strength = <14>; /* 14 MA */ + }; + }; + + sdc1_data_off: sdc1_data_off { + config { + pins = "sdc1_data"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc1_rclk_on: sdc1_rclk_on { + config { + pins = "sdc1_rclk"; + bias-pull-down; /* pull down */ + }; + }; + + sdc1_rclk_off: sdc1_rclk_off { + config { + pins = "sdc1_rclk"; + bias-pull-down; /* pull down */ + }; + }; + + sdc2_clk_on: sdc2_clk_on { + config { + pins = "sdc2_clk"; + bias-disable; /* NO pull */ + drive-strength = <16>; /* 16 MA */ + }; + }; + + sdc2_clk_off: sdc2_clk_off { + config { + pins = "sdc2_clk"; + bias-disable; /* NO pull */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc2_cmd_on: sdc2_cmd_on { + config { + pins = "sdc2_cmd"; + bias-pull-up; /* pull up */ + drive-strength = <14>; /* 14 MA */ + }; + }; + + sdc2_cmd_off: sdc2_cmd_off { + config { + pins = "sdc2_cmd"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc2_data_on: sdc2_data_on { + config { + pins = "sdc2_data"; + bias-pull-up; /* pull up */ + drive-strength = <14>; /* 14 MA */ + }; + }; + + sdc2_data_off: sdc2_data_off { + config { + pins = "sdc2_data"; + bias-pull-up; /* pull up */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + sdc2_cd_on: cd_on { + mux { + pins = "gpio88"; + function = "gpio"; + }; + + config { + pins = "gpio88"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + sdc2_cd_off: cd_off { + mux { + pins = "gpio88"; + function = "gpio"; + }; + + config { + pins = "gpio88"; + drive-strength = <2>; + bias-disable; + }; + }; + + /* WSA speaker reset pin1 */ + spkr_1_sd_n { + spkr_1_sd_n_sleep: spkr_1_sd_n_sleep { + mux { + pins = "gpio106"; + function = "gpio"; + }; + + config { + pins = "gpio106"; + drive-strength = <2>; /* 2 mA */ + bias-pull-down; + input-enable; + }; + }; + + spkr_1_sd_n_active: spkr_1_sd_n_active { + mux { + pins = "gpio106"; + function = "gpio"; + }; + + config { + pins = "gpio106"; + drive-strength = <16>; /* 16 mA */ + bias-disable; + output-high; + }; + }; + }; + + fsa_usbc_ana_en_n@102 { + fsa_usbc_ana_en: fsa_usbc_ana_en { + mux { + pins = "gpio102"; + function = "gpio"; + }; + + config { + pins = "gpio102"; + drive-strength = <2>; + bias-disable; + output-low; + }; + }; + }; + + qupv3_se0_i2c_pins: qupv3_se0_i2c_pins { + qupv3_se0_i2c_active: qupv3_se0_i2c_active { + mux { + pins = "gpio0", "gpio1"; + function = "qup0"; + }; + + config { + pins = "gpio0", "gpio1"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se0_i2c_sleep: qupv3_se0_i2c_sleep { + mux { + pins = "gpio0", "gpio1"; + function = "gpio"; + }; + + config { + pins = "gpio0", "gpio1"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se0_spi_pins: qupv3_se0_spi_pins { + qupv3_se0_spi_active: qupv3_se0_spi_active { + mux { + pins = "gpio0", "gpio1", + "gpio2", "gpio3"; + function = "qup0"; + }; + + config { + pins = "gpio0", "gpio1", + "gpio2", "gpio3"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se0_spi_sleep: qupv3_se0_spi_sleep { + mux { + pins = "gpio0", "gpio1", + "gpio2", "gpio3"; + function = "gpio"; + }; + + config { + pins = "gpio0", "gpio1", + "gpio2", "gpio3"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + qupv3_se1_i2c_pins: qupv3_se1_i2c_pins { + qupv3_se1_i2c_active: qupv3_se1_i2c_active { + mux { + pins = "gpio4", "gpio5"; + function = "qup1"; + }; + + config { + pins = "gpio4", "gpio5"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se1_i2c_sleep: qupv3_se1_i2c_sleep { + mux { + pins = "gpio4", "gpio5"; + function = "gpio"; + }; + + config { + pins = "gpio4", "gpio5"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + nfc { + nfc_int_active: nfc_int_active { + /* active state */ + mux { + /* GPIO 70 NFC Read Interrupt */ + pins = "gpio70"; + function = "gpio"; + }; + + config { + pins = "gpio70"; + drive-strength = <2>; /* 2 MA */ + bias-pull-up; + }; + }; + + nfc_int_suspend: nfc_int_suspend { + /* sleep state */ + mux { + /* GPIO 70 NFC Read Interrupt */ + pins = "gpio70"; + function = "gpio"; + }; + + config { + pins = "gpio70"; + drive-strength = <2>; /* 2 MA */ + bias-pull-up; + }; + }; + + nfc_enable_active: nfc_enable_active { + /* active state */ + mux { + /* 69: Enable 31: Firmware */ + pins = "gpio69", "gpio31"; + function = "gpio"; + }; + + config { + pins = "gpio69", "gpio31"; + drive-strength = <2>; /* 2 MA */ + bias-pull-up; + }; + }; + + nfc_enable_suspend: nfc_enable_suspend { + /* sleep state */ + mux { + /* 69: Enable 31: Firmware */ + pins = "gpio69", "gpio31"; + function = "gpio"; + }; + + config { + pins = "gpio69", "gpio31"; + drive-strength = <2>; /* 2 MA */ + bias-disable; + }; + }; + + nfc_clk_req_active: nfc_clk_req_active { + /* active state */ + mux { + /* GPIO 86: NFC CLOCK REQUEST */ + pins = "gpio86"; + function = "gpio"; + }; + + config { + pins = "gpio86"; + drive-strength = <2>; /* 2 MA */ + bias-pull-up; + }; + }; + + nfc_clk_req_suspend: nfc_clk_req_suspend { + /* sleep state */ + mux { + /* GPIO 86: NFC CLOCK REQUEST */ + pins = "gpio86"; + function = "gpio"; + }; + + config { + pins = "gpio86"; + drive-strength = <2>; /* 2 MA */ + bias-disable; + }; + }; + }; + + qupv3_se1_spi_pins: qupv3_se1_spi_pins { + qupv3_se1_spi_active: qupv3_se1_spi_active { + mux { + pins = "gpio4", "gpio5", + "gpio69", "gpio70"; + function = "qup1"; + }; + + config { + pins = "gpio4", "gpio5", + "gpio69", "gpio70"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se1_spi_sleep: qupv3_se1_spi_sleep { + mux { + pins = "gpio4", "gpio5", + "gpio69", "gpio70"; + function = "gpio"; + }; + + config { + pins = "gpio4", "gpio5", + "gpio69", "gpio70"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + qupv3_se2_i2c_pins: qupv3_se2_i2c_pins { + qupv3_se2_i2c_active: qupv3_se2_i2c_active { + mux { + pins = "gpio6", "gpio7"; + function = "qup2"; + }; + + config { + pins = "gpio6", "gpio7"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se2_i2c_sleep: qupv3_se2_i2c_sleep { + mux { + pins = "gpio6", "gpio7"; + function = "gpio"; + }; + + config { + pins = "gpio6", "gpio7"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se2_spi_pins: qupv3_se2_spi_pins { + qupv3_se2_spi_active: qupv3_se2_spi_active { + mux { + pins = "gpio6", "gpio7", + "gpio71", "gpio80"; + function = "qup2"; + }; + + config { + pins = "gpio6", "gpio7", + "gpio71", "gpio80"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se2_spi_sleep: qupv3_se2_spi_sleep { + mux { + pins = "gpio6", "gpio7", + "gpio71", "gpio80"; + function = "gpio"; + }; + + config { + pins = "gpio6", "gpio7", + "gpio71", "gpio80"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + qupv3_se3_4uart_pins: qupv3_se3_4uart_pins { + qupv3_se3_default_ctsrtsrx: + qupv3_se3_default_ctsrtsrx { + mux { + pins = "gpio8", "gpio9", "gpio11"; + function = "gpio"; + }; + + config { + pins = "gpio8", "gpio9", "gpio11"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + qupv3_se3_default_tx: + qupv3_se3_default_tx { + mux { + pins = "gpio10"; + function = "gpio"; + }; + + config { + pins = "gpio10"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se3_ctsrx: qupv3_se3_ctsrx { + mux { + pins = "gpio8", "gpio11"; + function = "qup3"; + }; + + config { + pins = "gpio8", "gpio11"; + drive-strength = <2>; + bias-disable; + }; + }; + + qupv3_se3_rts: qupv3_se3_rts { + mux { + pins = "gpio9"; + function = "qup3"; + }; + + config { + pins = "gpio9"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + qupv3_se3_tx: qupv3_se3_tx { + mux { + pins = "gpio10"; + function = "qup3"; + }; + + config { + pins = "gpio10"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + + qupv3_se5_i2c_pins: qupv3_se5_i2c_pins { + qupv3_se5_i2c_active: qupv3_se5_i2c_active { + mux { + pins = "gpio14", "gpio15"; + function = "qup5"; + }; + + config { + pins = "gpio14", "gpio15"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qupv3_se5_i2c_sleep: qupv3_se5_i2c_sleep { + mux { + pins = "gpio14", "gpio15"; + function = "gpio"; + }; + + config { + pins = "gpio14", "gpio15"; + drive-strength = <2>; + bias-disable; + }; + }; + }; + + qupv3_se5_spi_pins: qupv3_se5_spi_pins { + qupv3_se5_spi_active: qupv3_se5_spi_active { + mux { + pins = "gpio14", "gpio15", + "gpio16", "gpio17"; + function = "qup5"; + }; + + config { + pins = "gpio14", "gpio15", + "gpio16", "gpio17"; + drive-strength = <6>; + bias-disable; + }; + }; + + qupv3_se5_spi_sleep: qupv3_se5_spi_sleep { + mux { + pins = "gpio14", "gpio15", + "gpio16", "gpio17"; + function = "gpio"; + }; + + config { + pins = "gpio14", "gpio15", + "gpio16", "gpio17"; + drive-strength = <6>; + bias-disable; + }; + }; + }; + + pmx_sde: pmx_sde { + sde_dsi_active: sde_dsi_active { + mux { + pins = "gpio82", "gpio105"; + function = "gpio"; + }; + + config { + pins = "gpio82", "gpio105"; + drive-strength = <8>; + bias-disable = <0>; + }; + }; + + sde_dsi_suspend: sde_dsi_suspend { + mux { + pins = "gpio82", "gpio105"; + function = "gpio"; + }; + + config { + pins = "gpio82", "gpio105"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + pmx_sde_te { + sde_te_active: sde_te_active { + mux { + pins = "gpio81"; + function = "mdp_vsync"; + }; + + config { + pins = "gpio81"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + sde_te_suspend: sde_te_suspend { + mux { + pins = "gpio81"; + function = "mdp_vsync"; + }; + + config { + pins = "gpio81"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + pmx_ts_int_active { + ts_int_active: ts_int_active { + mux { + pins = "gpio80"; + function = "gpio"; + }; + + config { + pins = "gpio80"; + drive-strength = <8>; + bias-pull-up; + }; + }; + }; + + pmx_ts_int_suspend { + ts_int_suspend: ts_int_suspend { + mux { + pins = "gpio80"; + function = "gpio"; + }; + + config { + pins = "gpio80"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + pmx_ts_reset_active { + ts_reset_active: ts_reset_active { + mux { + pins = "gpio71"; + function = "gpio"; + }; + + config { + pins = "gpio71"; + drive-strength = <8>; + bias-pull-up; + }; + }; + }; + + pmx_ts_reset_suspend { + ts_reset_suspend: ts_reset_suspend { + mux { + pins = "gpio71"; + function = "gpio"; + }; + + config { + pins = "gpio71"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + pmx_ts_release { + ts_release: ts_release { + mux { + pins = "gpio80", "gpio71"; + function = "gpio"; + }; + + config { + pins = "gpio80", "gpio71"; + drive-strength = <2>; + bias-pull-down; + }; + }; + }; + + pm8008_interrupt: pm8008_interrupt { + mux { + pins = "gpio25"; + function = "gpio"; + }; + + config { + pins = "gpio25"; + bias-disable; + input-enable; + }; + }; + + pm8008_active: pm8008_active { + mux { + pins = "gpio26"; + function = "gpio"; + }; + + config { + pins = "gpio26"; + bias-pull-up; + output-high; + drive-strength = <2>; + }; + }; + + cci0_suspend: cci0_suspend { + mux { + /* CLK, DATA*/ + pins = "gpio23", "gpio22"; + function = "cci_i2c"; + }; + + config { + pins = "gpio23", "gpio22"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci0_active: cci0_active { + mux { + /* CLK, DATA*/ + pins = "gpio23", "gpio22"; + function = "cci_i2c"; + }; + + config { + pins = "gpio23", "gpio22"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci1_suspend: cci1_suspend { + mux { + /* CLK, DATA*/ + pins = "gpio30", "gpio29"; + function = "cci_i2c"; + }; + + config { + pins = "gpio30", "gpio29"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cci1_active: cci1_active { + mux { + /* CLK, DATA*/ + pins = "gpio30", "gpio29"; + function = "cci_i2c"; + }; + + config { + pins = "gpio30", "gpio29"; + bias-pull-up; /* PULL UP*/ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk0_active: cam_sensor_mclk0_active { + /* MCLK 0*/ + mux { + pins = "gpio20"; + function = "cam_mclk"; + }; + + config { + pins = "gpio20"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk0_suspend: cam_sensor_mclk0_suspend { + /* MCLK 0*/ + mux { + pins = "gpio20"; + function = "cam_mclk"; + }; + + config { + pins = "gpio20"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk1_active: cam_sensor_mclk1_active { + /* MCLK 1*/ + mux { + pins = "gpio21"; + function = "cam_mclk"; + }; + + config { + pins = "gpio21"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk1_suspend: cam_sensor_mclk1_suspend { + /* MCLK 1*/ + mux { + pins = "gpio21"; + function = "cam_mclk"; + }; + + config { + pins = "gpio21"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk2_active: cam_sensor_mclk2_active { + /* MCLK 2*/ + mux { + pins = "gpio27"; + function = "cam_mclk"; + }; + + config { + pins = "gpio27"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_mclk2_suspend: cam_sensor_mclk2_suspend { + /* MCLK 2*/ + mux { + pins = "gpio27"; + function = "cam_mclk"; + }; + + config { + pins = "gpio27"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear0_reset_active: cam_sensor_rear0_reset_active { + /* RESET0 */ + mux { + pins = "gpio18"; + function = "gpio"; + }; + + config { + pins = "gpio18"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear0_reset_suspend: cam_sensor_rear0_reset_suspend { + /* RESET0 */ + mux { + pins = "gpio18"; + function = "gpio"; + }; + + config { + pins = "gpio18"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_rear1_reset_active: cam_sensor_rear1_reset_active { + /* RESET1 */ + mux { + pins = "gpio19"; + function = "gpio"; + }; + + config { + pins = "gpio19"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_rear1_reset_suspend: cam_sensor_rear1_reset_suspend { + /* RESET1 */ + mux { + pins = "gpio19"; + function = "gpio"; + }; + + config { + pins = "gpio19"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + + cam_sensor_front0_reset_active: cam_sensor_front0_reset_active { + /* RESET0 */ + mux { + pins = "gpio24"; + function = "gpio"; + }; + + config { + pins = "gpio24"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_front0_reset_suspend: cam_sensor_front0_reset_suspend { + /* RESET0 */ + mux { + pins = "gpio24"; + function = "gpio"; + }; + + config { + pins = "gpio24"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_csi_mux_oe_active: cam_sensor_csi_mux_oe_active { + /*CSIMUX_OE*/ + mux { + pins = "gpio113"; + function = "gpio"; + }; + + config { + pins = "gpio113"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_csi_mux_oe_suspend: cam_sensor_csi_mux_oe_suspend { + /* CSIMUX_OE */ + mux { + pins = "gpio113"; + function = "gpio"; + }; + + config { + pins = "gpio113"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + cam_sensor_csi_mux_sel_active: cam_sensor_csi_mux_sel_active { + /*CSIMUX_SEL*/ + mux { + pins = "gpio114"; + function = "gpio"; + }; + + config { + pins = "gpio114"; + bias-disable; /* No PULL */ + drive-strength = <2>; /* 2 MA */ + }; + }; + + cam_sensor_csi_mux_sel_suspend: cam_sensor_csi_mux_sel_suspend { + /* CSIMUX_SEL */ + mux { + pins = "gpio114"; + function = "gpio"; + }; + + config { + pins = "gpio114"; + bias-pull-down; /* PULL DOWN */ + drive-strength = <2>; /* 2 MA */ + output-low; + }; + }; + + gpio_vol_up: gpio_vol_up { + mux { + pins = "gpio96"; + function = "gpio"; + }; + + config { + pins = "gpio96"; + drive-strength = <2>; + bias-pull-up; + input-enable; + }; + }; + + usb_id_interrupt: usb_id_interrupt { + mux { + pins = "gpio89"; + function = "gpio"; + }; + + config { + pins = "gpio89"; + bias-pull-up; + input-enable; + }; + }; + }; +}; diff --git a/qcom/scuba-iot.dts b/qcom/scuba-iot.dts new file mode 100644 index 000000000000..804c12bd9c93 --- /dev/null +++ b/qcom/scuba-iot.dts @@ -0,0 +1,9 @@ +/dts-v1/; + +#include "scuba-iot.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Scuba IOT SoC"; + compatible = "qcom,scuba-iot"; + qcom,board-id = <0 0>; +}; diff --git a/qcom/scuba-iot.dtsi b/qcom/scuba-iot.dtsi new file mode 100644 index 000000000000..c07dcefb4820 --- /dev/null +++ b/qcom/scuba-iot.dtsi @@ -0,0 +1,707 @@ +#include +#include +#include + +/ { + model = "Qualcomm Technologies, Inc. SCUBA"; + compatible = "qcom,scuba"; + qcom,msm-id = <441 0x10000>; + + #address-cells = <2>; + #size-cells = <2>; + memory { device_type = "memory"; reg = <0 0 0 0>; }; + + mem-offline { + compatible = "qcom,mem-offline"; + offline-sizes = <0x1 0x40000000 0x0 0x40000000>, + <0x1 0xc0000000 0x0 0x80000000>, + <0x2 0xc0000000 0x1 0x40000000>; + granule = <512>; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x0>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + next-level-cache = <&L2_0>; + L2_0: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + }; + + L1_I_0: l1-icache { + compatible = "arm,arch-cache"; + }; + + L1_D_0: l1-dcache { + compatible = "arm,arch-cache"; + }; + }; + + CPU1: cpu@1 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x1>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + next-level-cache = <&L2_0>; + + L1_I_1: l1-icache { + compatible = "arm,arch-cache"; + }; + + L1_D_1: l1-dcache { + compatible = "arm,arch-cache"; + }; + }; + + CPU2: cpu@2 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x2>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + next-level-cache = <&L2_0>; + + L1_I_2: l1-icache { + compatible = "arm,arch-cache"; + }; + + L1_D_2: l1-dcache { + compatible = "arm,arch-cache"; + }; + }; + + CPU3: cpu@3 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x3>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + next-level-cache = <&L2_0>; + + L1_I_3: l1-icache { + compatible = "arm,arch-cache"; + }; + + L1_D_3: l1-dcache { + compatible = "arm,arch-cache"; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + + core1 { + cpu = <&CPU1>; + }; + + core2 { + cpu = <&CPU2>; + }; + + core3 { + cpu = <&CPU3>; + }; + }; + }; + }; + + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + hyp_region: hyp_region@45700000 { + no-map; + reg = <0x0 0x45700000 0x0 0x600000>; + }; + + xbl_aop_mem: xbl_aop_mem@45e00000 { + no-map; + reg = <0x0 0x45e00000 0x0 0x100000>; + }; + + sec_apps_mem: sec_apps_region@45fff000 { + no-map; + reg = <0x0 0x45fff000 0x0 0x1000>; + }; + + smem_region: smem@46000000 { + no-map; + reg = <0x0 0x46000000 0x0 0x200000>; + }; + + pil_modem_mem: modem_region@4ab00000 { + no-map; + reg = <0x0 0x4ab00000 0x0 0x6900000>; + }; + + pil_video_mem: pil_video_region@51400000 { + no-map; + reg = <0x0 0x51400000 0x0 0x500000>; + }; + + wlan_msa_mem: wlan_msa_region@51900000 { + no-map; + reg = <0x0 0x51900000 0x0 0x100000>; + }; + + pil_adsp_mem: adsp_regions@51a00000 { + no-map; + reg = <0x0 0x51a00000 0x0 0x1c00000>; + }; + + pil_ipa_fw_mem: ips_fw_region@53600000 { + no-map; + reg = <0x0 0x53600000 0x0 0x10000>; + }; + + pil_ipa_gsi_mem: ipa_gsi_region@53610000 { + no-map; + reg = <0x0 0x53610000 0x0 0x5000>; + }; + + pil_gpu_mem: gpu_region@53615000 { + no-map; + reg = <0x0 0x53615000 0x0 0x2000>; + }; + + removed_region: removed_region@60000000 { + no-map; + reg = <0x0 0x60000000 0x0 0x3900000>; + }; + + adsp_mem: adsp_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x00000000 0 0xffffffff>; + reusable; + alignment = <0 0x400000>; + size = <0 0x800000>; + }; + + dump_mem: mem_dump_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + size = <0 0x800000>; + }; + + secure_display_memory: secure_display_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0 0x00000000 0 0xffffffff>; + reusable; + alignment = <0 0x400000>; + size = <0 0x5c00000>; + }; + + cont_splash_memory: cont_splash_region@5c000000 { + reg = <0x0 0x5c000000 0x0 0x00f00000>; + label = "cont_splash_region"; + }; + + dfps_data_memory: dfps_data_region@5cf00000 { + reg = <0x0 0x5cf00000 0x0 0x0100000>; + label = "dfps_data_region"; + }; + + disp_rdump_memory: disp_rdump_region@5c000000 { + reg = <0x0 0x5c000000 0x0 0x00f00000>; + label = "disp_rdump_region"; + }; + + qseecom_mem: qseecom_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x1400000>; + }; + + qseecom_ta_mem: qseecom_ta_region { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x1000000>; + }; + + /* global autoconfigured region for contiguous allocations */ + linux,cma { + compatible = "shared-dma-pool"; + alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>; + reusable; + alignment = <0x0 0x400000>; + size = <0x0 0x2000000>; + linux,cma-default; + }; + }; + + chosen { + bootargs = "rcupdate.rcu_expedited=1 rcu_nocbs=0-7"; + }; + + soc: soc { }; +}; + +&soc { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + compatible = "simple-bus"; + + intc: interrupt-controller@f200000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + interrupt-controller; + interrupt-parent = <&intc>; + #redistributor-regions = <1>; + redistributor-stride = <0x0 0x20000>; + reg = <0xf200000 0x10000>, /* GICD */ + <0xf300000 0x100000>; /* GICR * 8 */ + interrupts = <1 9 4>; + }; + + + timer { + compatible = "arm,armv8-timer"; + interrupts = <1 1 0xf08>, + <1 2 0xf08>, + <1 3 0xf08>, + <1 0 0xf08>; + clock-frequency = <19200000>; + }; + + + timer@f120000 { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "arm,armv7-timer-mem"; + reg = <0xf120000 0x1000>; + clock-frequency = <19200000>; + + frame@f121000 { + frame-number = <0>; + interrupts = <0 8 0x4>, + <0 7 0x4>; + reg = <0xf121000 0x1000>, + <0xf122000 0x1000>; + }; + + frame@f123000 { + frame-number = <1>; + interrupts = <0 9 0x4>; + reg = <0xf123000 0x1000>; + status = "disabled"; + }; + + frame@f124000 { + frame-number = <2>; + interrupts = <0 10 0x4>; + reg = <0xf124000 0x1000>; + status = "disabled"; + }; + + frame@f125000 { + frame-number = <3>; + interrupts = <0 11 0x4>; + reg = <0xf125000 0x1000>; + status = "disabled"; + }; + + frame@f126000 { + frame-number = <4>; + interrupts = <0 12 0x4>; + reg = <0xf126000 0x1000>; + status = "disabled"; + }; + + frame@f127000 { + frame-number = <5>; + interrupts = <0 13 0x4>; + reg = <0xf127000 0x1000>; + status = "disabled"; + }; + + frame@f128000 { + frame-number = <6>; + interrupts = <0 14 0x4>; + reg = <0xf128000 0x1000>; + status = "disabled"; + }; + }; + + qcom,msm-imem@c125000 { + compatible = "qcom,msm-imem"; + reg = <0xc125000 0x1000>; + ranges = <0x0 0xc125000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + mem_dump_table@10 { + compatible = "qcom,msm-imem-mem_dump_table"; + reg = <0x10 0x8>; + }; + + restart_reason@65c { + compatible = "qcom,msm-imem-restart_reason"; + reg = <0x65c 0x4>; + }; + + dload_type@1c { + compatible = "qcom,msm-imem-dload-type"; + reg = <0x1c 0x4>; + }; + + boot_stats@6b0 { + compatible = "qcom,msm-imem-boot_stats"; + reg = <0x6b0 0x20>; + }; + + kaslr_offset@6d0 { + compatible = "qcom,msm-imem-kaslr_offset"; + reg = <0x6d0 0xc>; + }; + + pil@94c { + compatible = "qcom,msm-imem-pil"; + reg = <0x94c 0xc8>; + }; + + diag_dload@c8 { + compatible = "qcom,msm-imem-diag-dload"; + reg = <0xc8 0xc8>; + }; + }; + + restart@440b000 { + compatible = "qcom,pshold"; + reg = <0x440b000 0x4>, + <0x03d3000 0x4>; + reg-names = "pshold-base", "tcsr-boot-misc-detect"; + status="disabled"; + }; + + qcom,mpm2-sleep-counter@4403000 { + compatible = "qcom,mpm2-sleep-counter"; + reg = <0x4403000 0x1000>; + clock-frequency = <32768>; + status="disabled"; + }; + + qcom,msm-rtb { + compatible = "qcom,msm-rtb"; + qcom,rtb-size = <0x100000>; + status="disabled"; + }; + + qcom,chd_silver { + compatible = "qcom,core-hang-detect"; + label = "silver"; + qcom,threshold-arr = <0x0f1880b0 0x0f1980b0 + 0x0f1a80b0 0x0f1b80b0>; + qcom,config-arr = <0x0f1880b8 0x0f1980b8 + 0x0f1a80b8 0x0f1b80b8>; + + status="disabled"; + }; + + qfprom: qfprom@1b40000 { + compatible = "qcom,qfprom"; + reg = <0x1b40000 0x7000>; + #address-cells = <1>; + #size-cells = <1>; + read-only; + ranges; + status="disabled"; + feat_conf5: feat_conf5@6018 { + reg = <0x6018 0x4>; + }; + + }; + + wdog: qcom,wdt@f017000 { + compatible = "qcom,msm-watchdog"; + reg = <0xf017000 0x1000>; + reg-names = "wdt-base"; + interrupts = , + ; + qcom,bark-time = <11000>; + qcom,pet-time = <9360>; + qcom,ipi-ping; + qcom,wakeup-enable; + status = "disabled"; + }; + +dcc: dcc_v2@1be2000 { + compatible = "qcom,dcc-v2"; + reg = <0x1be2000 0x1000>, + <0x1bee000 0x2000>; + reg-names = "dcc-base", "dcc-ram-base"; + dcc-ram-offset = <0x2000>; + status = "disabled"; + }; + + rpm_bus: qcom,rpm-smd { + compatible = "qcom,rpm-smd"; + rpm-channel-name = "rpm_requests"; + interrupts = ; + rpm-channel-type = <15>; /* SMD_APPS_RPM */ + }; + + mem_dump { + compatible = "qcom,mem-dump"; + memory-region = <&dump_mem>; + + c0_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x0>; + }; + + c1_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x1>; + }; + + c2_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x2>; + }; + + c3_context { + qcom,dump-size = <0x800>; + qcom,dump-id = <0x3>; + }; + + l1_icache0 { + qcom,dump-size = <0x9040>; + qcom,dump-id = <0x60>; + }; + + l1_icache1 { + qcom,dump-size = <0x9040>; + qcom,dump-id = <0x61>; + }; + + l1_icache2 { + qcom,dump-size = <0x9040>; + qcom,dump-id = <0x62>; + }; + + l1_icache3 { + qcom,dump-size = <0x9040>; + qcom,dump-id = <0x63>; + }; + + l1_dcache0 { + qcom,dump-size = <0x9040>; + qcom,dump-id = <0x80>; + }; + + l1_dcache1 { + qcom,dump-size = <0x9040>; + qcom,dump-id = <0x81>; + }; + + l1_dcache2 { + qcom,dump-size = <0x9040>; + qcom,dump-id = <0x82>; + }; + + l1_dcache3 { + qcom,dump-size = <0x9040>; + qcom,dump-id = <0x83>; + }; + + l2_tlb0 { + qcom,dump-size = <0x2000>; + qcom,dump-id = <0x120>; + }; + + l2_tlb1 { + qcom,dump-size = <0x2000>; + qcom,dump-id = <0x121>; + }; + + l2_tlb2 { + qcom,dump-size = <0x2000>; + qcom,dump-id = <0x122>; + }; + + l2_tlb3 { + qcom,dump-size = <0x2000>; + qcom,dump-id = <0x123>; + }; + }; + + spmi_bus: qcom,spmi@1c40000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0x1c40000 0x1100>, + <0x1e00000 0x2000000>, + <0x3e00000 0x100000>, + <0x3f00000 0xa0000>, + <0x1c0a000 0x26000>; + reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; + interrupt-names = "periph_irq"; + interrupts = ; + qcom,ee = <0>; + qcom,channel = <0>; + #address-cells = <1>; + #size-cells = <1>; + interrupt-controller; + #interrupt-cells = <4>; + cell-index = <0>; + }; +}; + +#include "pm2250.dtsi" +#include "pm2250-rpm-regulator.dtsi" +#include "scuba-regulator.dtsi" +#include "scuba-iot-pinctrl.dtsi" +#include "scuba-ion.dtsi" +#include "msm-arm-smmu-scuba.dtsi" + +&pm2250_vadc { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&conn_therm_default &skin_therm_default>; + + xo_therm { + reg = ; + label = "xo_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + pa_therm { + reg = ; + label = "pa_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + quiet_therm { + reg = ; + label = "quiet_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + msm_therm { + reg = ; + label = "msm_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + skin_therm { + reg = ; + label = "skin_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; + + conn_therm { + reg = ; + label = "conn_therm"; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + qcom,pre-scaling = <1 1>; + }; +}; + +&pm2250_gpios { + skin_therm { + skin_therm_default: skin_therm_default { + pins = "gpio5"; + bias-high-impedance; + }; + }; + + conn_therm { + conn_therm_default: conn_therm_default { + pins = "gpio6"; + bias-high-impedance; + }; + }; +}; + +&spmi_bus { + qcom,pm2250@0 { + pm2250_adc_tm_iio: adc_tm@3400 { + compatible = "qcom,adc-tm5-iio"; + reg = <0x3400 0x100>; + #thermal-sensor-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + io-channels = <&pm2250_vadc ADC5_XO_THERM_100K_PU>, + <&pm2250_vadc ADC5_AMUX_THM1_100K_PU>, + <&pm2250_vadc ADC5_AMUX_THM2_100K_PU>, + <&pm2250_vadc ADC5_AMUX_THM3_100K_PU>, + <&pm2250_vadc ADC5_GPIO3_100K_PU>, + <&pm2250_vadc ADC5_GPIO4_100K_PU>, + <&pm2250_vadc ADC5_SBUx>; + + xo_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + pa_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + quiet_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + msm_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + skin_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + conn_therm { + reg = ; + qcom,ratiometric; + qcom,hw-settle-time = <200>; + }; + + s3_die_temp { + reg = ; + }; + }; + }; +}; diff --git a/qcom/scuba-regulator.dtsi b/qcom/scuba-regulator.dtsi new file mode 100644 index 000000000000..a1344d005c24 --- /dev/null +++ b/qcom/scuba-regulator.dtsi @@ -0,0 +1,348 @@ +#include +#include + +&rpm_bus { + /* PM2250 S2 - VDD_CX supply */ + rpm-regulator-smpa2 { + status = "okay"; + qcom,resource-name = "rwcx"; + qcom,resource-id = <0>; + + VDD_CX_LEVEL: + VDD_GFX_LEVEL: + VDD_MSS_LEVEL: + S2A_LEVEL: pm2250_s2_level: regulator-s2-level { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm2250_s2_level"; + qcom,set = <3>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,use-voltage-level; + }; + + VDD_CX_FLOOR_LEVEL: + VDD_MSS_FLOOR_LEVEL: + S2A_FLOOR_LEVEL: + pm2250_s2_floor_level: regulator-s2-floor-level { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm2250_s2_floor_level"; + qcom,set = <3>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,use-voltage-floor-level; + qcom,always-send-voltage; + }; + + VDD_CX_LEVEL_AO: + VDD_MSS_LEVEL_AO: + S2A_LEVEL_AO: pm2250_s2_level_ao: regulator-s2-level-ao { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm2250_s2_level_ao"; + qcom,set = <1>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,use-voltage-level; + }; + }; + + /* PM2250 L1 - VDD_MX/WCSS_MX supply */ + rpm-regulator-ldoa1 { + status = "okay"; + qcom,resource-name = "rwmx"; + qcom,resource-id = <0>; + + VDD_MX_LEVEL: + L1A_LEVEL: pm2250_l1_level: regulator-l1-level { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm2250_l1_level"; + qcom,set = <3>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,use-voltage-level; + }; + + VDD_MX_FLOOR_LEVEL: + L1A_FLOOR_LEVEL: + pm2250_l1_floor_level: regulator-l1-floor-level { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm2250_l1_floor_level"; + qcom,set = <3>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,use-voltage-floor-level; + qcom,always-send-voltage; + }; + + VDD_MX_LEVEL_AO: + L1A_LEVEL_AO: pm2250_l1_level_ao: regulator-l1-level-ao { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm2250_l1_level_ao"; + qcom,set = <1>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,use-voltage-level; + }; + }; + + rpm-regulator-smpa3 { + status = "okay"; + S3A: pm2250_s3: regulator-s3 { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <1662500>; + qcom,init-voltage = <400000>; + status = "okay"; + }; + }; + + rpm-regulator-smpa4 { + status = "okay"; + S4A: pm2250_s4: regulator-s4 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <2350000>; + qcom,init-voltage = <1200000>; + status = "okay"; + }; + }; + + /* VDD_LPI_CX supply */ + rpm-regulator-ldoa8 { + status = "okay"; + qcom,resource-name = "rwlc"; + qcom,resource-id = <0>; + + VDD_LPI_CX_LEVEL: + L8A_LEVEL: pm2250_l8_level: regulator-l8-level { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm2250_l8_level"; + qcom,set = <3>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,use-voltage-level; + }; + }; + + /* VDD_LPI_MX supply */ + rpm-regulator-ldoa9 { + status = "okay"; + qcom,resource-name = "rwlm"; + qcom,resource-id = <0>; + + VDD_LPI_MX_LEVEL: + L9A_LEVEL: pm2250_l9_level: regulator-l9-level { + compatible = "qcom,rpm-smd-regulator"; + regulator-name = "pm2250_l9_level"; + qcom,set = <3>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,use-voltage-level; + }; + }; + + rpm-regulator-ldoa2 { + status = "okay"; + L2A: pm2250_l2: regulator-l2 { + regulator-min-microvolt = <1060000>; + regulator-max-microvolt = <1300000>; + qcom,init-voltage = <1060000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa3 { + status = "okay"; + L3A: pm2250_l3: regulator-l3 { + regulator-min-microvolt = <570000>; + regulator-max-microvolt = <650000>; + qcom,init-voltage = <570000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa4 { + status = "okay"; + L4A: pm2250_l4: regulator-l4 { + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <3050000>; + qcom,init-voltage = <1650000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa5 { + status = "okay"; + L5A: pm2250_l5: regulator-l5 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1312000>; + qcom,init-voltage = <1100000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa6 { + status = "okay"; + L6A: pm2250_l6: regulator-l6 { + regulator-min-microvolt = <488000>; + regulator-max-microvolt = <1000000>; + qcom,init-voltage = <488000>; + status = "okay"; + }; + }; + + /* WCSS_CX */ + rpm-regulator-ldoa7 { + status = "okay"; + WCSS_CX: + L7A: pm2250_l7: regulator-l7 { + regulator-min-microvolt = <400000>; + regulator-max-microvolt = <728000>; + qcom,init-voltage = <400000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa10 { + status = "okay"; + L10A: pm2250_l10: regulator-l10 { + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1380000>; + qcom,init-voltage = <1150000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa11 { + status = "okay"; + L11A: pm2250_l11: regulator-l11 { + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1150000>; + qcom,init-voltage = <950000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa12 { + status = "okay"; + L12A: pm2250_l12: regulator-l12 { + regulator-min-microvolt = <488000>; + regulator-max-microvolt = <1000000>; + qcom,init-voltage = <488000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa13 { + status = "okay"; + L13A: pm2250_l13: regulator-l13 { + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <1950000>; + qcom,init-voltage = <1650000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa14 { + status = "okay"; + L14A: pm2250_l14: regulator-l14 { + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <1950000>; + qcom,init-voltage = <1700000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa15 { + status = "okay"; + L15A: pm2250_l15: regulator-l15 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <2000000>; + qcom,init-voltage = <1200000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa16 { + status = "okay"; + L16A: pm2250_l16: regulator-l16 { + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1950000>; + qcom,init-voltage = <1500000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa17 { + status = "okay"; + L17A: pm2250_l17: regulator-l17 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3600000>; + qcom,init-voltage = <3000000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa18 { + status = "okay"; + L18A: pm2250_l18: regulator-l18 { + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <3300000>; + qcom,init-voltage = <1620000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa19 { + status = "okay"; + L19A: pm2250_l19: regulator-l19 { + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <3300000>; + qcom,init-voltage = <1620000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa20 { + status = "okay"; + L20A: pm2250_l20: regulator-l20 { + regulator-min-microvolt = <2400000>; + regulator-max-microvolt = <3600000>; + qcom,init-voltage = <2400000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa21 { + status = "okay"; + L21A: pm2250_l21: regulator-l21 { + regulator-min-microvolt = <2921000>; + regulator-max-microvolt = <3300000>; + qcom,init-voltage = <2921000>; + status = "okay"; + }; + }; + + rpm-regulator-ldoa22 { + status = "okay"; + L22A: pm2250_l22: regulator-l22 { + regulator-min-microvolt = <2850000>; + regulator-max-microvolt = <3400000>; + qcom,init-voltage = <2850000>; + status = "okay"; + }; + }; +}; From 7ff766a2eff619d278f2e85a71a71de62c17a662 Mon Sep 17 00:00:00 2001 From: Nitin Rawat Date: Mon, 31 Aug 2020 17:16:43 +0530 Subject: [PATCH 66/88] ARM: dts: msm: Update UFS VCC regulator min voltage for shima Update UFS VCC regulator min voltage for shima. Change-Id: I4d578084a83b9bcfb7a2b2e6d62b05c7e5ab2778 --- qcom/shima-idp.dtsi | 2 +- qcom/shima-qrd.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/qcom/shima-idp.dtsi b/qcom/shima-idp.dtsi index a4be84ba4aee..bc2af6b9abc1 100644 --- a/qcom/shima-idp.dtsi +++ b/qcom/shima-idp.dtsi @@ -98,7 +98,7 @@ vdd-hba-fixed-regulator; vcc-supply = <&L7B>; - vcc-voltage-level = <2950000 2960000>; + vcc-voltage-level = <2504000 2960000>; vcc-low-voltage-sup; vcc-max-microamp = <800000>; diff --git a/qcom/shima-qrd.dtsi b/qcom/shima-qrd.dtsi index fd21a2271113..ac9acf7b55a4 100644 --- a/qcom/shima-qrd.dtsi +++ b/qcom/shima-qrd.dtsi @@ -99,7 +99,7 @@ vdd-hba-fixed-regulator; vcc-supply = <&L7B>; - vcc-voltage-level = <2950000 2960000>; + vcc-voltage-level = <2504000 2960000>; vcc-low-voltage-sup; vcc-max-microamp = <800000>; From 0d20299e32d0aaf83127a25c36e9e9159c26d8a5 Mon Sep 17 00:00:00 2001 From: Ram Prakash Gupta Date: Tue, 18 Aug 2020 02:17:25 +0530 Subject: [PATCH 67/88] ARM: dts: msm: Add hw gcc reset support for eMMC on shima Add hw gcc reset support for eMMC on shima. Change-Id: Icf62ee290c28d128bf1afc32520f8f08f9befd26 --- qcom/shima.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi index 650f05e7da66..05e191168fdd 100644 --- a/qcom/shima.dtsi +++ b/qcom/shima.dtsi @@ -1791,6 +1791,8 @@ mmc-hs400-1_8v; mmc-hs400-enhanced-strobe; + cap-mmc-hw-reset; + bus-width = <8>; non-removable; supports-cqe; @@ -1798,6 +1800,10 @@ qcom,devfreq,freq-table = <50000000 200000000>; qcom,scaling-lower-bus-speed-mode = "DDR52"; + /* Add dt entry for gcc hw reset */ + resets = <&gcc GCC_SDCC1_BCR>; + reset-names = "core_reset"; + status = "disabled"; qos0 { From 9334593032d564043b66dbc0d12e4af81a6b4b00 Mon Sep 17 00:00:00 2001 From: priyankar Date: Mon, 12 Oct 2020 12:04:49 +0530 Subject: [PATCH 68/88] ARM: dts: msm: add WL_EN entry in BT node Add WLAN_EN GPIO entry for shima BT device tree node to handle AON LDO fully discharge issue. Change-Id: I4c471ca3f3eaaf1da38c298560930da123a87811 --- qcom/shima.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi index 650f05e7da66..09d41282e38a 100644 --- a/qcom/shima.dtsi +++ b/qcom/shima.dtsi @@ -3630,6 +3630,7 @@ pinctrl-0 = <&bt_en_sleep>; qcom,bt-reset-gpio = <&tlmm 65 0>; /* BT_EN */ qcom,bt-sw-ctrl-gpio = <&tlmm 91 0>; /* SW_CTRL */ + qcom,wl-reset-gpio = <&tlmm 64 0>; /* WL_EN */ qcom,bt-vdd-io-supply = <&S10B>; qcom,bt-vdd-aon-supply = <&S2C>; From f506fa55a8f4f9d6cc2eff26e5a53a5f6572c30c Mon Sep 17 00:00:00 2001 From: Ram Prakash Gupta Date: Tue, 18 Aug 2020 02:30:24 +0530 Subject: [PATCH 69/88] ARM: dts: msm: Add hw gcc reset for sdcc on holi Add hw gcc reset support for sdcc on holi. Change-Id: Ibe1d2180f86b7df331968154f5d4c989d0cb563a --- qcom/holi.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/qcom/holi.dtsi b/qcom/holi.dtsi index 1d8a294b6fd4..aaa777bd39ec 100644 --- a/qcom/holi.dtsi +++ b/qcom/holi.dtsi @@ -2170,6 +2170,8 @@ mmc-hs400-1_8v; mmc-hs400-enhanced-strobe; + cap-mmc-hw-reset; + bus-width = <8>; non-removable; supports-cqe; @@ -2177,6 +2179,10 @@ qcom,devfreq,freq-table = <50000000 200000000>; qcom,scaling-lower-bus-speed-mode = "DDR52"; + /* Add dt entry for gcc hw reset */ + resets = <&gcc GCC_SDCC1_BCR>; + reset-names = "core_reset"; + status = "disabled"; qos0 { From f08804195c395d6e2c62b96232a8019036c1d5e0 Mon Sep 17 00:00:00 2001 From: Nitin Rawat Date: Tue, 13 Oct 2020 18:54:09 +0530 Subject: [PATCH 70/88] ARM: dts: msm: remove low voltage VCC support entry from DT Remove Low Vcc voltage support entry from DT. Change-Id: Ief37d864891bf44e71636fc4f84d58b56e6f7d36 --- qcom/lahaina-cdp.dtsi | 1 - qcom/lahaina-mtp.dtsi | 1 - qcom/lahaina-qrd-common.dtsi | 1 - 3 files changed, 3 deletions(-) diff --git a/qcom/lahaina-cdp.dtsi b/qcom/lahaina-cdp.dtsi index 5bee66f2ef19..c9b2da960900 100644 --- a/qcom/lahaina-cdp.dtsi +++ b/qcom/lahaina-cdp.dtsi @@ -189,7 +189,6 @@ vcc-supply = <&pm8350_l7>; vcc-voltage-level = <2504000 2950000>; - vcc-low-voltage-sup; vcc-max-microamp = <800000>; vccq-supply = <&pm8350_l9>; diff --git a/qcom/lahaina-mtp.dtsi b/qcom/lahaina-mtp.dtsi index 98ff6a6a3903..b896ca9f97d0 100644 --- a/qcom/lahaina-mtp.dtsi +++ b/qcom/lahaina-mtp.dtsi @@ -144,7 +144,6 @@ vcc-supply = <&pm8350_l7>; vcc-voltage-level = <2504000 2950000>; - vcc-low-voltage-sup; vcc-max-microamp = <800000>; vccq-supply = <&pm8350_l9>; diff --git a/qcom/lahaina-qrd-common.dtsi b/qcom/lahaina-qrd-common.dtsi index a25037a3d397..935146de871d 100644 --- a/qcom/lahaina-qrd-common.dtsi +++ b/qcom/lahaina-qrd-common.dtsi @@ -24,7 +24,6 @@ vcc-supply = <&pm8350_l7>; vcc-voltage-level = <2504000 2950000>; - vcc-low-voltage-sup; vcc-max-microamp = <800000>; vccq-supply = <&pm8350_l9>; From e7187632a8cfb4b25eaff17663e6597c3a37e1fd Mon Sep 17 00:00:00 2001 From: Guru Das Srinagesh Date: Thu, 8 Oct 2020 17:16:46 -0700 Subject: [PATCH 71/88] ARM: dts: msm: Convert sdxlemur stub regulators to RPMh Convert stub regulator nodes to RPMh nodes by adding the correct voltage limits and correcting the labels to use the right PMIC suffix (B). Change-Id: Ie4aed5599663274d2f6db2516203db9f137968b2 --- qcom/sdxlemur-regulators.dtsi | 493 ++++++++++++++++++++++++++++++ qcom/sdxlemur-stub-regulator.dtsi | 265 ---------------- qcom/sdxlemur.dtsi | 2 +- 3 files changed, 494 insertions(+), 266 deletions(-) create mode 100644 qcom/sdxlemur-regulators.dtsi delete mode 100644 qcom/sdxlemur-stub-regulator.dtsi diff --git a/qcom/sdxlemur-regulators.dtsi b/qcom/sdxlemur-regulators.dtsi new file mode 100644 index 000000000000..f9bc61470178 --- /dev/null +++ b/qcom/sdxlemur-regulators.dtsi @@ -0,0 +1,493 @@ +#include + +/* RPMh regulators: */ +&apps_rsc { + rpmh-regulator-msslvl { + compatible = "qcom,rpmh-arc-regulator"; + qcom,resource-name = "mss.lvl"; + VDD_MODEM_LEVEL: + VDD_MSS_LEVEL: + S1B_LEVEL: pmx65_s1_level: regulator-pmx65-s1-level { + regulator-name = "pmx65_s1_level"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,init-voltage-level = + ; + }; + }; + + rpmh-regulator-smpb2 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "smpb2"; + S2B: pmx65_s2: regulator-pmx65-s2 { + regulator-name = "pmx65_s2"; + qcom,set = ; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1400000>; + qcom,init-voltage = <1224000>; + }; + }; + + rpmh-regulator-smpb3 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "smpb3"; + S3B: pmx65_s3: regulator-pmx65-s3 { + regulator-name = "pmx65_s3"; + qcom,set = ; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1040000>; + qcom,init-voltage = <776000>; + }; + }; + + rpmh-regulator-smpb4 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "smpb4"; + S4B: pmx65_s4: regulator-pmx65-s4 { + regulator-name = "pmx65_s4"; + qcom,set = ; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2024000>; + qcom,init-voltage = <1824000>; + }; + }; + + rpmh-regulator-mxlvl { + compatible = "qcom,rpmh-arc-regulator"; + qcom,resource-name = "mx.lvl"; + proxy-supply = <&VDD_MXA_LEVEL>; + + VDD_MXA_LEVEL: VDD_MX_LEVEL: + L19B_LEVEL: pmx65_l19_level: regulator-pmx65-l19-level { + regulator-name = "pmx65_l19_level"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,init-voltage-level = + ; + qcom,proxy-consumer-enable; + qcom,proxy-consumer-voltage = + ; + }; + + VDD_MXA_LEVEL_AO: VDD_MX_LEVEL_AO: L19B_LEVEL_AO: + pmx65_l19_level_ao: regulator-pmx65-l19-level_ao { + regulator-name = "pmx65_l19_level_ao"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,init-voltage-level = + ; + }; + }; + + rpmh-regulator-cxlvl { + compatible = "qcom,rpmh-arc-regulator"; + qcom,resource-name = "cx.lvl"; + proxy-supply = <&VDD_CX_LEVEL>; + + VDD_CX_LEVEL: + S5B_LEVEL: pmx65_s5_level: regulator-pmx65-s5-level { + regulator-name = "pmx65_s5_level"; + qcom,set = ; + pmx65_s5_level-parent-supply = <&VDD_MXA_LEVEL>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,init-voltage-level = + ; + qcom,min-dropout-voltage-level = <(-1)>; + qcom,proxy-consumer-enable; + qcom,proxy-consumer-voltage = + ; + }; + + VDD_CX_LEVEL_AO: + S5B_LEVEL_AO: pmx65_s5_level_ao: regulator-pmx65-s5-level_ao { + regulator-name = "pmx65_s5_level_ao"; + qcom,set = ; + vin-supply = <&VDD_MXA_LEVEL>; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,init-voltage-level = + ; + qcom,min-dropout-voltage-level = <(-1)>; + }; + }; + + rpmh-regulator-smpb7 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "smpb7"; + S7B: pmx65_s7: regulator-pmx65-s7 { + regulator-name = "pmx65_s7"; + qcom,set = ; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1040000>; + qcom,init-voltage = <936000>; + }; + }; + + rpmh-regulator-smpb8 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "smpb8"; + S8B: pmx65_s8: regulator-pmx65-s8 { + regulator-name = "pmx65_s8"; + qcom,set = ; + regulator-min-microvolt = <304000>; + regulator-max-microvolt = <1300000>; + qcom,init-voltage = <824000>; + }; + }; + + rpmh-regulator-ldob1 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob1"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + L1B: pmx65_l1: regulator-pmx65-l1 { + regulator-name = "pmx65_l1"; + qcom,set = ; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + qcom,init-voltage = <1200000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob2 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob2"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + L2B: pmx65_l2: regulator-pmx65-l2 { + regulator-name = "pmx65_l2"; + qcom,set = ; + regulator-min-microvolt = <1128000>; + regulator-max-microvolt = <1128000>; + qcom,init-voltage = <1128000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob3 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob3"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + L3B: pmx65_l3: regulator-pmx65-l3 { + regulator-name = "pmx65_l3"; + qcom,set = ; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <960000>; + qcom,init-voltage = <800000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob4 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob4"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + L4B: pmx65_l4: regulator-pmx65-l4 { + regulator-name = "pmx65_l4"; + qcom,set = ; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + qcom,init-voltage = <912000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob5 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob5"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + L5B: pmx65_l5: regulator-pmx65-l5 { + regulator-name = "pmx65_l5"; + qcom,set = ; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob6 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob6"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + L6B: pmx65_l6: regulator-pmx65-l6 { + regulator-name = "pmx65_l6"; + qcom,set = ; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + qcom,init-voltage = <1800000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-mxclvl { + compatible = "qcom,rpmh-arc-regulator"; + qcom,resource-name = "mxc.lvl"; + VDD_MXC_LEVEL: + L7B_LEVEL: pmx65_l7_level: regulator-pmx65-l7-level { + regulator-name = "pmx65_l7_level"; + qcom,set = ; + regulator-min-microvolt = + ; + regulator-max-microvolt = + ; + qcom,init-voltage-level = + ; + }; + }; + + rpmh-regulator-ldob8 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob8"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + L8B: pmx65_l8: regulator-pmx65-l8 { + regulator-name = "pmx65_l8"; + qcom,set = ; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + qcom,init-voltage = <800000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob9 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob9"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + L9B: pmx65_l9: regulator-pmx65-l9 { + regulator-name = "pmx65_l9"; + qcom,set = ; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + qcom,init-voltage = <800000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob10 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob10"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + L10B: pmx65_l10: regulator-pmx65-l10 { + regulator-name = "pmx65_l10"; + qcom,set = ; + regulator-min-microvolt = <3088000>; + regulator-max-microvolt = <3088000>; + qcom,init-voltage = <3088000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob11 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob11"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + L11B: pmx65_l11: regulator-pmx65-l11 { + regulator-name = "pmx65_l11"; + qcom,set = ; + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <2928000>; + qcom,init-voltage = <1808000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob12 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob12"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + L12B: pmx65_l12: regulator-pmx65-l12 { + regulator-name = "pmx65_l12"; + qcom,set = ; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + qcom,init-voltage = <1200000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob13 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob13"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + L13B: pmx65_l13: regulator-pmx65-l13 { + regulator-name = "pmx65_l13"; + qcom,set = ; + regulator-min-microvolt = <1704000>; + regulator-max-microvolt = <2928000>; + qcom,init-voltage = <1808000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob14 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob14"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + L14B: pmx65_l14: regulator-pmx65-l14 { + regulator-name = "pmx65_l14"; + qcom,set = ; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <800000>; + qcom,init-voltage = <624000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob15 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob15"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + L15B: pmx65_l15: regulator-pmx65-l15 { + regulator-name = "pmx65_l15"; + qcom,set = ; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + qcom,init-voltage = <1200000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob16 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob16"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 10000>; + L16B: pmx65_l16: regulator-pmx65-l16 { + regulator-name = "pmx65_l16"; + qcom,set = ; + regulator-min-microvolt = <1776000>; + regulator-max-microvolt = <1776000>; + qcom,init-voltage = <1776000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob17 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob17"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + L17B: pmx65_l17: regulator-pmx65-l17 { + regulator-name = "pmx65_l17"; + qcom,set = ; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <960000>; + qcom,init-voltage = <744000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob20 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob20"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + L20B: pmx65_l20: regulator-pmx65-l20 { + regulator-name = "pmx65_l20"; + qcom,set = ; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + qcom,init-voltage = <912000>; + qcom,init-mode = ; + }; + }; + + rpmh-regulator-ldob21 { + compatible = "qcom,rpmh-vrm-regulator"; + qcom,resource-name = "ldob21"; + qcom,regulator-type = "pmic5-ldo"; + qcom,supported-modes = + ; + qcom,mode-threshold-currents = <0 30000>; + L21B: pmx65_l21: regulator-pmx65-l21 { + regulator-name = "pmx65_l21"; + qcom,set = ; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <912000>; + qcom,init-voltage = <912000>; + qcom,init-mode = ; + }; + }; +}; diff --git a/qcom/sdxlemur-stub-regulator.dtsi b/qcom/sdxlemur-stub-regulator.dtsi deleted file mode 100644 index 3e0e649882a5..000000000000 --- a/qcom/sdxlemur-stub-regulator.dtsi +++ /dev/null @@ -1,265 +0,0 @@ -#include - -&soc { - VDD_MSS_LEVEL: - S1E_LEVEL: - pmx65_s1_level: regulator-pmx65-s1-level { - compatible = "qcom,stub-regulator"; - regulator-name = "pmx65_s1_level"; - qcom,hpm-min-load = <10000>; - regulator-min-microvolt = - ; - regulator-max-microvolt = ; - }; - - S2E: - pmx65_s2: regulator-pmx65-s2 { - compatible = "qcom,stub-regulator"; - regulator-name = "pmx65_s2"; - qcom,hpm-min-load = <10000>; - regulator-min-microvolt = <1060000>; - regulator-max-microvolt = <1560000>; - }; - - S4E: - pmx65_s4: regulator-pmx65-s4 { - compatible = "qcom,stub-regulator"; - regulator-name = "pmx65_s4"; - qcom,hpm-min-load = <10000>; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <2040000>; - }; - - VDD_CX_LEVEL: - S5E_LEVEL: - pmx65_s5_level: regulator-pmx65-s5-level { - compatible = "qcom,stub-regulator"; - regulator-name = "pmx65_s5_level"; - qcom,hpm-min-load = <10000>; - regulator-min-microvolt = - ; - regulator-max-microvolt = ; - }; - - VDD_CX_LEVEL_AO: - S5E_LEVEL_AO: - pmx65_s5_level_ao: regulator-pmx65-s5-level-ao { - compatible = "qcom,stub-regulator"; - regulator-name = "pmx65_s5_level_ao"; - qcom,hpm-min-load = <10000>; - regulator-min-microvolt = - ; - regulator-max-microvolt = ; - }; - - S7E: - pmx65_s7: regulator-pmx65-s7 { - compatible = "qcom,stub-regulator"; - regulator-name = "pmx65_s7"; - qcom,hpm-min-load = <10000>; - regulator-min-microvolt = <775000>; - regulator-max-microvolt = <1150000>; - }; - - L1E: - pmx65_l1: regulator-pmx65-l1 { - compatible = "qcom,stub-regulator"; - regulator-name = "pmx65_l1"; - qcom,hpm-min-load = <10000>; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1300000>; - }; - - L2E: - pmx65_l2: regulator-pmx65-l2 { - compatible = "qcom,stub-regulator"; - regulator-name = "pmx65_l2"; - qcom,hpm-min-load = <10000>; - regulator-min-microvolt = <960000>; - regulator-max-microvolt = <1170000>; - }; - - L3E: - pmx65_l3: regulator-pmx65-l3 { - compatible = "qcom,stub-regulator"; - regulator-name = "pmx65_l3"; - qcom,hpm-min-load = <10000>; - regulator-min-microvolt = <530000>; - regulator-max-microvolt = <800000>; - }; - - L4E: - pmx65_l4: regulator-pmx65-l4 { - compatible = "qcom,stub-regulator"; - regulator-name = "pmx65_l4"; - qcom,hpm-min-load = <10000>; - regulator-min-microvolt = <675000>; - regulator-max-microvolt = <1050000>; - }; - - L5E: - pmx65_l5: regulator-pmx65-l5 { - compatible = "qcom,stub-regulator"; - regulator-name = "pmx65_l5"; - qcom,hpm-min-load = <10000>; - regulator-min-microvolt = <1615000>; - regulator-max-microvolt = <1980000>; - }; - - L6E: - pmx65_l6: regulator-pmx65-l6 { - compatible = "qcom,stub-regulator"; - regulator-name = "pmx65_l6"; - qcom,hpm-min-load = <10000>; - regulator-min-microvolt = <1504000>; - regulator-max-microvolt = <2000000>; - }; - - VDD_MX_LEVEL: - L7E_LEVEL: - pmx65_l7_level: regulator-pmx65-l7-level { - compatible = "qcom,stub-regulator"; - regulator-name = "pmx65_l7_level"; - qcom,hpm-min-load = <10000>; - regulator-min-microvolt = - ; - regulator-max-microvolt = ; - }; - - VDD_MX_LEVEL_AO: - L7E_LEVEL_AO: - pmx65_l7_level_ao: regulator-pmx65-l7-level-ao { - compatible = "qcom,stub-regulator"; - regulator-name = "pmx65_l7_level_ao"; - qcom,hpm-min-load = <10000>; - regulator-min-microvolt = - ; - regulator-max-microvolt = ; - }; - - L8E: - pmx65_l8: regulator-pmx65-l8 { - compatible = "qcom,stub-regulator"; - regulator-name = "pmx65_l8"; - qcom,hpm-min-load = <10000>; - regulator-min-microvolt = <751000>; - regulator-max-microvolt = <824000>; - }; - - L9E: - pmx65_l9: regulator-pmx65-l9 { - compatible = "qcom,stub-regulator"; - regulator-name = "pmx65_l9"; - qcom,hpm-min-load = <10000>; - regulator-min-microvolt = <760000>; - regulator-max-microvolt = <840000>; - }; - - L10E: - pmx65_l10: regulator-pmx65-l10 { - compatible = "qcom,stub-regulator"; - regulator-name = "pmx65_l10"; - qcom,hpm-min-load = <10000>; - regulator-min-microvolt = <2700000>; - regulator-max-microvolt = <3544000>; - }; - - L11E: - pmx65_l11: regulator-pmx65-l11 { - compatible = "qcom,stub-regulator"; - regulator-name = "pmx65_l11"; - qcom,hpm-min-load = <10000>; - regulator-min-microvolt = <1650000>; - regulator-max-microvolt = <1950000>; - }; - - L12E: - pmx65_l12: regulator-pmx65-l12 { - compatible = "qcom,stub-regulator"; - regulator-name = "pmx65_l12"; - qcom,hpm-min-load = <10000>; - regulator-min-microvolt = <1140000>; - regulator-max-microvolt = <1260000>; - }; - - L13E: - pmx65_l13: regulator-pmx65-l13 { - compatible = "qcom,stub-regulator"; - regulator-name = "pmx65_l13"; - qcom,hpm-min-load = <10000>; - regulator-min-microvolt = <1650000>; - regulator-max-microvolt = <1950000>; - }; - - L14E: - pmx65_l14: regulator-pmx65-l14 { - compatible = "qcom,stub-regulator"; - regulator-name = "pmx65_l14"; - qcom,hpm-min-load = <10000>; - regulator-min-microvolt = <515000>; - regulator-max-microvolt = <1050000>; - }; - - L15E: - pmx65_l15: regulator-pmx65-l15 { - compatible = "qcom,stub-regulator"; - regulator-name = "pmx65_l15"; - qcom,hpm-min-load = <10000>; - regulator-min-microvolt = <1080000>; - regulator-max-microvolt = <1304000>; - }; - - L16E: - pmx65_l16: regulator-pmx65-l16 { - compatible = "qcom,stub-regulator"; - regulator-name = "pmx65_l16"; - qcom,hpm-min-load = <10000>; - regulator-min-microvolt = <1698000>; - regulator-max-microvolt = <1957000>; - }; - - L17E: - pmx65_l17: regulator-pmx65-l17 { - compatible = "qcom,stub-regulator"; - regulator-name = "pmx65_l17"; - qcom,hpm-min-load = <10000>; - regulator-min-microvolt = <536000>; - regulator-max-microvolt = <888000>; - }; - - L18E: - pmx65_l18: regulator-pmx65-l18 { - compatible = "qcom,stub-regulator"; - regulator-name = "pmx65_l18"; - qcom,hpm-min-load = <10000>; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1304000>; - }; - - L19E: - pmx65_l19: regulator-pmx65-l19 { - compatible = "qcom,stub-regulator"; - regulator-name = "pmx65_l19"; - qcom,hpm-min-load = <10000>; - regulator-min-microvolt = <700000>; - regulator-max-microvolt = <880000>; - }; - - L20E: - pmx65_l20: regulator-pmx65-l20 { - compatible = "qcom,stub-regulator"; - regulator-name = "pmx65_l20"; - qcom,hpm-min-load = <10000>; - regulator-min-microvolt = <826000>; - regulator-max-microvolt = <898000>; - }; - - L21E: - pmx65_l21: regulator-pmx65-l21 { - compatible = "qcom,stub-regulator"; - regulator-name = "pmx65_l21"; - qcom,hpm-min-load = <10000>; - regulator-min-microvolt = <530000>; - regulator-max-microvolt = <800000>; - }; -}; diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index c2dad689e452..b2124cb671ef 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -918,7 +918,7 @@ }; #include "sdxlemur-pinctrl.dtsi" -#include "sdxlemur-stub-regulator.dtsi" +#include "sdxlemur-regulators.dtsi" #include "msm-arm-smmu-sdxlemur.dtsi" #include "sdxlemur-ion.dtsi" #include "sdxlemur-usb.dtsi" From f6b1b9d2a3b8928ce47592b7f4f5f1c82201f6da Mon Sep 17 00:00:00 2001 From: Guru Das Srinagesh Date: Mon, 12 Oct 2020 15:58:12 -0700 Subject: [PATCH 72/88] ARM: dts: msm: Add SD card regulator devices for sdxlemur Add regulator devices for the external gpio-controlled regulators which power the SD Card slot on sdxlemur boards. Change-Id: I242680740f6f211ed25e70716fdb1c93512c70fe --- qcom/sdxlemur-regulators.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/qcom/sdxlemur-regulators.dtsi b/qcom/sdxlemur-regulators.dtsi index f9bc61470178..2fc8aaf2362f 100644 --- a/qcom/sdxlemur-regulators.dtsi +++ b/qcom/sdxlemur-regulators.dtsi @@ -1,4 +1,5 @@ #include +#include /* RPMh regulators: */ &apps_rsc { @@ -490,4 +491,25 @@ qcom,init-mode = ; }; }; + + vreg_vddpx_2: vddpx2-gpio-regulator { + compatible = "regulator-gpio"; + regulator-name = "vddpx_2"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2850000>; + enable-gpio = <&tlmm 98 GPIO_ACTIVE_HIGH>; + gpios = <&tlmm 100 GPIO_ACTIVE_HIGH>; + states = <1800000 0>, + <2850000 1>; + startup-delay-us = <200000>; + enable-active-high; + }; + + vreg_sd_vdd: sd-vdd-fixed-regulator { + compatible = "qcom,stub-regulator"; + regulator-name = "sd_vdd"; + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <2950000>; + parent-supply = <&vreg_vddpx_2>; + }; }; From 08267086f13e06ebad5197038aaadf3e4677793d Mon Sep 17 00:00:00 2001 From: Deepak Kumar Date: Tue, 13 Oct 2020 18:41:52 +0530 Subject: [PATCH 73/88] ARM: dts: msm: Add GPU_CPR register space for Shima Extend the GMU register space to include the GPU_CPR registers. Change-Id: I171e18ce3bd05def1326dfd0ece8b53fb19ee62d --- qcom/shima-gpu.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qcom/shima-gpu.dtsi b/qcom/shima-gpu.dtsi index 57672d085707..f7808d3470d0 100644 --- a/qcom/shima-gpu.dtsi +++ b/qcom/shima-gpu.dtsi @@ -438,7 +438,7 @@ gmu: qcom,gmu@3d69000 { compatible = "qcom,gpu-gmu"; - reg = <0x3d6a000 0x30000>, + reg = <0x3d6a000 0x34000>, <0xb290000 0x10000>; reg-names = "kgsl_gmu_reg", From b9878c46ffbe43412f17688bb557b087794eb8d4 Mon Sep 17 00:00:00 2001 From: Bavyasritha Alahari Date: Tue, 13 Oct 2020 19:04:47 +0530 Subject: [PATCH 74/88] ARM: dts: msm: Add cdsp rpmsg entry in holi and shima CDSPRM module relies on the rpmsg node to create a communication channel with CDSP. CDSPRM module implements a RPMSG interface to communicate with CDSP while provoding a way for CPU QoS to benefit CDSP applications performance. Change-Id: I8e151744db6943544a8b05e864b9c8e39e87291f --- qcom/holi.dtsi | 12 ++++++++++++ qcom/lahaina.dtsi | 2 +- qcom/shima.dtsi | 12 ++++++++++++ 3 files changed, 25 insertions(+), 1 deletion(-) diff --git a/qcom/holi.dtsi b/qcom/holi.dtsi index 1d8a294b6fd4..3e77d7072bf0 100644 --- a/qcom/holi.dtsi +++ b/qcom/holi.dtsi @@ -1786,6 +1786,18 @@ qcom,glink-channels = "glink_ssr"; qcom,notify-edges = <&glink_adsp>; }; + + qcom,msm_cdsprm_rpmsg { + compatible = "qcom,msm-cdsprm-rpmsg"; + qcom,glink-channels = "cdsprmglink-apps-dsp"; + qcom,intents = <0x20 12>; + + msm_cdsp_rm: qcom,msm_cdsp_rm { + compatible = "qcom,msm-cdsp-rm"; + qcom,qos-latency-us = <70>; + qcom,qos-maxhold-ms = <20>; + }; + }; }; }; diff --git a/qcom/lahaina.dtsi b/qcom/lahaina.dtsi index c57b755b6524..5a1ef7f0b987 100644 --- a/qcom/lahaina.dtsi +++ b/qcom/lahaina.dtsi @@ -4337,7 +4337,7 @@ msm_cdsp_rm: qcom,msm_cdsp_rm { compatible = "qcom,msm-cdsp-rm"; - qcom,qos-latency-us = <60>; + qcom,qos-latency-us = <70>; qcom,qos-maxhold-ms = <20>; }; }; diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi index 650f05e7da66..db4053736c2c 100644 --- a/qcom/shima.dtsi +++ b/qcom/shima.dtsi @@ -1460,6 +1460,18 @@ qcom,glink-channels = "glink_ssr"; qcom,notify-edges = <&glink_adsp>; }; + + qcom,msm_cdsprm_rpmsg { + compatible = "qcom,msm-cdsprm-rpmsg"; + qcom,glink-channels = "cdsprmglink-apps-dsp"; + qcom,intents = <0x20 12>; + + msm_cdsp_rm: qcom,msm_cdsp_rm { + compatible = "qcom,msm-cdsp-rm"; + qcom,qos-latency-us = <70>; + qcom,qos-maxhold-ms = <20>; + }; + }; }; }; From 1be676de59a1cc0a559a720945cfea45ef65b454 Mon Sep 17 00:00:00 2001 From: Abhishek Bohra Date: Tue, 22 Sep 2020 21:31:35 +0530 Subject: [PATCH 75/88] ARM: dts: msm: Add firmware node for yupik Add firmware node for vendor partition for yupik soc. Change-Id: Ifb8e21f5da45d66e9843301a3b0ece6501f14511 --- qcom/yupik.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/qcom/yupik.dtsi b/qcom/yupik.dtsi index 838e6ceccece..d9fd237a7c4c 100644 --- a/qcom/yupik.dtsi +++ b/qcom/yupik.dtsi @@ -31,6 +31,26 @@ scm { compatible = "qcom,scm"; }; + android { + compatible = "android,firmware"; + vbmeta { + compatible = "android,vbmeta"; + parts = "vbmeta,boot,system,vendor,dtbo"; + }; + + fstab { + compatible = "android,fstab"; + vendor { + compatible = "android,vendor"; + dev = "/dev/block/platform/soc/1d84000.ufshc/by-name/vendor"; + + type = "ext4"; + mnt_flags = "ro,barrier=1,discard"; + fsmgr_flags = "wait,slotselect,avb"; + status = "ok"; + }; + }; + }; }; cpus { From 11503499edcf50f1f5500bd5344de4dea541f0bd Mon Sep 17 00:00:00 2001 From: Gopala Krishna Nuthaki Date: Tue, 13 Oct 2020 19:24:15 +0530 Subject: [PATCH 76/88] ARM: dts: msm: Add beamer ADC and RF sensors for HOLI Add QMI beamer ADC, RF sensors to QMI supported sensors list and beamer ADC sensors thermal config. Add modem_bw_backoff cooling device support. Change-Id: I4d1dbfd0a4cae8887deb3a258a6e2e4b09da58dc --- qcom/holi-thermal-modem.dtsi | 92 ++++++++++++++++++++++-------------- 1 file changed, 57 insertions(+), 35 deletions(-) diff --git a/qcom/holi-thermal-modem.dtsi b/qcom/holi-thermal-modem.dtsi index 4d5b8f51b9a1..c0a9ba602c1d 100644 --- a/qcom/holi-thermal-modem.dtsi +++ b/qcom/holi-thermal-modem.dtsi @@ -20,8 +20,8 @@ #cooling-cells = <2>; }; - modem_bw: modem_bw { - qcom,qmi-dev-name = "modem_bw"; + modem_bw_backoff: modem_bw_backoff { + qcom,qmi-dev-name = "modem_bw_backoff"; #cooling-cells = <2>; }; @@ -127,9 +127,16 @@ "qfe_wtr_pa1", "qfe_wtr_pa2", "qfe_wtr_pa3", - "sys_therm1", - "sys_therm2", - "modem_tsens1"; + "modem_tsens1", + "beamer_n_therm", + "beamer_e_therm", + "beamer_w_therm", + "qfe_ret_pa0_fr1", + "qfe_wtr_pa0_fr1", + "qfe_wtr_pa1_fr1", + "qfe_wtr_pa2_fr1", + "qfe_wtr_pa3_fr1", + "qfe_wtr0_fr1"; }; }; }; @@ -240,36 +247,6 @@ }; }; - modem-wifi-usr { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-governor = "user_space"; - thermal-sensors = <&qmi_sensor - (QMI_MODEM_INST_ID+QMI_SYS_THERM_1)>; - trips { - active-config0 { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - }; - }; - - modem-ambient-usr { - polling-delay-passive = <0>; - polling-delay = <0>; - thermal-governor = "user_space"; - thermal-sensors = <&qmi_sensor - (QMI_MODEM_INST_ID+QMI_SYS_THERM_2)>; - trips { - active-config0 { - temperature = <125000>; - hysteresis = <1000>; - type = "passive"; - }; - }; - }; - modem-0-usr { polling-delay-passive = <0>; polling-delay = <0>; @@ -374,4 +351,49 @@ }; }; }; + + beamer-n-therm-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_BEAMER_N_THERM)>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + beamer-e-therm-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_BEAMER_E_THERM)>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + + beamer-w-therm-usr { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "user_space"; + thermal-sensors = <&qmi_sensor + (QMI_MODEM_INST_ID+QMI_BEAMER_W_THERM)>; + trips { + active-config0 { + temperature = <125000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; }; From 1a296131e5b7d300d1d78efe45ffd97d35248499 Mon Sep 17 00:00:00 2001 From: Neeraj Upadhyay Date: Wed, 14 Oct 2020 15:58:12 +0530 Subject: [PATCH 77/88] ARM: dts: msm: Export qfprom cell to userspace for Shima Add support to export qfprom cell values as sysfs entries to userspace. Change-Id: Iedc3fbdffeb1992323e514628961567479c0ed35 --- qcom/shima.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi index fd0b467f4806..3ef5da0e77b3 100644 --- a/qcom/shima.dtsi +++ b/qcom/shima.dtsi @@ -3451,6 +3451,21 @@ }; }; + qfprom_sys: qfprom@0 { + compatible = "qcom,qfprom-sys"; + + nvmem-cells = <&gpu_speed_bin>, + <&gpu_gaming_bin>, + <&adsp_variant>, + <&feat_conf_m7>, + <&feat_conf_qc_spare_20_lsb>; + nvmem-cell-names = "gpu_speed_bin", + "gpu_gaming_bin", + "adsp_variant", + "feat_conf_m7", + "feat_conf_qc_spare_20_lsb"; + }; + wlan: qcom,cnss-qca6490@b0000000 { compatible = "qcom,cnss-qca6490"; reg = <0xb0000000 0x10000>; From cd42f7bceff3846f0e23e6d79b095708e85be476 Mon Sep 17 00:00:00 2001 From: Elson Roy Serrao Date: Thu, 8 Oct 2020 15:48:37 -0700 Subject: [PATCH 78/88] ARM: dts: msm: Add QMP PHY dt entries on sdxlemur Add hsphy and ssphy related dt nodes and the phy init sequence on sdxlemur. Change-Id: I89177fecd76f5a9ace051e118f304698e9d1e636 --- qcom/sdxlemur-usb.dtsi | 154 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 154 insertions(+) diff --git a/qcom/sdxlemur-usb.dtsi b/qcom/sdxlemur-usb.dtsi index d11cad741801..c80dc7e4b561 100644 --- a/qcom/sdxlemur-usb.dtsi +++ b/qcom/sdxlemur-usb.dtsi @@ -1,3 +1,5 @@ +#include + &soc { usb: ssusb@a600000 { compatible = "qcom,dwc-usb3-msm"; @@ -44,6 +46,7 @@ compatible = "snps,dwc3"; reg = <0x0a600000 0xcd00>; interrupts = ; + usb-phy = <&usb2_phy>, <&usb_qmp_phy>; linux,sysdev_is_parent; snps,disable-clk-gating; snps,has-lpm-erratum; @@ -60,4 +63,155 @@ usb_nop_phy: usb_nop_phy { compatible = "usb-nop-xceiv"; }; + + usb2_phy: hsphy@ff4000 { + compatible = "qcom,usb-hsphy-snps-femto"; + reg = <0xff4000 0x120>; + reg-names = "hsusb_phy_base"; + + vdd-supply = <&pmx65_l4>; + qcom,vdd-voltage-level = <0 912000 912000>; + vdda18-supply = <&pmx65_l5>; + vdda33-supply = <&pmx65_l10>; + + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>; + clock-names = "ref_clk_src", "cfg_ahb_clk"; + + resets = <&gcc GCC_QUSB2PHY_BCR>; + reset-names = "phy_reset"; + qcom,no-rext-present; + }; + + usb_qmp_phy: ssphy@ff6000 { + compatible = "qcom,usb-ssphy-qmp-v2"; + reg = <0xff6000 0x2000>, + <0xff628c 0x4>; + reg-names = "qmp_phy_base", + "pcs_clamp_enable_reg"; + + vdd-supply = <&pmx65_l4>; + qcom,vdd-voltage-level = <0 912000 912000>; + qcom,vdd-max-load-uA = <47900>; + core-supply = <&pmx65_l1>; + qcom,core-max-load-uA = <15000>; + + clocks = <&gcc GCC_USB3_PHY_AUX_CLK>, + <&gcc GCC_USB3_PHY_PIPE_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>; + clock-names = "aux_clk", "pipe_clk", "ref_clk_src", + "cfg_ahb_clk"; + + resets = <&gcc GCC_USB3_PHY_BCR>, + <&gcc GCC_USB3PHY_PHY_BCR>; + reset-names = "phy_reset", "phy_phy_reset"; + + qcom,qmp-phy-init-seq = + /* */ + ; + + qcom,qmp-phy-reg-offset = + ; + + + }; }; From fd35c6b3ec1eafedd33e3f7605d8df8ae773bbd3 Mon Sep 17 00:00:00 2001 From: Elson Roy Serrao Date: Mon, 12 Oct 2020 19:21:45 -0700 Subject: [PATCH 79/88] ARM: dts: msm: Update the qmp register macro file name for Lahaina Update the qmp register macro definition file name from target specific to generic 5nm combo and uni file. Change-Id: I58da7126a19985e1fa26a71bff90fd83f0c2fcbb --- qcom/lahaina-usb.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/qcom/lahaina-usb.dtsi b/qcom/lahaina-usb.dtsi index c0b48ff2a264..9a0515fb941c 100644 --- a/qcom/lahaina-usb.dtsi +++ b/qcom/lahaina-usb.dtsi @@ -1,5 +1,6 @@ #include -#include +#include +#include &soc { usb0: ssusb@a600000 { From 2ab5c5ffbefd6e681965ee76472ced2a7462977c Mon Sep 17 00:00:00 2001 From: Veerabhadrarao Badiganti Date: Wed, 14 Oct 2020 22:40:24 +0530 Subject: [PATCH 80/88] ARM: dts: msm: Configure L9B from retention mode to LPM on shima L9B supply won't really support retention mode on shima, so move it from RM to LPM by increasing the load to 10mA. Change-Id: Ie3f10de1c63a123dae2c5dc2bf7a3ea5a6decc5a --- qcom/shima-idp.dtsi | 5 ++--- qcom/shima-qrd.dtsi | 5 ++--- 2 files changed, 4 insertions(+), 6 deletions(-) diff --git a/qcom/shima-idp.dtsi b/qcom/shima-idp.dtsi index a4be84ba4aee..6f22c8274d7a 100644 --- a/qcom/shima-idp.dtsi +++ b/qcom/shima-idp.dtsi @@ -104,15 +104,14 @@ vccq-supply = <&L9B>; vccq-max-microamp = <900000>; - vccq-min-microamp = <0>; + vccq-min-microamp = <10000>; vccq2-supply = <&S10B>; vccq2-voltage-level = <1800000 1800000>; vccq2-max-microamp = <800000>; qcom,vddp-ref-clk-supply = <&L9B>; - qcom,vddp-ref-clk-max-microamp = <100>; - qcom,vddp-ref-clk-min-microamp = <0>; + qcom,vddp-ref-clk-max-microamp = <10000>; status = "ok"; }; diff --git a/qcom/shima-qrd.dtsi b/qcom/shima-qrd.dtsi index fd21a2271113..0adde33e1398 100644 --- a/qcom/shima-qrd.dtsi +++ b/qcom/shima-qrd.dtsi @@ -105,14 +105,13 @@ vccq-supply = <&L9B>; vccq-max-microamp = <900000>; - vccq-min-microamp = <0>; + vccq-min-microamp = <10000>; vccq2-supply = <&S10B>; vccq2-voltage-level = <1800000 1800000>; qcom,vddp-ref-clk-supply = <&L9B>; - qcom,vddp-ref-clk-max-microamp = <100>; - qcom,vddp-ref-clk-min-microamp = <0>; + qcom,vddp-ref-clk-max-microamp = <10000>; status = "ok"; }; From 812302f3d21fcce100e5d75e4ed441a778f7b173 Mon Sep 17 00:00:00 2001 From: Jeykumar Sankaran Date: Thu, 24 Sep 2020 18:37:45 -0700 Subject: [PATCH 81/88] ARM: dts: msm: add display message queue to trusted vm for lahaina Add a bidirectional message queue in trusted vm for display. This message queue will be used to send display custom data across the vm's. Change-Id: I0e6bb8116acc126642a5bb57fe90fee011acab19 --- qcom/lahaina-vm.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/qcom/lahaina-vm.dtsi b/qcom/lahaina-vm.dtsi index 566dcd1074bd..46d744d95235 100644 --- a/qcom/lahaina-vm.dtsi +++ b/qcom/lahaina-vm.dtsi @@ -167,6 +167,15 @@ qcom,label = <0x0000001>; }; + display-message-queue-pair { + vdevice-type = "message-queue-pair"; + generate = "/hypervisor/display-msgq-pair"; + message-size = <0x000000f0>; + queue-depth = <0x00000008>; + peer-default; + qcom,label = <0x0000002>; + }; + neuron-ch1-shm { vdevice-type = "shm-doorbell"; generate = "/hypervisor/neuron-ch1-shm"; From 6b298addf1c7788a6b9c449f20eb64a2397607de Mon Sep 17 00:00:00 2001 From: Linyu Yuan Date: Thu, 15 Oct 2020 10:37:48 +0800 Subject: [PATCH 82/88] ARM: dts: msm: update PLL_BIAS_CONTROL_2 for holi QRD change PLL_BIAS_CONTROL_2 from 0x15 to 0x17. Change-Id: Ibad85b6ede20016c40ea0c84d96a6e1e799e0d90 --- qcom/holi-qrd.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/qcom/holi-qrd.dtsi b/qcom/holi-qrd.dtsi index 48e5127acab5..35c761d75f92 100644 --- a/qcom/holi-qrd.dtsi +++ b/qcom/holi-qrd.dtsi @@ -414,7 +414,7 @@ 0x0a 0x184 /* PLL_LOCK_DELAY */ 0x19 0xb4 /* PLL_DIGITAL_TIMERS_TWO */ 0x40 0x194 /* PLL_BIAS_CONTROL_1 */ - 0x15 0x198 /* PLL_BIAS_CONTROL_2 */ + 0x17 0x198 /* PLL_BIAS_CONTROL_2 */ 0x21 0x214 /* PWR_CTRL2 */ 0x08 0x220 /* IMP_CTRL1 */ 0x58 0x224 /* IMP_CTRL2 */ @@ -435,7 +435,7 @@ 0x0a 0x184 /* PLL_LOCK_DELAY */ 0x19 0xb4 /* PLL_DIGITAL_TIMERS_TWO */ 0x40 0x194 /* PLL_BIAS_CONTROL_1 */ - 0x15 0x198 /* PLL_BIAS_CONTROL_2 */ + 0x17 0x198 /* PLL_BIAS_CONTROL_2 */ 0x21 0x214 /* PWR_CTRL2 */ 0x08 0x220 /* IMP_CTRL1 */ 0x58 0x224 /* IMP_CTRL2 */ From d9780a09566a760e382b5907d29a5738b01ee348 Mon Sep 17 00:00:00 2001 From: Fenglin Wu Date: Wed, 14 Oct 2020 16:55:57 +0800 Subject: [PATCH 83/88] ARM: dts: msm: Add panel information to amoled-ecm for Shima platforms Add panel information for amoled-ecm device so that the driver can get display off/on notification from the DRM for the active panel and disable/re-enable ECM accordingly. Change-Id: I5dc22cd1b669e92991325f7be8ef4536a140277c --- qcom/shima-idp.dtsi | 8 ++++++++ qcom/shima-qrd.dtsi | 5 +++++ 2 files changed, 13 insertions(+) diff --git a/qcom/shima-idp.dtsi b/qcom/shima-idp.dtsi index a4be84ba4aee..855c9a746bac 100644 --- a/qcom/shima-idp.dtsi +++ b/qcom/shima-idp.dtsi @@ -148,6 +148,14 @@ status = "ok"; }; +&pm8350b_amoled_ecm { + display-panels = <&dsi_r66451_amoled_cmd + &dsi_r66451_amoled_video + &dsi_r66451_amoled_60hz_video + &dsi_r66451_amoled_60hz_cmd + &dsi_r66451_amoled_144hz_cmd>; +}; + &battery_charger { qcom,thermal-mitigation = <3000000 1500000 1000000 500000>; }; diff --git a/qcom/shima-qrd.dtsi b/qcom/shima-qrd.dtsi index fd21a2271113..0b6dff79f200 100644 --- a/qcom/shima-qrd.dtsi +++ b/qcom/shima-qrd.dtsi @@ -185,6 +185,11 @@ status = "ok"; }; +&pm8350b_amoled_ecm { + display-panels = <&dsi_r66451_amoled_cmd + &dsi_r66451_amoled_video>; +}; + &battery_charger { qcom,thermal-mitigation = <10000000 9500000 9000000 8500000 8000000 7500000 7000000 6500000 6000000 5500000 From c39aebbf55cc97674fc45aec145e9b013a038012 Mon Sep 17 00:00:00 2001 From: Sayali Lokhande Date: Mon, 12 Oct 2020 14:16:16 +0530 Subject: [PATCH 84/88] ARM: dts: msm: Add rmtfs_sharedmem support for sdxlemur Add shared memory support to enable rmt_storage service in userspace that allows other processor to access the primary storage device to store its data. Change-Id: I531df175ed7af586f29e274f174b1e7e6508b84c --- qcom/sdxlemur.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index c2dad689e452..3c50979bd76e 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -915,6 +915,14 @@ thermal_zones: thermal-zones { }; + + qcom,rmtfs_sharedmem@0 { + compatible = "qcom,sharedmem-uio"; + reg = <0x0 0x400000>; + reg-names = "rmtfs"; + qcom,client-id = <0x00000001>; + qcom,vm-nav-path; + }; }; #include "sdxlemur-pinctrl.dtsi" From b51f076234c2f627bc23819ec6da28979a702f48 Mon Sep 17 00:00:00 2001 From: Linyu Yuan Date: Mon, 12 Oct 2020 13:17:35 +0800 Subject: [PATCH 85/88] ARM: dts: msm: add USB3_DP_COM_TYPEC_STATUS register Add USB3_DP_COM_TYPEC_STATUS register for Lahaina and Shima, this register's bit0 is used indicates the type-c orientation. Change-Id: I42e35da3074497f24858a313ad4d9235b4729423 --- qcom/lahaina-usb.dtsi | 3 ++- qcom/shima-usb.dtsi | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/qcom/lahaina-usb.dtsi b/qcom/lahaina-usb.dtsi index c0b48ff2a264..0f901b4857d9 100644 --- a/qcom/lahaina-usb.dtsi +++ b/qcom/lahaina-usb.dtsi @@ -177,7 +177,8 @@ USB3_DP_COM_RESET_OVRD_CTRL USB3_DP_COM_PHY_MODE_CTRL USB3_DP_COM_TYPEC_CTRL - USB3_DP_PCS_CLAMP_ENABLE>; + USB3_DP_PCS_CLAMP_ENABLE + USB3_DP_COM_TYPEC_STATUS>; qcom,qmp-phy-init-seq = /* */ diff --git a/qcom/shima-usb.dtsi b/qcom/shima-usb.dtsi index 48b5d3839b21..6e1d3e73b03a 100644 --- a/qcom/shima-usb.dtsi +++ b/qcom/shima-usb.dtsi @@ -148,7 +148,8 @@ USB3_DP_COM_RESET_OVRD_CTRL USB3_DP_COM_PHY_MODE_CTRL USB3_DP_COM_TYPEC_CTRL - USB3_DP_PCS_CLAMP_ENABLE>; + USB3_DP_PCS_CLAMP_ENABLE + USB3_DP_COM_TYPEC_STATUS>; qcom,qmp-phy-init-seq = /* */ From 411a3dba3b425b7db34771b0ce4fcd9c20871457 Mon Sep 17 00:00:00 2001 From: Harigovindan P Date: Thu, 15 Oct 2020 12:20:10 +0530 Subject: [PATCH 86/88] ARM: dts: msm: Enable LCD_REG_EN gpio and LCD_BKLT_PWM on shima Enabling LCD_REG_EN gpio on shima pinctrls and LCD_BKLT_PWM on shima pmic overlays on shima target. Change-Id: If02438f5c28160b643248e3b403c65083e9b6e56 --- qcom/shima-pinctrl.dtsi | 8 ++++---- qcom/shima-pmic-overlay.dtsi | 12 ++++++++++++ 2 files changed, 16 insertions(+), 4 deletions(-) diff --git a/qcom/shima-pinctrl.dtsi b/qcom/shima-pinctrl.dtsi index 91e3b21c26af..eeb47a49d145 100644 --- a/qcom/shima-pinctrl.dtsi +++ b/qcom/shima-pinctrl.dtsi @@ -2872,12 +2872,12 @@ pmx_sde: pmx_sde { sde_dsi_active: sde_dsi_active { mux { - pins = "gpio24"; + pins = "gpio24", "gpio47"; function = "gpio"; }; config { - pins = "gpio24"; + pins = "gpio24", "gpio47"; drive-strength = <8>; /* 8 mA */ bias-disable = <0>; /* no pull */ }; @@ -2885,12 +2885,12 @@ sde_dsi_suspend: sde_dsi_suspend { mux { - pins = "gpio24"; + pins = "gpio24", "gpio47"; function = "gpio"; }; config { - pins = "gpio24"; + pins = "gpio24", "gpio47"; drive-strength = <2>; /* 2 mA */ bias-pull-down; /* PULL DOWN */ }; diff --git a/qcom/shima-pmic-overlay.dtsi b/qcom/shima-pmic-overlay.dtsi index de365f79de68..d83e6fa3b45c 100644 --- a/qcom/shima-pmic-overlay.dtsi +++ b/qcom/shima-pmic-overlay.dtsi @@ -47,6 +47,18 @@ power-source = <1>; }; }; + + lcd_backlight_ctrl { + lcd_backlight_ctrl_default: lcd_backlight_ctrl_default { + pins = "gpio9"; + function = "func1"; + input-disable; + output-enable; + bias-disable; + power-source = <1>; /* 1.8V */ + qcom,drive-strength = <2>; + }; + }; }; &pmk8350_vadc { From ea2569f0b365fbf99a1a98a66ca10e42794c6f8b Mon Sep 17 00:00:00 2001 From: Gopala Krishna Nuthaki Date: Tue, 13 Oct 2020 21:06:22 +0530 Subject: [PATCH 87/88] ARM: dts: msm: Update GPU, core isolation and hotplug threshold for SHIMA Update core isolation and hotplug threshold for silver CPUs to 110C and 112C. Update core isolation and hotplug threshold for gold and gold plus to 108C and 110C. GPU thermal mitigation configuration uses a virtual sensor, which will estimate the max of two GPU sensors. Change the GPU thermal rule to directly use these individual sensors in two separate rule to achieve a better thermal control. Change-Id: I8ee76573e9bef956ca7833d34c8f8aecf3adaa7e --- qcom/shima-thermal.dtsi | 232 ++++++++++++++++++++++++++++++++++++++-- 1 file changed, 226 insertions(+), 6 deletions(-) diff --git a/qcom/shima-thermal.dtsi b/qcom/shima-thermal.dtsi index fc97b1dddafa..abf3371998fc 100644 --- a/qcom/shima-thermal.dtsi +++ b/qcom/shima-thermal.dtsi @@ -110,6 +110,49 @@ }; }; + qcom,cpu-hotplug { + compatible = "qcom,cpu-hotplug"; + cpu0_hotplug: cpu0-hotplug { + qcom,cpu = <&CPU0>; + #cooling-cells = <2>; + }; + + cpu1_hotplug: cpu1-hotplug { + qcom,cpu = <&CPU1>; + #cooling-cells = <2>; + }; + + cpu2_hotplug: cpu2-hotplug { + qcom,cpu = <&CPU2>; + #cooling-cells = <2>; + }; + + cpu3_hotplug: cpu3-hotplug { + qcom,cpu = <&CPU3>; + #cooling-cells = <2>; + }; + + cpu4_hotplug: cpu4-hotplug { + qcom,cpu = <&CPU4>; + #cooling-cells = <2>; + }; + + cpu5_hotplug: cpu5-hotplug { + qcom,cpu = <&CPU5>; + #cooling-cells = <2>; + }; + + cpu6_hotplug: cpu6-hotplug { + qcom,cpu = <&CPU6>; + #cooling-cells = <2>; + }; + + cpu7_hotplug: cpu7-hotplug { + qcom,cpu = <&CPU7>; + #cooling-cells = <2>; + }; + }; + qcom,cpu-voltage-cdev { compatible = "qcom,cc-cooling-devices"; apc1_cluster: qcom,apc1-cluster { @@ -733,6 +776,12 @@ hysteresis = <10000>; type = "passive"; }; + + cpu00_config1: cpu00-config1 { + temperature = <112000>; + hysteresis = <12000>; + type = "passive"; + }; }; cooling-maps { @@ -740,6 +789,17 @@ trip = <&cpu00_config>; cooling-device = <&cpu0_isolate 1 1>; }; + + cpu00_cdev1 { + trip = <&cpu00_config>; + cooling-device = <&CPU0 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + cpu00_cdev2 { + trip = <&cpu00_config1>; + cooling-device = <&cpu0_hotplug 1 1>; + }; }; }; @@ -754,6 +814,12 @@ hysteresis = <10000>; type = "passive"; }; + + cpu01_config1: cpu01-config1 { + temperature = <112000>; + hysteresis = <12000>; + type = "passive"; + }; }; cooling-maps { @@ -761,6 +827,17 @@ trip = <&cpu01_config>; cooling-device = <&cpu1_isolate 1 1>; }; + + cpu01_cdev1 { + trip = <&cpu01_config>; + cooling-device = <&CPU0 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + cpu01_cdev2 { + trip = <&cpu01_config1>; + cooling-device = <&cpu1_hotplug 1 1>; + }; }; }; @@ -775,6 +852,12 @@ hysteresis = <10000>; type = "passive"; }; + + cpu02_config1: cpu02-config1 { + temperature = <112000>; + hysteresis = <12000>; + type = "passive"; + }; }; cooling-maps { @@ -782,6 +865,17 @@ trip = <&cpu02_config>; cooling-device = <&cpu2_isolate 1 1>; }; + + cpu02_cdev1 { + trip = <&cpu02_config>; + cooling-device = <&CPU0 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + cpu02_cdev2 { + trip = <&cpu02_config1>; + cooling-device = <&cpu2_hotplug 1 1>; + }; }; }; @@ -796,6 +890,12 @@ hysteresis = <10000>; type = "passive"; }; + + cpu03_config1: cpu03-config1 { + temperature = <112000>; + hysteresis = <12000>; + type = "passive"; + }; }; cooling-maps { @@ -803,6 +903,17 @@ trip = <&cpu03_config>; cooling-device = <&cpu3_isolate 1 1>; }; + + cpu03_cdev1 { + trip = <&cpu03_config>; + cooling-device = <&CPU0 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + + cpu03_cdev2 { + trip = <&cpu03_config1>; + cooling-device = <&cpu3_hotplug 1 1>; + }; }; }; @@ -813,6 +924,12 @@ thermal-governor = "step_wise"; trips { cpu10_config: cpu10-config { + temperature = <108000>; + hysteresis = <8000>; + type = "passive"; + }; + + cpu10_config1: cpu10-config1 { temperature = <110000>; hysteresis = <10000>; type = "passive"; @@ -830,6 +947,11 @@ cooling-device = <&CPU4 THERMAL_MAX_LIMIT THERMAL_MAX_LIMIT>; }; + + cpu10_cdev2 { + trip = <&cpu10_config1>; + cooling-device = <&cpu4_hotplug 1 1>; + }; }; }; @@ -840,6 +962,12 @@ thermal-governor = "step_wise"; trips { cpu11_config: cpu11-config { + temperature = <108000>; + hysteresis = <8000>; + type = "passive"; + }; + + cpu11_config1: cpu11-config1 { temperature = <110000>; hysteresis = <10000>; type = "passive"; @@ -857,6 +985,11 @@ cooling-device = <&CPU4 THERMAL_MAX_LIMIT THERMAL_MAX_LIMIT>; }; + + cpu11_cdev2 { + trip = <&cpu11_config1>; + cooling-device = <&cpu4_hotplug 1 1>; + }; }; }; @@ -867,6 +1000,12 @@ thermal-governor = "step_wise"; trips { cpu12_config: cpu12-config { + temperature = <108000>; + hysteresis = <8000>; + type = "passive"; + }; + + cpu12_config1: cpu12-config1 { temperature = <110000>; hysteresis = <10000>; type = "passive"; @@ -884,6 +1023,11 @@ cooling-device = <&CPU4 THERMAL_MAX_LIMIT THERMAL_MAX_LIMIT>; }; + + cpu12_cdev2 { + trip = <&cpu12_config1>; + cooling-device = <&cpu5_hotplug 1 1>; + }; }; }; @@ -894,6 +1038,12 @@ thermal-governor = "step_wise"; trips { cpu13_config: cpu13-config { + temperature = <108000>; + hysteresis = <8000>; + type = "passive"; + }; + + cpu13_config1: cpu13-config1 { temperature = <110000>; hysteresis = <10000>; type = "passive"; @@ -911,6 +1061,11 @@ cooling-device = <&CPU4 THERMAL_MAX_LIMIT THERMAL_MAX_LIMIT>; }; + + cpu13_cdev2 { + trip = <&cpu13_config1>; + cooling-device = <&cpu5_hotplug 1 1>; + }; }; }; @@ -921,6 +1076,12 @@ thermal-governor = "step_wise"; trips { cpu14_config: cpu14-config { + temperature = <108000>; + hysteresis = <8000>; + type = "passive"; + }; + + cpu14_config1: cpu14-config1 { temperature = <110000>; hysteresis = <10000>; type = "passive"; @@ -938,6 +1099,11 @@ cooling-device = <&CPU4 THERMAL_MAX_LIMIT THERMAL_MAX_LIMIT>; }; + + cpu14_cdev2 { + trip = <&cpu14_config1>; + cooling-device = <&cpu6_hotplug 1 1>; + }; }; }; @@ -948,6 +1114,12 @@ thermal-governor = "step_wise"; trips { cpu15_config: cpu15-config { + temperature = <108000>; + hysteresis = <8000>; + type = "passive"; + }; + + cpu15_config1: cpu15-config1 { temperature = <110000>; hysteresis = <10000>; type = "passive"; @@ -965,6 +1137,11 @@ cooling-device = <&CPU4 THERMAL_MAX_LIMIT THERMAL_MAX_LIMIT>; }; + + cpu15_cdev2 { + trip = <&cpu15_config1>; + cooling-device = <&cpu6_hotplug 1 1>; + }; }; }; @@ -975,6 +1152,12 @@ thermal-governor = "step_wise"; trips { cpu16_config: cpu16-config { + temperature = <108000>; + hysteresis = <8000>; + type = "passive"; + }; + + cpu16_config1: cpu16-config1 { temperature = <110000>; hysteresis = <10000>; type = "passive"; @@ -986,6 +1169,11 @@ trip = <&cpu16_config>; cooling-device = <&cpu7_isolate 1 1>; }; + + cpu16_cdev2 { + trip = <&cpu16_config1>; + cooling-device = <&cpu7_hotplug 1 1>; + }; }; }; @@ -996,6 +1184,12 @@ thermal-governor = "step_wise"; trips { cpu17_config: cpu17-config { + temperature = <108000>; + hysteresis = <8000>; + type = "passive"; + }; + + cpu17_config1: cpu17-config1 { temperature = <110000>; hysteresis = <10000>; type = "passive"; @@ -1007,17 +1201,21 @@ trip = <&cpu17_config>; cooling-device = <&cpu7_isolate 1 1>; }; + + cpu17_cdev2 { + trip = <&cpu17_config1>; + cooling-device = <&cpu7_hotplug 1 1>; + }; }; }; - gpuss-max-step { + gpuss-0-step { polling-delay-passive = <10>; - polling-delay = <100>; + polling-delay = <0>; thermal-governor = "step_wise"; - thermal-sensors = <&tsens1 1>, <&tsens1 2>; - sensor-aggregation = ; + thermal-sensors = <&tsens1 1>; trips { - gpuss_config: active-config0 { + gpuss0_config: active-config0 { temperature = <95000>; hysteresis = <0>; type = "passive"; @@ -1026,7 +1224,29 @@ cooling-maps { gpu_cdev { - trip = <&gpuss_config>; + trip = <&gpuss0_config>; + cooling-device = <&msm_gpu THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; + }; + + gpuss-1-step { + polling-delay-passive = <10>; + polling-delay = <100>; + thermal-governor = "step_wise"; + thermal-sensors = <&tsens1 2>; + trips { + gpuss1_config: active-config0 { + temperature = <95000>; + hysteresis = <0>; + type = "passive"; + }; + }; + + cooling-maps { + gpu_cdev { + trip = <&gpuss1_config>; cooling-device = <&msm_gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; From 8ceaeb345ea43c89f7ba79c38dd4dbc972d3affd Mon Sep 17 00:00:00 2001 From: Melody Olvera Date: Thu, 1 Oct 2020 16:47:12 -0700 Subject: [PATCH 88/88] ARM: dts: qcom: Fix watchdog entry for sdxlemur The old watchdog entry did not account for the new watchdog changes. This changes it to be compatible with the new watchdog driver. Change-Id: I18542ea7803e5ac2d32b8c41c876957fb2c9f592 --- qcom/sdxlemur.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/qcom/sdxlemur.dtsi b/qcom/sdxlemur.dtsi index 3c50979bd76e..dd2376f371ed 100644 --- a/qcom/sdxlemur.dtsi +++ b/qcom/sdxlemur.dtsi @@ -232,11 +232,12 @@ dcc-ram-offset = <0x800>; }; - watchdog: qcom,wdt@17817000 { + wdog: qcom,wdt@17817000 { compatible = "qcom,msm-watchdog"; reg = <0x17817000 0x1000>; reg-names = "wdt-base"; - interrupts = <1 3 0>, <1 2 0>; + interrupts = , + ; qcom,bark-time = <11000>; qcom,pet-time = <10000>; qcom,wakeup-enable;